SI5332AC09325-GM1R [SILICON]

Processor Specific Clock Generator,;
SI5332AC09325-GM1R
型号: SI5332AC09325-GM1R
厂家: SILICON    SILICON
描述:

Processor Specific Clock Generator,

文件: 总69页 (文件大小:1052K)
中文:  中文翻译
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Si5332 Data Sheet  
6/8/12-Output Any-Frequency Clock Generator  
KEY FEATURES  
Based on Silicon Labs proprietary MultiSynthflexible frequency synthesis technology,  
the Si5332 generates any combination of output frequencies with excellent jitter perfor-  
mance (230 fs rms). The device's highly flexible architecture enables a single device to  
generate a wide range of integer and non-integer related frequencies on up to 12 differ-  
ential clock outputs with 0 ppm frequency synthesis error. The device offers multiple  
banks of outputs that can each be tied to independent voltages, enabling usage in  
mixed-supply applications. Further, the signal format of each clock output is user-config-  
urable. Given its frequency, format, and supply voltage flexibility, the Si5332 is ideally  
suited to replace multiple clock ICs and oscillators with a single device.  
• Any-Frequency 6/8/12-output  
programmable clock generators  
• Offered in three different package sizes,  
supporting different combinations of output  
clocks and user configurable hardware  
input pins  
• 32-pin QFN, up to 6 outputs  
• 40-pin QFN, up to 8 outputs  
• 48-pin QFN, up to 12 outputs  
The Si5332 is quickly and easily configured using ClockBuilder Prosoftware. Clock-  
Builder Pro assigns a custom part number for each unique configuration. Devices  
ordered with custom part numbers are factory-programmed free of charge, making it  
easy to get a custom clock uniquely tailored for each application. Si5332 can also be  
programmed via an I2C serial interface.  
• MultiSynth technology enables any-  
frequency synthesis on any output up to  
250 MHz  
• Highly configurable output path featuring a  
cross point mux  
• Up to three independent fractional  
synthesis output paths  
• Up to five independent integer dividers  
• Embedded 50 MHz crystal option  
Applications:  
• Servers, Storage, Search Acceleration  
• Ethernet Switches, Routers  
• Communications  
• Broadcast Video  
• Input frequency range:  
• External crystal: 16 to 50 MHz  
• Differential clock: 10 to 250 MHz  
• LVCMOS clock: 10 to 170 MHz  
• Small Cells, Mobile Backhaul/Fronthaul • Test and Measurement  
• Print Imaging  
• Industrial, Embedded Computing  
• Output frequency range:  
• Differential: 5 to 312.5 MHz  
• LVCMOS: 5 to 170 MHz  
• User-configurable clock output signal  
format per output: LVDS, LVPECL, HCSL,  
LVCMOS  
• Temperature range: –40 to +85 °C  
• Down and center spread spectrum  
• RoHS-6 compliant  
Si5332 Family Reference Manual  
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Rev. 1.0  
Table of Contents  
1. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3.1 Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.2.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.3 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.4 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  
3.4.1 External Reference Input (XA/XB) . . . . . . . . . . . . . . . . . . . . .10  
3.4.2 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  
3.4.3 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .10  
3.5 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
3.5.1 Output Signal Format . . . . . . . . . . . . . . . . . . . . . . . . .11  
3.5.2 Differential Output Terminations. . . . . . . . . . . . . . . . . . . . . .12  
3.5.3 LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . .16  
3.5.4 LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . .16  
3.5.5 LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . .16  
3.5.6 LVCMOS Output Configurable Tr/Tf . . . . . . . . . . . . . . . . . . . .16  
3.5.7 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . .16  
3.5.8 Differential Output Configurable Skew Settings. . . . . . . . . . . . . . . . .16  
3.5.9 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . .17  
3.5.10 Synchronous Output Disable Feature . . . . . . . . . . . . . . . . . . .17  
3.6 Spread Spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . . .17  
3.7 Universal Hardware Input Pins . . . . . . . . . . . . . . . . . . . . . . . .18  
3.8 Custom Factory Pre-programmed Parts . . . . . . . . . . . . . . . . . . . . .19  
3.9 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .19  
3.10 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . .19  
4. Register Map  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
6.1 Pin Descriptions (48-QFN) . . . . . . . . . . . . . . . . . . . . . . . . .35  
6.2 Pin Descriptions (40-QFN) . . . . . . . . . . . . . . . . . . . . . . . . .40  
6.3 Pin Descriptions (32-QFN) . . . . . . . . . . . . . . . . . . . . . . . . .44  
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
7.1 Si5332 6x6 mm 48-QFN Package Diagram, External Crystal Versions (Si5332A/B/C/D) . . . . .48  
7.2 Si5332 6x6 mm 40-QFN Package Diagram, External Crystal Versions (Si5332A/B/C/D) . . . . .49  
7.3 Si5332 5x5 mm 32-QFN Package Diagram, External Crystal Versions (Si5332A/B/C/D) . . . . .50  
7.4 Si5332 6x6 mm 48-QFN Package Diagram, Embedded Crystal Versions (Si5332E/F/G/H) . . . .52  
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7.5 Si5332 6x6 mm 40-QFN Package Diagram, Embedded Crystal Versions (Si5332E/F/G/H) . . . .53  
7.6 Si5332 5x5 mm 32-QFN Package Diagram, Embedded Crystal Versions (Si5332E/F/G/H) . . . .54  
8. PCB Land Pattern  
. . . . . . . . . . . . . . . . . . . . . . . . . . . .55  
8.1 Si5332A/B/C/D 48-QFN Land Pattern . . . . . . . . . . . . . . . . . . . . . .55  
8.2 Si5332A/B/C/D 40-QFN Land Pattern . . . . . . . . . . . . . . . . . . . . . .57  
8.3 Si5332A/B/C/D 32-QFN Land Pattern . . . . . . . . . . . . . . . . . . . . . .59  
8.4 Si5332E/F/G/H 48-LGA Land Pattern . . . . . . . . . . . . . . . . . . . . . .61  
8.5 Si5332E/F/G/H 40-LGA Land Pattern . . . . . . . . . . . . . . . . . . . . . .63  
8.6 Si5332E/F/G/H 32-LGA Land Pattern . . . . . . . . . . . . . . . . . . . . . .65  
9. Top Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67  
10. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
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Si5332 Data Sheet  
Features List  
1. Features List  
• Any-Frequency 6/8/12-output programmable clock generators  
• Embedded crystal option on 8-output and 12-output devices.  
• Offered in three different package sizes, supporting different  
combinations of output clocks and user configurable hardware  
input pins  
• User-configurable clock output signal format per output: LVDS,  
LVPECL, HCSL, LVCMOS  
• Low phase jitter: 230 fs rms  
• 32-pin QFN, up to 6 outputs  
• 40-pin QFN, up to 8 outputs  
• 48-pin QFN, up to 12 outputs  
• PCIe Gen1/2/3/4, SRIS compliant  
• 1.8 V, 2.5 V, 3.3 V core VDD  
• Adjustable output-output delay  
MultiSynthtechnology enables any-frequency synthesis on  
any output up to 250 MHz  
• Independent glitchless on-the-fly output frequency changes  
• Very low power consumption  
• Embedded 50 MHz crystal option  
• Highly configurable output path featuring a cross point mux  
• Up to three independent fractional synthesis output paths  
• Up to five independent integer dividers  
• Ordering options for embedded 50 MHz reference crystal  
• Input frequency range:  
• Independent output supply pins for each bank of outputs:  
• 1.8 V, 2.5 V, or 3.3 V differential  
• 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS  
• Programmable spread spectrum  
• Down and center spread from –0.1% –2.5% in 0.01% steps  
at 30 to 33 kHz  
• External crystal: 16 to 50 MHz  
• Integrated power supply filtering  
Serial interface: I2C  
• Differential clock: 10 to 250 MHz  
• LVCMOS clock: 10 to 170 MHz  
• ClockBuilder Pro software utility simplifies device configuration  
and assigns custom part numbers  
• Output frequency range:  
• Differential: 5 to 312.5 MHz  
• Temperature range: –40 to +85 °C  
• RoHS-6 compliant  
• LVCMOS: 5 to 170 MHz  
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Si5332 Data Sheet  
Ordering Guide  
2. Ordering Guide  
Blank devices, in-system programmable  
Si5332X - C - GMpR  
Operating Temp Range: -40 to +85 C  
GM = QFN, ROHS6 compliant  
p = 1 for 6-output, 32-pin QFN  
2 for 8-output, 40-pin QFN  
3 for 12-output, 48-pin QFN  
R = Tape & Reel (ordering option)  
C = Product Revision  
Ordering Part Frequency Synthesis Mode Input Type  
Output Clock  
Operating  
Number  
Si5332A  
Si5332B  
Si5332C  
Si5332D  
Si5332E  
Si5332F  
Si5332G  
Si5332H  
Frequency Range  
Integer and Fractional mode External crystal 5MHz - 312.5MHz  
Temperature Range  
Integer and Fractional mode  
Integer mode only  
Integer mode only  
Integer and Fractional mode  
Integer and Fractional mode  
Integer mode only  
or Clock  
5MHz - 200MHz  
5MHz - 312.5MHz  
5MHz - 200MHz  
-40 to +85C  
Embedded 5MHz - 312.5MHz  
crystal or 5MHz - 200MHz  
External Clock 5MHz - 312.5MHz  
5MHz - 200MHz  
Integer mode only  
Pre-programmed devices using a ClockBuilder Pro configuration file  
Si5332X CXXXXX - GMpR  
Operating Temp Range: -40 to +85 C  
GM = QFN, ROHS6 compliant  
P = 1 for 6-output, 32-pin QFN  
2 for 8-output, 40-pin QFN  
3 for 12-output, 48-pin QFN  
R = Tape & Reel (ordering option)  
C = Product Revision  
XXXXX = NVM code. Aa unique 5-digit ordering sequence  
will be assigned by ClockBuilder Pro  
Ordering Part Frequency Synthesis Mode  
Number  
Input Type  
Output Clock  
Frequency Range  
Operating  
Temperature Range  
Si5332A  
Si5332B  
Si5332C  
Si5332D  
Si5332E  
Si5332F  
Si5332G  
Si5332H  
Integer and Fractional mode External crystal 5MHz - 312.5MHz  
Integer and Fractional mode  
Integer mode only  
Integer mode only  
or Clock  
5MHz - 200MHz  
5MHz - 312.5MHz  
5MHz - 200MHz  
-40 to +85C  
Integer and Fractional mode  
Integer and Fractional mode  
Integer mode only  
Embedded 5MHz - 312.5MHz  
crystal or 5MHz - 200MHz  
External Clock 5MHz - 312.5MHz  
5MHz - 200MHz  
Integer mode only  
Figure 2.1. Orderable Part Number Guide  
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Si5332 Data Sheet  
Functional Description  
3. Functional Description  
The Si5332 is a high-performance, low-jitter clock generator capable of synthesizing up to twelve user-programmable clock frequencies  
up to 312.5 MHz. The device supports free run operation using an external or embedded crystal, or it can lock to an external clock  
signal. The output drivers support up to twelve differential clocks or twenty four LVCMOS clocks, or a combination of both. The output  
drivers are configurable to support common signal formats, such as LVPECL, LVDS, HCSL, and LVCMOS. VDDO pins are provided for  
versatility, which can be set to 3.3 V, 2.5 V, 1.8 V or 1.5 V (CMOS only) to power the multi-format output drivers. The core voltage  
supply (VDD) accepts 3.3 V, 2.5 V, or 1.8 V and is independent from the output supplies (VDDOxs). Using its two-stage synthesis archi-  
tecture and patented high-resolution low-jitter MultiSynth technology, the Si5332 can generate an entire clock tree from a single device.  
The Si5332 combines a wideband PLL with next generation MultiSynth technology to offer the industry’s highest output count high per-  
formance programmable clock generator, while maintaining a jitter performance of 230 fs RMS. The PLL locks to either an external  
16-50 MHz crystal or an embedded 50 MHz crystal for generating for generating free-running clocks or to an external clock (CLKIN_2/  
CLKIN_2# or CLKIN_3/CLKIN_3#) for generating synchronous clocks. In free-run mode, the oscillator frequency is multiplied by the  
PLL and then divided down either by an integer divider or MultiSynth for fractional synthesis.  
The Si5332 features user-defined universal hardware input pins which can be configured in the ClockBuilder Pro software utility. Uni-  
versal hardware pins can be used for OE, spread spectrum enable, input clock selection, output frequency selection, or I2C address  
select. If additional hardware input pins are needed, a user can define a different clock output as universal hardware input pins instead  
using ClockBuilder Pro.  
The device provides the option of storing a user-defined clock configuration in its non-volatile memory (NVM), which becomes the de-  
fault clock configuration at power-up. To enable in-system programming, a power up mode is available through OTP which powers up  
the chip in an OTP defined default mode but with no outputs enabled. This allows a host processor to first write a user defined subset of  
the registers and then restart the power-up sequence to activate the newly programmed configuration without re-downloading the OTP.  
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Si5332 Data Sheet  
Functional Description  
3.1 Functional Block Diagrams  
Si5332: 12-Output, 48-QFN  
VDDO0  
OUT0  
÷INT  
OUT0b  
Bank A  
÷INT  
VDDO1  
CLKIN_2  
CLKIN_2b  
OUT1  
OUT1b  
Multi  
Synth  
CLKIN_3  
CLKIN_3b  
÷INT  
PLL  
OUT2  
OUT2b  
÷INT  
Multi  
Synth  
OSC  
XTAL  
Bank B  
÷INT  
VDDO2  
Si5332A/B/C/D: External Crystal  
Si5332E/F/G/H: Internal Crystal  
INT  
INT  
INT  
INT  
INT  
OUT3  
OUT3b  
NVM  
OUT4  
OUT4b  
÷INT  
÷INT  
SCLK  
I2C  
SDATA  
OUT5  
OUT5b  
Input1  
Input2  
Input3  
Bank C  
÷INT  
VDDO3  
OUT6  
OUT6b  
HW Input  
Control  
Input4  
Input5  
Input6  
Input7  
OUT7  
OUT7b  
÷INT  
÷INT  
OUT8  
OUT8b  
VDDO4  
OUT9  
OUT9b  
÷INT  
Bank D  
÷INT  
VDDO5  
OUT10  
OUT10b  
OUT11  
OUT11b  
÷INT  
Figure 3.1. Block Diagram for 12-Output Si5332 in 48-QFN  
The Si5332 48-QFN features:  
• Up to twelve differential clock outputs, with six VDDO pins.  
• Seven user-configurable HW input pins, defined using ClockBuilder Pro.  
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Si5332 Data Sheet  
Functional Description  
Si5332: 8-Output, 40-QFN  
VDDO0  
OUT0  
÷INT  
OUT0b  
VDDO1  
CLKIN_2  
CLKIN_2b  
OUT1  
OUT1b  
÷INT  
Multi  
Synth  
CLKIN_3  
CLKIN_3b  
÷INT  
PLL  
Bank A  
÷INT  
Multi  
Synth  
VDDO2  
OSC  
XTAL  
OUT2  
OUT2b  
Si5332A/B/C/D: External Crystal  
Si5332E/F/G/H: Internal Crystal  
INT  
INT  
INT  
INT  
INT  
OUT3  
OUT3b  
÷INT  
NVM  
I2C  
SCLK  
Bank B  
÷INT  
SDATA  
VDDO3  
OUT4  
OUT4b  
Input1  
Input2  
Input3  
OUT5  
OUT5b  
÷INT  
HW Input  
Control  
Input4  
Input5  
Input6  
Input7  
VDDO4  
OUT6  
OUT6b  
÷INT  
÷INT  
VDDO5  
OUT7  
OUT7b  
Figure 3.2. Block Diagram for 8-Output Si5332 in 40-QFN  
The Si5332 40-QFN features:  
• Up to eight differential clock outputs, with six VDDO pins.  
• Seven user-configurable HW input pins, defined using ClockBuilder Pro.  
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Si5332 Data Sheet  
Functional Description  
Si5332: 6-Output, 32-QFN  
VDDO0  
OUT0  
÷INT  
OUT0b  
VDDO1  
CLKIN_2  
OUT1  
OUT1b  
CLKIN_2b  
÷INT  
÷INT  
Multi  
Synth  
÷INT  
PLL  
VDDO2  
Multi  
Synth  
OUT2  
OUT2b  
OSC  
XTAL  
Si5332A/B/C/D: External Crystal  
Si5332E/F/G/H: Internal Crystal  
INT  
INT  
INT  
INT  
INT  
VDDO3  
NVM  
I2C  
OUT3  
OUT3b  
÷INT  
÷INT  
SCLK  
SDATA  
VDDO4  
Input1  
Input2  
Input3  
Input4  
OUT4  
OUT4b  
HW Input  
Control  
VDDO5  
Input5  
÷INT  
OUT5b  
OUT5  
Figure 3.3. Block Diagram for 6-Output Si5332 in 32-QFN  
The Si5332 32-QFN features:  
• Up to six differential clock outputs with individual VDDO.  
• Five user-configurable HW input pins, defined using ClockBuilder Pro.  
3.2 Modes of Operation  
The Si5332 supports both free-run and synchronous modes of operation. The default mode selection is set in ClockBuilder Pro. Alterna-  
tively, a universal hardware input pin can be defined as CLKIN_SEL to select between a crystal or clock input. There is also the option  
to select the input source via the serial interface by writing to the input select register.  
3.2.1 Initialization  
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from  
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-  
tion period is complete. The clock outputs will be squelched until the device initialization is done.  
3.3 Frequency Configuration  
The phase-locked loop is fully integrated and does not require external loop filter components. Its function is to phase lock to the selec-  
ted input and provide a common synchronous reference to the high-performance MultiSynth fractional or integer dividers.  
A cross point mux connects any of the MultiSynth divided frequencies or INT divided frequencies to individual output drivers or banks of  
output drivers. Additional output integer dividers provide further frequency division by an even integer from 1 to 63. The frequency con-  
figuration of the device is programmed by setting the input dividers (P), the PLL feedback fractional divider (Mn/Md), the MultiSynth  
fractional dividers (Nn/Nd), and the output integer dividers (R). Silicon Labs’ Clockbuilder Pro configuration utility determines the opti-  
mum divider values for any desired input and output frequency plan  
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Si5332 Data Sheet  
Functional Description  
3.4 Inputs  
The Si5332 requires an external 16–30 MHz crystal at its XIN/XOUT pins or the embedded 50 MHz crystal to operate in free-run mode,  
or an external input clock (CLKIN_2/CLKIN_2# or CLKIN_3/CLKIN_3#) for synchronous operation. An external crystal is not required in  
synchronous mode.  
3.4.1 External Reference Input (XA/XB)  
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) on Si5332A/B/C/D to produce a low jitter reference  
for the PLL when operating in the free-run mode. Frequency offsets due to CL mismatch can be adjusted using the frequency adjust-  
ment feature which allows frequency adjustments of ±1000 ppm. The Si5332 Reference Manual provides additional information on PCB  
layout recommendations for the crystal to ensure optimum jitter performance. Refer to Table 5.4 External Crystal Input Specification on  
page 24 for crystal specifications.  
For free-running operation, the internal oscillator can operate from a low-frequency fundamental mode crystal (XTAL) with a resonant  
frequency of 16 to 50 MHz. A crystal can easily be connected to pins XA and XB without external components, as shown in the figure  
below. A register bit will allow the device to use an internal loading capacitor (CL) with a typical value of 12 pF or bypass the internal CL  
and use external CL. Alternatively, an external CL can be used along with the internal CL.  
XA  
To synthesis stage  
or output selectors  
Osc  
XTAL  
XB  
Figure 3.4. External Reference Input (XA/XB)  
The Si5332E/F/G/H options feature an embedded 50 MHz reference crystal that is used in the free run mode.  
3.4.2 Input Clocks  
An input clock is available to synchronize the PLL when operating in synchronous mode. This input can be configured as LVPECL,  
LVDS or HCSL differential, or LVCMOS. The recommended input termination schemes are shown in the Si5332 Family Reference  
Manual. Differential signals must be AC coupled. The single-ended LVCMOS input is internally AC coupled, and only needs to meet a  
minimum voltage swing that may not exceed a maximum VIH or minimum VIL. Unused inputs can be disabled by register configuration.  
3.4.3 Input Selection  
The active clock input is selected by register control, or by defining a universal hardware input pin as CLKIN_SEL in ClockBuilder Pro.  
A register bit determines input selection as pin or register selectable. If a universal input pin is defined as CLKIN_SEL, that pin is selec-  
ted by default and is internally pulled high so that the free-run mode is automatically selected when left unconnected. If there is no clock  
signal on the selected input, the device will not generate output clocks.  
In a typical application, the Si5332 reference input is configured immediately after power-up and initialization. If the device is switched  
to another input more than ±1000 ppm offset from the initial input, the device must be recalibrated manually to the new frequency, tem-  
porarily turning off the clock outputs. After the VCO is recalibrated, the device will resume producing clock outputs. If the selected inputs  
are within ±1000 ppm, any phase error difference will propagate through the device at a rate determined by the PLL bandwidth. Hitless  
switching and phase build-out are not supported by the Si5332.  
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Si5332 Data Sheet  
Functional Description  
3.5 Outputs  
The Si5332 supports up to 12 differential output drivers. Each output can be independently configured as a differential pair or as dual  
LVCMOS outputs. The 8-output and 12-output devices feature banks of outputs, with each bank sharing a common VDDO.  
Table 3.1. Clock Outputs  
Package  
32-QFN  
40-QFN  
48-QFN  
Maximum Outputs  
6 Differential, 12 LVCMOS  
8 Differential, 16 LVCMOS  
12 Differential, 24 LVCMOS  
The output stage is different for each of the three versions of Si5332.  
• The 6-output device features individual VDDO pins for each clock output. Each clock output can be sourced from MultiSynth0, Multi-  
Synth1, the input reference clock, or one of the five INT dividers through the cross point MUX.  
• The 8-output device includes four clock outputs with dedicated VDDO pins, each of which can be sourced from MultiSynth0, Multi-  
Synth1, the input reference clock, or one of the five INT dividers through the cross point MUX. The remaining four clock outputs are  
divided into Bank A and Bank B. Each Bank of outputs can be sourced from MultiSynth0, MultiSynth1, the input reference clock, or  
one of the five INT dividers through the cross point MUX. The outputs in each of the two Banks share a common VDDO pin.  
• The 12-output device includes two clock outputs with dedicated VDDO pins, each of which can be sourced from MultiSynth0, Multi-  
Synth1, the input reference clock, or one of the five INT dividers through the cross point MUX. The remaining ten clock outputs are  
divided into Bank A, Bank B, Bank C, and Bank D. Each Bank of outputs can be sourced from MultiSynth0, MultiSynth1, the input  
reference clock, or one of the five INT dividers through the cross point MUX. The outputs in each of the four Banks share a common  
VDDO pin.  
Utilizing the reference clock enables a fan-out buffer function from an input clock source to any bank of outputs.  
Individual output Integer output dividers (R) allow the generation of additional synchronous frequencies. These integer dividers are con-  
figurable as divide by 1 (default) through 63.  
3.5.1 Output Signal Format  
The differential output swing and common mode voltage are both fully programmable and compatible with a wide variety of signal for-  
mats including HCSL, LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as  
LVCMOS drivers, enabling the device to support both differential and single-ended clock outputs. Output formats can be defined in  
ClockBuilder Pro or via the serial interface.  
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Rev. 1.0 | 11  
Si5332 Data Sheet  
Functional Description  
3.5.2 Differential Output Terminations  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 Ω and 132 Ω. The actual  
value should be selected to match the differential impedance (Z0) of the transmission line. A typical point-to-point LVDS design uses a  
100 Ω parallel resistor at the receiver and a 100 Ω differential transmission-line environment. In order to avoid any transmission-line  
reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. The standard  
LVDS termination schematic as shown in Figure 3.5 Standard LVDS Termination on page 12 can be used with either type of output  
structure. Figure 3.6 Optional LVDS Termination on page 12, which can also be used with both output types, is an optional termina-  
tion with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50 pF. If using a non-  
standard termination, please contact Silicon Labs to confirm if the output structure is current source or voltage source type. In addition,  
since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compati-  
bility with the output.  
Zo = ZT/2  
+
LVDS  
Driver  
LVDS  
Receiver  
ZT  
Zo = ZT/2  
-
Figure 3.5. Standard LVDS Termination  
Zo = ZT/2  
+
-
ZT/2  
ZT/2  
LVDS  
Driver  
LVDS  
Receiver  
C
Zo = ZT/2  
Figure 3.6. Optional LVDS Termination  
Termination for 3.3 V LVPECL Outputs  
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recom-  
mended only as guidelines. The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC  
current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 Ω transmission lines.  
Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 3.7 3.3 V  
LVPECL Output Termination, Option 1 on page 13 and Figure 3.8 3.3 V LVPECL Output Termination, Option 2 on page 13 show  
two different layouts. Other suitable clock layouts may exist, and it would be recommended that the board designers simulate to guar-  
antee compatibility across all printed circuit and clock component process variations.  
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Rev. 1.0 | 12  
Si5332 Data Sheet  
Functional Description  
3.3V  
3.3V  
Zo=50Ω  
Zo=50Ω  
+
-
Input  
LVPECL  
R1  
50Ω  
R2  
50Ω  
RTT = 54Ω  
RTT  
Vcc-2V  
Figure 3.7. 3.3 V LVPECL Output Termination, Option 1  
3.3V  
R3  
125Ω  
R4  
125Ω  
3.3V  
3.3V  
Zo=50Ω  
+
-
Zo=50Ω  
Input  
LVPECL  
R1  
84Ω  
R2  
84Ω  
Figure 3.8. 3.3 V LVPECL Output Termination, Option 2  
Termination for 2.5 V LVPECL Outputs  
Figure 3.9 2.5 V LVPECL Termination Example, Option 1 on page 14 and Figure 3.10 2.5 V LVPECL Termination Example, Option 2  
on page 14 show examples of termination for the 2.5 V LVPECL driver option. These terminations are equivalent to terminating 50 Ω  
to VDDO – 2 V. For VDDO = 2.5 V, the VDDO – 2 V is very close to ground level. The R3 in Figure 3.10 2.5 V LVPECL Termination  
Example, Option 2 on page 14 can be optionally eliminated using the termination shown in Figure 3.9 2.5 V LVPECL Termination  
Example, Option 1 on page 14.  
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Rev. 1.0 | 13  
Si5332 Data Sheet  
Functional Description  
2.5V  
R3  
250 ohm  
R4  
250 ohm  
2.5V  
2.5V  
Zo=50 ohm  
+
-
Zo=50 ohm  
Input  
2.5V LVPECL  
Driver  
R1  
62.5 ohm  
R2  
62.5 ohm  
RTT = 29.5 ohm  
Figure 3.9. 2.5 V LVPECL Termination Example, Option 1  
2.5V  
2.5V  
Zo=50 ohm  
Zo=50 ohm  
+
-
Input  
2.5V LVPECL  
Driver  
R1  
50ohm  
R2  
50ohm  
R3  
18ohm  
Figure 3.10. 2.5 V LVPECL Termination Example, Option 2  
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Rev. 1.0 | 14  
Si5332 Data Sheet  
Functional Description  
Termination for HCSL Outputs  
The Si5332 HCSL driver option integrated termination resistors to simplify interfacing to an HCSL receiver. The HCSL driver supports  
both 100 Ω and 85 Ω transmission line options. This configuration option may be specified using ClockBuilder Pro or via the device I2C  
interface.  
1.425V to 3.63V  
Zo=42.5Ω  
or 50Ω  
OUTx  
HCSL  
HCSL  
driver  
Zo=42.5Ω  
or 50Ω  
receiver  
OUTx  
Figure 3.11. HCSL Internal Termination Mode  
1.425V to 3.63V  
Zo=42.5Ω  
or 50Ω  
OUTx  
RT = Zo  
RT = Zo  
HCSL  
receiver  
Zo=42.5Ω  
or 50Ω  
OUTx  
Figure 3.12. HCSL External Termination Mode  
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Rev. 1.0 | 15  
Si5332 Data Sheet  
Functional Description  
3.5.3 LVCMOS Output Terminations  
LVCMOS outputs are dc-coupled, as shown in the figure below.  
1.71 to 6.36V  
Zo=50Ω  
Zo=50Ω  
OUTx  
Set output driver  
to 50Ω mode.  
OUTxb  
Figure 3.13. LVCMOS Output Termination Example, Option 1  
1.425 to 3.63V  
OUTx  
Rs  
Set output driver  
to 25Ω mode.  
OUTxb  
Rs  
Rs = Zo – Rdrv  
(see Table 5.8)  
Figure 3.14. LVCMOS Output Termination Example, Option 2  
3.5.4 LVCMOS Output Signal Swing  
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pin for the respective bank.  
3.5.5 LVCMOS Output Polarity  
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default, the clock on  
the OUTxb pin is generated in phase with the clock on the OUTx pin. The polarity of these clocks is configurable enabling complimenta-  
ry clock generation and/or inverted polarity with respect to other output drivers.  
3.5.6 LVCMOS Output Configurable Tr/Tf  
The Si5332 has four settings to choose from for LVCMOS outputs up to 66 MHz at 50 Ω internal impedance drive a 5”, 50 Ω trace. This  
can be configured using the ClockBuilder Pro software utility, or through the I2C programming interface. Output frequencies greater  
than 66 MHz must use the fastest setting.  
3.5.7 Output Enable/Disable  
The universal hardware input pins can be programmed with either active low or active high polarity, to operate as output enable (OEb),  
controlling one or more outputs. Pin assignment is done using ClockBuilder Pro. An output enable pin provides a convenient method of  
disabling or enabling the output drivers. When the output enable pin is held high all designated outputs will be disabled. When held low,  
the designated outputs will be enabled. Outputs in the enabled state can be individually disabled through register control.  
3.5.8 Differential Output Configurable Skew Settings  
Skew on the differential outputs can be independently configured. The skew is adjustable in 35 ps steps across a range of 280 ps.  
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Si5332 Data Sheet  
Functional Description  
3.5.9 Output Driver State When Disabled  
The disabled state of an output driver is configurable as: disable low, disable high, or disable high-impedance.  
3.5.10 Synchronous Output Disable Feature  
Output clocks are always enabled and disabled synchronously. The output will wait until a clock period has completed before the driver  
is disabled. This prevents unwanted runt pulses from occurring when disabling an output.  
3.6 Spread Spectrum  
To help reduce electromagnetic interference (EMI), the Si5332 supports spread spectrum modulation. The output clock frequencies can  
be modulated to spread energy across a broader range of frequencies, lowering system EMI. The Si5332 implements spread spectrum  
using its patented MultiSynth technology to achieve previously unattainable precision in both modulation rate and spreading magnitude.  
Spread spectrum can be enabled through I2C, or by configuring one of the universal hardware input pins using ClockBuilder Pro.  
The Si5332 features both center and down spread spectrum modulation capability, from 0.1% to 2.5%. Each MultiSynth is capable of  
generating an independent spread spectrum clock. The feature is enabled using a user-defined universal hardware input pin or via the  
device I2C interface. Spread spectrum can be applied to any output clock, with any clock frequency up to 250 MHz. Since the spread  
spectrum clock generation is performed in the MultiSynth fractional dividers, the spread spectrum waveform is highly consistent across  
process, voltage and temperature. The Si5332 features two independent MultiSynth dividers, enabling the device to provide two inde-  
pendent spread profiles simultaneously to the clock output banks.  
Spread spectrum is commonly used for 100 MHz PCI Express clock outputs. To comply with the spread spectrum specifications for PCI  
Express, the spreading frequency should be set to a maximum of 33 kHz and –0.5% down spread. A universal hardware input pin can  
be configured to toggle spread spectrum on/off.  
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Rev. 1.0 | 17  
Si5332 Data Sheet  
Functional Description  
3.7 Universal Hardware Input Pins  
Universal hardware input pins are user configurable control input pins that can have one or more of the functions listed below assigned  
to them using ClockBuilder Pro.  
If more hardware input pins are needed, the differential input pins can be alternatively configured as two universal hardware input pins.  
Contact Silicon Labs for further details. Universal hardware input pins can be utilized for the following functions:  
Table 3.2. Universal Hardware Input Pins  
Description  
Spread_EN0  
Spread_EN1  
FS_INTx  
Function  
Spread spectrum enable on MultiSynth0 (N0).  
Spread spectrum enable on MultiSynth0 (N1).  
Used to switch an integer output divider frequency from frequency A to frequency B.  
FS_MSx  
Used to switch a MultiSynth output divider output from frequency and/or change spread  
spectrum profile.  
OE  
Output enable for one or more outputs.  
Sets the LSB of the I2C address to either 0 or 1.  
Selects between crystal or clock inputs.  
I2C address select  
CLKIN_SEL[1:0]  
MultiSynth Spread Enable Pins  
Spread_EN[1:0] pins are active pins that enable/disable spread spectrum on all outputs that correspond to MutliSynth0 or MultiSynth1,  
respectively. The change in frequency or spread spectrum will be instantaneous and may not be glitch free.  
Table 3.3. SPREAD_EN Pin Selection Table  
Spread_ENx  
0
1
Spread Spectrum disabled on MultiSynthx  
Spread Spectrum enabled on MultiSynthx  
Output Frequency Select Pins  
There are five integer dividers, one corresponding to each of the five output banks. Using ClockBuilder Pro, a universal hardware input  
pin can be assigned for each integer divider, providing capability to select between two different pre-programmed divide values. Divider  
values of every integer from 8 to 255 are available in ClockBuilder Pro for each integer divider.  
Table 3.4. FS_INT Pin Selection Table  
FS_INTx  
Output Frequency from INTx  
0
1
Frequency A, as defined in ClockBuilder Pro  
Frequency B, as defined in ClockBuilder Pro  
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Rev. 1.0 | 18  
Si5332 Data Sheet  
Functional Description  
Output Enable  
A universal hardware input pin can be defined to control output enable of a differential output, a bank of differential outputs, or as a  
global output enable pin controlling all outputs. Upon de-assertion of an OE pin, the corresponding output will be disabled within 2-6  
clock cycles. Asserting an OE pin from disable to enable will take <20 µs for the output to have a clean clock. OE pins have program-  
mable 100 kΩ pull-up/pull-down or no pull resistors setting  
The disable state is programmable as 0, 1, Hi-Z, or free running. See the Si5332 Family Reference Manual for details.  
Output enabled/disabled for LVCMOS are done in pairs. Each differential buffer True and Compliment output can generate an  
LVCMOS clock and the OE pin associated with the True and Compliment output buffer will control the respective LVCMOS pair.  
For example: If DIFF0 is configured to be SE1 and DIFF0# is configured to be SE2 and OE1 is the associated OE pin, de-asserting the  
OE1 pin will disable both SE1 and SE2 outputs. The disable and enable of the outputs to a known state is glitch free.  
I2C Address Pin  
This pin sets the LSB of the I2C address. For example, if the I2C address is A6h, setting this pin high will set the I2C address to A7h.  
CLKIN_SEL[0:1] Pins  
These pins are used to set the input source clock between the input clock channels (Crystal, CLKIN_2/CLKIN_2# or CLKIN_3/  
CLKIN_3#). Upon switching the input clock source, the output will not be glitch free. It is intended for the user to set this pin to a known  
state before the system is powered up or have the receiver address any unintended output signals when switching to a different input  
source clock. This pin has an internal 50 kΩ internal pull-up or pull-down at all times.  
3.8 Custom Factory Pre-programmed Parts  
Custom pre-programmed parts can be ordered corresponding to a specific configuration file generated using the ClockBuilder Pro soft-  
ware utility. Silicon Labs writes the configuration file into the device prior to shipping. Use the ClockBuilder Pro custom part number  
wizard (http://www.silabs.com/clockbuilderpro) to quickly and easily generate a custom part number for your ClockBuilder Pro configu-  
ration file. A factory pre-programmed part will generate clocks at power-up.  
In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your  
design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local  
Silicon Labs sales representative. Samples of your pre-programmed device will ship within two weeks.  
3.9 I2C Serial Interface  
The Si5332 is fully compliant to rev6 of the I2C specification, including Standard, Fast, and Fast+ modes.  
Configuration and operation of the Si5332 can be controlled by reading and writing registers using the I2C . Communication with a 1.8 V  
to 3.3 V host is supported. See the Si5332 Family Reference Manual for details.  
3.10 In-Circuit Programming  
The Si5332 is fully configurable using the I2C serial interface. At power-up the device downloads its default register values from internal  
non-volatile memory (NVM). Refer to the Si5332 Family Reference Manual for a detailed procedure for writing registers to volatile mem-  
ory.  
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Rev. 1.0 | 19  
Si5332 Data Sheet  
Register Map  
4. Register Map  
Refer to the Si5332 Family Reference Manual for a complete list of registers descriptions and settings.  
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Rev. 1.0 | 20  
Si5332 Data Sheet  
Electrical Specifications  
5. Electrical Specifications  
Table 5.1. Recommended Operating Conditions  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Ambient Temperature  
Junction Temperature  
Core Supply Voltage  
Symbol  
TA  
Test Condition  
Min  
–40  
Typ  
25  
Max  
85  
Units  
°C  
TJMAX  
125  
3.63  
°C  
VDDA, VDD_DIG  
VDD_xtal  
,
1.71  
V
Output Driver Supply Voltage  
VDDO  
1.425  
3.63  
V
Note:  
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-  
ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.  
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Rev. 1.0 | 21  
Si5332 Data Sheet  
Electrical Specifications  
Table 5.2. DC Characteristics  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Symbol  
IDD  
Test Condition  
Min  
Typ  
45  
Max  
70  
Units  
mA  
Core Supply Current  
LVPECL Output4 @ 156.25 MHz  
HCSL Output4 @ 100 MHz  
Output Buffer Supply Cur-  
rent  
IDDOx  
33  
35  
mA  
20  
11  
16  
22  
13  
19  
mA  
mA  
mA  
LVDS Output4 @ 156.25 MHz  
3.3 V VDDO  
LVCMOS5 output @ 170 MHz  
2.5 V VDDO  
9
11  
mA  
mA  
LVCMOS5 output @ 170 MHz  
1.8 VDDO  
LVCMOS5 output @ 170 MHz  
7.5  
8.5  
Total Power Dissipation  
Pd  
48-pin  
40-pin  
32-pin  
Notes 1, 6  
Note 2, 6  
Notes 3, 6  
590  
320  
270  
mW  
mW  
mW  
Notes:  
1. Si5332 48-pin test configuration: VDDD = VDDA = VDDI = 1.8 V, 3 × 2.5 V LVDS outputs enabled @156.25 MHz, 4x 1.8V HCSL  
outputs enabled @ 100 MHz, 3x 2.5 V LVPECL outputs enabled @ 125 MHz, 2x 3.3 V LVCMOS outputs enabled @ 25 MHz.  
Excludes power in termination resistors.  
2. Si5332 40-pin test configuration: VDDD = VDDA = VDDI = 1.8 V, 4 × 2.5 V LVDS outputs enabled @ 156.25 MHz, 2 × 1.8 V HCSL  
outputs enabled @ 100 MHz, 2x 3.3 V LVCMOS outputs enabled @ 25 MHz. . Excludes power in termination resistors.  
3. Si5332 32-pin test configuration: VDDD = VDDA = VDDI = 1.8 V, 2 × 2.5 V LVDS outputs enabled @ 156.25 MHz, 2 × 1.8 V HCSL  
outputs enabled @ 100 MHz. 2x 3.3 V LVCMOS outputs enabled @ 25 MHz. Excludes power in termination resistors.  
4. Differential outputs terminated into a 100 Ω load.  
5. LVCMOS outputs measured into a 5 inch 50 Ω PCB trace with 4 pF load.  
Differential Output Test Configuration  
LVCMOS Output Test Configuration  
5 inch  
IDDO  
IDDO  
50  
50  
5 inch  
50  
OUT  
OUT  
100  
OUTa  
OUTb  
4 pF  
6. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not  
available. All EVBs support detailed current measurements for any configuration.  
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Rev. 1.0 | 22  
Si5332 Data Sheet  
Electrical Specifications  
Table 5.3. Clock Input Specifications  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Input Clock (AC-coupled Differential Input Clock on CLKIN_2/CLKIN_2# or CLKIN_3/CLKIN_3#)  
Frequency  
FIN  
Differential  
10  
250  
1.8  
MHz  
Voltage Swing  
VPP  
Differential AC-coupled  
< 312.5 MHz  
0.5  
VPP_diff  
Slew Rate  
SR/SF  
DC  
20-80%  
0.75  
40  
10  
2
60  
6
V/ns  
%
Duty Cycle  
Input Impedance  
Input Capacitance  
RIN  
kΩ  
pF  
CIN  
3.5  
Input Clock (DC-coupled LVCMOS Input Clock on CLKIN_2 or CLKIN_3)  
Frequency  
FIN  
VIH  
10  
0.8 × VDD  
170  
MHz  
V
Input High Voltage  
Input Low Voltage  
VIL  
0.2 × VDD  
V
Slew Rate1,2  
Duty Cycle  
SR/SF  
20-80%  
0.75  
V/ns  
DC  
CIN  
40  
2
60  
6
%
Input Capacitance  
3.5  
pF  
Input Clock (DC-coupled LVCMOS Input Clock on CLKIN_1)  
Frequency  
FIN  
10  
170  
MHz  
V
Voltage Swing  
Input Low Voltage  
1
0.2 x VDD  
VIL  
V
Slew Rate1, 2  
Duty Cycle  
SR/SF  
20-80%  
0.75  
V/ns  
DC  
CIN  
40  
2
60  
6
%
Input Capacitance  
3.5  
pF  
Notes:  
1. Imposed for jitter performance.  
2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) * VIN_Vpp_se) / SR.  
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Rev. 1.0 | 23  
Si5332 Data Sheet  
Electrical Specifications  
Table 5.4. External Crystal Input Specification  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Symbol  
Fxtal  
Test Condition  
Min  
Typ  
16-50  
12  
Max  
Units  
MHz  
pF  
Crystal Frequency  
Load Capacitance  
CL  
16 - 30 MHz  
31 - 50 MHz  
16 - 30 MHz  
31 - 50 MHz  
16 - 30 MHz  
31 - 50 MHz  
6
18  
10  
7
pF  
Shunt Capacitance  
ESR  
CO  
CL  
2.5  
pF  
2
pF  
50  
50  
24  
Max Crystal Drive Level  
Input Capacitance 1  
dL  
250  
µW  
pF  
CIN  
Internal cap disabled  
Internal cap enabled  
(per pad)  
12  
pF  
Input Voltage  
VXIN  
-0.3  
1.3  
V
Notes:  
1. Internal capacitance on the xtal input pads is programmable or can be disabled. Please reference section 5.3.1 for more detailed  
information.  
Table 5.5. Embedded Crystal Specifications  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Initial Accuracy  
Total Stability  
fi  
Measured at +25 °C at  
time of shipping  
±20  
ppm  
–50  
–30  
50  
30  
ppm  
ppm  
Temperature Stability  
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Rev. 1.0 | 24  
Si5332 Data Sheet  
Electrical Specifications  
Table 5.6. Control Pins  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Si5332 Control Input Pins (Inputx)  
Input Voltage  
VIL  
VIH  
-0.1  
0.3 × VDDOX  
1.1 × VDD  
V
V
1
0.7 × VDDOX  
Input Capacitance  
Pull-up/down Resistance  
Note:  
CIN  
RIN  
4
pF  
kΩ  
50  
1. In the 48-QFN package, all universal input pins are powered by VDD_DIG.  
2. In the 40-QFN package, universal Input4, Input5, Input6, and Input7 on pins 21, 22, 29, 30 are powered by VDDOB. All other  
universal Inputx pins are powered by VDD_DIG.  
3. In the 32-pin package, universal Input2 and Input3 on pins 23, 24 are powered by VDDOB. All other universal Inputx pins are  
powered by VDD_DIG.  
4. If an output pair is instead defined as universal input pins in ClockBuilder Pro, those pins will be powered by the corresponding  
VDDOx of that corresponding bank.  
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Rev. 1.0 | 25  
Si5332 Data Sheet  
Electrical Specifications  
Table 5.7. Differential Clock Output Specifications  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Symbol  
Test Condition  
Min  
5
Typ  
Max  
312.5  
250  
Units  
MHz  
MHz  
%
Output Frequency  
fOUT  
Integer synthesis mode  
Fractional synthesis mode  
5
Duty Cycle  
DC  
48  
52  
Output-Output Skew  
TSK  
Within the same bank  
Across banks  
30  
ps  
80  
ps  
Output Voltage Swing  
Common Mode Voltage  
VSEPP  
LVPECL  
0.6  
0.3  
0.7  
0.75  
0.375  
0.8  
VDDO-1.4  
1.2  
0.8  
0.4  
0.85  
0.45  
0.9  
VPP  
VPP  
VPP  
V
LVDS  
HCSL  
1.8/2.5/3.3 V  
VCM  
LVPECL  
LVDS  
2.5/3.3 V  
1.8 V  
1.125  
0.75  
0.35  
1
1.275  
0.85  
0.45  
4.5  
V
LVDS  
V
HCSL  
V
HCSL Edge Rate  
HCSL Delta Tr  
HCSL Delta Tf  
HCSL Vcross Abs  
HCSL Delta Vcross  
HCSL Vovs  
Edgr  
Dtr  
Notes 12,14,18  
V/ns  
ps  
Notes 14, 17, 18  
Notes 14, 17, 18  
135  
Dtf  
125  
ps  
Vxa  
Notes 11, 13, 14, 17  
250  
550  
mV  
mV  
mV  
mV  
mV  
ps  
Dvcrs  
Vovs  
Vuds  
Vrng  
tR/tF  
Notes 14, 17  
140  
Notes 14, 17  
Notes 14, 17  
Notes 14, 17  
LVDS  
VHIGH+300  
VLOW-300  
VLOW+200  
350  
HCSL Vuds  
HCSL Vrng  
VHIGH-200  
150  
150  
150  
Rise and Fall Times  
(20% to 80%)  
3.3 V or 2.5 V  
1.8 V  
200  
225  
350  
ps  
Rise and Fall Times  
(20% to 80%)  
tR/tF  
LVPECL  
HCSL  
320  
ps  
400  
ps  
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Si5332 Data Sheet  
Electrical Specifications  
Parameter  
Notes:  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
1. For best jitter performance, keep the midpoint differential input slew rate faster than 0.3 V/ns.  
2. Not in PLL bypass mode.  
3. For best jitter performance, keep the midpoint input single ended slew rate faster than 1 V/ns.  
4. On chip termination resistance can be programmed on (100ohm) or off (high impedance).  
5. Not including R divider.  
6. Input capacitance on crystal pins targets 23 pf each plus 1 pf external trace capacitance to provide 12 pf series equivalent crystal  
load capacitance.  
7. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.  
8. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from -150mV to +150mV  
on the differential waveform . Scope is set to average because the scope sample clock is making most of the dynamic wiggles  
along the clock edge Only valid for Rising clock and Falling Clock#. Signal must be monotonic through the Vol to Voh region for  
Trise and Tfall.  
9. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.  
10. Test configuration is Rs=33.2 Ω, Rp=49.9, 2 pF.  
11. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg - 0.700), Vcross(rel) Max = 0.550 -  
0.5 (0.700 – Vhavg).  
12. Measurement taken from Single Ended waveform.  
13. Measurement taken from differential waveform VLow Math function.  
14. Overshoot is defined as the absolute value of the maximum voltage.  
15. Undershoot is defined as the absolute value of the minimum voltage.  
16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.  
17. ΔVcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK#. This is the maximum  
allowed variance in Vcross for any particular system.  
18. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.  
OUTx  
Vpp_se  
Vpp_se  
Vcm  
Vcm  
Vpp_diff = 2*Vpp_se  
Vcm  
OUTx  
19. LVDS swing levels for 50 Ω transmission lines.  
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Si5332 Data Sheet  
Electrical Specifications  
Table 5.8. LVCMOS Clock Output Specifications  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Symbol  
Test Condition  
1.8-3.3 V CMOS  
1.5 V CMOS  
Min  
5
Typ  
Max  
170  
Units  
MHz  
MHz  
ns  
Frequency  
fout  
5
133.33  
0.8  
Rise/Fall Time, 3.3 V  
(20-80%)  
tR/tF  
tR/tF  
tR/tF  
tR/tF  
50 Ω impedance, 5”  
trace, CL = 4 pf  
0.5  
Rise/Fall Time, 2.5 V  
(20-80%)  
50 Ω impedance, 5”  
trace CL = 4 pf  
0.6  
0.75  
0.9  
0.95  
1.3  
1.3  
ns  
ns  
ns  
Rise/Fall Time, 1.8 V  
(20-80%)  
50 Ω impedance, 5”  
trace CL = 4 pf  
Rise/Fall Time, 1.5 V  
(20-80%)  
50 Ω impedance, 5”  
trace CL = 4 pf  
CMOS Output Resistance  
(Single Strength)  
3.3 V  
2.5 V  
46  
48  
53  
58  
23  
24  
27  
29  
V
1.8 V  
1.5 V  
CMOS Output Resistance  
(Double Strength)  
3.3 V  
2.5 V  
1.8 V  
1.5 V  
VDDO-0.3  
CMOS Output Voltage  
Duty Cycle  
VOH  
VOL  
DC  
–4 mA load  
4 mA load  
XO and PLL mode  
0.3  
55  
V
45  
%
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Si5332 Data Sheet  
Electrical Specifications  
Table 5.9. Performance Characteristics  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Symbol  
tVDD  
Test Condition  
Min  
0.1  
Typ  
Max  
10  
Units  
ms  
Power Ramp  
Initialization Time  
0 V to VDDmin  
tinitialization  
Time for I2C to become  
operational after core  
supply exceeds VDDmin  
15  
ms  
Clock Stabilization from Power-up  
Input to Output Propagation Delay  
tSTABLE  
Time for clock outputs to  
appear after POR  
15  
25  
4
ms  
ns  
tPROP  
Buffer mode  
2.5  
(PLL Bypass)  
Spread Spectrum PP Frequency  
Deviation  
SSDEV  
SSDEV  
SSDEV  
MultiSynth Output  
< 250 MHz  
0.1  
0.4  
30  
2.5  
0.5  
33  
%
%
0.5% Spread Frequency Deviation  
Spread Spectrum Modulation Rate  
Notes:  
MultiSynth Output  
< 250 MHz  
0.45  
31.5  
MultiSynth Output  
< 250 MHz  
kHz  
1. Outputs at same frequencies and using the same driver format.  
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept between 5  
MHz and 250MHz.  
3. Update rate via I2C is also limited by the time it takes to perform a write operation.  
4. Default value is ~31.5 kHz.  
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Si5332 Data Sheet  
Electrical Specifications  
Table 5.10. Jitter Performance Specifications  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Jitter Generation,  
Locked to External 25 MHz  
Clock  
Symbol  
Test Condition  
Typ  
Max  
Units  
JGEN  
INT Mode  
12 kHz – 20 MHz 1,2  
230  
280  
fs RMS  
FRAC/DCO Mode  
12 kHz – 20 MHz 3,5  
500  
fs RMS  
JPER  
JCC  
JPER  
JCC  
Derived from integrated phase noise at a  
BER of 1e-12  
3.3  
3.1  
12  
ps Pk-Pk  
ps Pk  
N = 10, 000 cycles Integer or Fractional  
ps Pk-Pk  
ps Pk  
Mode. 2,3 Measured in the time domain.  
Performance is limited by the noise floor of  
the equipment.  
11  
Jitter Generation,  
Locked to External 25 MHz  
Crystal  
JGEN  
INT Mode  
230  
500  
280  
fs RMS  
fs RMS  
12 kHz – 20 MHz 1,2  
FRAC/DCO Mode  
12 kHz – 20 MHz 3,5  
JPER  
JCC  
JPER  
JCC  
Derived from integrated phase noise at a  
BER of 1e-12  
3.5  
3.1  
12  
ps Pk-Pk  
ps Pk  
N = 10, 000 cycles Integer or Fractional  
ps Pk-Pk  
ps Pk  
Mode. 2,3 Measured in the time domain.  
Performance is limited by the noise floor of  
the equipment.  
11  
Jitter Generation,  
Locked to Embedded 50 MHz  
Crystal  
JGEN  
INT Mode  
190  
500  
220  
fs RMS  
fs RMS  
12 kHz – 20 MHz 1,2  
FRAC/DCO Mode  
12 kHz – 20 MHz 3,5  
JPER  
JCC  
JPER  
JCC  
Derived from integrated phase noise at a  
BER of 1e-1  
3.5  
3.1  
12  
ps Pk-Pk  
ps Pk  
N = 10, 000 cycles Integer or Fractional  
ps Pk-Pk  
ps Pk  
Mode. 2,3 Measured in the time domain.  
Performance is limited by the noise floor of  
the equipment.  
11  
Power Supply Noise Rejection6  
PSNR  
25 kHz  
50 kHz  
100 kHz  
500 kHz  
1 MHz  
–100  
–97  
–72  
–83  
-91  
dBc  
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Si5332 Data Sheet  
Electrical Specifications  
Parameter  
Symbol  
Test Condition  
Typ  
Max  
Units  
Notes:  
1. INT jitter generation test conditions fOUT = 156.25 MHz LVPECL.  
2. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.  
3. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the feedback divid-  
er is integer.  
4. All jitter data in this table is based upon all output formats being differential. When LVCMOS outputs are used, there is the poten-  
tial that the output jitter may increase due to the nature of LVCMOS outputs. If your configuration implements any LVCMOS out-  
put and any output is required to have jitter less than 3 ps RMS, contact Silicon Labs for support to validate your configuration  
and ensure the best jitter performance.  
5. FRAC jitter generation test conditions fOUT = 150 MHz LVPECL.  
6. Measured at 156.25 MHz carrier frequency. 100 mVpp sine wave noise added and noise spur amplitude measured.  
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Si5332 Data Sheet  
Electrical Specifications  
Table 5.11. PCI-Express Clock Outputs (100 MHz HCSL)  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Test Condition  
SSC On/Off  
Typ  
11  
Max  
19  
Units  
PCIe Gen 1.1  
Includes PLL BW 1.5–22 MHz,  
Peaking = 3dB, Td=10 ns,  
Off  
On  
ps RMS  
ps RMS  
22  
30  
Ftrk=1.5 MHz with BER = 1E-12 2  
Includes PLL BW 5MHz & 8–16 MHz,  
Jitter Peaking = 0.01-1 dB & 3 dB,  
Td=12ns, Low Band, F < 1.5 MHz  
Includes PLL BW 5 MHz & 8–16 MHz,  
Jitter Peaking = 0.01-1dB & 3dB,  
PCIe Gen 2.1  
Off  
On  
0.12  
0.8  
0.17  
1.3  
ps RMS  
ps RMS  
Off  
On  
0.016  
0.12  
0.023  
0.21  
ps RMS  
ps RMS  
Td=12ns, High Band, 1.5 MHz < F < Nyquist2  
PCIe Gen 3.0 Com-  
mon Clock  
Includes PLL BW 2–4 MHz & 5 MHz, Peaking =  
0.01-2dB & 1dB,  
Off  
On  
0.037  
0.26  
0.048  
0.34  
ps RMS  
ps RMS  
Td=12 ns, CDR = 10 MHz 2, 3  
Includes PLL BW 4 MHz  
PCIe Gen3.0 SRIS  
On  
0.35  
0.41  
ps RMS  
Peaking = 2dB & 1dB, Td=12 ns  
CDR = 10 MHz 2, 3  
PCIe Gen 4.0 Com-  
mon Clock  
Includes PLL BW 2–4 MHz & 5 MHz, Peaking =  
0.01-2dB & 1dB,  
Off  
On  
0.037  
0.26  
0.048  
0.34  
ps RMS  
ps RMS  
Td=12 ns, CDR = 10 MHz 2, 3  
Includes PLL BW 4 MHz  
PCIe Gen4.0 SRIS  
On  
0.37  
0.42  
ps RMS  
Peaking = 2dB & 1dB, Td=12 ns  
CDR = 10 MHz 2, 3  
Notes:  
1. All jitter data in this table is based upon all output formats being differential. When LVCMOS outputs are used, there is the poten-  
tial that the output jitter may increase due to the nature of LVCMOS outputs. If your configuration implements any LVCMOS out-  
put and any output is required to have jitter less than 3 ps RMS, contact Silicon Labs for support to validate your configuration  
and ensure the best jitter performance.  
2. All output clocks 100 MHz HCSL format. Jitter data taken from Clock Jitter Tool v.1.3.  
3. Excludes oscilloscope sampling noise.  
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Si5332 Data Sheet  
Electrical Specifications  
Table 5.12. Fanout Mode Additive Jitter Performance Specifications  
(VDD = VDDA = 1.8 V to 3.3 V +10%/-5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)  
Parameter  
Symbol  
Test Condition  
Typ  
Max  
Units  
Additive Phase Jitter  
156.25MHz,  
12kHz-20MHz,  
LVDS  
145  
170  
fs RMS  
156.25MHz,  
12kHz-20MHz,  
LVPECL  
130  
130  
150  
160  
fs RMS  
fs RMS  
156.25MHz,  
12kHz-20MHz,  
HCSL  
Note:  
1. Measured with differential input on CLKIN_2, bypassing the PLL to any output.  
Table 5.13. Thermal Characteristics (Si5332A/B/C/D only)  
Test Condition1  
Parameter  
Symbol  
Value  
Units  
Si5332 — 48 QFN  
Thermal Resistance, Junction to Ambient  
θJA  
Still Air  
25.5  
22.1  
20.9  
14  
°C/W  
Air Flow 1 m/s  
Air Flow 2 m/s  
Thermal Resistance, Junction to Case  
Thermal Resistance, Junction to Board  
θJC  
θJB  
ψJB  
ψJT  
11.3  
11.0  
0.4  
Thermal Resistance, Junction to Top Center  
Si5332 — 40 QFN  
Thermal Resistance, Junction to Ambient  
θJA  
Still Air  
25.6  
22.2  
21.0  
14.1  
11.4  
11.1  
0.4  
°C/W  
Air Flow 1 m/s  
Air Flow 2 m/s  
Thermal Resistance, Junction to Case  
Thermal Resistance, Junction to Board  
θJC  
θJB  
ψJB  
ψJT  
Thermal Resistance, Junction to Top Center  
Si5332 — 32 QFN  
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Si5332 Data Sheet  
Electrical Specifications  
Test Condition1  
Still Air  
Parameter  
Symbol  
Value  
Units  
Thermal Resistance, Junction to Ambient  
θJA  
32.8  
28.8  
27.6  
18.5  
15.1  
14.9  
0.5  
°C/W  
Air Flow 1 m/s  
Air Flow 2 m/s  
Thermal Resistance, Junction to Case  
Thermal Resistance, Junction to Board  
θJC  
θJB  
ψJB  
ψJT  
Thermal Resistance, Junction to Top Center  
Note:  
1. Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via under GND pad: 36, Number of Cu Layers: 4.  
2. Thermal characteristics for Si5332E/F/G/H for embedded crystal package options will be available soon.  
Table 5.14. Absolute Maximum Ratings1,2,3  
Parameter  
Symbol  
TSTG  
VDD  
Test Condition  
Value  
Units  
°C  
V
Storage Temperature Range  
DC Supply Voltage  
–55 to +150  
–0.5 to 3.8  
–0.5 to 3.8  
–0.5 to 3.8  
–0.5 to 3.8  
–0.3 to 1.3  
VDDA  
VDDxtal  
VDDO  
VI  
V
V
V
Input Voltage Range  
Latch-up Tolerance  
ESD Tolerance  
XIN/XOUT  
V
LU  
JESD78 Compliant  
HBM  
TJCT  
TPEAK  
TP  
100 pF, 1.5 kΩ  
2.0  
–55 to 125  
260  
kV  
°C  
Junction Temperature  
Soldering Temperature  
Soldering Temperature Time at TPEAK  
Notes:  
°C  
20 to 40  
sec  
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to  
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-  
tended periods may affect device reliability.  
2. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.  
3. The device is compliant with JEDEC J-STD-020.  
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Si5332 Data Sheet  
Pin Descriptions  
6. Pin Descriptions  
6.1 Pin Descriptions (48-QFN)  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
2
3
4
VDD_DIG  
CLKIN_2  
OUT8  
OUT8b  
OUT7  
CLKIN_2b  
VDD_XTAL  
OUT7b  
OUT6  
5
6
XA/CLKIN1  
XB  
OUT6b  
49  
GND  
OUT5  
OUT5b  
OUT4  
7
CLKIN_3  
8
CLKIN_3b  
VDDA  
9
OUT4b  
OUT3  
10  
11  
12  
Input1  
Input2  
Input3  
OUT3b  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Figure 6.1. 48-QFN  
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Si5332 Data Sheet  
Pin Descriptions  
Table 6.1. Si5332 Pin Descriptions (48-QFN)  
Pin Number  
Pin Name  
VDD_DIG  
CLKIN_2  
CLKIN_2b  
Pin Type  
Function  
1
2
3
P
I
Voltage supply for digital functions. Connect to 1.8–3.3 V.  
These pins accept both differential and single-ended clock signals. Refer to  
Section 3.4.2 Input Clocks for input termination options. These pins are  
high-impedance and must be terminated externally. If both the CLKIN_2  
and CLKIN_2b inputs are un-used and powered down, then both inputs can  
be left floating. ClockBuilder Pro will power down an input that is set as "Un-  
used".  
I
4
5
6
VDD_XTAL  
XA/CLKIN1  
XB  
P
Voltage supply for crystal oscillator. Connect to 1.8–3.3 V.  
I or P  
I or P  
Si5332A/B/C/D:  
These pins are used for an optional XTAL input when operating the device  
in asynchronous mode (i.e. free-run mode). Alternatively, an external  
LVCMOS reference clock (REFCLK) can be applied to pin 5. Refer to Sec-  
tion 5. Electrical Specifications for recommended crystal specifications.  
Si5332E/F/G/H (Embedded Crystal)  
No Connect. Do not connect pins 5 or 6 to anything.  
7
8
CLKIN_3  
I
I
These pins accept both differential and single-ended clock signals. Refer to  
Section 3.4.2 Input Clocks for input termination options. These pins are  
high-impedance and must be terminated externally. If both the CLKIN_3  
and CLKIN_3b inputs are unused and powered down, then both inputs can  
be left floating. ClockBuilder Pro will power down an input that is set as "Un-  
used".  
CLKIN_3b  
9
VDDA  
P
Core Supply Voltage. Connect to 1.8–3.3 V.  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
10  
11  
12  
INPUT1  
INPUT2  
INPUT3  
I
I
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
13  
14  
SCLK  
SDA  
I
Serial Clock Input  
This pin functions as the serial clock input for I2C.  
I/O  
Serial Data Interface  
This is the bidirectional data pin (SDA) for the I2C mode.  
15  
16  
OUT0b  
OUT0  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
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Si5332 Data Sheet  
Pin Descriptions  
Pin Number  
Pin Name  
Pin Type  
Function  
17  
VDDO0  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT0  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
18  
19  
OUT1b  
OUT1  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
20  
VDDO1  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT1 and OUT2  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
21  
22  
OUT2b  
OUT2  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
23  
24  
INPUT4  
VDDO2  
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT3, OUT4,  
and OUT5  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
25  
26  
OUT3b  
OUT3  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
27  
28  
OUT4b  
OUT4  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
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Si5332 Data Sheet  
Pin Descriptions  
Pin Number  
Pin Name  
OUT5b  
OUT5  
Pin Type  
Function  
29  
30  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
31  
32  
OUT6b  
OUT6  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
33  
34  
OUT7b  
OUT7  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
35  
36  
OUT8b  
OUT8  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
37  
VDDO3  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT6, OUT7,  
and OUT8  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
38  
39  
INPUT5  
VDDO4  
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to 3.7 Universal Hardware Input Pins for a list of  
definitions that hardware input pins can be used for.  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT9  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
40  
41  
OUT9b  
OUT9  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
42  
INPUT6  
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to 3.7 Universal Hardware Input Pins for a list of  
definitions that hardware input pins can be used for.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 38  
Si5332 Data Sheet  
Pin Descriptions  
Pin Number  
Pin Name  
Pin Type  
Function  
43  
INPUT7  
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to 3.7 Universal Hardware Input Pins for a list of  
definitions that hardware input pins can be used for.  
44  
VDDO5  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT10 and  
OUT11  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
45  
46  
OUT10b  
OUT10  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
47  
48  
OUT11b  
OUT11  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
49  
GND PAD  
P
Ground Pad  
This pad provides electrical and thermal connection to ground and must be  
connected for proper operation.  
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Rev. 1.0 | 39  
Si5332 Data Sheet  
Pin Descriptions  
6.2 Pin Descriptions (40-QFN)  
1
OUT5  
30  
VDD_DIG  
2
3
4
5
6
CLKIN_2  
29  
28  
OUT5b  
VDDO3  
OUT4  
CLKIN_2b  
VDD_XTAL  
XA/CLKIN1  
XB  
27  
26 OUT4b  
41  
Ground  
VDDO2  
OUT3  
25  
24  
7
8
9
CLKIN_3  
CLKIN_3b  
VDDA  
23  
22  
OUT3b  
OUT2  
10  
21  
OUT2b  
Input1  
Figure 6.2. 40-QFN  
silabs.com | Building a more connected world.  
Rev. 1.0 | 40  
Si5332 Data Sheet  
Pin Descriptions  
Table 6.2. Si5332 Pin Descriptions (40-QFN)  
Pin Type Function  
Pin Number  
Pin Name  
VDD_DIG  
CLKIN_2  
CLKIN_2b  
1
2
3
P
I
Voltage supply for digital functions. Connect to 1.8–3.3 V.  
These pins accept both differential and single-ended clock signals. Refer to  
Section 3.4.2 Input Clocks for input termination options. These pins are  
high-impedance and must be terminated externally. If both the CLKIN_2  
and CLKIN_2b inputs are un-used and powered down, then both inputs can  
be left floating. ClockBuilder Pro will power down an input that is set as "Un-  
used".  
I
4
5
6
VDD_XTAL  
XA/CLKIN1  
XB  
P
Voltage supply for crystal oscillator. Connect to 1.8–3.3 V.  
I or P  
I or P  
Si5332A/B/C/D:  
These pins are used for an optional XTAL input when operating the device  
in asynchronous mode (i.e. free-run mode). Alternatively, an external  
LVCMOS reference clock (REFCLK) can be applied to pin5. Refer to Sec-  
tion 5. Electrical Specifications for recommended crystal specifications.  
Si5332E/F/G/H (Embedded Crystal)  
No Connect. Do not connect pins 5 or 6 to anything.  
7
8
CLKIN_3  
I
I
These pins accept both differential and single-ended clock signals. Refer to  
Section 3.4.2 Input Clocks for input termination options. These pins are  
high-impedance and must be terminated externally. If both the CLKIN_3  
and CLKIN_3b inputs are un-used and powered down, then both inputs can  
be left floating. ClockBuilder Pro will power down an input that is set as "Un-  
used".  
CLKIN_3b  
9
VDDA  
P
I
Core Supply Voltage. Connect to 1.8–3.3 V.  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
10  
INPUT1  
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
11  
12  
SCLK  
SDA  
I
Serial Clock Input  
This pin functions as the serial clock input for I2C.  
I/O  
Serial Data Interface  
This is the bidirectional data pin (SDA) for the I2C mode.  
13  
14  
OUT0b  
OUT0  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
15  
VDDO0  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT0  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
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Rev. 1.0 | 41  
Si5332 Data Sheet  
Pin Descriptions  
Pin Number  
Pin Name  
OUT1b  
OUT1  
Pin Type  
Function  
16  
17  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
18  
VDDO1  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT1  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
19  
20  
INPUT2  
INPUT3  
I
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to 3.7 Universal Hardware Input Pins for a list of  
definitions that hardware input pins can be used for.  
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to 3.7 Universal Hardware Input Pins for a list of  
definitions that hardware input pins can be used for.  
21  
22  
OUT2b  
OUT2  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
23  
24  
OUT3b  
OUT3  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
25  
VDDO2  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT2 and OUT3  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
26  
27  
OUT4b  
OUT4  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
28  
VDDO3  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT4 and OUT5  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 42  
Si5332 Data Sheet  
Pin Descriptions  
Pin Number  
Pin Name  
OUT5b  
OUT5  
Pin Type  
Function  
29  
30  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
31  
32  
33  
INPUT4  
INPUT5  
VDDO4  
I
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to 3.7 Universal Hardware Input Pins for a list of  
definitions that hardware input pins can be used for.  
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to 3.7 Universal Hardware Input Pins for a list of  
definitions that hardware input pins can be used for.  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT6  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
34  
35  
OUT6b  
OUT6  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
36  
37  
INPUT6  
INPUT7  
I
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to 3.7 Universal Hardware Input Pins for a list of  
definitions that hardware input pins can be used for.  
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to 3.7 Universal Hardware Input Pins for a list of  
definitions that hardware input pins can be used for.  
38  
39  
OUT7b  
OUT7  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
40  
41  
VDDO5  
P
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT7  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
GND PAD  
Ground Pad  
This pad provides electrical and thermal connection to ground and must be  
connected for proper operation.  
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Rev. 1.0 | 43  
Si5332 Data Sheet  
Pin Descriptions  
6.3 Pin Descriptions (32-QFN)  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
1
2
3
4
5
6
7
8
VDD_DIG  
CLKIN_2  
Input3  
VDDO3  
CLKIN_2b  
VDD_XTAL  
XA/CLKIN1  
OUT3  
22  
21  
OUT3b  
VDDO2  
33  
GND  
20  
19  
OUT2  
XB  
VDDA  
Input1  
OUT2b  
Input2  
18  
17  
14  
15  
16  
9
10  
11  
12  
13  
Figure 6.3. 32-QFN  
Table 6.3. Si5332 Pin Descriptions, (32-QFN)  
Pin Number  
Pin Name  
VDD_DIG  
CLKIN_2  
CLKIN_2b  
Pin Type  
Function  
Voltage supply for digital functions. Connect to 1.8–3.3 V.  
1
2
3
P
I
These pins accept both differential and single-ended clock signals. Refer to  
Section 3.4.2 Input Clocks for input termination options. These pins are  
high-impedance and must be terminated externally. If both the CLKIN_2  
and CLKIN_2b inputs are un-used and powered down, then both inputs can  
be left floating. ClockBuilder Pro will power down an input that is set as "Un-  
used".  
I
4
5
6
VDD_XTAL  
XA/CLKIN1  
XB  
P
Voltage supply for crystal oscillator. Connect to 1.8–3.3 V.  
I or P  
I or P  
Si5332A/B/C/D  
These pins are used for an optional XTAL input when operating the device  
in asynchronous mode (i.e. free-run mode). Alternatively, an external  
LVCMOS reference clock (REFCLK) can be applied to pin 5. Refer to Sec-  
tion 5. Electrical Specifications for recommended crystal specifications.  
Si5332E/F/G/H (Embedded Crystal)  
No Connect. Do not connect these pins 5 or 6 to anything.  
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Rev. 1.0 | 44  
Si5332 Data Sheet  
Pin Descriptions  
Pin Number  
Pin Name  
Pin Type  
Function  
7
VDDA  
P
Core Supply Voltage. Connect to 1.8–3.3 V.  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
8
INPUT1  
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
9
SCLK  
SDA  
I
Serial Clock Input  
This pin functions as the serial clock input for I2C.  
10  
I/O  
Serial Data Interface  
This is the bidirectional data pin (SDA) for the I2C mode.  
11  
12  
OUT0b  
OUT0  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
13  
VDDO0  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT0  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
14  
15  
OUT1b  
OUT1  
O
O
Output Clock  
These output clocks support a programmable signal swing & common mode  
voltage. Desired output signal format is configurable using register control.  
Termination recommendations are provided in 3.5.2 Differential Output Ter-  
minations and 3.5.3 LVCMOS Output Terminations. Unused outputs should  
be left unconnected.  
16  
VDDO1  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT1  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
17  
INPUT2  
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
18  
19  
OUT2b  
OUT2  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
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Rev. 1.0 | 45  
Si5332 Data Sheet  
Pin Descriptions  
Pin Number  
Pin Name  
Pin Type  
Function  
20  
VDDO2  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT2  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
21  
22  
OUT3b  
OUT3  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
23  
VDDO3  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT3  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
24  
25  
INPUT3  
VDDO4  
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT4  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
26  
27  
OUT4b  
OUT4  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
28  
29  
INPUT4  
INPUT5  
I
I
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
Universal HW Input pin. This hardware input pin is user definable through  
ClockBuilder Pro. Refer to Section 3.7 Universal Hardware Input Pins for a  
list of definitions that hardware input pins can be used for.  
30  
31  
OUT5b  
OUT5  
O
O
Output Clock  
These output clocks support a programmable signal swing and common  
mode voltage. Desired output signal format is configurable using register  
control. Termination recommendations are provided in 3.5.2 Differential  
Output Terminations and 3.5.3 LVCMOS Output Terminations. Unused out-  
puts should be left unconnected.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 46  
Si5332 Data Sheet  
Pin Descriptions  
Pin Number  
Pin Name  
Pin Type  
Function  
32  
VDDO5  
P
Supply Voltage (1.8–3.3 V, or 1.5 V for CMOS only) for OUT5  
See the Si5332 Family Reference Manual for power supply filtering recom-  
mendations.  
Leave VDDOx pins of unused output drivers unconnected. An alternate op-  
tion is to connect the VDDOx pin to a power supply and disable the output  
driver to minimize current consumption.  
33  
GND PAD  
P
Ground Pad  
This pad provides electrical and thermal connection to ground and must be  
connected for proper operation.  
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Rev. 1.0 | 47  
Si5332 Data Sheet  
Package Outline  
7. Package Outline  
7.1 Si5332 6x6 mm 48-QFN Package Diagram, External Crystal Versions (Si5332A/B/C/D)  
The figure below illustrates the package details for the Si5332A/B/C/D in 48-QFN. The table below lists the values for the dimensions  
shown in the illustration.  
Figure 7.1. 48-Pin Quad Flat No-Lead (QFN)  
Table 7.1. Package Dimensions  
Dimension  
Min  
0.80  
0.00  
0.15  
Nom  
0.85  
Max  
0.90  
0.05  
0.25  
A
A1  
b
0.02  
0.20  
D
6.00 BSC  
3.60  
D2  
e
3.50  
3.70  
0.40 BSC  
6.00 BSC  
3.60  
E
E2  
L
3.50  
0.30  
3.70  
0.50  
0.10  
0.10  
0.10  
0.10  
0.08  
0.40  
aaa  
bbb  
ccc  
ddd  
eee  
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-220.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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Rev. 1.0 | 48  
Si5332 Data Sheet  
Package Outline  
7.2 Si5332 6x6 mm 40-QFN Package Diagram, External Crystal Versions (Si5332A/B/C/D)  
The figure below illustrates the package details for the Si5332A/B/C/D in 40-QFN. The table below lists the values for the dimensions  
shown in the illustration.  
Figure 7.2. 40-Pin Quad Flat No-Lead (QFN)  
Table 7.2. Package Dimensions  
Dimension  
Min  
0.80  
0.00  
0.18  
Nom  
0.85  
Max  
0.90  
0.05  
0.30  
A
A1  
b
0.02  
0.25  
D
6.00 BSC  
4.50  
D2  
e
4.35  
4.65  
0.50 BSC  
6.00 BSC  
4.50  
E
E2  
L
4.35  
0.30  
4.65  
0.50  
0.15  
0.15  
0.08  
0.10  
0.05  
0.40  
aaa  
bbb  
ccc  
ddd  
eee  
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-220.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 49  
Si5332 Data Sheet  
Package Outline  
7.3 Si5332 5x5 mm 32-QFN Package Diagram, External Crystal Versions (Si5332A/B/C/D)  
The figure below illustrates the package details for the Si5332A/B/C/D 32-QFN option. The table below lists the values for the dimen-  
sions shown in the illustration.  
Figure 7.3. 32-Pin Quad Flat No-Lead (QFN)  
Table 7.3. Package Dimensions  
Dimension  
MIN  
0.80  
0.00  
NOM  
0.85  
MAX  
0.90  
0.05  
A
A1  
A3  
b
0.02  
0.20 REF  
0.25  
0.18  
4.90  
3.40  
0.30  
5.10  
3.60  
D/E  
D2/E2  
e
5.00  
3.50  
0.50 BSC  
0.40  
L
0.30  
0.20  
0.09  
0.50  
---  
K
---  
R
---  
0.14  
aaa  
bbb  
ccc  
0.15  
0.10  
0.10  
silabs.com | Building a more connected world.  
Rev. 1.0 | 50  
Si5332 Data Sheet  
Package Outline  
Dimension  
MIN  
NOM  
0.05  
0.08  
0.10  
MAX  
ddd  
eee  
fff  
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 51  
Si5332 Data Sheet  
Package Outline  
7.4 Si5332 6x6 mm 48-QFN Package Diagram, Embedded Crystal Versions (Si5332E/F/G/H)  
The figure below illustrates the package details for the Si5332E/F/G/H in 48-QFN. The table below lists the values for the dimensions  
shown in the illustration.  
Figure 7.4. 48-Pin Quad Flat No-Lead (QFN)  
Table 7.4. Package Dimensions  
Dimension  
Min  
Nom  
1.0  
Max  
A
A1  
A2  
b
0.90  
1.1  
0.26 REF  
0.70 REF  
0.23  
0.18  
0.28  
D
6.00 BSC  
2.5 REF  
6.00 BSC  
2.5 REF  
0.40 BSC  
0.35  
D2  
E
E2  
e
L
0.30  
0.40  
L1  
aaa  
bbb  
ccc  
ddd  
eee  
0.10 REF  
0.10  
0.10  
0.08  
0.10  
0.08  
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-220.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 52  
Si5332 Data Sheet  
Package Outline  
7.5 Si5332 6x6 mm 40-QFN Package Diagram, Embedded Crystal Versions (Si5332E/F/G/H)  
The figure below illustrates the package details for the Si5332E/F/G/H in 40-QFN. The table below lists the values for the dimensions  
shown in the illustration.  
Figure 7.5. 40-Pin Quad Flat No-Lead (QFN)  
Table 7.5. Package Dimensions  
Dimension  
Min  
Nom  
1.0  
Max  
A
A1  
A2  
b
0.90  
1.1  
0.26 REF  
0.70 REF  
0.23  
0.18  
0.28  
D
6.00 BSC  
2.5 REF  
6.00 BSC  
2.5 REF  
0.50 BSC.  
0.35  
D2  
E
E2  
e
L
0.30  
0.40  
L1  
aaa  
bbb  
ccc  
ddd  
eee  
0.10 REF  
0.10  
0.10  
0.08  
0.10  
0.08  
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-220.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 53  
Si5332 Data Sheet  
Package Outline  
7.6 Si5332 5x5 mm 32-QFN Package Diagram, Embedded Crystal Versions (Si5332E/F/G/H)  
The figure below illustrates the package details for the Si5332E/F/G/H 32-QFN option. The table below lists the values for the dimen-  
sions shown in the illustration.  
Figure 7.6. 32-Pin Quad Flat No-Lead (QFN)  
Table 7.6. Package Dimensions  
Dimension  
Min  
Nom  
1.0  
Max  
A
A1  
A2  
b
0.90  
1.1  
0.26 REF  
0.70 REF  
0.25  
0.2  
0.30  
D
5.00 BSC  
2.1 REF  
5.00 BSC  
2.1 REF  
0.50 BSC  
0.37  
D2  
E
E2  
e
L
0.32  
0.42  
L1  
aaa  
bbb  
ccc  
ddd  
eee  
0.10 REF  
0.10  
0.10  
0.08  
0.10  
0.08  
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-220.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 54  
Si5332 Data Sheet  
PCB Land Pattern  
8. PCB Land Pattern  
8.1 Si5332A/B/C/D 48-QFN Land Pattern  
Figure 8.1. 48-QFN Land Pattern  
Table 8.1. PCB Land Pattern Dimensions  
Dimension  
mm  
5.90  
C1  
C2  
e
5.90  
0.40 BSC  
0.20  
X1  
Y1  
X2  
Y2  
0.85  
3.60  
3.60  
silabs.com | Building a more connected world.  
Rev. 1.0 | 55  
Si5332 Data Sheet  
PCB Land Pattern  
Dimension  
mm  
Notes:  
General  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This Land Pattern Design is based on the IPC-7351 guidelines.  
Solder Mask Design  
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
Stencil Design  
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
2. The stencil thickness should be 0.125 mm (5 mils).  
3. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.  
4. A 3×3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.  
Card Assembly  
1. A No-Clean, Type-3 solder paste is recommended.  
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 56  
Si5332 Data Sheet  
PCB Land Pattern  
8.2 Si5332A/B/C/D 40-QFN Land Pattern  
Figure 8.2. 40-QFN Land Pattern  
Table 8.2. PCB Land Pattern Dimensions  
Dimension  
mm  
5.90  
C1  
C2  
e
5.90  
0.50 BSC  
0.30  
X1  
Y1  
X2  
Y2  
0.85  
4.65  
4.65  
silabs.com | Building a more connected world.  
Rev. 1.0 | 57  
Si5332 Data Sheet  
PCB Land Pattern  
Dimension  
mm  
Notes:  
General  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This Land Pattern Design is based on the IPC-7351 guidelines.  
Solder Mask Design  
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
Stencil Design  
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
2. The stencil thickness should be 0.125 mm (5 mils).  
3. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.  
4. A 3×3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.  
Card Assembly  
1. A No-Clean, Type-3 solder paste is recommended.  
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 58  
Si5332 Data Sheet  
PCB Land Pattern  
8.3 Si5332A/B/C/D 32-QFN Land Pattern  
The figure below illustrates the PCB land pattern details for Si5332 in 32-GFN package. The table below lists the values for the dimen-  
sions shown in the illustration.  
Figure 8.3. 32-QFN Land Pattern  
Table 8.3. PCB Land Pattern Dimensions  
Dimension  
mm  
4.90  
C1  
C2  
e
4.90  
0.50 BSC  
0.30  
X1  
Y1  
X2  
Y2  
0.85  
3.60  
3.60  
silabs.com | Building a more connected world.  
Rev. 1.0 | 59  
Si5332 Data Sheet  
PCB Land Pattern  
Dimension  
mm  
Notes:  
General  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This Land Pattern Design is based on the IPC-7351 guidelines.  
Solder Mask Design  
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
Stencil Design  
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
2. The stencil thickness should be 0.125 mm (5 mils).  
3. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.  
4. A 3×3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.  
Card Assembly  
1. A No-Clean, Type-3 solder paste is recommended.  
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 60  
Si5332 Data Sheet  
PCB Land Pattern  
8.4 Si5332E/F/G/H 48-LGA Land Pattern  
Figure 8.4. 48-LGA Land Pattern  
Table 8.4. PCB Land Pattern Dimensions  
Dimension  
mm  
5.52  
C1  
C2  
e
5.52  
0.40 BSC  
0.20  
X1  
Y1  
X2  
Y2  
0.50  
2.60  
2.60  
silabs.com | Building a more connected world.  
Rev. 1.0 | 61  
Si5332 Data Sheet  
PCB Land Pattern  
Dimension  
mm  
Notes:  
General  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This Land Pattern Design is based on the IPC-7351 guidelines.  
Solder Mask Design  
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
Stencil Design  
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
2. The stencil thickness should be 0.125 mm (5 mils).  
3. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.  
4. A 3×3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.  
Card Assembly  
1. A No-Clean, Type-3 solder paste is recommended.  
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 62  
Si5332 Data Sheet  
PCB Land Pattern  
8.5 Si5332E/F/G/H 40-LGA Land Pattern  
Figure 8.5. 40-LGA Land Pattern  
Table 8.5. PCB Land Pattern Dimensions  
Dimension  
mm  
5.52  
C1  
C2  
e
5.52  
0.50 BSC  
0.30  
X1  
Y1  
X2  
Y2  
0.50  
2.60  
2.60  
silabs.com | Building a more connected world.  
Rev. 1.0 | 63  
Si5332 Data Sheet  
PCB Land Pattern  
Dimension  
mm  
Notes:  
General  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This Land Pattern Design is based on the IPC-7351 guidelines.  
Solder Mask Design  
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
Stencil Design  
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
2. The stencil thickness should be 0.125 mm (5 mils).  
3. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.  
4. A 3×3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.  
Card Assembly  
1. A No-Clean, Type-3 solder paste is recommended.  
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 64  
Si5332 Data Sheet  
PCB Land Pattern  
8.6 Si5332E/F/G/H 32-LGA Land Pattern  
The figure below illustrates the PCB land pattern details for Si5332 in 32-LGA package. The table below lists the values for the dimen-  
sions shown in the illustration.  
Figure 8.6. 32-LGA Land Pattern  
Table 8.6. PCB Land Pattern Dimensions  
Dimension  
mm  
4.50  
C1  
C2  
e
4.50  
0.50 BSC  
0.30  
X1  
Y1  
X2  
Y2  
0.45  
2.20  
2.20  
silabs.com | Building a more connected world.  
Rev. 1.0 | 65  
Si5332 Data Sheet  
PCB Land Pattern  
Dimension  
mm  
Notes:  
General  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This Land Pattern Design is based on the IPC-7351 guidelines.  
Solder Mask Design  
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
Stencil Design  
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
2. The stencil thickness should be 0.125 mm (5 mils).  
3. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.  
4. A 3×3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.  
Card Assembly  
1. A No-Clean, Type-3 solder paste is recommended.  
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 66  
Si5332 Data Sheet  
Top Marking  
9. Top Marking  
Figure 9.1. Si5332 Top Marking  
Table 9.1. Top Marking Explanation  
Line  
Characters  
Description  
1
Si5332g  
Base part number and device grade  
g = Device Grade (A, B, C, D, E, F, G, H)  
2
R-GMp  
R = Product revision (see Ordering Guide for current revision)  
- = Dash character  
GM = Package (QFN) and temperature range (-40 to +85C)  
p = Package Size  
• 1 = 6-output, 32-pin QFN  
• 2 = 8-output, 40-pin QFN  
• 3 = 12-output, 48-pin QFN  
Rxxxxx  
R = Product revision (see ordering guide for current revision)  
xxxxx = Customer specific NVM sequence number. NVM code assigned for custom,  
factory pre-programmed devices using ClockBuilder Pro.  
See Ordering Guide for more information.  
Manufacturing trace code.  
3
4
TTTTTT  
YYWW  
Year (YY) and work week (WW) of package assembly  
silabs.com | Building a more connected world.  
Rev. 1.0 | 67  
Si5332 Data Sheet  
Document Change List  
10. Document Change List  
Revision 1.0  
February 2018  
• Updated Si5332 5x5 mm 32-QFN package diagram for external crystal versions  
• Updated Si5332 32-QFN land pattern  
• Updated jitter specifications for embedded crystal reference (Table 5.7 Differential Clock Output Specifications on page 26)  
Revision 0.7  
September 2017  
• Initial release.  
silabs.com | Building a more connected world.  
Rev. 1.0 | 68  
ClockBuilder Pro  
One-click access to Timing tools,  
documentation, software, source  
code libraries & more. Available for  
Windows and iOS (CBGo only).  
www.silabs.com/CBPro  
Timing Portfolio  
www.silabs.com/timing  
SW/HW  
www.silabs.com/CBPro  
Quality  
www.silabs.com/quality  
Support and Community  
community.silabs.com  
Disclaimer  
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or  
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"  
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes  
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included  
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted  
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