SI5340B-B05212-GMR_技术文档

Si5341/40

LOW-JITTER, 10-OUTPUT, ANY-FREQUENCY, ANY-OUTPUT

CLOCK GENERATOR

Features



Generates up to 10 independent

output clocks

Ultra-low jitter: <100 fs RMS typical

MultiSynth™ technology enables any-

frequency synthesis on any-output

Highly configurable outputs

compatible with LVDS, LVPECL, CML,  Status monitoring: LOS, LOL

LVCMOS, HCSL, or programmable

voltage



DCO mode with frequency steps as

low as 0.001 ppb

Independent output clock supply pins:

3.3 V, 2.5 V, or 1.8 V

Built-in power supply filtering and

regulation



2



Serial Interface: I C or SPI (3-wire or

4-wire)

9x9 mm

7x7 mm

Input frequency range:



User programmable (2x) non-volatile

OTP memory

External crystal: 25, 48-54 MHz

Differential clock: 10 to 750 MHz

LVCMOS clock: 10 to 250 MHz

Output frequency range:

Differential: 100 Hz to 712.5 MHz

LVCMOS: 100 Hz to 250 MHz

Output-output skew: 20 ps typ

Adjustable output-output delay

Optional zero delay mode

Ordering Information

TM



ClockBuilder Pro software utility

See Section 8.

simplifies device configuration and

assigns customer part numbers

Si5341: 4 input, 10 output, compact

9x9 mm, 64 QFN

Si5340: 4 input, 4 output, compact

7x7 mm, 44 QFN



Functional Block Diagram



Temperature range: –40 to +85 °C

Pb-free, RoHS-6 compliant

Independent glitchless on-the-fly

output frequency changes

Si5341/40

IN_SEL[1:0]

Device Selector Guide

IN0

IN1

IN2

÷INT

Grade

Si534xA

Si534xB

Si534xC

Si534xD

Max Output Frequency

712.5 MHz

Frequency Synthesis Mode

Integer + Fractional

PLL

350 MHz

XA

712.5 MHz

OSC

Integer Only

350 MHz

XB

FB_IN

÷INT

Applications



Clock tree generation replacing XOs,



Ethernet switches/routers

OTN framers/mappers/processors

Test equipment & instrumentation

Broadcast video

Multi

Synth

buffers, signal format translators

Any-frequency clock translation

Clocking for FPGAs, processors,

memory

÷INT

OUT0

OUT1

OUT2



Multi

Synth

Multi

Synth

÷INT

Description

Multi

Synth

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL

with proprietary MultiSynth fractional synthesizer technology to offer a versatile and

high performance clock generator platform. This highly flexible architecture is capable

of synthesizing a wide range of integer and non-integer related frequencies up to

712.5 MHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter

performance with 0 ppm error. Each of the clock outputs can be assigned its own

format and output voltage enabling the Si5341/40 to replace multiple clock ICs and

oscillators with a single device making it a true “clock tree on a chip”.

Multi

Synth

NVM

I²C/SPI

The Si5341/40 can be quickly and easily configured using ClockBuilder Pro software.

Custom part numbers are automatically assigned using a ClockBuilder Pro for fast,

free, and easy factory pre-programming, or the Si5341/40 can be programmed in-

Control/

Status

2

circuit via I C and SPI serial interfaces.

Rev. 1.0 7/15

Si5341/40

2

Rev. 1.0

Si5341/40

TABLE OF CONTENTS

1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

5.1. Power-up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

5.2. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5.3. Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5.4. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.5. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.6. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.7. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.8. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.9. Custom Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.10. Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro

for Factory Pre-programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

6.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

6.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

9.1. Si5341 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

9.2. Si5340 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Rev. 1.0

3

Si5341/40

1. Typical Application Schematic

Buffer

161.1328125

MHz

133.33 MHz

2x 161.1328125 MHz

LVDS

2x 133.33 MHz

1.8V LVCMOS

Buffer

Level

Delay Line

Translator

3x 125 MHz

LVPECL

125 MHz

Buffer

Clock

Generator

4x 125 MHz

3.3V LVCMOS

Level

Translator

XA

XB

200 MHz

2.5V LVCMOS

25 MHz

“Traditional Discrete” Clock Tree

One Si5341 replaces:

3x crystal oscillators (XO)

2x buffers

1x Clock Generator

2x level translators

1x delay line

1x 161.1328125 MHz

LVDS

1x 161.1328125 MHz

LVDS

XA

XB

2x 133.33 MHz

1.8V LVCMOS

25 MHz

1x 125 MHz

LVPECL

1x 125 MHz

LVPECL

Si5341

1x 125 MHz

LVPECL

2x 125 MHz

3.3V LVCMOS

2x 125 MHz

3.3V LVCMOS

2x 200 MHz

2.5V LVCMOS

“Clock Tree

On-a-Chip”

2x 200 MHz

2.5V LVCMOS

Figure 1. Using The Si5341 to Replace a Traditional Clock Tree

4

Rev. 1.0

Si5341/40

2. Electrical Specifications

Table 1. Recommended Operating Conditions

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%,T_A= –40 to 85 °C)

Parameter

Ambient Temperature

Junction Temperature

Core Supply Voltage

Symbol

Min

–40

—

Typ

25

Max

85

Units

°C

V

T

A

TJ

—

125

1.89

3.47

2.62

1.89

MAX

V

1.71

3.14

2.38

1.71

1.80

3.30

2.50

1.80

DD

V

DDA

DDO

Output Driver Supply Voltage

V

*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Rev. 1.0

5

Si5341/40

Table 2. DC Characteristics

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

—

Typ

100

85

Max

150

130

Units

mA

1

2

Core Supply Current

I

Si5341

Note

DD

—

mA

Si5340

Si5341

Si5340

1

2

I

—

115

21

125

25

mA

Note

DDA

Note

3

Output Buffer Supply Current

I

LVPECL Output

@ 156.25 MHz

DDOx

3

LVDS Output

—

15

21

16

12

18

25

18

13

mA

@ 156.25 MHz

4

3.3 V LVCMOS output

@ 156.25 MHz

4

2.5 V LVCMOS output

@ 156.25 MHz

4

1.8 V LVCMOS output

@ 156.25 MHz

1,5

Total Power Dissipation

P

Si5341

Si5340

Notes

—

830

685

980

815

mW

d

2,5

Notes:

1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.

2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.

3. Differential outputs terminated into an ac-coupled 100 load.

4. LVCMOS outputs measured into a 6-inch 50  PCB trace with 5 pF load. The LVCMOS outputs were set to

OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5341/40 Family Reference Manual for more

details on register settings.

Differential Output Test Configuration

LVCMOS Output Test Configuration

I_DDO

6 inch

0.1 uF

50

OUT

OUTa

50

100

OUTb

OUT

5 pF

50

0.1 uF

5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board

(EVB) is not available. All EVBs support detailed current measurements for any configuration.

6

Rev. 1.0

Si5341/40

Table 3. Input Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Differential or Single-Ended/LVCMOS — AC-Coupled (IN0/IN0, IN1/IN1, IN2/IN2, FB_IN/FB_IN)

Input Frequency Range

f

Differential

10

—

750

250

MHz

IN

Single-ended/LVCMOS

5

Input Voltage Swing

V

IN

Differential AC Coupled

fin < 250 MHz

100

1800

mVpp_se

Differential AC Coupled

250 MHz < fin < 750 MHz

225

100

—

1800

3600

Single-ended AC Coupled

fin < 250 MHz

1, 2

Slew Rate

SR

DC

400

40

—

2

—

60

—

V/µs

%

Duty Cycle

Capacitance

C

—

pF

IN

DC-Coupled CMOS Input Buffer (IN0, IN1, IN2)⁴

Input Frequency

Input Voltage

f

10

–0.2

0.49

400

40

—

8

250

0.33

—

MHz

V

IN

V

IL

V

IH

1, 2

Slew Rate

SR

DC

PW

—

V/µs

%

Duty Cycle

Clock Input

Pulse Input

60

Minimum Pulse Width

Input Resistance

1.6

—

ns

R

—

kΩ

IN

Differential or Single-Ended/LVCMOS Clock at XA/XB

Input Frequency Range

f

Frequency range for best

output

48

—

200

MHz

IN

jitter performance

10

—

200

MHz

Input Single-ended Voltage Swing

V

365

2000

mVpp_se

IN_SE

Notes:

1. Imposed for jitter performance.

2. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20= ((0.8 - 0.2) * V_{IN_Vpp_se}) / SR.

3. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD

.

4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended

LVCMOS inputs to IN0,1,2 it is required to ac-couple into the differential input buffer.

5. Voltage swing is specified as single-ended mVpp.

6. Contact Silicon Labs Technical Support for more details.

Rev. 1.0

7

Si5341/40

Table 3. Input Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

—

Max

2500

—

Units

mVpp_diff

V/µs

Input Differential Voltage Swing

V

365

IN_DIFF

1, 2

Slew rate

SR

Imposed for best jitter per- 400

formance

—

Input Duty Cycle

DC

40

—

60

%

Notes:

1. Imposed for jitter performance.

2. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20= ((0.8 - 0.2) * V_{IN_Vpp_se}) / SR.

3. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD

.

4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended

LVCMOS inputs to IN0,1,2 it is required to ac-couple into the differential input buffer.

5. Voltage swing is specified as single-ended mVpp.

6. Contact Silicon Labs Technical Support for more details.

Table 4. Control Input Pin Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDS= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol Test Condition

Min

Typ

Max

Units

Si5341 Control Input Pins

(I2C_SEL, IN_SEL[1:0], RST, OE, SYNC, A1, SCLK, A0/CS, FINC, FDEC, SDA/SDIO)

Input Voltage

V

—

2

0.3xV

*

DDIO

V

IL

IH

IN

V

C

R

0.7xV

*

—

DDIO

Input Capacitance

Input Resistance

—

pF

k

ns

20

—

Minimum Pulse Width

T

RST, SYNC,

100

PW

FINC, and FDEC

Frequency Update Rate

F

FINC and FDEC

—

1

MHz

UR

Si5340 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, A1, SDA, SDI, SCLK, A0/CS, SDA/SDIO)

Input Voltage

V

—

2

0.3xV

*

DDIO

V

IL

IH

IN

V

C

R

0.7xV

*

—

DDIO

Input Capacitance

Input Resistance

—

pF

k

ns

20

—

Minimum Pulse Width

T

RST only

100

PW

*Note: V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD. Refer to the Reference Manual for more

details on register settings.

8

Rev. 1.0

Si5341/40

Table 5. Differential Clock Output Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Output Frequency

Symbol

Test Condition

Min

0.0001

48

Typ

—

Max

712.5

52

Units

MHz

%

f

OUT

Duty Cycle

DC

f

< 400 MHz

—

OUT

400 MHz < f

<

45

—

55

%

OUT

712.5 MHz

Output-Output Skew

T

Outputs on same Multisynth,

Normal Mode

—

20

0

50

ps

SK

Outputs on same Multisynth,

Pow Power Mode

100

OUT-OUT Skew

T

Measured from the positive

to negative output pins

SK_OUT

1, 5

Output Amplitude

Normal Mode

V

= 3.3 V,

DDO

LVDS

350

470

810

550

mVpp_se

OUT

2.5 V, or 1.8 V

V

= 3.3 V

LVPECL

660

1000

DDO

or 2.5 V

Low Power Mode

V

= 3.3 V,

LVDS

300

420

820

530

DDO

2.5 V, or 1.8 V

V

= 3.3 V

LVPECL

620

1060

DDO

or 2.5 V

Notes:

1. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644

maximum. For normal and low-power modes, the amplitudes are programmable through register settings and can be

stored in NVM. Each output driver can be programmed independently. See Appendix A of the Si5341/40 Reference

Manual.

2. Driver output impedance depends on selected output mode (Normal, Low Power).

3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/

3.3 V = 100 mVpp) and noise spur amplitude measured.

OUTx

Vpp_se

Vcm

Vpp_diff = 2*Vpp_se

OUTx

4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor

at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet

Infrastructure Systems”, guidance on crosstalk minimization.

5. For other amplitudes see Appendix A of the Si5341/40 Reference Manual.

6. See Note 4, but in this case the measurement is across two output clocks that have a single clock between them.

7. Same as Note 4, but the Si5340 has less crosstalk due to the spacing of adjacent outputs.

Rev. 1.0

9

Si5341/40

Table 5. Differential Clock Output Specifications (Continued)

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

1

Common Mode Voltage

Normal Mode or Low Power Modes

V

= 3.3 V

= 2.5 V

LVDS

1.10

1.90

1.15

1.25

2.05

1.25

1.35

2.15

1.35

V

CM

DDO

LVPECL

V

LVPECL

LVDS

DDO

= 1.8 V Sub-LVDS

Normal Mode

0.87

—

0.93

170

300

100

650

1.0

240

430

—

Rise and Fall Times

(20% to 80%)

t /t

ps

R F

Low Power Mode

Normal Mode

—

2

Differential Output Impedance

Z

—



O

Low Power Mode

—

3

Power Supply Noise Rejection

PSRR

Normal Mode

10 kHz sinusoidal noise

—

–93

–84

–79

—

dBc

100 kHz sinusoidal noise

500 kHz sinusoidal noise

1 MHz sinusoidal noise

—

Low Power Mode

10 kHz sinusoidal noise

—

–98

—

dBc

100 kHz sinusoidal noise

500 kHz sinusoidal noise

1 MHz sinusoidal noise

–95

–84

–76

Notes:

1. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644

maximum. For normal and low-power modes, the amplitudes are programmable through register settings and can be

stored in NVM. Each output driver can be programmed independently. See Appendix A of the Si5341/40 Reference

Manual.

2. Driver output impedance depends on selected output mode (Normal, Low Power).

3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/

3.3 V = 100 mVpp) and noise spur amplitude measured.

OUTx

Vpp_se

Vcm

Vpp_diff = 2*Vpp_se

OUTx

4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor

at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet

Infrastructure Systems”, guidance on crosstalk minimization.

5. For other amplitudes see Appendix A of the Si5341/40 Reference Manual.

6. See Note 4, but in this case the measurement is across two output clocks that have a single clock between them.

7. Same as Note 4, but the Si5340 has less crosstalk due to the spacing of adjacent outputs.

10

Rev. 1.0

Si5341/40

Table 5. Differential Clock Output Specifications (Continued)

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

—

Typ

–75

–85

Max

—

Units

dBc

Note ⁴

Output-Output Crosstalk

XTALK

Si5341

Si5340

Note ⁶

Note ⁷

—

dBc

—

dBc

Notes:

1. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644

maximum. For normal and low-power modes, the amplitudes are programmable through register settings and can be

stored in NVM. Each output driver can be programmed independently. See Appendix A of the Si5341/40 Reference

Manual.

2. Driver output impedance depends on selected output mode (Normal, Low Power).

3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/

3.3 V = 100 mVpp) and noise spur amplitude measured.

OUTx

Vpp_se

Vcm

Vpp_diff = 2*Vpp_se

OUTx

4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor

at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet

Infrastructure Systems”, guidance on crosstalk minimization.

5. For other amplitudes see Appendix A of the Si5341/40 Reference Manual.

6. See Note 4, but in this case the measurement is across two output clocks that have a single clock between them.

7. Same as Note 4, but the Si5340 has less crosstalk due to the spacing of adjacent outputs.

Table 6. Output Status Pin Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDS= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol Test Condition

Min

Typ

Max

Units

Si5341 Status Output Pins (LOL, INTR), SDA/SDIO², SDO

1

Output Voltage

V

I

= –2 mA

= 2 mA

V

x 0.75

—

V

OH

DDIO

1

V

I

—

V

x 0.15

OL

DDIO

Si5340 Status Output Pins (INTR), LOL, LOS_XAXB, SDA/SDIO², SDO

1

Output Voltage

V

I

= –2 mA

= 2 mA

V

x 0.75

—

V

OH

DDIO

1

V

I

—

x 0.15

OL

DDIO

Notes:

1. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD. Refer to the Reference Manual for more

details on register settings.

2. The V_OHspecification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is

unused with I2C_SEL pulled high. V_OLremains valid in all cases.

Rev. 1.0

11

Si5341/40

Table 7. LVCMOS Clock Output Specifications

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Output Frequency

Duty Cycle

Symbol

Test Condition

Min

0.0001

47

Typ

—

Max Units

250

53

MHz

%

DC

f

< 100 MHz

—

OUT

100 MHz < f

< 250 MHz

44

—

55

OUT

Output-to-Output Skew

T

—

100

ps

V

SK

1, 2, 3

Output Voltage High

V

= 3.3 V

DDO

OH

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I

–10 mA

–12 mA

–17 mA

V

x

—

OH =

DDO

0.75

V

= 2.5 V

DDO

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I

–6 mA

–8 mA

–11 mA

—

V

OH =

DDO

0.75

I

V

= 1.8 V

DDO

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I

–4 mA

–5 mA

—

OH =

DDO

0.75

I

Notes:

1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer

to the Reference Manual for more details on register settings.

2. I_OL/I_OHis measured at V_OL/V_OHas shown in the dc test configuration.

3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50  PCB trace. A 5 pF

capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.

AC Test Configuration

Trace length 5 inches

DC Test Configuration

499 

4.7 pF

0.1 uF

I_OL/I_OH

I_DDO

50 probe, scope

50 

OUT

Zs

56 

0.1 uF

V_OL/V_OH

499 

4.7 pF

56 

12

Rev. 1.0

Si5341/40

Table 7. LVCMOS Clock Output Specifications (Continued)

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max Units

1, 2, 3

Output Voltage Low

V

= 3.3 V

DDO

OL

OUTx_CMOS_DRV=1

I

= 10 mA

—

V

OL

DDO

x 0.15

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

= 12 mA

= 17 mA

V

= 2.5 V

DDO

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I

= 6 mA

= 8 mA

= 11 mA

—

V

DDO

x 0.15

OL

I

V

= 1.8 V

DDO

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

I

= 4 mA

= 5 mA

—

V

DDO

x 0.15

OL

I

—

LVCMOS Rise and Fall

Times

tr/tf

VDDO = 3.3V

420

475

525

550

625

705

ps

3

VDDO = 2.5 V

VDDO = 1.8 V

(20% to 80%)

Notes:

1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer

to the Reference Manual for more details on register settings.

2. I_OL/I_OHis measured at V_OL/V_OHas shown in the dc test configuration.

3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50  PCB trace. A 5 pF

capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.

AC Test Configuration

Trace length 5 inches

DC Test Configuration

499 

4.7 pF

0.1 uF

I_OL/I_OH

I_DDO

50 probe, scope

50 

OUT

Zs

56 

0.1 uF

V_OL/V_OH

499 

4.7 pF

56 

Rev. 1.0

13

Si5341/40

Table 8. Performance Characteristics

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

13.5

—

Typ

—

Max

14.256

—

Units

GHz

MHz

ms

V

Frequency Range

F

VCO

CO

PLL Loop Bandwidth

Initial Start-Up Time

f

1.0

30

BW

t

Time from power-up to when the

device generates clocks (Input

Frequency > 48 MHz)

—

45

START

1

POR to Serial Interface

t

—

15

ms

RDY

Ready

6

PLL Lock Time

t

f

= 19.44 MHz

22

—

180

—

ms

ps

ACQ

IN

Output Delay Adjustment

t

f

= 14 GHz

VCO

0.28

DELAY_-

frac

Delay is controlled by the Multi-

Synth

t

—

71.4

—

ps

ns

DELAY_int

t

±9.14

RANGE

3

Jitter Generation

Locked to External Clock

J

Integer Mode

0.135 0.175

ps RMS

GEN

2

12 kHz to 20 MHz

4

Fractional/DCO Mode

—

0.160 0.205

ps RMS

12 kHz to 20 MHz

J

Derived from

integrated phase noise

—

0.140

0.250

7.3

—

ps pk-pk

ps pk

PER

J

CC

N = 10,000 cycles

Integer or Fractional Mode

Measured in the time domain.

Performance is limited by the

noise floor of the

ps pk-pk

ps pk

PER

3,4

.

J

8.1

CC

equipment.

Notes:

1. Measured as time from valid V_DDand V_DD33rails (90% of their value) to when the serial interface is ready to respond

to commands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz.

2. Jitter generation test conditions f_IN= 100 MHz, f_OUT= 156.25 MHz LVPECL.

3. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.

4. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the

feedback divider is integer.

5. Initiate a soft reset command to align the outputs to within +/- 100 ps.

6. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input

clock. The time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time.

14

Rev. 1.0

Si5341/40

Table 8. Performance Characteristics (Continued)

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Jitter Generation

XTAL Frequency = 48 MHz

Locked to External XTAL

3

J

Integer Mode

—

0.090 0.150

ps RMS

GEN

12 kHz to 20 MHz

4

Fractional/DCO Mode

12 kHz to 20 MHz

—

0.120 0.165

J

Derived from

integrated phase noise

—

0.150

0.270

7.3

—

ps pk-pk

ps pk

PER

J

CC

N = 10, 000 cycles

Integer or Fractional Mode

Measured in the time domain.

Performance is limited by the

noise floor of the equipment.

ps pk-pk

ps pk

PER

3,4

.

J

7.8

CC

XTAL Frequency = 25 MHz

J

Integer Mode

12 kHz to 20 MHz

0.125 0.330

0.170 0.360

ps RMS

GEN

Fractional

12 kHz to 20 MHz

Notes:

1. Measured as time from valid V_DDand V_DD33rails (90% of their value) to when the serial interface is ready to respond

to commands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz.

2. Jitter generation test conditions f_IN= 100 MHz, f_OUT= 156.25 MHz LVPECL.

3. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.

4. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the

feedback divider is integer.

5. Initiate a soft reset command to align the outputs to within +/- 100 ps.

6. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input

clock. The time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time.

Rev. 1.0

15

Si5341/40

Table 9. I²C Timing Specifications (SCL,SDA)

Parameter

Symbol Test Condition

Min

Max

Min

Max

Units

Standard Mode

100 kbps

Fast Mode

400 kbps

SCL Clock

Frequency

f

—

100

—

400

—

kHz

µs

SCL

Hold Time

t

4.0

—

0.6

HD:STA

(Repeated)

START Condition

Low Period of the

SCL Clock

t

4.7

4.0

4.7

—

1.3

0.6

—

µs

LOW

HIGH Period of

the SCL Clock

t

HIGH

Set-up Time for a

Repeated START

Condition

t

SU:STA

Data Hold Time

t

100

250

—

100

20

—

ns

HD:DAT

Data Set-up Time

t

SU:DAT

Rise Time of Both

SDA and SCL

Signals

t

1000

300

r

Fall Time of Both

SDA and SCL

Signals

t

—

300

—

300

ns

f

Set-up Time for

STOP Condition

t

4.0

4.7

—

0.6

1.3

—

µs

SU:STO

Bus Free Time

between a STOP

and START Con-

dition

t

BUF

Data Valid Time

t

—

3.45

—

0.9

µs

VD:DAT

t

VD:ACK

Data Valid

Acknowledge

Time

16

Rev. 1.0

Si5341/40

Figure 2. I²C Serial Port Timing Standard and Fast Modes

Rev. 1.0

17

Si5341/40

Table 10. SPI Timing Specifications (4-Wire)

(V_DD= 1.8 V ±5%, V_DDA= 3.3V ±5%, T_A= –40 to 85 °C)

Parameter

SCLK Frequency

Symbol

Min

—

40

50

—

5

Typ

—

Max

20

60

—

Units

MHz

%

f

SPI

SCLK Duty Cycle

T

—

DC

SCLK Period

T

—

ns

C

Delay Time, SCLK Fall to SDO Active

Delay Time, SCLK Fall to SDO

Delay Time, CS Rise to SDO Tri-State

Setup Time, CS to SCLK

T

12.5

10

—

18

15

—

ns

D1

D2

D3

ns

T

ns

SU1

Hold Time, CS to SCLK Rise

Setup Time, SDI to SCLK Rise

Hold Time, SDI to SCLK Rise

Delay Time Between Chip Selects (CS)

T

5

—

ns

H1

T

5

—

ns

SU2

T

5

—

ns

H2

CS

T

2

—

T

C

T_D1

T_C

T_SU1

SCLK

CS

T_H1

T_SU2

T_H2

T_CS

SDI

T_D2

T_D3

SDO

Figure 3. 4-Wire SPI Serial Interface Timing

18

Rev. 1.0

Si5341/40

Table 11. SPI Timing Specifications (3-Wire)

(V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C)

Parameter

SCLK Frequency

Symbol

Min

—

40

50

—

5

Typ

—

Max

20

60

—

Units

MHz

%

f

SPI

SCLK Duty Cycle

T

—

DC

SCLK Period

T

—

ns

C

Delay Time, SCLK Fall to SDIO Turn-on

Delay Time, SCLK Fall to SDIO Next-bit

Delay Time, CS Rise to SDIO Tri-State

Setup Time, CS to SCLK

T

12.5

10

—

20

15

—

ns

D1

D2

D3

ns

T

ns

SU1

Hold Time, CS to SCLK Rise

Setup Time, SDI to SCLK Rise

Hold Time, SDI to SCLK Rise

Delay Time Between Chip Selects (CS)

T

5

—

ns

H1

T

5

—

ns

SU2

T

5

—

ns

H2

CS

T

2

—

T

C

T_SU1

T_C

SCLK

T_H1

T_D1

T_D2

CS

T_SU2

T_H2

T_CS

SDIO

T_D3

Figure 4. 3-Wire SPI Serial Interface Timing

Rev. 1.0

19

Si5341/40

Table 12. Crystal Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Crystal Frequency Range

f

Frequency range for

48

—

54

MHz

XTAL_48-54

best jitter performance

Load Capacitance

C

—

8

—

2

pF

L_48-54

O_48-54

L_48-54

Shunt Capacitance

Crystal Drive Level

Equivalent Series Resistance

Crystal Frequency Range

Load Capacitance

C

d

—

200

µW

r

Refer to the Si5341/40 Family Reference Manual to determine ESR.

ESR_48-54

f

—

25

8

—

MHz

pF

XTAL_25

C

L_25

O_25

L_25

Shunt Capacitance

Crystal Drive Level

Equivalent Series Resistance

Notes:

C

d

—

3

pF

200

µW

r_{ESR_25}

Refer to the Si5341/40 Family Reference Manual to determine ESR

1. The Si5341/40 is designed to work with crystals that meet the specifications in Table 12.

2. Refer to the Si5341/40 Family Reference Manual for recommended 48 to 54 MHz crystals.

20

Rev. 1.0

Si5341/40

Table 13. Thermal Characteristics

Test Condition^*

Parameter

Symbol

Value

Units

Si5341 — 64QFN

Thermal Resistance

Junction to Ambient



Still Air

22

°C/W

JA

Air Flow 1 m/s

Air Flow 2 m/s

19.4

18.3

9.5

Thermal Resistance

Junction to Case



JC

Thermal Resistance

Junction to Board



9.4

9.3

0.2

JB



JB

Thermal Resistance



JT

Junction to Top Center

Si5340–44QFN

Thermal Resistance

Junction to Ambient



Still Air

22.3

19.4

18.4

10.9

°C/W

JA

Air Flow 1 m/s

Air Flow 2 m/s

Thermal Resistance

Junction to Case



JC

Thermal Resistance

Junction to Board



9.3

9.2

JB



JB

Thermal Resistance



0.23

JT

Junction to Top Center

*Note: Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via under GND pad: 36, Number of Cu

Layers: 4

Rev. 1.0

21

Si5341/40

Table 14. Absolute Maximum Ratings^1,2,3,4

Parameter

Storage Temperature Range

DC Supply Voltage

Symbol

Test Condition

Value

Units

°C

V

T

–55 to +150

–0.5 to 3.8

–0.85 to 3.8

–0.5 to 3.8

STG

V

DD

V

DDA

DDO

V

Input Voltage Range

V

IN0-IN2, FB_IN

V

I1

I2

IN_SEL[1:0],

RST,

V

OE,

SYNC,

I2C_SEL,

SDI,

SCLK,

A0/CS

A1,

SDA/SDIO

FINC/FDEC

V

XA/XB

–0.5 to 2.7

V

I3

Latch-up Tolerance

ESD Tolerance

LU

JESD78 Compliant

HBM

100 pF, 1.5 k

2.0

–55 to 150

260

kV

°C

Junction Temperature

Soldering Temperature

T

JCT

T

PEAK

4

(Pb-free profile)

Soldering Temperature Time at T

(Pb-free profile)

T

20-40

sec

PEAK

P

4

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

2. 64-QFN and 44-QFN packages are RoHS-6 compliant.

3. For MSL and more packaging information, go to www.silabs.com/support/quality/pages/rohsinformation.aspx.

4. The device is compliant with JEDEC J-STD-020.

22

Rev. 1.0

Si5341/40

3. Typical Operating Characteristics

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ͲϭϴϬ͘ϬϬ

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ϭϬϬ

ϭŬ

ϭϬŬ

ϭD

ϭϬD

Figure 5. Integer Mode—48 MHz Crystal, 625 MHz Output (2.5 V LVDS)

Rev. 1.0

23

Si5341/40

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ϭϬD

Figure 6. Integer Mode—48 MHz Crystal, 156.25 MHz Output (2.5 V LVDS)

24

Rev. 1.0

Si5341/40

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Figure 7. Fractional Mode—48 MHz Crystal, 155.52 MHz Output (2.5 V LVDS)

Rev. 1.0

25

Si5341/40

4. Detailed Block Diagrams

3

IN_SEL[1:0]

Si5341

Dividers/

Drivers

Clock

Generator

VDDO0

OUT0

IN0

÷P₀

÷R₀

÷R₁

÷R₂

÷R₃

÷R₄

÷R₅

÷R₆

÷R₇

÷R₈

÷R₉

IN0

PLL

PD

VDDO1

OUT1

IN1

÷P₁

IN1

IN2

VDDO2

OUT2

÷P₂

LPF

IN2

M_n

÷

VDDO3

OUT3

M_d

VDDO4

OUT4

P

XAXB

÷

MultiSynth

N_0n

XB

XA

25MHz,

48-54MHz

XTAL

VDDO5

OUT5

÷

t₀

OSC

N_0d

N_1n

N_1d

t₁

t₂

VDDO6

OUT6

Zero Delay

Mode

N_2n

N_2d

VDDO7

OUT7

FB_IN

÷P_fb

N_3n

N_3d

VDDO8

OUT8

t₃

t₄

N_4n

N_4d

I2C_SEL

VDDO9

OUT9

SDA/SDIO

A1/SDO

SCLK

SPI/

I²C

NVM

Frequency

Control

Status

Monitors

A0/CS

Figure 8. Si5341 Block Diagram

26

Rev. 1.0

Si5341/40

2

4

Si5340

Clock

÷P_XAXB

OSC

Generator

XB

XA

25MHz,

48-54MHz

XTAL

Dividers/

Drivers

MultiSynth

N_n0

VDDO0

OUT0

÷

t₀

÷R₀

PLL

N_d0

VDDO1

OUT1

N_n1

N_d1

÷

÷R₁

÷R₂

÷R₃

t₁

t₂

IN0

LPF

PD

÷P₀

÷P₁

÷P₂

M_d

÷

IN0

VDDO2

OUT2

M_n

N_2n

N_2d

IN1

VDDO3

OUT3

IN2

N_3n

N_3d

t₃

IN_SEL[1:0]

Zero Delay

Mode

FB_IN

÷P_fb

SPI/

I²C

Status

Monitors

NVM

Figure 9. Si5340 Detailed Block Diagram

Rev. 1.0

27

Si5341/40

5. Functional Description

The Si5341/40 combines a wide band PLL with next generation MultiSynth technology to offer the industry’s most

versatile and high performance clock generator. The PLL locks to either an external crystal between XA/XB or to

an external clock connected to XA/XB or IN0,1,2. A fractional or integer multiplier takes the selected input clock or

crystal frequency up to a very high frequency that is then divided by the MultiSynth output stage to any frequency in

the range of 100 Hz to 712.5 MHz on each output. The MultiSynth stage can divide by both integer and fractional

values.The high-resolution fractional MultiSynth dividers enables true any-frequency input to any-frequency on any

of the outputs. The output drivers offer flexible output formats which are independently configurable on each of the

2

outputs. This clock generator is fully configurable via its serial interface (I C/SPI) and includes in-circuit

programmable non-volatile memory.

5.1. Power-up and Initialization

Once power is applied, the device begins an initialization period where it downloads default register values and

configuration data from NVM and performs other initialization tasks. Communicating with the device through the

serial interface is possible once this initialization period is complete. No clocks will be generated until the

initialization is done. There are two types of resets available. A hard reset is functionally similar to a device power-

up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state

including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft

reset bypasses the NVM download. It is simply used to initiate register configuration changes.

Hard Reset

bit asserted

RST

pin asserted

Power-Up

NVM download

Initialization

Soft Reset

bit asserted

Serial interface

ready

Figure 10. Si5341 Power-up and Initialization

28

Rev. 1.0

Si5341/40

5.2. Frequency Configuration

The phase-locked loop is fully contained and does not require external loop filter components to operate. Its

function is to phase lock to the selected input and provide a common reference to the MultiSynth high-performance

fractional dividers.

A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional

output integer dividers provide further frequency division by an even integer from 2 to (2^25)-2. The frequency

configuration of the device is programmed by setting the input dividers (P), the PLL feedback fractional divider (Mn/

Md), the MultiSynth fractional dividers (Nn/Nd), and the output integer dividers (R). Silicon Labs’ Clockbuilder Pro

configuration utility determines the optimum divider values for any desired input and output frequency plan.

5.3. Inputs

The Si5341/40 requires either an external crystal at its XA/XB pins or an external clock at XA/XB or IN0,1,2.

5.3.1. XA/XB Clock and Crystal Input

An internal crystal oscillator exists between pin XA and XB. When this oscillator is enabled, an external crystal

connected across these pins will oscillate and provide a clock input to the PLL. A crystal frequency of 25 MHz can

be used although crystals in the frequency range of 48 MHz to 54 MHz are recommended for best jitter

performance. Frequency offsets due to C mismatch can be adjusted using the frequency adjustment feature

L

which allows frequency adjustments of ±1000 ppm. The Si5341/40 Family Reference Manual provides additional

information on PCB layout recommendations for the crystal to ensure optimum jitter performance. Refer to

Table 12 for crystal specifications.

The Si5341/40 can also accommodate an external input clock instead of a crystal. This allows the use of crystal

oscillator (XO) instead of a XTAL. Selection between the external XTAL or input clock is controlled by register

configuration. The internal crystal load capacitors (C ) are disabled in the input clock mode. Refer to Table 3 for the

L

input clock requirements at XAXB. Both a single-ended or a differential input clock can be connected to the XA/XB

pins as shown in Figure 11. A P

54 MHz.

divider is available to accommodate external clock frequencies higher than

XAXB

Rev. 1.0

29

Si5341/40

DifferentialConnection

Single‐ended XO Connection

X1

nc

X2

nc

Note: 2.0 Vpp_se max

2xC_L

0.1 uf

XA

XB

XA

XB

OSC

XO with Clipped Sine Wave

Output

0.1 uf

2xC_L

Si5341/40

0.1 uf

Note: 2.5 Vpp diff max

Crystal Connection

X1

Single‐ended Connection

X1

nc

X2

nc

Note: 2.0 Vpp_se max

2xCL

2xC_L

CMOS Output

XA

0.1 uf

R1

XA

XB

XTAL

OSC

R2

XO VDD

3.3 V

2.5 V

R1

R2

0.1 uf

XB

X2

523 

442 

2xC_L



475

649

Si5341/40

1.8 V

158 

866 

Figure 11. XAXB External Crystal and Clock Connections

5.3.2. Input Clocks (IN0, IN1, IN2)

A differential or single-ended clock can be applied at IN2, IN1, or IN0. The recommended input termination

schemes are shown in Figure 12.

AC Coupled Differential

0.1 uf

50

Si5341/40

INx

50

0.1 uf

Differential

Driver LVDS,

LVPECL, CML

50

0.1 uf

AC Coupled LVCMOS or Single Ended

0.1 uf

Si5341/40

50

INx

3.3V, 2.5V, 1.8V

LVCMOS or Single

Ended Signal

0.1 uf

INx

Figure 12. Termination of Differential and LVCMOS Input Signals

30

Rev. 1.0

Si5341/40

5.3.3. Input Selection (IN0, IN1, IN2, XA/XB)

The active clock input is selected using the IN_SEL[1:0] pins or by register control. A register bit determines input

selection as pin or register selectable. There are internal pull ups on the IN_SEL pins.

Table 15. Manual Input Selection Using IN_SEL[1:0] Pins

IN_SEL[1:0]

Selected Input

0

1

0

1

0

1

IN0

IN1

IN2

XA/XB

5.4. Fault Monitoring

The Si5341/40 provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB,

FB_IN) and loss of lock (LOL) for the PLL. This is shown in Figure 13.

Si5341/40

IN0

LOS0

÷P₀

IN0

LOL

IN1

LOS1

÷P₁

IN1

PLL

PD LPF

IN2

LOS2

÷P₂

IN2

Mn

÷

Md

LOSXAB

XA

OSC

XB

FB_IN

LOSFB

÷P_fb

FB_IN

Figure 13. LOS and LOL Fault Monitors

5.4.1. Status Indicators

The state of the status monitors are accessible by reading registers through the serial interface or with dedicated

pin (LOL). Each of the status indicator register bits has a corresponding sticky bit in a separate register location.

Once a status bit is asserted its corresponding sticky bit (_FLG) will remain asserted until cleared. Writing a logic

zero to a sticky register bit clears its state.

5.4.2. Interrupt Pin (INTR)

An interrupt pin (INTR) indicates a change in state with any of the status registers. All status registers are maskable

to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the status registers.

Rev. 1.0

31

Si5341/40

5.5. Outputs

The Si5341 supports 10 differential output drivers which can be independently configured as differential or

LVCMOS. The Si5340 supports 4 output drivers independently configurable as differential or LVCMOS.

5.5.1. Output Signal Format

The differential output amplitude and common mode voltage are both fully programmable and compatible with a

wide variety of signal formats including LVDS and LVPECL. In addition to supporting differential signals, any of the

outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs, or

any combination of differential and single-ended outputs.

5.5.2. Differential Output Terminations

The differential output drivers support both ac-coupled and dc-coupled terminations as shown in Figure 14.

AC Coupled LVDS/LVPECL

DC Coupled LVDS

V_DDO= 3.3V, 2.5V, 1.8V

50

OUTx

100

50

Internally

self-biased

Si5341/40

AC Coupled LVPECL/CML

DC Coupled LVCMOS

3.3V, 2.5V, 1.8V

LVCMOS

VDD – 1.3V

V

_DDO= 3.3V, 2.5V, 1.8V

V_DDO= 3.3V, 2.5V

50

Rs

OUTx

50

OUTx

Si5341/40

AC Coupled HCSL

VDD_RX

V_DDO= 3.3V, 2.5V, 1.8V

R1

R2

OUTx

50

Standard

HCSL

Receiver

Option 1

For V_CM= 0.37 V

Si5341/40

R2

VDD_RX

R1

R2

442 Ohms 56.2 Ohms

332 Ohms 59 Ohms

243 Ohms 63.4 Ohms

3.3 V

2.5 V

1.8 V

Figure 14. Supported Differential Output Terminations

32

Rev. 1.0

Si5341/40

5.5.3. Differential Output Modes

There are two selectable* differential output modes: Normal and Low Power. Each output can support a unique

mode. In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these

signaling standards.

 Differential Normal Mode: When an output driver is configured in normal mode, its output amplitude is

selectable as one of 7 settings ranging from ~130 mVpp_se to ~920 mVpp_se in increments of ~100 mV. See

Appendix A for additional information. The output impedance in the normal mode is 100 differentialAny of

the terminations shown in Figure 14 are supported in this mode.

 Differential Low Power Mode: When an output driver is configured in low power mode, its output amplitude is

configurable as one of 7 settings ranging from ~200 mVpp_se to ~1600 mVpp_se in increments of ~200 mV.

When in Differential Low Power Mode, the output impedance of the driver is much greater than 100 however

the signal integrity will still be optimum as long as the differential clock traces are properly terminated in their

characteristic impedance. Any of the terminations shown in Figure 14 are supported in this mode.

*Note: Not all amplitude levels are available for selection in the CBPro device configuration Wizard. Refer to Sections 5.9 and

5.10 for more information. See also Appendix A of the Si5341/40 Reference Manual.

5.5.4. Programmable Common Mode Voltage For Differential Outputs

The common mode voltage (V ) for the differential Normal and Low Power modes are programmable so that

CM

LVDS specifications can be met and for the best signal integrity with different supply voltages. When dc coupling

the output driver it is essential that the receiver should have a relatively high common mode impedance so that the

common mode current from the output driver is very small.

5.5.5. LVCMOS Output Terminations

LVCMOS outputs are typically dc-coupled as shown in Figure 15.

DC Coupled LVCMOS

3.3V, 2.5V, 1.8V

LVCMOS

V_DDO= 3.3V, 2.5V, 1.8V

50

Rs

OUTx

50

Figure 15. LVCMOS Output Terminations

Rev. 1.0

33

Si5341/40

5.5.6. LVCMOS Output Impedance And Drive Strength Selection

Each LVCMOS driver has a configurable output impedance. It is highly recommended that the minimum output

impedance (strongest drive setting) is selected and a suitable series resistor (Rs) is chosen to match the trace

impedance.

Table 16. Nominal Output Impedance vs OUTx_CMOS_DRV (register)

CMOS_DRIVE_Selection

VDDO

3.3 V

2.5 V

1.8 V

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

38 

43 

—

30 

35 

46 

22 

24 

31 

*Note: Refer to the Si5341/40 Family Reference Manual for more information on register settings.

5.5.7. LVCMOS Output Signal Swing

The signal swing (V /V ) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output

OL OH

driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

5.5.8. LVCMOS Output Polarity

When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTx). By

default the clock on the OUTx pin is generated with complementary polarity with the clock on the OUTx pin. The

LVCMOS OUTx and OUTx outputs can also be generated in phase.

5.5.9. Output Enable/Disable

The OE pin provides a convenient method of disabling or enabling the output drivers. When the OE pin is held high

all outputs will be disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be

individually disabled through register control.

5.5.10. Output Driver State When Disabled

The disabled state of an output driver is configurable as: disable low or disable high.

5.5.11. Synchronous/Asynchronous Output Disable Feature

Outputs can be configured to disable synchronously or asynchronously. The default state is synchronous output

disable. In synchronous disable mode the output will wait until a clock period has completed before the driver is

disabled. This prevents unwanted runt pulses from occurring when disabling an output. In asynchronous disable

mode the output clock will disable immediately without waiting for the period to complete.

34

Rev. 1.0

Si5341/40

5.5.12. Output Delay Control (t₀– t₄)

The Si5341/40 uses independent MultiSynth dividers (N - N ) to generate up to 5 unique frequencies to its 10

0

4

outputs through a crosspoint switch. By default all clocks are phase aligned. A delay path (t - t ) associated with

0

4

each of these dividers is available for applications that need a specific output skew configuration. Each delay path

is controlled by a register parameter call Nx_DELAY with a resolution of ~0.28 ps over a range of ~±9.14 ns. This is

useful for PCB trace length mismatch compensation. After the delay controls are configured, the soft reset bit

SOFT_RST must be set high so that the output delay takes effect and the outputs are re-aligned.

VDDO0

OUT0

÷R₀

t₀

t₁

t₂

t₃

t₄

÷N₀

÷N₁

÷N₂

÷N₃

÷N₄

VDDO1

OUT1

÷R₁

÷R₂

÷R₃

÷R₄

÷R₅

÷R₆

÷R₇

÷R₈

VDDO2

OUT2

VDDO3

OUT3

VDDO4

OUT4

VDDO5

OUT5

VDDO6

OUT6

VDDO7

OUT7

VDDO8

OUT8

VDDO9

OUT9

÷R₉

Figure 16. Example of Independently Configurable Path Delays

All delay values are restored to their NVM programmed values after power-up or after a hard reset. Delay default

values can be written to the NVM allowing a custom delay offset configuration at power-up or after a hardware

reset.

Rev. 1.0

35

Si5341/40

5.5.13. Zero Delay Mode

A zero delay mode is available for applications that require fixed and consistent minimum delay between the

selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through

software configuration and closing the loop externally as shown in Figure 17. This helps to cancel out the internal

delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed

back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to

minimize the input-to-output delay. It is recommended to connect OUT9 (Si5341) or OUT3 (Si5340) to FB_IN for

external feedback. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A

differential external feedback path connection is necessary for best performance.

VDDO0

OUT0

Si5341

VDDO1

OUT1

IN0

P

÷

0

f_IN

IN1

VDDO2

OUT2

P

1

IN2

P₂

VDDO3

OUT3

IN_SEL[1:0]

MultiSynth

& Dividers

PLL

Zero Delay

Mode

FB_IN

PD

VDDO7

OUT7

f_FB= f_IN

LPF

P

÷

fb

M_n

VDDO8

OUT8

÷

M_d

VDDO9

N_9n

N_9d

OUT9

÷

÷R₉

External Feedback Path

Figure 17. Si5341 Zero Delay Mode Setup

5.5.14. Sync Pin (Synchronizing R Dividers)

All the output R dividers are reset to the default NVM register state after a power-up or a hard reset. This ensures

consistent and repeatable phase alignment across all output drivers to within ±100 ps of the expected value from

the NVM download. Resetting the device using the RST pin or asserting the hard reset bit will have the same

result. The SYNC pin provides another method of re-aligning the R dividers without resetting the device, however,

the outputs will only align to within 50 ns when using the SYNC pin. This pin is positive edge triggered. Asserting

the sync register bit provides the same function as the SYNC pin. A soft reset will align the outputs to within

±100 ps of the expected value based upon the Nx_DELAY parameter.

5.5.15. Output Crosspoint

The output crosspoint allows any of the N dividers to connect to any of the clock outputs.

36

Rev. 1.0

Si5341/40

5.5.16. Digitally Controlled Oscillator (DCO) Modes

Each MultiSynth can be digitally controlled to so that all outputs connected to the MultiSynth change frequency in

real time without any transition glitches. There are two ways to control the MultiSynth to accomplish this task:

Use the Frequency Increment/Decrement Pins or register bits

Write directly to the numerator of the MultiSynth divider.

An output that is controlled as a DCO is useful for simple tasks such as frequency margining or CPU speed control.

The output can also be used for more sophisticated tasks such as FIFO management by adjusting the frequency of

the read or write clock to the FIFO or using the output as a variable Local Oscillator in a radio application.

5.5.16.1. DCO with Frequency Increment/Decrement Pins/Bits

Each of the MultiSynth fractional dividers can be independently stepped up or down in predefined steps with a

resolution as low as 0.001 ppb. Setting of the step size and control of the frequency increment or decrement is

accomplished by setting the step size with the 44 bit Frequency Step Word (FSTEPW). When the FINC or FDEC

pin or register bit is asserted the output frequency will increment or decrement respectivley by the amount specified

in the FSTEPW.

5.5.16.2. DCO with Direct Register Writes

When a MultiSynth numerator and its corresponding update bit is written, the new numerator value will take effect

and the output frequency will change without any glitches. The MultiSynth numerator and denominator terms can

be left and right shifted so that the least significant bit of the numerator word represents the exact step resolution

that is needed for your application.

5.6. Power Management

Several unused functions can be powered down to minimize power consumption. Consult the Si5341/40 Family

Reference Manual and ClockBuilder Pro configuration utility for details.

5.7. In-Circuit Programming

2

The Si5341/40 is fully configurable using the serial interface (I C or SPI). At power-up the device downloads its

default register values from internal non-volatile memory (NVM). Application specific default configurations can be

written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to

NVM is in-circuit programmable with normal operating power supply voltages applied to its V and V

pins. The

DD

DDA

NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer

accessible. Refer to the Si5341/40 Family Reference Manual for a detailed procedure for writing registers to NVM.

5.8. Serial Interface

2

Configuration and operation of the Si5341/40 is controlled by reading and writing registers using the I C or SPI

interface. The I2C_SEL pin selects I C or SPI operation. Communication with both 3.3V and 1.8V host is

2

supported. The SPI mode operates in either 4-wire or 3-wire. See the Si5341/40 Family Reference Manual for

details.

5.9. Custom Factory Preprogrammed Devices

For applications where a serial interface is not available for programming the device, custom pre-programmed

parts can be ordered with a specific configuration written into NVM. A factory pre-programmed device will generate

clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part

number wizard (www.silabs.com/clockbuilderpro) to quickly and easily request and generate a custom part number

for your configuration. In less than three minutes, you will be able to generate a custom part number with a detailed

data sheet addendum matching your design’s configuration. Once you receive the confirmation email with the data

sheet addendum, simply place an order with your local Silicon Labs sales representative. Samples of your pre-

programmed device will ship to you typically within two weeks.

Rev. 1.0

37

Si5341/40

5.10. Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro

for Factory Pre-programmed Devices

As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at

www.silabs.com and opting in for updates to software, you will be notified whenever changes are made and what

the impact of those changes are. This update process will ultimately enable ClockBuilder Pro users to access all

features and register setting values documented in this data sheet and the Si5341/40 Family Reference Manual.

However, if you must enable or access a feature or register setting value so that the device starts up with this

feature or a register setting, but the feature or register setting is NOT yet available in CBPro, you must contact a

Silicon Labs applications engineer for assistance. An example of this type of feature or custom setting is the

customizable amplitudes for the clock outputs. After careful review of your project file and custom requirements, a

Silicon Labs applications engineer will email back your CBPro project file with your specific features and register

settings enabled, using what is referred to as the manual "settings override" feature of CBPro. "Override" settings

to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro design

report are shown below:

Setting Overrides

Location

Customer Name

Engineering Name

Type

Target

Dec

Hex

Value Value

0x0435[0] FORCE_HOLD_PLLA

0x0B48[0:4] OOF_DIV_CLK_DIS

OLA_HO_FORCE

No NVM

User

N/A

1

0

0x1

OOF_DIV_CLK_DIS

OPN & EVB

0x00

Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will

begin operation after startup with the values in the NVM file, including the Silicon Labs-supplied override settings.

Place sample

Start

order

Do I need a

pre‐programmed device

with a feature or setting

which is unavailable in

ClockBuilder Pro?

Generate

Custom OPN

in CBPro

Configure device

using CBPro

No

Yes

Contact Silicon Labs

Technical Support

to submit & review

your

Yes

non‐standard

configuration

request & CBPro

project file

Receive

updated CBPro

project file

from

Silicon Labs

with “Settings

Override”

Does the updated

CBPro Project file

match your

Load project file

into CBPro and test

requirements?

Figure 18. Flowchart to Order Custom Parts with Features not Available in CBPro

38

Rev. 1.0

Si5341/40

6. Register Map

The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains

frequently accessible registers such as alarm status, resets, device identification, etc. Other pages contain

registers that need less frequent access such as frequency configuration, and general device settings. A high level

map of the registers is shown in section “6.2. High-Level Register Map” . Refer to the Si5341/40 Family Reference

Manual for a complete list of registers descriptions and settings.

6.1. Addressing Scheme

The device registers are accessible using a 16-bit address which consists of an 8-bit page address + 8-bit register

address. By default the page address is set to 0x00. Changing to another page is accomplished by writing to the

‘Set Page Address’ byte located at address 0x01 of each page.

6.2. High-Level Register Map

Table 17. High-Level Register Map

16-Bit Address

Content

8-bit Page

8-bit Register

Address

Address Range

00

01

Revision IDs

Set Page Address

Device IDs

02–0A

0B–15

17–1B

1C

Alarm Status

INTR Masks

Reset controls

2C–E1

E2–E4

FE

Alarm Configuration

NVM Controls

Device Ready Status

Set Page Address

Output Driver Controls

Output Driver Disable Masks

Device Ready Status

01

08–3A

41–42

FE

Rev. 1.0

39

Si5341/40

Table 17. High-Level Register Map (Continued)

16-Bit Address

Content

8-bit Page

Address

8-bit Register

Address Range

02

01

02–05

08–2F

30

Set Page Address

XTAL Frequency Adjust

Input Divider (P) Settings

Input Divider (P) Update Bits

PLL Feedback Divider (M) Settings

PLL Feedback Divider (M) Update Bit

Output Divider (R) Settings

User Scratch Pad Memory

Device Ready Status

35–3D

3E

47–6A

6B–72

FE

03

01

Set Page Address

02–37

0C

MultiSynth Divider (N0–N4) Settings

MultiSynth Divider (N0) Update Bit

MultiSynth Divider (N1) Update Bit

MultiSynth Divider (N2) Update Bit

MultiSynth Divider (N3) Update Bit

MultiSynth Divider (N4) Update Bit

FINC/FDEC Settings N0–N4

Output Delay (t) Settings

Frequency Readback N0–N4

Device Ready Status

17

22

2D

38

39–58

59–62

63–94

FE

04–08

09

00–FF

01

Reserved

Set Page Address

49

Input Settings

1C

Zero Delay Mode Settings

Reserved

A0–FF

00–FF

40

Rev. 1.0

Si5341/40

7. Pin Descriptions

Si5340 44QFN

Top View

Si5341 64QFN

Top View

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

IN1

FINC

LOL

1

2

33

IN1

INTR

3

IN_SEL0

IN_SEL1

SYNC

RST

VDD

32

VDD

4

OUT6

VDDO6

OUT5

VDDO5

I2C_SEL

OUT4

VDDO4

OUT3

VDDO3

3

31

30

29

28

27

26

25

24

23

OUT2

IN_SEL0

5

4

OUT2

X1

XA

6

5

VDDO2

LOS_XAXB

LOL

7

X1

GND

Pad

6

XB

XA

8

GND

Pad

7

X2

9

XB

VDDS

OUT1

8

VDDA

10

11

X2

9

VDDA

IN2

OE

10

11

OUT1

INTR 12

VDDO1

13

VDDA

IN2

14

15

IN2

SCLK 16

Rev. 1.0

41

Si5341/40

Table 18. Pin Descriptions

Pin Type¹

Pin Number

Si5341 Si5340

Pin Name

Function

Inputs

XA

8

9

5

6

I

Crystal and External Clock Input

These pins are used to connect an external crystal or an external

clock. See section “5.3.1. XA/XB Clock and Crystal Input” and

“Figure 11. XAXB External Crystal and Clock Connections” for

connection information. If IN_SEL[1:0] = 11b, then the XAXB input

is selected. If the XAXB input is not used and powered down, then

both inputs can be left unconnected. ClockBuilder Pro will power

down an input that is set as "Unused".

XB

X1

X2

7

4

7

I

XTAL Shield

Connect these pins directly to the XTAL ground pins. X1, X2, and

the XTAL ground pins must not be connected to the PCB ground

plane. DO NOT GROUND THE CRYSTAL GROUND PINS. Refer

to the Si5341/40 Family Reference Manual for layout guidelines.

These pins should be left disconnected when connecting XA/XB

pins to an external reference clock.

10

IN0

63

64

1

43

44

1

I

Clock Inputs

These pins accept both differential and single-ended clock sig-

nals. Refer to "5.3.2. Input Clocks (IN0, IN1, IN2)" on page 30 for

input termination options. These pins are high-impedance and

must be terminated externally. If both the INx and INx (with over-

strike) inputs are un-used and powered down, then both inputs

can be left floating. ClockBuilder Pro will power down an input that

is set as "Unused".

IN1

2

IN2

14

15

61

62

10

11

41

42

IN2

FB_IN

External Feedback Input

These pins are used as the external feedback input (FB_IN/

FB_IN) for the optional zero delay mode. See "5.5.13. Zero Delay

Mode" on page 36 for details on the optional zero delay mode. If

FB_IN and FB_IN (with overstrike) are un-used and powered

down, then both inputs can be left floating. ClockBuilder Pro will

power down an input that is set as "Unused".

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input

pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.

3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK

low.

42

Rev. 1.0

Si5341/40

Table 18. Pin Descriptions (Continued)

Pin Number

Pin Type¹

Pin Name

Function

Si5341 Si5340

Outputs

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

Notes:

24

23

28

27

31

30

35

34

38

37

42

41

45

44

51

50

54

53

59

58

20

19

25

24

31

30

36

35

—

O

Output Clocks

These output clocks support a programmable signal amplitude

when configured as a differential output. Desired output signal for-

mat is configurable using register control. Termination recommen-

dations are provided in "5.5.2. Differential Output Terminations"

on page 32 and "5.5.5. LVCMOS Output Terminations" on page

33. Unused outputs should be left unconnected.

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input

pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.

3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK

low.

Rev. 1.0

43

Si5341/40

Table 18. Pin Descriptions (Continued)

Pin Number

Si5341 Si5340

Pin Type¹

Pin Name

Function

Serial Interface

I2C_SEL

39

18

38

13

I

I2C Select²

2

This pin selects the serial interface mode as I C (I2C_SEL = 1) or

SPI (I2C_SEL = 0). This pin is internally pulled up by a ~ 20 k

resistor to the voltage selected by the IO_VDD_SEL register bit.

SDA/SDIO

I/O

Serial Data Interface²

This is the bidirectional data pin (SDA) for the I C mode, or the

2

bidirectional data pin (SDIO) in the 3-wire SPI mode, or the input

2

data pin (SDI) in 4-wire SPI mode. When in I C mode, this pin

must be pulled-up using an external resistor of at least 1 k. No

pull-up resistor is needed when in SPI mode.

A1/SDO

SCLK

17

16

15

14

I/O

Address Select 1/Serial Data Output²

In I C mode, this pin functions as the A1 address input pin and

does not have an internal pull up or pull down resistor. In 4-wire

SPI mode this is the serial data output (SDO) pin (SDO) pin and

drives high to the voltage selected by the IO_VDD_SEL pin.

2

I

Serial Clock Input²

This pin functions as the serial clock input for both I C and SPI

2

modes.This pin is internally pulled up by a ~20 k resistor to the

2

voltage selected by the IO_VDD_SEL register bit. In I C mode

this pin should have an external pull up of at least 1 k. No pull-up

resistor is needed when in SPI mode.

A0/CS

19

16

I

Address Select 0/Chip Select²

This pin functions as the hardware controlled address A0 in I C

2

mode. In SPI mode, this pin functions as the chip select input

(active low). This pin is internally pulled up by a ~20 k resistor to

the voltage selected by the IO_VDD_SEL register bit.

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input

pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.

3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK

low.

44

Rev. 1.0

Si5341/40

Table 18. Pin Descriptions (Continued)

Pin Number

Pin Type¹

Pin Name

Function

Si5341 Si5340

Control/Status

INTR

12

6

33

17

O

Interrupt²

This pin is asserted low when a change in device status has

occurred. This interrupt has a push pull output and should be left

unconnected when not in use.

RST

I

Device Reset²

Active low input that performs power-on reset (POR) of the

device. Resets all internal logic to a known state and forces the

device registers to their default values. Clock outputs are disabled

during reset. This pin is internally pulled up with a ~20 k resistor

to the voltage selected by the IO_VDD_SEL bit.

OE

11

47

—

12

—

27

I

Output Enable²

This pin disables all outputs when held high. This pin is internally

pulled low and can be left unconnected when not in use.

LOL

O

Loss Of Lock²

This output pin indicates when the DSPLL is locked (high) or out-

of-lock (low). An external pull up or pull down is not needed.

Loss Of Lock

This output pin indicates when the DSPLL is locked (high) or out-

of-lock (low). An external pull up or pull down is not needed. The

voltage on the VDDS pin sets the VOH/VOL for this pin. See

Table 6.

LOS_XAXB

SYNC

—

5

28

—

O

I

Loss Of Signal

This output pin indicates a loss of signal at the XA/XB pins.

Output Clock Synchronization²

An active low signal on this pin resets the output dividers for the

purpose of re-aligning the output clocks. For a tighter alignment of

the clocks, a soft reset should be applied. This pin is internally

pulled up with a ~20 k resistor to the voltage selected by the

IO_VDD_SEL bitand can be left unconnected when not in use.

FDEC

25

—

I

Frequency Decrement Pin²

This pin is used to step-down the output frequency of a selected

output. The affected output driver and its frequency change step

size is register configurable. This pin is internally pulled low with a

~20 k resistor and can be left unconnected when not in use.

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input

pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.

3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK

low.

Rev. 1.0

45

Si5341/40

Table 18. Pin Descriptions (Continued)

Pin Number

Si5341 Si5340

Pin Type¹

Pin Name

Function

FINC

48

—

I

Frequency Increment Pin²

This pin is used to step-up the output frequency of a selected out-

put. The affected output and its frequency change step size is reg-

ister configurable. This pin is internally pulled low with a ~20 k

resistor and can be left unconnected when not in use.

IN_SEL0

IN_SEL1

3

4

3

I

Input Reference Select²

The IN_SEL[1:0] pins are used in the manual pin controlled mode

to select the active clock input as shown in Table 15. These pins

are internally pulled up with a ~20 k resistor to the voltage

selected by the IO_VDD_SEL bit and can be left unconnected

when not in use.

37

RSVD

20

21

55

56

—

22

—

Reserved

These pins are connected to the die. Leave disconnected.

NC

No Connect

These pins are not connected to the die. Leave disconnected.

Power

VDD

32

46

60

—

13

—

21

32

39

40

8

P

Core Supply Voltage

The device core operates from a 1.8 V supply. A 1.0 µf bypass

capacitor is recommended

VDDA

VDDS

P

Core Supply Voltage 3.3 V

This core supply pin requires a 3.3 V power source.

A 1.0 µf bypass capacitor is recommended.

9

—

26

P

Status Output Voltage

The voltage on this pin determines the V /V on LOL and

OL OH

LOS_XAXB status output pins.

A 0.1 µf to 1.0 µf bypass capacitor is recommended.

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input

pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.

3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK

low.

46

Rev. 1.0

Si5341/40

Table 18. Pin Descriptions (Continued)

Pin Number

Pin Type¹

Pin Name

Function

Output Clock Supply Voltage 0–9

Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTx, OUTx outputs.

See the Si5341/40 Family Reference Manual for power supply fil-

tering recommendations.

Leave VDDO pins of unused output drivers unconnected. An

alternate option is to connect the VDDO pin to a power supply and

disable the output driver to minimize current consumption.

Si5341 Si5340

VDDO0

VDDO1

VDDO2

VDDO3

VDDO4

VDDO5

VDDO6

VDDO7

VDDO8

VDDO9

GND PAD

22

26

29

33

36

40

43

49

52

57

18

23

29

34

—

P

Ground Pad

This pad provides electrical and thermal connection to ground and

must be connected for proper operation. Use as many vias as

practical and keep the via length to an internal ground plan as

short as possible.

Notes:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation for the serial interface pins, control input

pins, and status output pins. Refer to the Si5341/40 Family Reference Manual for more information on register settings.

3. If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected and tie SDA/SDIO and SCLK

low.

Rev. 1.0

47

Si5341/40

8. Ordering Guide

Si534fg-Rxxxxx-GM

Timing product family

f = Clock generator family member (1, 0)

g = Device grade (A, B)

Product Revision*

Custom ordering part number (OPN) sequence ID**

Package, ambient temperature range (QFN, -40°C to +85°C)

*See Ordering Guide table for current product revision

** 5 digits; assigned by ClockBuilder Pro

Ordering

Part Number

(OPN)

Number of

Input/Output Frequency Range

Output Clock

Frequency

Synthesis Mode

Temperature

Range

Package

Clocks

(MHz)

Si5341

1,2

Si5341A-B-GM

Si5341B-B-GM

Si5341C-B-GM

Si5341D-B-GM

0.0001 to 712.5 MHz

0.0001 to 350 MHz

0.0001 to 712.5 MHz

0.0001 to 350 MHz

Integer and

fractional mode

1,2

64-Lead

9x9 QFN

4/10

–40 to 85 °C

Integer mode only

Si5340

1,2

Si5340A-B-GM

Si5340B-B-GM

Si5340C-B-GM

Si5340D-B-GM

Si5341/40-EVB

Si5341-EVB

0.0001 to 712.5 MHz

0.0001 to 350 MHz

0.0001 to 712.5 MHz

0.0001 to 350 MHz

Integer and

fractional mode

44-Lead

7x7 QFN

4/4

—

–40 to 85 °C

Integer Only

Evaluation

Board

—

Si5340-EVB

Notes:

1. Add an R at the end of the OPN to denote tape and reel ordering options.

2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by Silicon Labs and the

ClockBuilder Pro software utility.

3. Custom part number format is: e.g., Si5341A-Bxxxxx-GM, where “xxxxx” is a unique numerical sequence representing

the preprogrammed configuration.

4. See Sections 5.9 and 5.10 for important notes about specifying a preprogrammed device to use features or device

register settings not yet available in CBPro.

48

Rev. 1.0

Si5341/40

9. Package Outlines

9.1. Si5341 9x9 mm 64-QFN Package Diagram

Figure 19 illustrates the package details for the Si5341. Table 19 lists the values for the dimensions shown in the

illustration.

Figure 19. 64-Pin Quad Flat No-Lead (QFN)

Table 19. Package Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

A

A1

0.02

b

0.25

D

9.00 BSC

5.20

D2

e

5.10

5.30

0.50 BSC

9.00 BSC

5.20

E

E2

5.10

0.30

—

5.30

0.50

0.15

0.10

0.08

0.10

0.05

L

0.40

aaa

bbb

ccc

ddd

eee

Notes:

—

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

Rev. 1.0

49

Si5341/40

9.2. Si5340 7x7 mm 44-QFN Package Diagram

Figure 20 illustrates the package details for the Si5340. Table 20 lists the values for the dimensions shown in the

illustration.

Figure 20. 44-Pin Quad Flat No-Lead (QFN)

Table 20. Package Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

A

A1

0.02

b

0.25

D

7.00 BSC

5.20

D2

e

5.10

5.30

0.50 BSC

7.00 BSC

5.20

E

E2

5.10

0.30

—

5.30

0.50

0.15

0.10

0.08

0.10

L

0.40

aaa

bbb

ccc

ddd

Notes:

—

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

50

Rev. 1.0

Si5341/40

10. PCB Land Pattern

Figure 21 illustrates the PCB land pattern details for the devices. Table 21 lists the values for the dimensions

shown in the illustration.

Si5341

Si5340

Figure 21. PCB Land Pattern

Rev. 1.0

51

Si5341/40

Table 21. PCB Land Pattern Dimensions

Dimension

Si5341 (Max)

8.90

Si5340 (Max)

C1

C2

E

6.90

0.50

0.30

0.85

5.30

8.90

0.50

X1

Y1

X2

Y2

0.30

0.85

5.30

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least

Material Condition is calculated based on a fabrication Allowance of 0.05 mm.

Solder Mask Design

4. All metal pads are to be non-solder mask defined (NSMD). Clearance

between the solder mask and the metal pad is to be 60 µm minimum, all the

way around the pad.

Stencil Design

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls

should be used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter

pads.

8. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for

the center ground pad.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

52

Rev. 1.0

Si5341/40

11. Top Marking

Si5341g-

Rxxxxx-GM

YYWWTTTTTT

Si5340g-

Rxxxxx-GM

YYWWTTTTTT

e4

TW

e4

64-QFN

44-QFN

Figure 22. Si5341-40 Top Markings

Table 22. Si5341-40 Top Marking Explanation

Characters Description

Line

1

Si5341g-

Si5340g-

Base part number and Device Grade for Low Jitter, Any-Frequency, 10-

output Clock Generator.

Si5341: 10-output, 64-QFN

Si5340: 4-output, 44-QFN

g = Device Grade (A, B, C, D). See "8. Ordering Guide" on page 48 for

more information.

– = Dash character.

2

Rxxxxx-GM

R = Product revision. (See ordering guide for current revision).

xxxxx = Customer specific NVM sequence number. Optional NVM code

assigned for custom, factory pre-programmed devices.

Characters are not included for standard, factory default configured

devices. See Ordering Guide for more information.

–GM = Package (QFN) and temperature range (–40 to +85 °C)

3

4

YYWWTTTTTT

YYWW = Characters correspond to the year (YY) and work week (WW)

of package assembly.

TTTTTT = Manufacturing trace code.

Circle w/ 1.6 mm (64-QFN) Pin 1 indicator; left-justified

or 1.4 mm (44-QFN)

diameter

e4

Pb-free symbol; Center-Justified

TW

TW = Taiwan; Country of Origin (ISO Abbreviation)

Rev. 1.0

53

Si5341/40

12. Device Errata

Please log in or register at www.silabs.com to access the device errata document.

54

Rev. 1.0

Si5341/40

DOCUMENT CHANGE LIST

Revision 0.9 to Revision 0.95

Removed advanced product information

revision history.

Updated Ordering Guide and changed

references to revision B

Updated parametric Tables 2,3,5,6,7,8 to reflect

production characterization

Updated terminology to align with ClockBuilder

Pro software

2

Table 9: I C data hold time specification

corrected to 100 ns from 5 µs

Revision 0.95 to Revision 1.0

General updates to typos in Tables 2,3,4,5,8,11,

and 12.

Changed Vin_diff minimum value in Table 3 to

be the same as Vin_se.

Added crosstalk spec for Si5340 to Table 5.

Changed the schematic for AC Test

Configuration in Table 7.

Changed the PLL lock time in Table 8.

Added a spec to Table 8 for the VCO frequency

range.

Changed the "Delay Time Between Chip

Selects" to be 2.0 clock periods.

Changed Note 2 in Table 12 as only 25 and 48–

54 Mhz crystals are supported.

2

Changed the timing specs for I C and SPI.

Added a 1.0 µf bypass capacitor

recommendation to be consistent with the

reference manual.

Updated output-to-output skew spec.

Rev. 1.0

55

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers

using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific

device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories

reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy

or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply

or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific

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型号：	SI5340B-B05212-GMR
厂家：	SILICON
描述：	Processor Specific Clock Generator,
文件：	总56页 (文件大小：2501K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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