SI5342A-B03868-GMR [SILICON]
Processor Specific Clock Generator,;型号: | SI5342A-B03868-GMR |
厂家: | SILICON |
描述: | Processor Specific Clock Generator, 时钟 外围集成电路 晶体 |
文件: | 总60页 (文件大小:1365K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si5345/44/42
10-CHANNEL, ANY-FREQUENCY, ANY-OUTPUT JITTER
ATTENUATOR/CLOCK MULTIPLIER
Features
Generates any combination of output
frequencies from any input frequency
Input frequency range:
Differential: 8 kHz to 750 MHz
LVCMOS: 8 kHz to 250 MHz
Output frequency range:
Differential: up to 712.5 MHz
LVCMOS: up to 250 MHz
Ultra-low jitter:
<100 fs typ (12 kHz–20 MHz)
Programmable jitter attenuation
bandwidth from 0.1 Hz to 4 kHz
Meets G.8262 EEC Opt 1, 2 (SyncE)
Highly configurable outputs compatible
with LVDS, LVPECL, LVCMOS, CML,
and HCSL with programmable signal
amplitude
Status monitoring (LOS, OOF, LOL)
Hitless input clock switching:
automatic or manual
Locks to gapped clock inputs
Automatic free-run and holdover
modes
Optional zero delay mode
Fastlock feature: 50 ms typ lock time
Glitchless on the fly output frequency
changes
DCO mode: as low as 0.001 ppb
steps.
Core voltage
V : 1.8 V ±5%
DD
V
: 3.3 V ±5%
DDA
Independent output supply pins: 3.3 V,
2.5 V, or 1.8 V
Output-output skew: <100 ps
2
Serial interface: I C or SPI
Ordering Information:
In-circuit programmable with
non-volatile OTP memory
See section 8
TM
ClockBuilder Pro software simplifies
Functional Block Diagram
device configuration
Si5345: 4 input, 10 output, 64 QFN
Si5344: 4 input, 4 output, 44 QFN
Si5342: 4 input, 2 output, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
XTAL
XB
Si5345/44/42
XA
IN_SEL
OSC
Device Selector Guide
÷FRAC
÷FRAC
÷FRAC
÷FRAC
IN0
IN1
IN2
Grade
Si534xA
Si534xB
Si534xC
Si534xD
Max Output Frequency Frequency Synthesis Modes
712.5 MHz
350 MHz
712.5 MHz
350 MHz
Integer+Fractional
Integer+Fractional
Integer
DSPLL
IN3/
FB_IN
Optional
External
Feedback
Integer
Applications
Multi
Synth
÷INT
OUT0
OUT1
OUT2
OTN Muxponders and Transponders Carrier Ethernet switches
10/40/100G networking line cards
GbE/10GbE/100GbE Synchronous
Ethernet (ITU-T G.8262)
SONET/SDH Line Cards
Broadcast video
Test and measurement
ITU-T G.8262 (SyncE) Compliant
Multi
Synth
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
Multi
Synth
Multi
Synth
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Description
Multi
Synth
These jitter attenuating clock multipliers combine fourth-generation DSPLL and
MultiSynth™ technologies to enable any-frequency clock generation and jitter
attenuation for applications requiring the highest level of jitter performance. These
devices are programmable via a serial interface with in-circuit programmable non-
volatile memory (NVM) so they always power up with a known frequency configuration.
They support free-run, synchronous, and holdover modes of operation, and offer both
automatic and manual input clock switching. The loop filter is fully integrated on-chip,
eliminating the risk of noise coupling associated with discrete solutions. Further, the
jitter attenuation bandwidth is digitally programmable, providing jitter performance
optimization at the application level. Programming the Si5345/44/42 is easy with
Silicon Labs’ ClockBuilderPro software. Factory preprogrammed devices are also
available.
NVM
I2C/SPI
Control/
Status
Preliminary Rev. 0.95 3/15
Copyright © 2015 by Silicon Laboratories
Si5345/44/42
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5345/44/42
TABLE OF CONTENTS
1. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.1. Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.2. DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.3. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.4. External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.5. Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.6. Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.7. Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.8. Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.9. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.10. In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.11. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.12. Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.13. Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for
Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
6.1. Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
6.2. High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8.1. Ordering Part Number Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
9. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
9.1. Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
9.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . .55
10. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
12. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2
Preliminary Rev. 0.95
Si5345/44/42
1. Typical Application Schematic
100 MHz (HCSL)
PCIe 3.0
133.333 MHz (CMOS)
CPU/NPU
Si5345
83.333 MHZ (CMOS)
50 MHz (CMOS)
DSPLL
100 MHz
FPGA/ASIC/
SWITCH
156.25 MHz (LVDS)
156.25 MHz (LVDS)
125 MHz
MultiSynth
19.44 MHz
MultiSynth
MultiSynth
156.525 MHz (LVDS)
155.52 MHz (LVDS)
2.048 MHz
10G PHY
10G PHY
MultiSynth
MultiSynth
125 MHz (LVPECL)
125 MHz (LVPECL)
1G PHY
1G PHY
Figure 1. 10G Ethernet Data Center Switch and Compute Blade Schematic
Preliminary Rev. 0.95
3
Si5345/44/42
2. Electrical Specifications
Table 1. Recommended Operating Conditions*
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%,TA = –40 to 85 °C)
Parameter
Ambient Temperature
Symbol
Min
–40
—
Typ
25
Max
85
Unit
°C
°C
V
T
A
Junction Temperature
Core Supply Voltage
TJ
—
125
MAX
V
1.71
3.14
3.14
2.38
1.71
3.14
1.71
1.80
3.30
3.30
2.50
1.80
3.30
1.80
1.89
3.47
3.47
2.62
1.89
3.47
1.89
DD
V
V
DDA
DDO
Clock Output Driver Supply Voltage
Status Pin Supply Voltage
V
V
V
V
V
V
DDS
V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
4
Preliminary Rev. 0.95
Si5345/44/42
Table 2. DC Characteristics
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
—
Typ
125
120
Max
185
125
Units
mA
1 2 3
Core Supply Current
I
Si5345,
Si5344,
Si5342
Notes , ,
DD
I
—
mA
DDA
4
Output Buffer Supply Current
I
LVPECL Output
—
—
—
—
—
21
15
21
16
12
25
17
25
18
13
mA
mA
mA
mA
mA
DDOx
@ 156.25 MHz
4
LVDS Output
@ 156.25 MHz
5
3.3 V LVCMOS output
@ 156.25 MHz
5
2.5 V LVCMOS output
@ 156.25 MHz
5
1.8 V LVCMOS output
@ 156.25 MHz
1 6
Total Power Dissipation
P
Si5345
Si5344
Si5342
Note ,
—
—
—
880
720
715
1040
850
mW
mW
mW
d
2 6
Note ,
3 6
Note ,
840
Notes:
1. Si5345 test configuration: 10x 3.3 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2. Si5344 test configuration: 4x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3. Si5342 test configuration: 2x 3.3 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
4. Differential outputs terminated into an AC coupled 100 load.
5. LVCMOS outputs measured into a 6 inch 50 PCB trace with 5 pF load. Measurements were made in CMOS3 mode.
Differential Output Test Configuration
LVCMOS Output Test Configuration
IDDO
IDDO
6 inch
0.1 uF
50
OUTa
OUT
50
100
OUTb
OUT
5 pF
50
0.1 uF
6. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board
(EVB) is not available. All EVBs support detailed current measurements for any configuration.
Preliminary Rev. 0.95
5
Si5345/44/42
Table 3. Input Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Standard Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1, IN2/IN2, IN3/IN3, FB_IN/FB_IN)
Input Frequency Range
Voltage Swing
f
Differential
10
10
—
—
—
750
250
MHz
MHz
IN_DIFF
Single-ended/LVCMOS
V
f < 400 MHz
100
3600
mVpp_se,
mVpp_diff
IN
in
400 MHz < f < 800 MHz
225
—
3600
mVpp_se,
mVpp_diff
in
1, 2
Slew Rate
SR
DC
400
40
—
—
2
—
60
—
V/µs
%
Duty Cycle
Capacitance
C
—
pF
IN
Pulsed CMOS - DC Coupled (IN0, IN1, IN2, IN3)
3
Input Frequency
f
0.008
–0.2
0.49
400
1.6
—
—
—
—
—
8
250
0.33
3.8
—
MHz
V
IN_PULSED_CMOS
3
Input Voltage
V
IL
V
V
IH
1, 2
Slew Rate
SR
V/µs
ns
Minimum Pulse Width
Input Resistance
PW
Pulse Input
—
R
—
—
k
IN
REFCLK (applied to XA/XB)
REFCLK Frequency
f
Frequency range for best
output jitter performance
48
—
—
54
—
MHz
MHz
IN_REF
TCXO frequency for
SyncE
40
applications. Jitter perfor-
mance may be reduced
Input Voltage Swing
V
365
350
400
—
2000
2500
—
mVpp_se
mVpp_diff
V/µs
IN
1, 2
Slew rate
SR
DC
Imposed for best
jitter performance
—
—
Input Duty Cycle
40
60
%
Notes:
1. Imposed for jitter performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 – 0.2) x VIN_Vpp_se) / SR
3. This mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, are dc-coupled, and have a duty cycle
significantly less than 50%. A typical application example is a low-frequency video frame sync pulse. Since the input
thresholds (VIL, VIH) of this buffer are non-standard (0.33 and 0.49 V, respectively) refer to the input attenuator circuit for
dc-coupled pulsed LVCMOS in the Family Reference Manual at: www.silabs.com/Support%20Documents/
TechnicalDocs/Si5345-44-42-RM.pdf. Otherwise, for standard LVCMOS input clocks, use the Standard Differential or
Single-Ended ac-coupled input mode.
4. A programmable internal divider (PREF) is available to help support REFCLK frequencies up to 200 MHz.
6
Preliminary Rev. 0.95
Si5345/44/42
Table 4. Control Input Pin Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Units
Si5345 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, A1, SCLK, A0/CS, FINC, FDEC)
*
Input Voltage
V
–0.1
0.7 x V
—
—
2
0.3 x V
V
V
IL
IH
IN
DDIO
*
V
C
I
3.6
—
—
—
DDIO
Input Capacitance
Input Resistance
—
—
50
pF
k
ns
20
—
L
Minimum Pulse Width
PW
RST, FINC and
FDEC
Update Rate
T
FINC and FDEC
1
—
—
ns
UR
Si5344/42 Control Input Pins (I2C_SEL, IN_SEL[1:0], RST, OE, A1, SCLK, A0/CS)
*
Input Voltage
V
–0.1
0.7 x V
—
—
2
0.3 x V
V
V
IL
IH
IN
DDIO
*
V
C
I
3.6
—
—
—
DDIO
Input Capacitance
Input Resistance
—
—
50
pF
k
ns
20
—
L
Minimum Pulse Width
PW
RST
*Note: VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5345/44/42 Family Reference
Manual for more details on the proper register settings.
Preliminary Rev. 0.95
7
Si5345/44/42
Table 5. Differential Clock Output Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Output Frequency
Symbol
Test Condition
Min
0.0001
48
Typ
—
—
—
20
0
Max
712.5
52
Units
MHz
%
f
OUT
Duty Cycle
DC
f < 400 MHz
400 MHz < f < 800 MHz
Differential Output
45
55
%
Output-Output Skew
OUT-OUT Skew
T
—
100
100
ps
SK
T
Measured from the positive to
negative output pins
—
ps
SK_OUT
1
Output Voltage Swing
Normal Mode
V
V
= 3.3 V
or
LVDS
350
660
470
810
550 mVpp_se
950
OUT
DDO
LVPECL
2.5 V or 1.8 V
Low-Power Mode
V
V
= 3.3 V
or
LVDS
300
620
420
820
530 mVpp_se
1060
OUT
DDO
2.5 V or 1.8 V
V
= 3.3 V
LVPECL
DDO
or 2.5 V
1,2
Common Mode Voltage
Normal Mode or Low-Power Mode
(100 Ω load line-to-line)
V
V
V
= 3.3 V
= 2.5 V
LVDS
1.10
1.90
1.15
1.25
2.05
1.25
1.30
2.10
1.30
V
CM
DDO
DDO
LVPECL
LVPECL
LVDS
Note:
1. For normal and low-power modes, the amplitude and common-mode settings are programmable through register
settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode
(or low-power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum.
2. Not all combinations of voltage swing and common mode voltages settings are possible. See the Si5345/44/42 Family
Reference Manual for details.
3. Driver output impedance depends on selected output mode (Normal, High).
4. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO
(1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and noise spur amplitude measured.
5. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor
at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure
Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring
crosstalk.
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
Vcm
OUTx
8
Preliminary Rev. 0.95
Si5345/44/42
Table 5. Differential Clock Output Specifications (Continued)
(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Normal Mode
Min
—
Typ
170
300
100
Hi-Z
Max
240
430
—
Units
Rise and Fall Times
(20% to 80%)
t /t
ps
R F
Low-Power Mode
Normal Mode
—
3
Differential Output Impedance
Z
—
O
Low Power Mode
—
—
4
Power Supply Noise Rejection
PSRR Normal Mode
10 kHz sinusoidal noise
—
—
—
—
–93
–93
–84
–79
—
—
—
—
dB
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
Low Power Mode
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
Measured spur from adjacent
—
—
—
—
—
–98
–95
–84
–76
–75
—
—
—
—
—
dB
dB
Output-output Crosstalk
XTALK
5
output
Note:
1. For normal and low-power modes, the amplitude and common-mode settings are programmable through register
settings and can be stored in NVM. Each output driver can be programmed independently. The typical normal mode
(or low-power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum.
2. Not all combinations of voltage swing and common mode voltages settings are possible. See the Si5345/44/42 Family
Reference Manual for details.
3. Driver output impedance depends on selected output mode (Normal, High).
4. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO
(1.8 V = 50 mVpp, 2.5 V/3.3 V = 100 mVpp) and noise spur amplitude measured.
5. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor
at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure
Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring
crosstalk.
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
Vcm
OUTx
Preliminary Rev. 0.95
9
Si5345/44/42
Table 6. LVCMOS Clock Output Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Output Frequency
Duty Cycle
Symbol
Test Condition
Min
0.0001
47
Typ
—
Max
250
53
Unit
MHz
%
f
OUT
DC
f
<100 MHz
—
OUT
100 MHz < f
< 250 MHz
44
—
55
OUT
Output-to-Output Skew
T
—
—
100
ps
V
SK
1, 2, 3
Output Voltage High
V
V
= 3.3 V
DDO
OH
OUTx_CMOS_DRV = 1
OUTx_CMOS_DRV = 2
OUTx_CMOS_DRV = 3
I
I
I
= –10 mA
= –12 mA
= –17 mA
V
V
V
x
x
x
—
—
—
—
—
—
OH
OH
DDO
0.85
OH
V
= 2.5 V
DDO
OUTx_CMOS_DRV = 1
OUTx_CMOS_DRV = 2
OUTx_CMOS_DRV = 3
I
I
= –6 mA
—
—
—
—
—
—
V
V
OH
OH
OH
DDO
0.85
= –8 mA
I
= –11 mA
V
= 1.8 V
DDO
OUTx_CMOS_DRV = 2
OUTx_CMOS_DRV = 3
I
= –4 mA
—
—
—
—
OH
OH
DDO
0.85
I
= –5 mA
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer
to the Si5345/44/42 Family Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 PCB trace. A 5 pF
capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
DC Test Configuration
Trace length 5 inches
499 Ohm
IOL/IOH
IDDO
50
Zs
OUT
OUT
4.7 pF
56 Ohm
56 Ohm
VOL/VOH
499 Ohm
50
4.7 pF
10
Preliminary Rev. 0.95
Si5345/44/42
Table 6. LVCMOS Clock Output Specifications (Continued)
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1, 2, 3
Output Voltage Low
V
V
= 3.3 V
DDO
OL
OUTx_CMOS_DRV=1
I
I
I
= 10 mA
—
—
—
—
—
—
V
V
OL
OL
OL
DDO
x 0.15
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
= 12 mA
= 17 mA
V
= 2.5 V
DDO
OUTx_CMOS_DRV=1
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
I
= 6 mA
= 8 mA
= 11 mA
—
—
—
—
—
—
V
V
OL
OL
OL
DDO
x 0.15
I
I
V
= 1.8 V
DDO
OUTx_CMOS_DRV=2
OUTx_CMOS_DRV=3
I
= 4 mA
= 5 mA
—
—
—
—
—
—
V
DDO
x 0.15
V
OL
OL
I
—
LVCMOS Rise and Fall
Times
tr/tf
VDDO = 3.3V
420
475
525
550
625
705
ps
ps
ps
3
VDDO = 2.5 V
VDDO = 1.8 V
(20% to 80%)
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer
to the Si5345/44/42 Family Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 PCB trace. A 5 pF
capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
DC Test Configuration
Trace length 5 inches
499 Ohm
IOL/IOH
IDDO
50
Zs
OUT
OUT
4.7 pF
56 Ohm
56 Ohm
VOL/VOH
499 Ohm
50
4.7 pF
Preliminary Rev. 0.95
11
Si5345/44/42
Table 7. Output Status Pin Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Si5345 Status Output Pins (LOL, INTR)
*
Output Voltage
V
I
I
I
I
= –2 mA
= 2 mA
V
V
x 0.75
—
—
—
V
V
OH
OH
DDIO
*
V
I
—
V
V
x 0.15
OL
OL
DDIO
Si5344 Status Output Pins (INTR)
Output Voltage
*
V
= –2 mA
= 2 mA
x 0.75
—
—
—
V
V
OH
OH
DDIO
*
V
I
—
x 0.15
OL
OL
DDIO
Si5344 Status Output Pins (LOL)
Output Voltage
V
= –2 mA
= 2 mA
V x 0.85
DDS
—
—
—
V
V
OH
OH
V
I
—
V
x 0.15
DDS
OL
OL
Si5342 Status Output Pins (INTR)
Output Voltage
1
V
= –2 mA
V
x 0.75
—
—
—
V
V
OH
OH
DDIO
*
VOL
Si5342 Status Output Pins (LOL, LOS0, LOS1, LOS2, LOS3, LOS_XAXB)
IOL = 2 mA
—
V
x 0.15
DDIO
Output Voltage
V
I
= –2 mA
= 2 mA
V x 0.85
DDS
—
—
—
V
V
OH
OH
V
I
—
V
x 0.15
DDS
OL
OL
*Note: VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. See the Si5345/44/42 Family Reference
Manual for more details on the proper register settings.
12
Preliminary Rev. 0.95
Si5345/44/42
Table 8. Performance Characteristics
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
PLL Loop Bandwidth Pro-
gramming Range
f
0.1
—
4000
Hz
BW
2
Initial Start-Up Time
t
Time from power-up to when the
—
30
45
ms
START
device generates free-running clocks
PLL Lock Time
t
With Fastlock enabled
—
—
—
—
—
50
0.28
71.8
±9.14
—
60
—
—
—
15
ms
ps
ACQ
Output Delay Adjustment
t
f
= 14 GHz
VCO
DELAY_frac
t
ps
DELAY_int
t
ns
ms
RANGE
POR to Serial Interface
t
RDY
1
Ready
Jitter Peaking
J
Measured with a frequency plan run-
ning a 25 MHz input, 25 MHz output,
and a Loop Bandwidth of 4 Hz
—
—
—
0.1
—
dB
PK
Jitter Tolerance
J
Compliant with G.8262 Options 1 and
2 Carrier Frequency = 10.3125 GHz
Jitter Modulation
3180
UI pk-pk
TOL
Frequency = 10 Hz
Maximum Phase Tran-
sient During a Hitless
Switch
t
Only valid for a single switch between
two input clocks running at the same
frequency
—
—
2.8
ns
SWITCH
Pull-in Range
—
—
—
500
2
—
—
—
ppm
ns
P
Input-to-Output Delay
Variation
t
IODELAY
t
In Zero Delay Mode. Measured as the
time delay difference between the ref-
erence input and the feedback input,
with both clocks running at 10 MHz
and having the same slew rate. The
rise time of the reference input should
not exceed 200 ps in order to guaran-
tee this spec.
110
ps
ZDELAY
3
RMS Phase Jitter
J
Integer Mode
12 kHz to 20 MHz
—
—
0.090 0.140 ps RMS
0.130 0.165 ps RMS
GEN
Fractional Mode
12 kHz to 20 MHz
Notes:
1. Measured as time from valid VDD/VDD33 rails (90% of their value) to when the serial interface is ready to respond to
commands. Measured in SPI 4-wire mode, SCLK = 10 MHz.
2. Actual loop bandwidth might be lower; please refer to CBPro for actual value for your frequency plan.
3. Jitter generation test conditions: fIN = 19.44 MHz, fOUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz.
Preliminary Rev. 0.95
13
Si5345/44/42
Table 9. I2C Timing Specifications (SCL,SDA)
Parameter
Symbol
Test Condition
Min
Max
Min
Fast Mode
400 kbps
Max
Units
Standard Mode
100 kbps
SCL Clock Frequency
SMBus Timeout
f
0
100
35
0
400
35
kHz
ms
SCL
—
When Timeout is
Enabled
25
25
Hold time (repeated)
START condition
t
t
4.0
4.7
4.0
4.7
—
—
—
—
0.6
1.3
0.6
0.6
—
—
—
—
µs
µs
µs
µs
HD:STA
Low period of the SCL
clock
t
LOW
HIGH period of the SCL
clock
t
HIGH
Set-up time for a
repeated START condi-
tion
SU:STA
Data hold time
t
100
250
—
—
—
100
100
20
—
—
ns
ns
ns
HD:DAT
Data set-up time
t
SU:DAT
Rise time of both SDA
and SCL signals
t
1000
300
r
Fall time of both SDA
and SCL signals
t
—
300
—
—
300
—
ns
µs
µs
f
Set-up time for STOP
condition
t
t
4.0
4.7
0.6
1.3
SU:STO
Bus free time between a
STOP and START con-
dition
t
—
—
BUF
Data valid time
—
—
3.45
3.45
—
—
0.9
0.9
µs
µs
VD:DAT
VD:ACK
Data valid acknowledge
time
t
14
Preliminary Rev. 0.95
Si5345/44/42
Figure 2. I2C Serial Port Timing Standard and Fast Modes
Preliminary Rev. 0.95
15
Si5345/44/42
Table 10. SPI Timing Specifications (4-Wire)
(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, TA = –40 to 85 °C)
Parameter
SCLK Frequency
Symbol
Min
—
Typ
—
Max
20
Units
MHz
%
f
SPI
SCLK Duty Cycle
T
40
—
—
60
DC
SCLK Rise & Fall Time
Tr/Tf
—
10
ns
SCLK High & Low Time
T
HL
SCLK Period
T
50
—
—
—
—
—
—
—
—
—
—
—
12.5
12.5
12.5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
Delay Time, SCLK Fall to SDO Active
Delay Time, SCLK Fall to SDO
Delay Time, CS Rise to SDO Tri-State
Setup Time, CS to SCLK
T
T
T
D1
D2
D3
—
—
T
25
SU1
Hold Time, CS to SCLK Rise
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CS)
T
25
—
H1
T
12.5
12.5
50
—
SU2
T
—
H2
T
—
CS
TSU1
TD1
TC
SCLK
CS
TH1
TSU2
TH2
TCS
SDI
TD2
TD3
SDO
Figure 3. 4-Wire SPI Serial Interface Timing
16
Preliminary Rev. 0.95
Si5345/44/42
Table 11. SPI Timing Specifications (3-Wire)
(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, TA = –40 to 85 °C)
Parameter
SCLK Frequency
Symbol
Min
—
Typ
—
Max
20
Units
MHz
%
f
SPI
SCLK Duty Cycle
T
40
—
—
60
DC
SCLK Rise & Fall Time
Tr/Tf
—
10
ns
SCLK High & Low Time
T
HL
SCLK Period
T
50
—
—
—
—
—
—
—
—
—
—
—
12.5
12.5
12.5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
Delay Time, SCLK Fall to SDIO Turn-on
Delay Time, SCLK Fall to SDIO Next-bit
Delay Time, CS Rise to SDIO Tri-State
Setup Time, CS to SCLK
T
T
T
D1
D2
D3
—
—
T
25
SU1
Hold Time, CS to SCLK Rise
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CS)
T
25
—
H1
T
12.5
12.5
50
—
SU2
T
—
H2
T
—
CS
TSU1
TC
SCLK
TH1
TD1
TD2
CS
TSU2
TH2
TCS
SDIO
TD3
Figure 4. 3-Wire SPI Serial Interface Timing
Preliminary Rev. 0.95
17
Si5345/44/42
Table 12. Crystal Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Crystal Frequency Range
f
Frequency range for
48
—
54
MHz
XTAL_48-54
best jitter performance
Load Capacitance
C
—
—
—
8
—
2
pF
pF
L_48-54
O_48-54
L_48-54
Shunt Capacitance
C
d
—
—
Crystal Drive Level
200
µW
Equivalent Series Resistance
r
Refer to the Si5345/44/42 Family Reference Manual to determine
ESR.
ESR_48-54
Crystal Frequency Range
Load Capacitance
f
—
—
—
—
25
8
—
—
MHz
pF
XTAL_25
C
L_25
O_25
L_25
Shunt Capacitance
C
d
—
—
3
pF
Crystal Drive Level
200
µW
rESR_25
Equivalent Series Resistance
Refer to the Si5345/44/42 Family Reference Manual to determine
ESR.
Notes:
1. The Si5345/44/42 is designed to work with crystals that meet the specifications in Table 12.
2. Refer to the Si5345/44/42 Family Reference Manual for recommended 48 to 54 MHz crystals. Crystal frequencies from
24.97 to 54.06 MHz are supported, but jitter performance is best from 48 to 54 MHz.
18
Preliminary Rev. 0.95
Si5345/44/42
Table 13. Thermal Characteristics
Parameter
*
Symbol
Value
Units
Test Condition
Si5345-64QFN
Thermal Resistance
Junction to Ambient
Still Air
22
°C/W
JA
Air Flow 1 m/s
Air Flow 2 m/s
19.4
18.3
9.5
Thermal Resistance
Junction to Case
JC
Thermal Resistance
Junction to Board
9.4
9.3
0.2
JB
JB
Thermal Resistance
JT
Junction to Top Center
Si5344, Si5342-44QFN
Thermal Resistance
Junction to Ambient
Still Air
22.3
19.4
18.4
10.9
°C/W
JA
Air Flow 1 m/s
Air Flow 2 m/s
Thermal Resistance
Junction to Case
JC
Thermal Resistance
Junction to Board
9.3
9.2
JB
JB
Thermal Resistance
0.23
JT
Junction to Top Center
*Note: Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via: 36, Number of Cu Layers: 4.
Preliminary Rev. 0.95
19
Si5345/44/42
Table 14. Absolute Maximum Ratings1,2,3,4
Parameter
Storage Temperature Range
DC Supply Voltage
Symbol
Test Condition
Value
Units
°C
V
T
–55 to +150
–0.5 to 3.8
–0.5 to 3.8
–0.5 to 3.8
–0.5 to 3.8
–0.85 to 3.8
–0.5 to 3.8
STG
V
DD
V
V
DDA
DDO
V
V
V
V
DDS
Input Voltage Range
V
V
IN0 – IN3/FB_IN
V
I1
I2
IN_SEL1, IN_SEL0, RST,
OE, I2C_SEL, FINC, FDEC,
SDI, SCLK, A0/CS, A1
V
V
XA/XB
–0.5 to 2.7
V
I3
Latch-up Tolerance
LU
JESD78 Compliant
ESD Tolerance
HBM
100 pF, 1.5 k
2.0
kV
Storage Temperature Range
Junction Temperature
Soldering Temperature
T
–55 to 150
–55 to 150
260
°C
°C
°C
STG
T
JCT
T
PEAK
TP
4
(Pb-free profile)
s
Soldering Temperature Time at T
20–40
PEAK
4
(Pb-free profile)
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. 64-QFN and 44-QFN packages are RoHS-6 compliant.
3. For more packaging information, including MSL rating, go to www.silabs.com/support/quality/pages/
RoHSInformation.aspx.
4. The device is compliant with JEDEC J-STD-020.
20
Preliminary Rev. 0.95
Si5345/44/42
3. Typical Operating Characteristics
The phase noise plots below were taken under the following conditions: V = 1.8 V, V
= 3.3 V, V = 3.3 V,
DDS
DD
DDA
1.8 V, and T = 25 °C.
A
Figure 5. Input = 25 MHz; Output = 625 MHz, 2.5 V LVDS
Figure 6. Input = 25 MHz; Output = 156.25 MHz, 2.5 V LVDS
Preliminary Rev. 0.95
21
Si5345/44/42
Figure 7. Input = 25 MHz; Output = 155.52 MHz, 2.5 V LVDS
22
Preliminary Rev. 0.95
Si5345/44/42
4. Detailed Block Diagrams
48-54MHz XTAL
or REFCLK
3
XA
XB
Si5345
OSC
IN_SEL[1:0]
÷PREF
IN0
IN0
IN1
IN1
P0n
÷
P0d
P1n
÷
DSPLL
P1d
PD LPF
P2n
÷
IN2
P2d
IN2
IN3/FB_IN
Mn
Md
P3n
÷
÷
Optional
External
IN3/FB_IN
P3d
Feedback
VDDO0
OUT0
OUT0
Multi
Synth
N0n
÷
t0
t1
t2
t3
t4
÷R0
N0d
VDDO1
OUT1
OUT1
Multi
Synth
N1n
÷
N1d
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
÷R9
VDDO2
OUT2
OUT2
Multi
Synth
N2n
÷
N2d
Multi
Synth
N3n
÷
VDDO3
OUT3
OUT3
N3d
Multi
Synth
N4n
÷
VDDO4
OUT4
OUT4
N4d
VDDO5
OUT5
OUT5
I2C_SEL
VDDO6
OUT6
OUT6
SDA/SDIO
A1/SDO
SCLK
SPI/
NVM
I2C
VDDO7
OUT7
OUT7
A0/CS
VDDO8
OUT8
OUT8
INTR
LOL
Status
Monitors
VDDO9
OUT9
OUT9
Figure 8. Si5345 Block Diagram
Preliminary Rev. 0.95
23
Si5345/44/42
48-54MHz XTAL
or REFCLK
2
4
XA
XB
Si5344
OSC
IN_SEL[1:0]
P
÷
REF
IN0
IN0
IN1
IN1
P0n
÷
P0d
P1n
÷
DSPLL
P1d
PD LPF
P2n
÷
IN2
P2d
IN2
IN3/FB_IN
Mn
Md
P3n
÷
÷
Optional
External
IN3/FB_IN
P3d
Feedback
I2C_SEL
SDA/SDIO
A1/SDO
SCLK
VDDO0
OUT0
OUT0
SPI/
I2C
Multi
Synth
N0n
N0d
÷
÷
÷
÷
t0
t1
t2
t3
÷R0
A0/CS
VDDO1
OUT1
OUT1
Multi
Synth
N1n
N1d
÷R1
÷R2
÷R3
NVM
VDDO2
OUT2
OUT2
Multi
Synth
N2n
N2d
Multi
Synth
N3n
N3d
VDDO3
OUT3
OUT3
Status
Monitors
Figure 9. Si5344 Block Diagram
24
Preliminary Rev. 0.95
Si5345/44/42
48-54MHz XTAL
or REFCLK
2
4
3
XA
XB
Si5342
OSC
IN_SEL[1:0]
P
÷
REF
IN0
IN0
IN1
IN1
P0n
÷
P0d
P1n
÷
DSPLL
P1d
PD LPF
P2n
÷
IN2
IN2
P2d
IN3/FB_IN
Mn
Md
P3n
÷
÷
Optional
External
IN3/FB_IN
P3d
Feedback
I2C_SEL
VDDO0
OUT0
OUT0
Multi
Synth
N0n
N0d
SDA/SDIO
A1/SDO
SCLK
÷
÷
t0
t1
SPI/
I2C
÷R0
÷R1
VDDO1
OUT1
OUT1
Multi
Synth
N1n
N1d
A0/CS
NVM
Status
Monitors
Figure 10. Si5342 Block Diagram
Preliminary Rev. 0.95
25
Si5345/44/42
5. Functional Description
The Si5345’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input
frequency. Fractional input dividers (P) allow the DSPLL to perform hitless switching between input clocks (INx)
that are fractionally related. Input switching is controlled manually or automatically using an internal state machine.
The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and
accuracy while the device is in free-run or holdover mode. The high-performance MultiSynth dividers (N) generate
integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the
MultiSynth generated frequencies to any of the outputs. Additional integer division (R) determines the final output
frequency.
5.1. Frequency Configuration
The frequency configuration of the DSPLL is programmable through the serial interface and can also be stored in
non-volatile memory. The combination of fractional input dividers (P /P ), fractional frequency multiplication (M /
n
d
n
M ), fractional output MultiSynth division (N /N ), and integer output division (R ) allows the generation of virtually
d
n
d
n
any output frequency on any of the outputs. All divider values for a specific frequency plan are easily determined
using the ClockBuilder Pro utility.
5.2. DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL
loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection. Since the loop bandwidth is
controlled digitally, the DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop
bandwidth selection.
5.2.1. Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock
feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process.
Higher fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of
in the range of 100 Hz to 4 kHz are available for selection. The DSPLL will revert to its normal loop bandwidth once
lock acquisition has completed.
5.3. Modes of Operation
Once initialization is complete the DSPLL operates in one of four modes: Free-run Mode, Lock Acquisition Mode,
Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 11. The
following sections describe each of these modes in greater detail.
5.3.1. Initialization and Reset
Once power is applied, the device begins an initialization period where it downloads default register values and
configuration data from NVM and performs other initialization tasks. Communicating with the device through the
serial interface is possible once this initialization period is complete. No clocks will be generated until the
initialization is complete. There are two types of resets available. A hard reset is functionally similar to a device
power-up. All registers will be restored to the values stored in NVM, and all circuits including the serial interface will
be restored to their initial state. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft
reset bypasses the NVM download. It is simply used to initiate register configuration changes.
26
Preliminary Rev. 0.95
Si5345/44/42
Power-Up
Reset and
Initialization
No valid
input clocks
selected
Free-run
Valid input clock
selected
An input is qualified
and available for
selection
Lock Acquisition
(Fast Lock)
Phase lock on
selected input
clock is achieved
Holdover
Mode
No
Selected input
clock fails
Is holdover
history valid?
Locked
Mode
Figure 11. Modes of Operation
5.3.2. Freerun Mode
The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete.
The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency
accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is
±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode.
Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is
recommended for applications that need better frequency accuracy and stability while in freerun or holdover
modes.
5.3.3. Lock Acquisition Mode
The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the
DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will
acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting
when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO
frequency change as it pulls-in to the input clock frequency.
5.3.4. Locked Mode
Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to their selected
input clocks. At this point any XTAL frequency drift will not affect the output frequency. A loss of lock pin (LOL) and
status bit indicate when lock is achieved. See section 5.7.4 for more details on the operation of the loss of lock
circuit.
5.3.5. Holdover Mode
The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other
valid input clocks are available for selection. The DSPLL uses an averaged input clock frequency as its final
holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock
suddenly fails. The holdover circuit for the DSPLL stores up to 120 seconds of historical frequency data while
locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable
window within the stored historical frequency data. Both the window size and the delay are programmable as
shown in Figure 12. The window size determines the amount of holdover frequency averaging. The delay value
allows ignoring frequency data that may be corrupt just before the input clock failure.
Preliminary Rev. 0.95
27
Si5345/44/42
Clock Failure and
Entry into Holdover
Historical Frequency Data Collected
time
Programmable historical data window
Programmable delay
used to determine the final holdover value
120s
0s
30ms, 60ms, 1s,10s, 30s, 60s
1s,10s, 30s, 60s
Figure 12. Programmable Holdover Window
When entering holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover
frequency. While in holdover, the output frequency drift is entirely dependent on the external crystal or external
reference clock connected to the XA/XB pins. If the clock input becomes valid, the DSPLL will automatically exit the
holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequency
to achieve frequency and phase lock with the input clock. This pull-in process is glitchless and its rate is controlled
by the DSPLL or the Fastlock bandwidth.
5.4. External Reference (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter
reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. A
simplified diagram is shown in Figure 13. The device includes internal XTAL loading capacitors which eliminates
the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to
Table 12 for crystal specifications. A crystal in the range of 48 MHz to 54 MHz is recommended for best jitter
performance. Frequency offsets due to C mismatch can be adjusted using the frequency adjustment feature
L
which allows frequency adjustments of ±200 ppm. The Si5345/44/42 Family Reference Manual provides additional
information on PCB layout recommendations for the crystal to ensure optimum jitter performance.
The device can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between
the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (C )
L
are disabled in this mode. Refer to Table 3 for REFCLK requirements when using this mode. A P
divider is
REF
available to accommodate external clock frequencies higher than 54 MHz. Frequencies in the range of 48 MHz to
54 MHz will achieve the best output jitter performance.
5.5. Digitally Controlled Oscillator (DCO) Mode
The output MultiSynths support a DCO mode where their output frequencies are adjustable in pre-defined steps
defined by frequency step words (FSW). The frequency adjustments are controlled through the serial interface or
by pin control using frequency increment (FINC) or decrement (FDEC). A FINC will add the frequency step word to
the DSPLL output frequency, while a FDEC will decrement it. Any number of MultiSynths can be can be updated at
once or independently controlled. The DCO mode is available when the DSPLL is operating in either free-run or
locked mode.
28
Preliminary Rev. 0.95
Si5345/44/42
48-54MHz
XO
48-54MHz
XO
48-54MHz
XTAL
100
XA
XB
XA
XB
XA
XB
2xCL
2xCL
2xCL
2xCL
2xCL
2xCL
OSC
OSC
OSC
P
÷
REF
P
P
÷
REF
÷
REF
Si5345/44/42
Si5345/44/42
Si5345/44/42
Crystal Resonator
Connection
Differential XO
Connection
Single-ended XO
Connection
Figure 13. Crystal Resonator and External Reference Clock Connection Options
5.6. Inputs (IN0, IN1, IN2, IN3)
There are four inputs that can be used to synchronize the DSPLL. The inputs accept both differential and single-
ended clocks. Input selection can be manual (pin or register controlled) or automatic with user definable priorities.
5.6.1. Manual Input Switching (IN0, IN1, IN2, IN3)
Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit
determines input selection as pin selectable or register selectable. The IN_SEL pins are selected by default. If
there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode. When
the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN) and is not available for selection as a
clock input.
Table 15. Manual Input Selection Using IN_SEL[1:0] Pins
Selected Input
IN_SEL[1:0]
Zero Delay
Zero Delay
Mode Disabled
Mode Enabled
0
0
1
1
0
1
0
1
IN0
IN1
IN2
IN3
IN0
IN1
IN2
Reserved
Preliminary Rev. 0.95
29
Si5345/44/42
5.6.2. Automatic Input Selection (IN0, IN1, IN2, IN3)
An automatic input selection state machine is available in addition to the manual switching option. In automatic
mode, the selection criteria is based on input clock qualification, input priority, and the revertive option. Only input
clocks that are valid can be selected by the automatic clock selection state machine. If there are no valid input
clocks available the DSPLL will enter the holdover mode. With revertive switching enabled, the highest priority
input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic
switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected
while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be
initiated.
5.6.3. Hitless Input Switching
Hitless switching is a feature that prevents a phase transient from propagating to the output when switching
between two clock inputs that have a fixed phase relationship. A hitless switch can only occur when the two input
frequencies are frequency locked meaning that they have to be exactly at the same frequency, or at a fractional
frequency relationship to each other. When hitless switching is enabled, the DSPLL simply absorbs the phase
difference between the two input clocks during a input switch. When disabled, the phase difference between the
two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching
feature supports clock frequencies down to the minimum input frequency of 8 kHz.
5.6.4. Glitchless Input Switching
The DSPLL has the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The
DSPLL will pull-in to the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if
enabled. The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency. There
will be no output runt pulses generated at the output during the transition.
5.6.5. Input Configuration and Terminations
Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination
schemes are shown in Figure 14. Differential signals must be ac-coupled, while single-ended LVCMOS signals can
be ac or dc-coupled. Unused inputs can be disabled and left unconnected when not in use.
30
Preliminary Rev. 0.95
Si5345/44/42
Standard AC Coupled Differential LVDS
Si5345/44/42
Standard
50
INx
INx
100
3.3V, 2.5V
LVDS or CML
50
Pulsed CMOS
Standard AC Coupled Differential LVPECL
Si5345/44/42
Standard
50
INx
INx
100
50
3.3V, 2.5V
LVPECL
Pulsed CMOS
Standard AC Coupled Single Ended
Si5345/44/42
Standard
50
INx
INx
3.3V, 2.5V, 1.8V
LVCMOS
Pulsed CMOS
Pulsed CMOS DC Coupled Single Ended
R1
Si5345/44/42
Standard
50
INx
INx
3.3V, 2.5V, 1.8V
LVCMOS
R2
VDD
1.8V
2.5V
3.3V
R1 ()
549
680
R2 ()
Pulsed CMOS
442
324
243
750
Figure 14. Termination of Differential and LVCMOS Input Signals
Preliminary Rev. 0.95
31
Si5345/44/42
5.6.6. Synchronizing to Gapped Input Clocks
The DSPLL supports locking to an input clock that has missing periods. This is also referred to as a gapped clock.
The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of
its cycles. Gapping a clock severely increases its jitter so a phase-locked loop with high jitter tolerance and low
loop bandwidth is required to produce a low-jitter periodic clock. The resulting output will be a periodic non-gapped
clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with
one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is shown in
Figure 15. For more information on gapped clocks, see “AN561: Introduction to Gapped Clocks and PLLs”.
Gapped Input Clock
Periodic Output Clock
100 MHz clock
1 missing period every 10
90 MHz non-gapped clock
100 ns
100 ns
DSPLL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
Period Removed
10 ns
11.11111... ns
Figure 15. Generating an Averaged Clock Output Frequency from a Gapped Clock Input
A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out
of every 8. Locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching
between gapped clocks may violate the hitless switching specification in Table 8 when the switch occurs during a
gap in either input clock.
5.7. Fault Monitoring
All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF)
as shown in Figure 16. The reference at the XA/XB pins is also monitored for LOS since it provides a critical
reference clock for the DSPLL. There is also a Loss Of Lock (LOL) indicator which is asserted when the DSPLL
loses synchronization.
XA XB
Si5345/44/42
OSC
IN0
IN0
Precision
Fast
LOS
LOS
LOS
LOS
LOS
OOF
OOF
OOF
OOF
÷P0
÷P1
÷P2
÷P3
DSPLL
IN1
IN1
Precision
Fast
LOL
PD LPF
÷M
Precision
Fast
IN2
IN2
IN3/FB_IN
IN3/FB_IN
Precision
Fast
Figure 16. Si5345/44/42 Fault Monitors
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Preliminary Rev. 0.95
Si5345/44/42
5.7.1. Input LOS Detection
The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing
clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing
edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility.
The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always
displays the current LOS state and a sticky register always stays asserted until cleared. An option to disable any of
the LOS monitors is also available.
Sticky
Monitor
LOS
LOS
en
Live
Figure 17. LOS Status Indicators
5.7.2. XA/XB LOS Detection
A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output
clocks are disabled when XAXB_LOS is detected. This feature can be disabled such that the device will continue to
produce output clocks when XAXB_LOS is detected.
5.7.3. OOF Detection
Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its
“0_ppm” reference.
This OOF reference can be selected as either:
XA/XB pins
Any input clock (IN0, IN1, IN2, IN3)
The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as
shown in Figure 18. An option to disable either monitor is also available. The live OOF register always displays the
current OOF state, and its sticky register bit stays asserted until cleared.
Sticky
Monitor
Precision
Fast
en
en
OOF
OOF
Live
Figure 18. OOF Status Indicator
5.7.3.1. Precision OOF Monitor
The precision OOF monitor circuit measures the frequency of all input clocks to within ±1 ppm accuracy with
respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the OOF
frequency range which is register configurable from ±2 ppm to ±500 ppm in steps of 2 ppm.
A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure
boundary. An example is shown in Figure 19. In this case the OOF monitor is configured with a valid frequency
range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0 - IN3) as the 0 ppm OOF
reference instead of the XA/XB pins is available. This option is register configurable.
Preliminary Rev. 0.95
33
Si5345/44/42
OOF Declared
OOF Cleared
fIN
Hysteresis
Hysteresis
-4 ppm
(Clear)
-6 ppm
(Set)
+4 ppm
(Clear)
+6 ppm
(Set)
0 ppm
OOF
Reference
Figure 19. Example of Precise OOF Monitor Assertion and De-assertion Triggers
5.7.3.2. Fast OOF Monitor
Because the precision OOF monitor needs to provide 1 ppm of frequency measurement accuracy, it must measure
the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input
clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs
in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF monitor
asserts OOF on an input clock frequency that has changed by greater than ±4000 ppm.
5.7.4. LOL Detection
The Loss Of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its
selected input clock.
There is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by
measuring the frequency difference between the input and feedback clocks at the phase detector. There are two
LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL
Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to
completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering
as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in Figure 20. The live LOL
register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL
pin reflects the current state of the LOL monitor.
LOL Monitor
Sticky
LOL
Clear
Timer
LOL
LOL
Set
Live
LOL
DSPLL
fIN
PD LPF
Feedback
Clock
÷M
Si5345/44/42
Figure 20. LOL Status Indicators
34
Preliminary Rev. 0.95
Si5345/44/42
The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.2 ppm to
20000 ppm. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status.
An example configuration where LOCK is indicated when there is less than 0.2 ppm frequency difference at the
inputs of the phase detector and LOL is indicated when there’s more than 2 ppm frequency difference is shown in
Figure 21.
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
LOL
Hysteresis
Lost Lock
LOCKED
0
0.2
2
20,000
Phase Detector Frequency Difference (ppm)
Figure 21. LOL Set and Clear Thresholds
Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling
standards.
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to
completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering
as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and
loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro utility.
5.7.5. Interrupt pin (INTR)
An interrupt pin (INTR) indicates a change in state of the status indicators (LOS, OOF, LOL, HOLD). Any of the
status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by
clearing the status register that caused the interrupt.
Preliminary Rev. 0.95
35
Si5345/44/42
5.8. Outputs
Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential
signal formats. In addition to supporting differential signals, any of the outputs can be configured as single-ended
LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 20 single-ended outputs, or any combination of differential and
single-ended outputs.
5.8.1. Output Crosspoint
A crosspoint allows any of the output drivers to connect with any of the MultiSynths as shown in Figure 22. The
crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is
ready at power up.
VDDO0
OUT0
OUT0
Multi
Synth
N0n
N0d
÷
÷
÷
÷
÷
t0
t1
t2
t3
t4
÷R0
VDDO1
OUT1
OUT1
Multi
Synth
N1n
N1d
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
÷R9
VDDO2
OUT2
OUT2
Multi
Synth
N2n
N2d
Multi
Synth
N3n
N3d
VDDO3
OUT3
OUT3
Multi
Synth
N4n
N4d
VDDO4
OUT4
OUT4
VDDO5
OUT5
OUT5
VDDO6
OUT6
OUT6
VDDO7
OUT7
OUT7
VDDO8
OUT8
OUT8
VDDO9
OUT9
OUT9
Figure 22. MultiSynth to Output Driver Crosspoint
5.8.2. Output Signal Format
The differential output swing and common mode voltage are both fully programmable covering a wide variety of
signal formats including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be
configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination
of differential and single-ended outputs.
36
Preliminary Rev. 0.95
Si5345/44/42
5.8.3. Differential Output Terminations
Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling
standards.
The differential output drivers support both ac coupled and dc coupled terminations as shown in Figure 23.
DC Coupled LVDS/LVPECL
VDDO = 3.3V, 2.5V, 1.8V
50
OUTx
100
OUTx
50
Si5345/44/42
AC Coupled LVPECL
AC Coupled LVDS/LVPECL
VDD – 1.3V
VDDO = 3.3V, 2.5V, 1.8V
VDDO = 3.3V, 2.5V
50
50
50
50
50
50
OUTx
OUTx
OUTx
OUTx
100
Internally
self-biased
Si5345/44/42
Si5345/44/42
Figure 23. Supported Differential Output Terminations
5.8.4. LVCMOS Output Terminations
LVCMOS outputs are dc-coupled as shown in Figure 24.
3.3V, 2.5V, 1.8V
LVCMOS
VDDO = 3.3V, 2.5V, 1.8V
50
50
Rs
Rs
OUTx
OUTx
Si5345/44/42
Figure 24. LVCMOS Output Terminations
5.8.5. Output Signal Format
The differential output swing and common mode voltage are both fully programmable and compatible with a wide
variety of signal formats, including LVDS and LVPECL. In addition to supporting differential signals, any of the
outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 20 single-ended outputs or
any combination of differential and single-ended outputs.
Preliminary Rev. 0.95
37
Si5345/44/42
5.8.6. Differential Output Swing Modes
There are two selectable differential output swing modes: Normal and high swing. Each output can support a
unique mode.
Differential Normal Swing Mode: When an output driver is configured in normal swing mode, its output
swing is selectable as one of 7 settings ranging from 200 mVpp_se to 800 mVpp_se in increments of
100 mV. The output impedance in the Normal Swing Mode is 100differentialAny of the terminations
shown in Figure 23 is supported in this mode.
Differential Low Power Mode: When an output driver is configured in low power mode, its output swing is
configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV.
The output driver is in high impedance mode and supports standard 50 PCB traces. Any of the
terminations shown in Figure 23 is supported in this mode.
5.8.7. LVCMOS Output Terminations
LVCMOS outputs are DC coupled as shown in Figure 25.
DC Coupled LVCMOS
3.3V, 2.5V, 1.8V
LVCMOS
VDDO = 3.3V, 2.5V, 1.8V
50
50
Rs
Rs
OUTx
OUTx
Figure 25. LVCMOS Output Terminations
5.8.8. LVCMOS Output Impedance Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances. A source
termination resistor is recommended to help match the selected output impedance to the trace impedance, where
Rs = Transmission line impedance – Z . There are three programmable output impedance selections (CMOS1,
O
CMOS2, CMOS3) for each VDDO options as shown in Table 16.
Table 16. Typical Output Impedance (Z )
S
CMOS_DRIVE_Selection
VDDO
3.3 V
2.5 V
1.8 V
CMOS1
CMOS2
30
CMOS3
22
38
43
—
35
24
46
31
5.8.9. LVCMOS Output Signal Swing
The signal swing (V /V ) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output
OL OH
driver has its own VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. Each output
driver automatically detects the voltage on the VDDO pin to properly determine the correct output voltage.
5.8.10. LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTx). By
default the clock on the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTx pin.
The polarity of these clocks is configurable enabling complementary clock generation and/or inverted polarity with
respect to other output drivers.
38
Preliminary Rev. 0.95
Si5345/44/42
5.8.11. Output Enable/Disable
The OE pin provides a convenient method of disabling or enabling the output drivers. When the OE pin is held high
all outputs will be disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be
individually disabled through register control.
5.8.12. Output Driver State When Disabled
The disabled state of an output driver is configurable as: disable low, disable high, or disable high-impedance.
5.8.13. Synchronous Output Disable Feature
The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will
wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from
occurring when disabling an output. When this feature is turned off, the output clock will disable immediately
without waiting for the period to complete.
5.8.14. Output Skew Control (t0 – t4)
The Si5345 uses independent MultiSynth dividers (N - N ) to generate up to 5 unique frequencies to its 10 outputs
0
4
through a crosspoint switch. By default all clocks are phase aligned. A delay path (t - t ) associated with each of
0
4
these dividers is available for applications that need a specific output skew configuration. This is useful for PCB
trace length mismatch compensation. The resolution of the phase adjustment is approximately 0.28 ps per step
definable in a range of ±9.14 ns. Phase adjustments are register configurable. An example of generating two
frequencies with unique configurable path delays is shown in Figure 26.
VDDO0
OUT0
OUT0
÷R0
t0
t1
t2
t3
t4
÷N0
÷N1
÷N2
÷N3
÷N4
VDDO1
OUT1
OUT1
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
VDDO2
OUT2
OUT2
VDDO3
OUT3
OUT3
VDDO4
OUT4
OUT4
VDDO5
OUT5
OUT5
VDDO6
OUT6
OUT6
VDDO7
OUT7
OUT7
VDDO8
OUT8
OUT8
VDDO9
OUT9
OUT9
÷R9
Figure 26. Example of Independently Configurable Path Delays
All phase delay values are restored to their default values after power-up, hard reset, or a reset using the RST pin.
Phase delay default values can be written to NVM allowing a custom phase offset configuration at power-up or
after power-on reset, or after a hardware reset using the RST pin.
Preliminary Rev. 0.95
39
Si5345/44/42
5.8.15. Zero Delay Mode
A zero delay mode is available for applications that require fixed and consistent minimum delay between the
selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through
software configuration and closing the loop externally as shown in Figure 27.
This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output
drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves
the shortest trace length will help to minimize the input-to-output delay. The OUT9 and FB_IN pins are
recommended for the external feedback connection. The FB_IN input pins must be terminated and ac-coupled
when zero delay mode is used. A differential external feedback path connection is necessary for best performance.
Note that automatic input clock switching and hitless switching features are not available when zero delay mode is
enabled.
IN0
Si5345/44/42
÷P0
IN0
IN1
DSPLL
15GHz
÷P1
÷P2
IN1
PD LPF
IN2
IN2
÷M
IN3/FB_IN
IN3/FB_IN
÷P3
VDDO0
OUT0
OUT0
÷R0
÷R1
÷R2
VDDO1
OUT1
OUT1
t0
t1
t2
t3
t4
÷N0
÷N1
÷N2
÷N3
÷N4
VDDO2
OUT2
OUT2
VDDO7
OUT7
OUT7
÷R7
÷R8
÷R9
VDDO8
OUT8
OUT8
VDDO9
OUT9
OUT9
External Feedback Path
Figure 27. Si5345 Zero Delay Mode Setup
5.8.16. Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures
consistent and repeatable phase alignment across all output drivers. Resetting the device using the RST pin or
asserting the hard reset bit will have the same result. Asserting the sync register bit provides another method of re-
aligning the R dividers without resetting the device.
40
Preliminary Rev. 0.95
Si5345/44/42
5.9. Power Management
Unused inputs and output drivers can be powered down when unused. Consult the Si5345/44/42 Family
Reference Manual and ClockBuilder Pro configuration utility for details.
5.10. In-Circuit Programming
2
The Si5345/44/42 is fully configurable using the serial interface (I C or SPI). At power-up the device downloads its
default register values from internal non-volatile memory (NVM). Application specific default configurations can be
written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to
NVM is in-circuit programmable with normal operating power supply voltages applied to its V and V
pins. The
DD
DDA
NVM is two time writable. Once a new configuration has been written to NVM, the old configuration is no longer
accessible. Refer to the Si5345/44/42 Family Reference Manual for a detailed procedure for writing registers to
NVM.
5.11. Serial Interface
2
Configuration and operation of the Si5345/44/42 is controlled by reading and writing registers using the I C or SPI
interface. The I2C_SEL pin selects I C or SPI operation. Communication with both 3.3 V and 1.8 V host is
2
supported. The SPI mode operates in either 4-wire or 3-wire. See the Si5345/44/42 Family Reference Manual for
details.
5.12. Custom Factory Preprogrammed Parts
For applications where a serial interface is not available for programming the device, custom pre-programmed
parts can be ordered with a specific configuration written into NVM. A factory pre-programmed part will generate
clocks at power-up. Custom, factory-preprogrammed devices are available. Use the ClockBuilder Pro custom part
number wizard (www.silabs.com/clockbuilderpro) to quickly and easily request and generate a custom part number
for your configuration.
In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum
matching your design’s configuration. Once you receive the confirmation email with the data sheet addendum,
simply place an order with your local Silicon Labs sales representative. Samples of your preprogrammed device
will typically ship in about two weeks.
5.13. Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro
for Factory Preprogrammed Devices
As with essentially all modern software utilities, ClockBuilder Pro is continuously updated and enhanced. By
registering at www.silabs.com, you will be notified whenever changes are made and what the impact of those
changes are. This update process will ultimately enable ClockBuilder Pro users to access all features and register
setting values documented in this data sheet and the Si5345/44/42 Family Reference Manual.
However, if you must enable or access a feature or register setting value so that the device starts up with this
feature or a register setting, but the feature or register setting is not yet available in CBPro, you must contact a
Silicon Labs applications engineer for assistance. One example of this type of feature or custom setting is the
customizable output amplitude and common voltages for the clock outputs. After careful review of your project file
and requirements, the Silicon Labs applications engineer will email back your CBPro project file with your specific
features and register settings enabled using what's referred to as the manual "settings override" feature of CBPro.
"Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides"
in a CBPro design report are shown in Table 17.
Preliminary Rev. 0.95
41
Si5345/44/42
Table 17. Setting Overrides
Location
0x0435[0]
Customer Name
Engineering Name
OLA_HO_FORCE
OOF_DIV_CLK_DIS
Type
No NVM
User
Target
N/A
Dec Value Hex Value
FORCE_HOLD_PLLA
OOF_DIV_CLK_DIS
1
0
0x1
0x0B48[0:4]
OPN&EVB
0x00
Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup
with the values in the NVM file. The flowchart for this process is shown in Figure 28.
End: Place
sample order
Start
Do I need a
pre‐programmed device with
a feature or setting which is
unavailable in ClockBuilder
Pro?
Generate
Custom OPN
in CBPro
Configure device
using CBPro
No
Yes
Contact Silicon Labs
Technical Support
to submit & review
your
Yes
non‐standard
configuration
request & CBPro
project file
Receive
updated CBPro
project file
from
Silicon Labs
with “Settings
Override”
Does the updated
CBPro Project file
match your
Load project file
into CBPro and test
requirements?
Figure 28. Process for Requesting Non-Standard CBPro Features
42
Preliminary Rev. 0.95
Si5345/44/42
6. Register Map
The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains
frequently accessible registers, such as alarm status, resets, device identification, etc. Other pages contain
registers that need less frequent access such as frequency configuration, and general device settings. A high level
map of the registers is shown in “6.2. High-Level Register Map” . Refer to the Si5345/44/42 Family Reference
Manual for a complete list of register descriptions and settings. Silicon Labs strongly recommends using
ClockBuilderPro to create and manage register settings.
6.1. Addressing Scheme
The device registers are accessible using a 16-bit address which consists of an 8-bit page address + 8-bit register
address. By default the page address is set to 0x00. Changing to another page is accomplished by writing to the
‘Set Page Address’ byte located at address 0x01 of each page.
6.2. High-Level Register Map
Table 18. High-Level Register Map
16-Bit Address
Content
8-bit Page
8-bit Register
Address
Address Range
00
00
01
Revision IDs
Set Page Address
02–0A
0B–15
17–1B
1C
Device IDs
Alarm Status
INTR Masks
Reset controls
1D
FINC, FDEC Control Bits
SPI (3-Wire vs 4-Wire)
Alarm Configuration
NVM Controls
2B
2C–E1
E2–E4
FE
Device Ready Status
Set Page Address
01
02
01
08–3A
41–42
FE
Output Driver Controls
Output Driver Disable Masks
Device Ready Status
Set Page Address
01
02–05
08–2F
30
XTAL Frequency Adjust
Input Divider (P) Settings
Input Divider (P) Update Bits
Output Divider (R) Settings
User Scratch Pad Memory
Device Ready Status
47–6A
6B–72
FE
Preliminary Rev. 0.95
43
Si5345/44/42
Table 18. High-Level Register Map (Continued)
16-Bit Address
Content
8-bit Page
Address
8-bit Register
Address Range
03
01
02–37
0C
Set Page Address
MultiSynth Divider (N0–N4) Settings
MultiSynth Divider (N0) Update Bit
MultiSynth Divider (N1) Update Bit
MultiSynth Divider (N2) Update Bit
MultiSynth Divider (N3) Update Bit
MultiSynth Divider (N4) Update Bit
FINC/FDEC Settings N0 - N4
Output Delay (t) Settings
Device Ready Status
17
22
2D
38
39–58
59–62
FE
04
05
87
Zero Delay Mode Set Up
Fast Lock Loop Bandwidth
Feedback Divider (M) Settings
Input Select Control
0E - 14
15–1F
2A
2B
Fast Lock Control
2C–35
36
Holdover Settings
Input Clock Switching Mode Select
Input Priority Settings
38–39
3F
Holdover History Valid Data
Reserved
06–08
09
00–FF
01
Set Page Address
1C
Zero Delay Mode Settings
Control I/O Voltage Select
Input Settings
43
49
10–FF
00–FF
Reserved
44
Preliminary Rev. 0.95
Si5345/44/42
7. Pin Descriptions
Si5345
Top View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
IN1
FINC
IN1
IN_SEL0
IN_SEL1
RSVD
RST
LOL
3
VDD
4
OUT6
OUT6
VDDO6
OUT5
OUT5
VDDO5
I2C_SEL
OUT4
OUT4
VDDO4
OUT3
OUT3
VDDO3
5
6
7
X1
XA
8
GND
Pad
9
XB
10
11
12
13
14
15
X2
OE
INTR
VDDA
IN2
IN2
SCLK 16
Si5342 44QFN
Top View
Si5344 44QFN
Top View
1
2
33
32
31
30
29
28
27
26
25
24
23
1
2
33
32
31
30
29
28
27
26
25
24
23
IN1
IN1
IN1
INTR
VDD
INTR
VDD
IN1
3
LOS1
3
OUT2
IN_SEL0
IN_SEL0
4
LOS0
4
OUT2
X1
XA
X1
XA
5
VDDS
LOS_XAXB
LOL
5
VDDO2
LOS_XAXB
LOL
GND
Pad
GND
Pad
6
6
XB
XB
7
7
X2
X2
VDDS
OUT1
VDDS
8
8
VDDA
VDDA
9
OUT1
9
VDDA
IN2
VDDA
IN2
10
11
OUT1
10
11
OUT1
VDDO1
VDDO1
IN2
IN2
Preliminary Rev. 0.95
45
Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions
Pin Type1
Pin Number
Pin Name
Function
Si5345 Si5344 Si5342
Inputs
XA
8
9
5
6
5
6
I
I
Crystal Input
Input pins for external crystal (XTAL). Alternatively these
pins can be driven with an external reference clock (REF-
CLK). An internal register bit selects XTAL or REFCLK
mode. Default is XTAL mode.
XB
X1
X2
7
4
7
4
7
I
I
XTAL Shield
Connect these pins directly to the XTAL ground pins. X1,
X2 and the XTAL ground pins should be separated from
the PCB ground plane. Refer to the Si5345/44/42 Family
Reference Manual for layout guidelines. These pins
should be left disconnected when connecting XA/XB pins
to an external reference clock (REFCLK).
10
IN0
IN0
IN1
IN1
IN2
IN2
63
64
1
43
44
1
43
44
1
I
I
I
I
I
I
Clock Inputs
These pins accept an input clock for synchronizing the
device. They support both differential and single-ended
clock signals. Refer to "5.6.5. Input Configuration and Ter-
minations" on page 30 for input termination options.
These pins are high-impedance and must be terminated
externally. The negative side of the differential input must
be grounded through a capacitor when accepting a sin-
gle-ended clock.
2
2
2
14
15
10
11
10
11
IN3/FB_IN
IN3/FB_IN
61
62
41
42
41
42
I
I
Clock Input 3/External Feedback Input
By default these pins are used as the fourth clock input
(IN3/IN3). They can also be used as the external feed-
back input (FB_IN/FB_IN) for the optional zero delay
mode. See section "5.8.15. Zero Delay Mode" on page 40
for details on the optional zero delay mode.
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
46
Preliminary Rev. 0.95
Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions (Continued)
Pin Number
Si5345 Si5344 Si5342
Pin Type1
Pin Name
Function
Outputs
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6
OUT6
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
Notes:
24
23
28
27
31
30
35
34
38
37
42
41
45
44
51
50
54
53
59
58
20
19
25
24
31
30
36
35
—
—
—
—
—
—
—
—
—
—
—
—
20
19
25
24
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Output Clocks
These output clocks support a programmable signal
swing and common mode voltage. Desired output signal
format is configurable using register control. Termination
recommendations are provided in “5.8.3. Differential Out-
put Terminations” and section “5.8.4. LVCMOS Output
Terminations” . Unused outputs should be left uncon-
nected.
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
Preliminary Rev. 0.95
47
Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions (Continued)
Pin Number
Si5345 Si5344 Si5342
Pin Type1
Pin Name
Function
Serial Interface
I2C_SEL
39
38
38
I
I2C Select
2
This pin selects the serial interface mode as I C
(I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally
pulled high. Leave disconnected when unused. See Note
2
.
SDA/SDIO
18
13
13
I/O
Serial Data Interface
This is the bidirectional data pin (SDA) for the I C mode,
2
or the bidirectional data pin (SDIO) in the 3-wire SPI
mode, or the input data pin (SDI) in 4-wire SPI mode.
2
When in I C mode, this pin must be pulled-up using an
external resistor of at least 1 k. No pull-up resistor is
needed when is SPI mode. Tie low when unused. See
2
Note .
A1/SDO
SCLK
17
16
15
14
15
14
I/O
I
Address Select 1/Serial Data Output
In I C mode this pin functions as the A1 address input pin.
In 4-wire SPI mode this is the serial data output (SDO)
pin. Leave disconnected when unused. See Note .
2
2
Serial Clock Input
2
This pin functions as the serial clock input for both I C and
2
SPI modes. When in I C mode, this pin must be pulled-up
using an external resistor of at least 1 k. No pull-up
resistor is needed when in SPI mode. Tie high or low
2
when unused. See Note .
A0/CS
19
16
16
I
Address Select 0/Chip Select
This pin functions as the hardware controlled address A0
2
in I C mode. In SPI mode, this pin functions as the chip
select input (active low). This pin is internally pulled-up
and can be left unconnected when not in use. See Note .
2
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
48
Preliminary Rev. 0.95
Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions (Continued)
Pin Number
Si5345 Si5344 Si5342
Pin Type1
Pin Name
Function
Control/Status
INTR
12
6
33
17
33
17
O
Interrupt
This pin is asserted low when a change in device status
has occurred. It should be left unconnected when not in
use. See Note .
2
RST
I
Device Reset
Active low input that performs power-on reset (POR) of
the device. Resets all internal logic to a known state and
forces the device registers to their default values. Clock
outputs are disabled during reset. This pin is internally
pulled-up and can be left unconnected when not in use.
2
See Note .
OE
11
47
—
12
—
12
—
I
Output Enable
This pin disables all outputs when held high. This pin is
internally pulled low and can be left unconnected when
2
not in use. See Note .
LOL
O
O
Loss Of Lock (Si5345)
This output pin indicates when the DSPLL is locked (high)
or out-of-lock (low). It can be left unconnected when not in
2
use. See Note .
27
27
Loss Of Lock (Si5344/42)
This output pin indicates when the DSPLL is locked (high)
or out-of-lock (low). It can be left unconnected when not in
3
use. See Note .
—
—
—
—
LOS0
LOS1
—
—
—
—
30
31
35
36
O
O
O
O
Loss Of Signal for IN0
This pin indicate a loss of clock at the IN0 pin when low.
3
See Note .
Loss Of Signal for IN1
This pin indicate a loss of clock at the IN1 pin when low.
3
See Note .
LOS2
Loss Of Signal for IN2
This pin indicate a loss of clock at the IN2 pin when low.
3
See Note .
LOS3
Loss Of Signal for IN3
This pin indicate a loss of clock at the IN3 pin when low.
3
See Note .
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
Preliminary Rev. 0.95
49
Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions (Continued)
Pin Number
Si5345 Si5344 Si5342
Pin Type1
Pin Name
Function
LOS_XAXB
—
28
28
O
Loss Of Signal on XA/XB Pins
This pin indicates a loss of signal at the XA/XB pins when
3
low. See Note .
FINC
48
—
—
I
I
Frequency Increment Pin
This pin is used to step-up the output frequency of a
selected output. The affected output and its frequency
change step size is register configurable. This pin is inter-
nally pulled low and can be left unconnected when not in
2
use. See Note .
FDEC
25
—
—
Frequency Decrement Pin
This pin is used to step-down the output frequency of a
selected output. The affected output driver and its fre-
quency change step size is register configurable. This pin
is internally pulled low and can be left unconnected when
2
not in use. See Note .
IN_SEL0
IN_SEL1
3
4
3
3
I
I
Input Reference Select
The IN_SEL[1:0] pins are used in manual pin controlled
mode to select the active clock input as shown in Table 15
on page 29. These pins are internally pulled low. See
37
37
2
Note .
RSVD
5
—
—
—
—
—
22
—
—
—
—
—
22
—
—
—
—
—
Reserved
These pins are connected to the die. Leave disconnected.
20
21
55
56
—
NC
No Connect
These pins are not connected to the die. Leave discon-
nected.
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
50
Preliminary Rev. 0.95
Si5345/44/42
Table 19. Si5345/44/42 Pin Descriptions (Continued)
Pin Number
Si5345 Si5344 Si5342
Pin Type1
Pin Name
Function
Power
VDD
32
46
60
—
21
32
39
40
8
21
32
39
40
8
P
P
P
P
P
Core Supply Voltage
The device operates from a 1.8 V supply. A 0.1 µF bypass
capacitor should be placed very close to this pin. See the
Si5345/44/42 Family Reference Manual for power supply
filtering recommendations.
VDDA
VDDS
13
Core Supply Voltage 3.3 V
This core supply pin requires a 3.3 V power source. A
1 µF bypass capacitor should be placed very close to this
pin. See the Si5345/44/42 Family Reference Manual for
power supply filtering recommendations.
—
9
9
P
—
—
—
26
—
—
26
29
34
P
P
P
Status Output Voltage
The voltage on this pin determines VOL/VOH on the
Si5342/44 LOL_A and LOL_B outputs. Connect to either
3.3 V or 1.8 V. A 0.1 µF bypass capacitor should be
placed very close to this pin.
VDDO0
VDDO1
VDDO2
VDDO3
VDDO4
VDDO5
VDDO6
VDDO7
VDDO8
VDDO9
GND PAD
22
26
29
33
36
40
43
49
52
57
—
18
23
29
34
—
—
—
—
—
—
—
18
23
—
—
—
—
—
—
—
—
—
P
P
P
P
P
P
P
P
P
P
P
Output Clock Supply Voltage
Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTn, OUTn out-
puts. For unused outputs, leave VDDO pins unconnected.
An alternative option is to connect the VDDO pin to a
power supply and disable the output driver to minimize
current consumption.
Ground Pad
This pad provides connection to ground and must be con-
nected for proper operation. Use as many vias as practi-
cal and keep the via length to an internal ground plan as
short as possible.
Notes:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
4. Refer to the Si5345/44/42 Family Reference Manual for more information on register setting names.
Preliminary Rev. 0.95
51
Si5345/44/42
8. Ordering Guide
Ordering
Part Number
(OPN)
Number of
Input/Output Frequency Range
Output Clock
Supported
Frequency
Synthesis Modes
Temperature
Range
Package
Clocks
(MHz)
Si5345
1,2
Si5345A-B-GM
Si5345B-B-GM
Si5345C-B-GM
Si5345D-B-GM
4/10
0.001 to 712.5 MHz
0.001 to 350 MHz
0.001 to 712.5 MHz
0.001 to 350 MHz
Integer
Fractional
64-Lead
9x9 QFN
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
—
1,2
1,2
1,2
Integer Only
Si5344
1,2
1,2
1,2
1,2
Si5344A-B-GM
Si5344B-B-GM
Si5344C-B-GM
Si5344D-B-GM
4/4
4/2
—
0.001 to 712.5 MHz
0.001 to 350 MHz
0.001 to 712.5 MHz
0.001 to 350 MHz
Integer
Fractional
44-Lead
7x7 QFN
Integer Only
Si5342
1,2
1,2
1,2
1,2
Si5342A-B-GM
Si5342B-B-GM
Si5342C-B-GM
Si5342D-B-GM
0.001 to 712.5 MHz
0.001 to 350 MHz
0.001 to 712.5 MHz
0.001 to 350 MHz
Integer
Fractional
44-Lead
7x7 QFN
Integer Only
Si5345/44/42-EVB
Si5345-EVB
Si5344-EVB
Si5342-EVB
Notes:
—
—
Evaluation
Board
1. Add an R at the end of the OPN to denote tape and reel ordering options.
2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Silicon Labs and the
ClockBuilder Pro software utility.
3. Custom part number format is: e.g. Si5345A-Bxxxxx-GM where “xxxxx” is a unique numerical sequence representing
the pre-programmed configuration.
52
Preliminary Rev. 0.95
Si5345/44/42
8.1. Ordering Part Number Fields
Si534fg-Rxxxxx-GM
Timing product family
f = Jitter attenuator family member (5, 4, 2)
g = Device grade (A, B, C, D)
Product Revision*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40°C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Preliminary Rev. 0.95
53
Si5345/44/42
9. Package Outlines
9.1. Si5345 9x9 mm 64-QFN Package Diagram
Figure 29 illustrates the package details for the Si5345. Table 20 lists the values for the dimensions shown in the
illustration.
Figure 29. 64-Pin Quad Flat No-Lead (QFN)
Table 20. Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
A
A1
0.02
b
0.25
D
9.00 BSC
5.20
D2
e
5.10
5.30
0.50 BSC
9.00 BSC
5.20
E
E2
5.10
0.30
—
5.30
0.50
0.10
0.10
0.08
0.10
L
0.40
aaa
bbb
ccc
ddd
Notes:
—
—
—
—
—
—
—
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
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9.2. Si5344 and Si5342 7x7 mm 44-QFN Package Diagram
Figure 30 illustrates the package details for the Si5344 and Si5342. Table 21 lists the values for the dimensions
shown in the illustration.
Figure 30. 44-Pin Quad Flat No-Lead (QFN)
Table 21. Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
A
A1
0.02
b
0.25
D
7.00 BSC
5.20
D2
e
5.10
5.30
0.50 BSC
7.00 BSC
5.20
E
E2
5.10
0.30
—
5.30
0.50
0.10
0.10
0.08
0.10
L
0.40
aaa
bbb
ccc
ddd
Notes:
—
—
—
—
—
—
—
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Preliminary Rev. 0.95
55
Si5345/44/42
10. PCB Land Pattern
Figure 31 illustrates the PCB land pattern details for the devices. Table 22 lists the values for the dimensions
shown in the illustration.
Si5345
Si5344 and Si5342
Figure 31. PCB Land Pattern
Table 22. PCB Land Pattern Dimensions
Dimension
Si5345 (Max)
8.90
Si5344/42 (Max)
C1
C2
E
6.90
6.90
0.50
0.30
0.85
5.30
5.30
8.90
0.50
X1
Y1
X2
Y2
0.30
0.85
5.30
5.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is
calculated based on a fabrication Allowance of 0.05 mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask
and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
8. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground
pad.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
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Si5345/44/42
11. Top Marking
Si534Xg-
Rxxxxx-GM
YYWWTTTTTT
Si534Xg-
Rxxxxx-GM
YYWWTTTTTT
e4
TW
TW
e4
64-QFN
44-QFN
Line
1
Characters
Description
Si534Xg-
Base part number and Device Grade for Any-frequency, Any-output, Jitter
Cleaning Clock (single PLL):
X = 5: 10-output Si5345: 64-QFN
X = 4: 4-output Si5344: 44-QFN
X = 2: 2-output Si5342: 44-QFN
g = Device Grade (A, B, C, D). See “8. Ordering Guide” for more information.
– = Dash character.
2
Rxxxxx-GM
R = Product revision. (Refer to “8. Ordering Guide” for latest revision).
xxxxx = Customer specific NVM sequence number. Optional NVM code
assigned for custom, factory pre-programmed devices.
Characters are not included for standard, factory default configured devices.
See Ordering Guide for more information.
-GM = Package (QFN) and temperature range (–40 to +85 °C)
3
4
YYWWTTTTTT
YYWW = Characters correspond to the year (YY) and work week (WW) of pack-
age assembly.
TTTTTT = Manufacturing trace code.
Circle w/ 1.6 mm
(64-QFN) or 1.4 mm
(44-QFN) diameter
Pin 1 indicator; left-justified
e4
Pb-free symbol; Center-Justified
TW
TW = Taiwan; Country of Origin (ISO Abbreviation)
Preliminary Rev. 0.95
57
Si5345/44/42
12. Device Errata
Please log in or register at www.silabs.com to access the device errata document.
58
Preliminary Rev. 0.95
Si5345/44/42
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 0.95
Removed advanced product information revision
history.
Updated “8. Ordering Guide” and changed
references to Revision B.
Updated parametric tables 2, 3, 5, 6, 7, and 8 to
reflect production characterization.
Updated terminology to align with ClockBuilder Pro
software.
Corrected Table 3 references and specifications
from “LVCMOS - DC coupled” to “Pulsed CMOS -
DC-Coupled”.
2
Corrected Table 9 I C data hold time specification to
100 ns from 5 µs.
Preliminary Rev. 0.95
59
Si5345/44/42
CONTACT INFORMATION
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Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
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Please visit the Silicon Labs Technical Support web page:
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and register to submit a technical support request.
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60
Preliminary Rev. 0.95
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