SI5394P-A10073-GMR_技术文档

Si5395/94/92 Data Sheet

12-Channel, Any-Frequency, Any-Output Jitter Attenuator/

Clock Multiplier with Ultra-Low Jitter

KEY FEATURES

• Generates any combination of output

frequencies from any input frequency

The Si5395/94/92 Jitter attenuators combine fourth-generation DSPLL™ and Multi-

Synth™ technologies to deliver ultra-low jitter (69 fs) for high performance applica-

tions like 56G SerDes. They are used in applications that demand the highest level

of integration and jitter performance. All PLL components are integrated on-chip,

eliminating the risk of noise coupling associated with discrete solutions. Device

grades J/K/L/M/E have an integrated reference to save board space, improve sys-

tem reliability and reduces the effect of acoustic emissions noise caused by temper-

ature ramps. Grades A/B/C/D/P use an external crystal (XTAL) or crystal oscillator

(XO) reference.

• Ultra low phase jitter:

• 69 fs RMS (Grade P)

• 71 fs RMS (Grade E)

• 85 fs RMS (integer mode)

• 100 fs RMS (fractional mode)

• Enhanced hitless switching minimizes output

phase transients (0.2 ns typ)

• Input frequency range

• Differential: 8 kHz to 750 MHz

The Si5395/94/92 support free-run, synchronous and holdover modes as well as en-

hanced hitless switching, minimizing the phase transients associated when switching

between input clocks. These devices are programmable via a serial interface with in-

circuit programmable non-volatile memory (NVM) so they always power up with a

known frequency configuration. Programming the Si5395/94/92 is easy with Silicon

• LVCMOS: 8 kHz to 250 MHz

• Output frequency range

• Differential: 100 Hz to 1028 MHz

Labs’ ClockBuilder^TMPro software. Factory preprogrammed devices are also availa-

ble.

• LVCMOS: 100 Hz to 250 MHz

• Meets G.8262, E.8262.1 EEC Standards

• Status monitoring

For more information, visit the https://www.silabs.com/contact-sales page.

• Si5395: 4 input, 12 output

• Si5394: 4 input, 4 output

Applications:

• Si5392: 4 input, 2 output

• 56G/112G PAM4 SerDes clocking

• OTN muxponders and transponders

• 10/40/100/200/400G networking line cards

• 10/40/100/400 GbE Synchronous Ethernet (ITU-T G.8262)

• Medical imaging

• External reference: Grades A/B/C/D/P

• Integrated reference: Grades J/K/L/M/E

• Drop-in compatible with Si5345/44/42

• Test and measurement

OUT0A

÷INT

Integrated

Reference*

MultiSynth

÷INT

OUT0

OUT1

OUT2

÷INT

IN0

IN1

IN2

÷FRAC

DSPLL

OUT3

4 Input

Clocks

Up to 12

Output Clocks

÷FRAC

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT9A

÷INT

IN3/FB_IN

÷FRAC

Status Flags

I²C/SPI

Status Monitor

Control

NVM

*Only for Si539x J/K/L/M/E grades. Si539x A/B/C/D/P grades have external reference (XTAL or XO)

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Rev. 1.1

Si5395/94/92 Data Sheet

Features List

1. Features List

The Si5395/94/92 features are listed below:

• Generates any output frequency in any format from any input

frequency

• Optional zero delay mode

• Fast-lock acquisition for low nominal bandwidths

• Independent Frequency-on-the fly for each MultiSynth

• DCO mode: as low as 0.001 ppb step size

• Core voltage

• External XTAL or XO reference (A/B/C/D/P)

• Integrated reference (J/K/L/M/E)

• Ultra-low phase jitter of 69 fs (P-Grade)

• Dynamic phase adjust

• V_DD: 1.8 V ±5%

• Input frequency range

• V_DDA: 3.3 V ±5%

• Differential: 8 kHz–750 MHz

• Independent output clock supply pins

• 3.3 V, 2.5 V, or 1.8 V

• LVCMOS: 8 kHz–250 MHz

• Output frequency range

Serial interface: I²C or SPI

•

• Differential: 100 Hz to 1028 MHz

• LVCMOS: 100 Hz to 250 MHz

• In-circuit programmable with non-volatile OTP memory

• ClockBuilder Pro software simplifies device configuration

• Si5395: 4 input, 12 output

• Programmable jitter attenuation bandwidth: 0.1 Hz to 4 kHz

• Meets requirements of:

• Grade A/B/C/D/P: 64-QFN 9×9 mm

• Grade J/K/L/M/E: 64-LGA 9x9 mm

• Si5394: 4 input, 4 output

• ITU-T G.8262 (SyncE) EEC Options 1 and 2

• ITU-T G.8262.1 (Enhanced SyncE) eEEC

• Highly configurable outputs compatible with LVDS, LVPECL,

LVCMOS, CML, and HCSL with programmable signal ampli-

tude

• Grade A/B/C/D/P: 44-QFN 7×7 mm

• Grade J/K/L/M/E: 44-LGA 7x7 mm

• Si5392: 4 input, 2 output

• Status monitoring (LOS, OOF, LOL)

• Grade A/B/C/D/P: 44-QFN 7×7 mm

• Grade J/K/L/M/E: 44-LGA 7x7 mm

• Temperature range: –40 to +85 °C

• Pb-free, RoHS-6 compliant

• Enhanced hitless switching for 8 kHz, 19.44 MHz, 25 MHz in-

puts and other frequencies

• Locks to gapped clock inputs

• Free-run and holdover modes

• Drop-in compatible with Si5345/44/42

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Rev. 1.1 | 2

Si5395/94/92 Data Sheet

Related Documents

2. Related Documents

Table 2.1. Related Documentation and Software

Document/Resource

Description/URL

Si5395-94-92 Family Reference Manual

Si5395/94/92 Family Reference Manual

https://www.silabs.com/documents/public/reference-manuals/

si534x-8x-9x-recommended-crystals-rm.pdf

Crystal Reference Manual (Grades A/B/C/D/P only)

UG387: Si5392 Evaluation Board User's Guide

https://www.silabs.com/documents/public/user-guides/ug387-

si5392-evb.pdf

https://www.silabs.com/documents/public/user-guides/ug334-

si5394evb.pdf

UG334: Si5394 Evaluation Board User's Guide

https://www.silabs.com/documents/public/user-guides/ug335-

si5395evb.pdf

UG335: Si5395 Evaluation Board User's Guide

AN1151: Using the Si539x in 56G SerDes Applications

https://www.silabs.com/documents/public/application-notes/

an1151-using-si539x.pdf

https://www.silabs.com/documents/public/application-notes/

an1155-differences-between-si5342-47-and-si5392-97.pdf

AN1155: Differences between Si5342-47 and Si5392-97

AN1178: Frequency-On-the-Fly for Silicon Labs Jitter Attenuators https://www.silabs.com/documents/public/application-notes/

and Clock Generators

Frequently Asked Questions

Quality and Reliability

an1178-frequency-otf-jitter-atten-clock-gen.pdf

http://www.silabs.com/Si5395-94-92-FAQ

http://www.silabs.com/quality

https://www.silabs.com/products/development-tools/timing/

clock#highperformance

Development Kits

https://www.silabs.com/products/development-tools/software/

clockbuilder-pro-software

ClockBuilder Pro (CBPro) Software

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Rev. 1.1 | 3

Si5395/94/92 Data Sheet

Ordering Guide

3. Ordering Guide

Table 3.1. Si5395/94/92 A/B/C/D/P Ordering Guide (External Reference)

Ordering Part

Number (OPN)

Number of Input/

Output Clocks

Output Clock

Frequency Range (MHz)

Supported Frequency

Synthesis Modes

Package

Reference

Si5395

Si5395A-A-GM^{1, 2}

Si5395B-A-GM^{1, 2}

Si5395C-A-GM^{1, 2}

Si5395D-A-GM^{1, 2}

0.0001 to 1028 MHz

0.0001 to 350 MHz

0.0001 to 1028 MHz

0.0001 to 350 MHz

Integer and Fractional

64-QFN

9×9 mm

4/12

External

Integer Only

Up to 3 domains

(Section 4.9.2 Grades P and E)

Si5395P-A-GM^{1, 2}

Precision Calibration

Si5394

Si5394A-A-GM^{1, 2}

Si5394B-A-GM^{1, 2}

Si5394C-A-GM^{1, 2}

Si5394D-A-GM^{1, 2}

0.0001 to 1028 MHz

0.0001 to 350 MHz

0.0001 to 1028 MHz

0.0001 to 350 MHz

Integer and Fractional

44-QFN

7×7 mm

4/4

External

Integer Only

Up to 2 domains

(Section 4.9.2 Grades P and E)

Si5394P-A-GM^{1, 2}

Precision Calibration

Si5392

Si5392A-A-GM^{1, 2}

Si5392B-A-GM^{1, 2}

Si5392C-A-GM^{1, 2}

Si5392D-A-GM^{1, 2}

0.0001 to 1028 MHz

0.0001 to 350 MHz

0.0001 to 1028 MHz

0.0001to 350 MHz

Integer and Fractional

44-QFN

7×7 mm

4/2

External

Integer Only

1 domain

(Section 4.9.2 Grades P and E)

Si5392P-A-GM^{1, 2}

Precision Calibration

Si5395/94/92 Evaluation Board

64-QFN

EVB

Si5395A-A-EVB

Si5395P-A-EVB

Si5394A-A-EVB

Si5394P-A-EVB

12-output

Any-frequency, any Output

—

Low jitter clocks for 56G PAM4

SerDes

64-QFN

EVB

12-output

4-output

44-QFN

EVB

Any-frequency, any Output

Low jitter clocks for 56G PAM4

SerDes

44-QFN

EVB

Notes:

1. Add an R at the end of the OPN to denote tape and reel ordering options.

2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuilder

Pro software utility. Custom part number format is “Si5395A-Axxxxx-GM” where “xxxxx” is a unique numerical sequence repre-

senting the preprogrammed configuration.

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Si5395/94/92 Data Sheet

Ordering Guide

Table 3.2. Si5395/4/2 J/K/L/M/E Ordering guide (Integrated Reference)

Ordering Part

Number (OPN)

Number of Input/

Output Clocks

Output Clock

Frequency Range (MHz)

Supported Frequency

Synthesis Modes

Package

Reference

Si5395

Si5395J-A-GM^{1, 2}

Si5395K-A-GM^{1, 2}

Si5395L-A-GM^{1, 2}

Si5395M-A-GM^{1, 2}

0.0001 to 1028 MHz

0.0001 to 350 MHz

0.0001 to 1028 MHz

0.0001 to 350 MHz

Integer and Fractional

64-LGA

9×9 mm

4/12

Internal

Integer Only

Up to 3 domains

(Section 4.9.2 Grades P and E)

Si5395E-A-GM^{1, 2}

Precision Calibration

Si5394

Si5394J-A-GM^{1, 2}

Si5394K-A-GM^{1, 2}

Si5394L-A-GM^{1, 2}

Si5394M-A-GM^{1, 2}

0.0001 to 1028 MHz

0.0001 to 350 MHz

0.0001 to 1028 MHz

0.0001 to 350 MHz

Integer and Fractional

44-LGA

7×7 mm

4/4

Internal

Integer Only

Up to 2 domains

(Section 4.9.2 Grades P and E)

Si5394E-A-GM^{1, 2}

Precision Calibration

Si5392

Si5392J-A-GM^{1, 2}

Si5392K-A-GM^{1, 2}

Si5392L-A-GM^{1, 2}

Si5392M-A-GM^{1, 2}

0.0001 to 1028 MHz

0.0001 to 350 MHz

0.0001 to 1028 MHz

0.0001to 350 MHz

Integer and Fractional

44-LGA

7×7 mm

4/2

Internal

Integer Only

1 domain

(Section 4.9.2 Grades P and E)

Si5392E-A-GM^{1, 2}

Precision Calibration

Si5395/94/92 Evaluation Board

64-LGA

EVB

Si5395J-A-EVB

Si5395E-A-EVB

Si5394J-A-EVB

Si5394E-A-EVB

Si5392J-A-EVB

Si5392E-A-EVB

12-output

Any-frequency, any Output

—

Low jitter clocks for 56G PAM4

SerDes

64-LGA

EVB

12-output

4-output

2-output

44-LGA

EVB

Any-frequency, any Output

Low jitter clocks for 56G PAM4

SerDes

44-LGA

EVB

44-LGA

EVB

Any-frequency, any Output

Low jitter clocks for 56G PAM4

SerDes

44-LGA

EVB

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Rev. 1.1 | 5

Si5395/94/92 Data Sheet

Ordering Guide

Ordering Part

Number (OPN)

Number of Input/

Output Clocks

Output Clock

Frequency Range (MHz)

Supported Frequency

Synthesis Modes

Package

Reference

Notes:

1. Add an R at the end of the OPN to denote tape and reel ordering options.

2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuilder

Pro software utility. Custom part number format is “Si5395J-Axxxxx-GM” where “xxxxx” is a unique numerical sequence repre-

senting the preprogrammed configuration.

Figure 3.1. Ordering Part Number Fields

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Rev. 1.1 | 6

Table of Contents

1. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.3 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.4.1 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.4.2 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.4.3 Lock Acquisition Mode . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.4.4 Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.4.5 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.4.6 Frequency-on-the-Fly (FOTF) . . . . . . . . . . . . . . . . . . . . . . .11

4.5 Digitally Controlled Oscillator (DCO) Mode (Grade A/B/C/D and J/K/L/M ) . . . . . . . . . .11

4.6 External Reference (Grade A/B/C/D/P Only) . . . . . . . . . . . . . . . . . . . .12

4.7 Inputs (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.7.1 Manual Input Selection (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . .13

4.7.2 Automatic Input Selection (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . .13

4.7.3 Hitless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.7.4 Frequency Ramped Input Switching . . . . . . . . . . . . . . . . . . . . .15

4.7.5 Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . .15

4.7.6 Synchronizing to Gapped Input Clocks (Grade A/B/C/D and J/K/L/M Only) . . . . . . . .16

4.8 Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.8.1 Input LOS Detection. . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.8.2 XA/XB LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.8.3 OOF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.8.4 LOL Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.8.5 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.9 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.9.1 Grade A/B/C/D and J/K/L/M . . . . . . . . . . . . . . . . . . . . . . . .19

4.9.2 Grades P and E . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.9.3 Output Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.9.4 Output Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.9.5 Programmable Common Mode Voltage For Differential Outputs . . . . . . . . . . . .21

4.9.6 LVCMOS Output Impedance Selection . . . . . . . . . . . . . . . . . . . .21

4.9.7 LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . .21

4.9.8 LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . .21

4.9.9 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.9.10 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . . .22

4.9.11 Synchronous Output Disable Feature . . . . . . . . . . . . . . . . . . . .22

4.9.12 Input/Output Skew Control . . . . . . . . . . . . . . . . . . . . . . . .22

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4.9.13 Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.9.14 Output Divider (R) Synchronization . . . . . . . . . . . . . . . . . . . . .23

4.10 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.11 In-Circuit Programming. . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.12 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.13 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .23

4.14 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . 42

7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8. Typical Operating Characteristics

9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

. . . . . . . . . . . . . . . . . . . . . .44

10.1 Si5395 A/B/C/D/P (External Reference) 9x9 mm 64-QFN Package Diagram . . . . . . . . .52

10.2 Si5395 J/K/L/M/E (Internal Reference) 9x9 mm 64-LGA Package Diagram . . . . . . . . .53

10.3 Si5394 and Si5392 A/B/C/D/P (External Reference) 7x7 mm 44-QFN Package Diagram . . . .54

10.4 Si5394 and Si5392 J/K/L/M/E (Internal Reference) 7x7 mm 44-LGA Package Diagram . . . . .55

11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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Si5395/94/92 Data Sheet

Functional Description

4. Functional Description

The Si5392-95’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input frequency. Fractional

input dividers (P) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally related. Input switching is

controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which

determines output frequency stability and accuracy while the device is in free-run or holdover mode. The high-performance MultiSynth

dividers (N) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the

MultiSynth generated frequencies to any of the outputs. Additional integer division (R) determines the final output frequency.

4.1 Frequency Configuration

The frequency configuration of the DSPLL is programmable through the serial interface and can also be stored in non-volatile memory.

The combination of fractional input dividers (P_n/P_d), fractional frequency multiplication (M_n/M_d), fractional output MultiSynth division

(N_n/N_d), and integer output division (R_n) allows the generation of virtually any output frequency on any of the outputs. All divider values

for a specific frequency plan are easily determined using the ClockBuilder Pro utility.

4.2 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-

tings in the range of 0.1 Hz to 4 kHz are available for selection for Grade A/B/C/D. Since the loop bandwidth is controlled digitally, the

DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. For grade P and E devi-

ces, the DSPLL bandwidth is fixed at 100 Hz.

4.3 Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting

a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-

ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of in the range of 100 Hz to 4 kHz are available for selection. The

DSPLL will revert to its normal loop bandwidth once lock acquisition has completed.

4.4 Modes of Operation

Once initialization is complete the DSPLL operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or

Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of

these modes in greater detail.

Power-Up

Reset and

Initialization

No valid

input clocks

selected

Free-run

Valid input clock

selected

Lock Acquisition

(Fast Lock)

Phase lock on

selected input

clock is achieved

An input is

qualified and

available for

selection

Locked

Mode

No valid input

clocks available

for selection

Holdover

Mode

Input Clock

Switch

Selected input

clock fails

Yes

No

Other Valid

Clock Inputs

Available?

Yes

Holdover

History

Valid?

No

Figure 4.1. Modes of Operation

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Si5395/94/92 Data Sheet

Functional Description

4.4.1 Initialization and Reset

Once power is applied, the device begins an initialization period, downloads default register values and configuration data from NVM,

and performs other initialization tasks. To communicate with the device through the serial interface, wait untl the initialization period is

complete. No clocks will be generated until the initialization is complete.

Clocks that feature the integrated crystal may require a slightly longer settling time compared to the external crystal device. See the

Reference Manual for more details.

Two types of resets are available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values

stored in NVM and all circuits including the serial interface will be restored to their initial state. A hard reset is initiated using the RSTb

pin or by asserting the hard reset register bit.

A soft reset bypasses the NVM download. It is used to initiate register configuration changes.

4.4.2 Freerun Mode

The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency ac-

curacy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or refer-

ence clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their

configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A

TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes.

4.4.3 Lock Acquisition Mode

The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL will automatically

start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth

setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs

will generate a clock that follows the VCO frequency change as it pulls in to the input clock frequency.

4.4.4 Locked Mode

Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this

point, any XTAL frequency drift will not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is ach-

ieved. See 4.8.4 LOL Detection for more details on the operation of the loss-of-lock circuit.

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Si5395/94/92 Data Sheet

Functional Description

4.4.5 Holdover Mode

The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are

available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance

of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for the DSPLL stores up to 120 sec-

onds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a

programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in

the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency

data that may be corrupt just before the input clock failure.

Clock Failure and Entry

into Holdover

Historical Frequency Data Collected

time

Programmable historical data window used to

determine the final holdover value

Programmable delay

120 seconds

0

Figure 4.2. Programmable Holdover Window

When entering holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in hold-

over, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If

the clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This

process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is

glitchless and its rate is controlled by the DSPLL or the Fastlock bandwidth.

The DSPLL output frequency when exiting holdover can be ramped (recommend). Just before the exit is initiated, the difference be-

tween the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selecta-

ble ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40

values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit

from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on

ramped input switching, see 4.7.4 Frequency Ramped Input Switching.

Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable

holdover exit BW.

4.4.6 Frequency-on-the-Fly (FOTF)

The Si5395/94/92 use register writes to support frequency-on-the-fly to allow frequency changes on one MultiSynth without affecting

the clocks generated from other MultiSynths. See the Si5395-94-92 Family Reference Manual and AN1178: Frequency-On-the-Fly for

Silicon Labs Jitter Attenuators and Clock Generators for more details.

4.5 Digitally Controlled Oscillator (DCO) Mode (Grade A/B/C/D and J/K/L/M )

The output MultiSynths support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency

step words (FSW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increment

(FINC) or decrement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it.

Any number of MultiSynths can be updated at once or independently controlled. The DCO mode is available when the DSPLL is operat-

ing in either free-run or locked mode.

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Si5395/94/92 Data Sheet

Functional Description

4.6 External Reference (Grade A/B/C/D/P Only)

An external crystal (XTAL) or crystal oscillator (XO) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter

reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown

in the figure below. The device includes internal XTAL loading capacitors which eliminates the need for external capacitors and also

has the benefit of reduced noise coupling from external sources. Refer to Table 5.12 External Crystal Specifications for Grades

A/B/C/D/P on page 39 for crystal specifications. For the A/B/C/D grades, a crystal in the range of 48 MHz to 54 MHz is recommended

for best jitter performance. The P grade devices must use a high quality 48 MHz crystal to achieve the ultra low jitter specification. The

family referernce manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter per-

formance.

To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. For SyncE

pizza box applications (e.g. loop bandwidth set to 0.1 Hz), a TCXO is required on the XA/XB reference to minimize wander and to pro-

vide a stable holdover reference. See the Si5395-94-92 Family Reference Manual for more information. Selection between the external

XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in the REFCLK mode.

Refer to Table 5.3 Input Clock Specifications on page 26 for REFCLK requirements when using this mode. A PREF divider is availa-

ble to accommodate external clock frequencies higher than 54 MHz. Frequencies in the range of 48 MHz to 54 MHz will achieve the

best output jitter performance.

25-54 MHz

XO/Clock

LVCMOS

C1 is recommended

to increase the slew

rate at Xa

C1

R1

See the Reference Manual for the

recommended R1, R2, C1 values

25-54 MHz

XTAL

R2

Note: See Pin

Descriptions for

X1/X2 connections

nc nc

X1

X2

XB

XA

XB

XA

X2

XB

XA

X2

2xC_L

OSC

÷ PXAXB

Crystal Resonator

Connection

Differential XO/Clock

Connection

LVCMOS XO/Clock

Connection

(Recommended)

(Not Recommended)

Note: XA and XB must not exceed the maximum input voltage listed in Table 5.3 Input Clock Specifications on page 24

Figure 4.3. Crystal Resonator and External Reference Clock Connection Options

Note that connecting an external reference to a device that already has an integrated reference (grades J/K/L/M/E) is not allowed. Do-

ing so could lead to internal damage to the circuits.

4.7 Inputs (IN0, IN1, IN2, IN3)

There are four inputs that can be used to synchronize to the DSPLL. The inputs accept three formats of input clock: Standard Differen-

tial/Single-Ended, Standard LVCMOS or Pulsed CMOS (See Family Reference Manual for more details). Input selection can be manual

(pin or register controlled) or automatic with user definable priorities.

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Si5395/94/92 Data Sheet

Functional Description

4.7.1 Manual Input Selection (IN0, IN1, IN2, IN3)

Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection

as pin selectable (default) or register selectable. If there is no clock signal on the selected input, the device will automatically enter free-

run or holdover mode. When the zero delay mode is enabled, IN3 becomes the feedback input (FB_IN) and is not available for

selection as a clock input.

Table 4.1. Manual Input Selection Using IN_SEL[1:0] Pins

Selected Input

IN_SEL[1:0]

Zero Delay Mode Disabled

Zero Delay Mode Enabled

0

1

0

1

0

1

IN0

IN1

IN2

IN3

IN0

IN1

IN2

Reserved

4.7.2 Automatic Input Selection (IN0, IN1, IN2, IN3)

An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection

criteria is based on input clock qualification, input priority, and the revertive option. Only input clocks that are valid can be selected by

the automatic clock selection state machine. If there are no valid input clocks available the DSPLL will enter the holdover mode. With

revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority be-

comes valid then an automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain

selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be initiated.

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Si5395/94/92 Data Sheet

Functional Description

4.7.3 Hitless Input Switching

Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that

have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked meaning that they

have to be exactly at the same frequency, or at an integer frequency relationship to each other. When hitless switching is enabled, the

DSPLL simply absorbs the phase difference between the two input clocks during a input switch. When disabled, the phase difference

between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature

supports clock frequencies down to the minimum input frequency of 8 kHz; however, for optimum hitless switching performance, higher

input frequencies are recommended.

Figure 4.4. Output Phase Transient—Hitless Switching between Two 25 MHz Inputs (0 ppm, 180 Degree Phase Shift)

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Rev. 1.1 | 14

Si5395/94/92 Data Sheet

Functional Description

4.7.4 Frequency Ramped Input Switching

The ramped input switching feature is enabled/disabled depending on both the frequency of the Phase-Frequency detector (Fpfd) and

the difference in input frequencies (Zero-PPM vs non-zero PPM). The table below shows the selection criteria to enable ramped input

switching. The same ramp rate settings are used for both holdover exit and clock switching. For more information on ramped exit from

holdover, see 4.4.5 Holdover Mode and the Si5395-94-92 Family Reference Manual.

Figure 4.5. Output Frequency Transient—Ramped Switching between Two 8 kHz Inputs (±4.6 ppm Offset)

Table 4.2. Recommended Ramped Input Switching Settings for Internal Clock Switches

Fpfd¹< 500 kHz

Ramped Exit from Holdover

Fpfd¹≥ 500 kHz

Maximum Input Frequency Difference

0 ppm Frequency Locked

≤ 10 ppm

> 10 ppm

Ramped Input Switching and Ramped Exit from Holdover Ramped Exit from Holdover

Ramped Input Switching and Ramped Exit from Holdover

Note:

1. The Fpfd value is determineby various requirements of the frequency plan and is displayed in the CBPro project file.

Always enable hitless switching and enable phase buildout on holdover exit. See the latest version of CBPro to properly configure the

device.

.

4.7.5 Glitchless Input Switching

The glitchless switching feature allows the DSPLL to switch between two input clock frequencies that are up to ±500 ppm apart without

an abrupt phase change at the output. The DSPLL will pull-in to the new frequency using a ramped frequency step (if ramping is ena-

bled) or using Fastlock/nominal lock parameters (if ramping is disabled).

The loss of lock (LOL) indicator will assert while the DSPLL is pulling-in to the new clock frequency.

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Si5395/94/92 Data Sheet

Functional Description

4.7.6 Synchronizing to Gapped Input Clocks (Grade A/B/C/D and J/K/L/M Only)

The DSPLL supports locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose of

gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely

increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic

clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For exam-

ple, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is

shown in the following figure. For more information on gapped clocks, see “AN561: Introduction to Gapped Clocks and PLLs”.

Gapped Input Clock

100 MHz clock

1 missing period every 10

Periodic Output Clock

90 MHz non-gapped clock

100 ns

DSPLL

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

10

Period Removed

10 ns

11.11111... ns

Figure 4.6. Generating an Averaged Clock Output Frequency from a Gapped Clock Input

A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every eight. Lock-

ing to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the

hitless switching specification in Table 5.8 Performance Characteristics on page 34 when the switch occurs during a gap in either

input clock.

4.8 Fault Monitoring

All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the fig-

ure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is

also a Loss Of Lock (LOL) indicator, which is asserted when the DSPLL loses synchronization.

XA XB

Si5395/94/92

OSC

IN0

Precision

Fast

LOS

OOF

÷P₀

÷P₁

÷P₂

÷P₃

IN0b

DSPLL

IN1

Precision

Fast

LOL

IN1b

PD LPF

÷M

Precision

Fast

IN2

IN2b

IN3/FB_IN

Precision

Fast

IN3/FB_INb

Figure 4.7. Si5395/94/92 Fault Monitors

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Rev. 1.1 | 16

Si5395/94/92 Data Sheet

Functional Description

4.8.1 Input LOS Detection

The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of

the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal

sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status

register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option

to disable any of the LOS monitors is also available.

Sticky

Monitor

LOS

en

Live

Figure 4.8. LOS Status Indicators

4.8.2 XA/XB LOS Detection

A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when

XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is

detected.

4.8.3 OOF Detection

Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0_ppm” reference. This

OOF reference can be selected as either:

• XA/XB pins

• Any input clock (IN0, IN1, IN2, IN3)

The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure

below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state, and its sticky

register bit stays asserted until cleared.

Sticky

Monitor

Precision

Fast

en

LOS

OOF

Live

en

Figure 4.9. OOF Status Indicator

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Rev. 1.1 | 17

Si5395/94/92 Data Sheet

Functional Description

4.8.3.1 Precision OOF Monitor

The precision OOF monitor circuit measures the frequency of all input clocks to within ±1/16 ppm accuracy with respect to the selected

OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range which is register configura-

ble up to ±512 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling

at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency

range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of

the XA/XB pins is available. This option is register configurable.

OOF Declared

OOF Cleared

f_IN

Hysteresis

-4 ppm

(Clear)

-6 ppm

(Set)

+4 ppm

(Clear)

+6 ppm

(Set)

0 ppm

OOF Reference

Figure 4.10. Example of Precise OOF Monitor Assertion and Deassertion Triggers

4.8.3.2 Fast OOF Monitor

Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored

input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in

frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quick-

ly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than

±4000 ppm.

4.8.4 LOL Detection

The Loss Of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock. There

is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency differ-

ence between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indi-

cator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to

allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from

toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The

live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects

the current state of the LOL monitor.

LOL Monitor

Sticky

LOL

Clear

Timer

LOS

LOL

Set

Live

LOLb

DSPLL

f_IN

PD LPF

Feedback

Clock

÷M

Si5395/94/92

Figure 4.11. LOL Status Indicators

The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.1 ppm to 10,000 ppm. Having two sep-

arate frequency monitors allows for hysteresis to help prevent chattering of LOL status.

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Rev. 1.1 | 18

Si5395/94/92 Data Sheet

Functional Description

An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase

detector and LOL is indicated when there’s more than 1 ppm frequency difference is shown in the following figure.

Clear LOL

Threshold

Set LOL

Threshold

Lock Acquisition

Lost Lock

LOL

Hysteresis

LOCKED

0

0.1

1

10,000

Phase Detector Frequency Difference (ppm)

Figure 4.12. LOL Set and Clear Thresholds

An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input

clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The

configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using

the ClockBuilder Pro utility.

4.8.5 Interrupt Pin (INTRb)

An interrupt pin (INTRb) indicates a change in state of the status indicators (LOS, OOF, LOL, HOLD). Any of the status indicators are

maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the

interrupt.

4.9 Outputs

Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats. In addi-

tion to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing

up to 20 single-ended outputs, or any combination of differential and single-ended outputs.

4.9.1 Grade A/B/C/D and J/K/L/M

The Si539x "standard" grades A/B/C/D (external reference) and J/K/L/M (integrated reference) can generate any output frequency in

any format with best-in-class jitter. These devices are available as a preprogrammed option or can be written to the device via I²C. The

input/output frequency plan determines whether the output divider operates in integer or fractional mode. In the fractional mode, the

device can generate any output frequency or any format from any input frequency with best-in-class jitter. Some frequency plans allow

the user to use an integer mode that delivers even lower jitter. See the Si5395-94-92 Family Reference Manual for more details.

PHYs

156.25 MHz

Backplane

Clock

Si5395A

Jitter

Attenuator

19.44 MHz

PHYs

155.52 MHz

Figure 4.13. Si5395 A/B/C/D/J/K/L/M Jitter Attenuator

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Si5395/94/92 Data Sheet

Functional Description

4.9.2 Grades P and E

Some applications, like 56G PAM4 SerDes, require even higher performance (< 100fs MAX) than is already provided by standard Sili-

con Labs jitter attenuators (<140fs MAX). The Si539x grades P (external reference) and E (integrated reference) are Precision grade

jitter attenuators that calibrate out linearity errors to deliver the world's best jitter performance over a wide range of frequency plans.

The Si5392P/E can support 1 clock domain while the Si5394P/E supports 1 or 2 clock domains and the Si5395P/E can support 1, 2 or

3 clock domains while delivering guaranteed low jitter of 100fs MAX on the primary SerDes clocks. The frequencies supported by the 3

domains are

• Domain#1 (Si5395/94/92 P/E) - 156.25/312.5/625 MHz

• Domain#2 (Si5395/94 P/E) - 25/50/100/125/200/156.25/312.5/625 MHz

• Domain#3 (Si5395 P/E) - 25/50/100/125/200/156.25/312.5/625/322.265625/644.53125 MHz

The examples below show examples of how each of the 3 devices can be used as jitter attenuators in 56G Pam4 SerDes applications.

156.25 MHz

PHYs

(100fs MAX)

5

PHYs

Backplane

Clock

PHYs

25 MHz

50 MHz

100 MHz

Si5395P/E

Jitter

System

Clocks

Attenuator

644.53125 MHz /

322.265625 MHz

Si5395P/E typical 56G SerDes application (up to 3

domains)

156.25 MHz

(100fs MAX)

PHYs

Backplane

Clock

Si5394P/E

Jitter

Attenuator

25 MHz

25/50/100/125/200 MHz

Si5394P/E typical 56G SerDes application (up to 2 domains)

Backplane

Clock

156.25 MHz

Si5392P/E

(100fs MAX)

PHYs

25 MHz

Jitter

Attenuator

Si5392P/E typical 56G SerDes application (1 domain)

Figure 4.14. Typical Grade P and Grade E 56G SerDes Applications

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Rev. 1.1 | 20

Si5395/94/92 Data Sheet

Functional Description

The external reference used on the XA/XB pins of the P grade is restricted to a 48 MHz crystal. No other values of crystal or other

reference sources like XO or VCXO are allowed. If the design requires other crystal frequencies, then the standard Si539xA/B/C/D

should be used instead of the Si539xP.

To deliver guaranteed jitter performance 100fs MAX on the 56 G Pam4 SerDes clocks, the additional system clocks must follow some

specific design rules. Additionally, the device input clocks should be traceable back to a Stratum 3 primary reference clock. See the

Si5395/94/92 Family Reference manual for more details on these design rules.

4.9.3 Output Crosspoint

A crosspoint allows any of the output drivers to connect with any of the MultiSynths. The crosspoint configuration is programmable and

can be stored in NVM so that the desired output configuration is ready at power up.

4.9.4 Output Signal Format

The differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including

LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8

V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs.

4.9.5 Programmable Common Mode Voltage For Differential Outputs

The common mode voltage (V_CM) for the differential modes are programmable so that LVDS specifications can be met and for the best

signal integrity with different supply voltages. When DC coupling the output driver, it is essential that the receiver have a relatively high

common mode impedance so that the common mode current from the output driver is very small.

4.9.6 LVCMOS Output Impedance Selection

Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances. A source termination resistor

is recommended to help match the selected output impedance to the trace impedance, where Rs = Transmission line impedance – Z_O.

There are three programmable output impedance selections (CMOS1, CMOS2, CMOS3) for each VDDO option as shown in the follow-

ing table.

Table 4.3. Typical Output Impedance (Z_S)

VDDO

CMOS Drive Selections

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

3.3 V

2.5 V

1.8 V

38 Ω

43 Ω

—

30 Ω

35 Ω

46 Ω

22 Ω

24 Ω

31 Ω

4.9.7 LVCMOS Output Signal Swing

The signal swing (V_OL/V_OH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own

VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

4.9.8 LVCMOS Output Polarity

When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default, the clock

on the OUTx pin is generated with the same polarity (in phase) as the clock on the OUTxb pin. The polarity of these clocks is configura-

ble, enabling complementary clock generation and/or inverted polarity with respect to other output drivers.

4.9.9 Output Enable/Disable

The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high, all outputs are

disabled. When held low, the outputs are enabled. Outputs in the enabled state can be individually disabled through register control.

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Rev. 1.1 | 21

Si5395/94/92 Data Sheet

Functional Description

4.9.10 Output Driver State When Disabled

The disabled state of an output driver is configurable as disable low or disable high.

4.9.11 Synchronous Output Disable Feature

The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will wait until a clock

period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. When

this feature is turned off, the output clock will disable immediately without waiting for the period to complete.

4.9.12 Input/Output Skew Control

The input-output skew can be adjusted in dynamic mode. The dynamic phase adjust will allow the device to dynamically and glitchlessly

change the output phase using register writes with the device still powered up. The skew value may change after each reset or power

cycle. See the family reference manual for more details.

4.9.13 Zero Delay Mode

A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.

The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally

as shown in the figure below. (Zero delay mode is only available for clock inputs that are higher than 128 kHz.)

This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the

outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize

the input-to-output delay. The OUT9 and FB_IN pins are recommended for the external feedback connection. The FB_IN input pins

must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for

best performance. Note that the hitless switching feature is not available when zero delay mode is enabled.

IN0

÷P₀

IN0b

IN1

DSPLL

÷P₁

IN1b

PD LPF

IN2

÷P₂

IN2b

÷M

÷5

IN3/FB_IN

÷P₃

VDDO0

OUT0A

OUT0Ab

÷R^0A

÷R₀

÷R₁

IN3/FB_INb

OUT0

OUT0b

VDDO1

OUT1

OUT1b

t₀

t₁

t₂

t₃

t₄

÷N₀

÷N₁

÷N₂

÷N₃

÷N₄

VDDO2

OUT2

OUT2b

÷R₂

VDDO7

OUT7

OUT7b

÷R₇

÷R₈

VDDO8

OUT8

OUT8b

OUT9

OUT9b

÷R₉

OUT9A

OUT9Ab

÷R^9A

VDDO9

External Feedback Path

Figure 4.15. Si5395 Zero Delay Mode Setup

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Si5395/94/92 Data Sheet

Functional Description

4.9.14 Output Divider (R) Synchronization

All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable

phase alignment across all output drivers that are connected to the same N divider.

4.10 Power Management

Unused inputs and output drivers can be powered down when unused. Consult the Si5395-94-92 Family Reference Manual and Clock-

Builder Pro configuration utility for details.

4.11 In-Circuit Programming

The Si5395/94/92 is fully configurable using the serial interface (I²C or SPI). At power-up the device downloads its default register val-

ues from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to

generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power

supply voltages applied to its V_DDand V_DDApins. The NVM is two time writable. Once a new configuration has been written to NVM,

the old configuration is no longer accessible. Refer to the Si5395-94-92 Family Reference Manual for a detailed procedure for writing

registers to NVM.

4.12 Serial Interface

Configuration and operation of the Si5395/94/92 is controlled by reading and writing registers using the I²C or SPI interface. The

I2C_SEL pin selects I²C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in

either 4-wire or 3-wire. See the Si5395-94-92 Family Reference Manual for details.

4.13 Custom Factory Preprogrammed Parts

For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered

with a specific configuration written into NVM. A factory preprogrammed part will generate clocks at power-up. Custom, factory-preprog-

rammed devices are available. The ClockBuilder Pro custom part number wizard can be used to quickly and easily generate a custom

part number for your configuration.

In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your

design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local

Silicon Labs sales representative. Samples of your preprogrammed device will typically ship in about two weeks.

4.14 Register Map

The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible

registers, such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as

frequency configuration, and general device settings. Refer to the Si5395-94-92 Family Reference Manual for a complete list of register

descriptions and settings. It is strongly recommended that ClockBuilder Pro be used to create and manage register settings.

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Rev. 1.1 | 23

Si5395/94/92 Data Sheet

Electrical Specifications

5. Electrical Specifications

Table 5.1. Recommended Operating Conditions¹

Parameter

Ambient Temperature

Junction Temperature

Symbol

T_A

Min

–40

—

Typ

25

Max

Unit

°C

V

85

TJ_MAX

V_DD

—

125

1.71

3.14

2.37

1.71

3.14

1.71

1.80

3.30

2.50

1.80

3.30

1.80

1.89

3.47

2.62

1.89

3.47

1.89

Core Supply Voltage

V_DDA

V

V_DDO

Clock Output Driver Supply Voltage

V

V_DDS

Status Pin Supply Voltage

V

Note:

1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-

ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

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Rev. 1.1 | 24

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.2. DC Characteristics

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDIO/V_DDS= 3.3 V ±5%, 1.8 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to

85 °C

Parameter

Symbol

Test Condition

Si5395

Min

—

Typ

150

125

115

22

Max

300

250

140

130

26

Unit

mA

I_DD

Si5394/92

Si5395

—

Core Supply Current^{1, 2, 3}

—

I_DDA

Si5394/92

—

2.5 V LVPECL Output⁴

2.5 V LVDS Output⁴

3.3 V LVCMOS Output⁵

2.5 V LVCMOS Output⁵

1.8 V LVCMOS Output⁵

Si5395¹

—

15

22

18

30

mA

mW

I_DDOx

Output Buffer Supply Current

18

23

12

16

1000

750

680

1400

1100

1000

Total Power Dissipation⁶

Si5394²

P_d

Si5392³

Notes:

1. Si5395 test configuration: 7 x 2.5 V LVDS outputs enabled at 156.25 MHz. Excludes power in termination resistors.

2. Si5394 test configuration: 4 x 2.5 V LVDS outputs enabled at 156.25 MHz. Excludes power in termination resistors.

3. Si5392 test configuration: 2 x 2.5 V LVDS outputs enabled at 156.25 MHz. Excludes power in termination resistors.

4. Differential outputs enabled at 156.25 MHz and terminated into an ac-coupled 100 Ω load.

Differential Output Test Configuration

0.1 uF

IDDO

50

OUT

100 Ω

OUTb

50

0.1 uF

5. LVCMOS outputs enabled at 156.25 MHz and measured into a 5 inch 50 Ω PCB trace with 4.7 pF load. Measurements were

made with OUTx_CMOS_DRV=3. See Reference Manual for more details on register settings.

LVCMOS Output Test Configuration

Trace length 5

inches

499

50 Scope Input

50

I^DDO

OUTx

56

4.7pF

499

OUTxb

4.7pF

6. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is

not available. All EVBs support detailed current measurements for any configuration.

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Rev. 1.1 | 25

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.3. Input Clock Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Standard Differential or Single-Ended - AC Coupled Input Buffer (IN0/IN0b, IN1/IN1b, IN2/IN2b, IN3/FB_IN, IN3b/FB_INb)

Differential

0.008

—

750

250

MHz

f_IN

Input Frequency Range

All Single-ended signals

(including LVCMOS)

Differential AC-coupled

f_IN< 250 MHz

100

225

100

—

1800

3600

mVpp_se

Differential AC-coupled

250 MHz < f_IN< 750 MHz

Single-ended AC-coupled

f_IN< 250 MHz

Voltage Swing¹

V_IN

Slew Rate^{2, 3}

SR

DC

400

40

—

2.4

16

8

—

60

—

V/µs

%

Duty Cycle

C_IN

Input Capacitance

pF

R_{IN_DIFF}

R_{IN_SE}

Input Resistance Differential

Input Resistance Single-Ended

—

kΩ

—

LVCMOS / Pulsed CMOS DC-Coupled Input Buffer (IN0, IN1, IN2, IN3/FB_IN)⁴

Standard CMOS &

Non-standard CMOS

0.008

—

250

MHz

f_{IN_CMOS}

Input Frequency

Input Voltage⁵

Pulsed CMOS

0.008

—

1

MHz

V

Standard CMOS

0.5

V_IL

Non-standard CMOS &

Pulsed CMOS

—

1.3

0.8

400

40

—

0.4

—

V

Standard CMOS

V_IH

SR

DC

Non-standard CMOS &

Pulsed CMOS

—

V

Slew Rate^{2, 3}

Duty Cycle

—

V/µs

Standard CMOS &

Non-standard CMOS

60

95

%

Pulsed CMOS

Standard CMOS &

5

Non-standard CMOS

(250 MHz @ 40% Duty Cycle)

1.6

—

Minimum Pulse Width

Input Resistance

PW

R_IN

ns

Pulsed CMOS

(1 MHz @ 40% Duty Cycle)

50

—

8

—

kΩ

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Rev. 1.1 | 26

Si5395/94/92 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

REFCLK (Applied to XA/XB) (Grade A/B/C/D)

Full operating range. Jitter per-

formance may be reduced.

24.97

48

—

54.06

54

MHz

Range for best jitter.

f_{IN_REF}

REFCLK Frequency

TCXO frequency for SyncE

applications. Jitter perform-

ance may be reduced.

—

40

—

MHz

Input Single-ended Voltage

Swing

V_{IN_SE}

V_{IN_DIFF}

SR

365

2000

mVpp_se

Input Differential Voltage Swing

365

400

40

2500

—

mVpp_diff

V/µs

Slew Rate^{2, 3}

Duty Cycle

Note:

—

DC

60

%

1. Voltage swing is specified as single-ended mVpp.

OUTx

Vcm

Vpp_se

Vpp_diff = 2*Vpp_se

OUTxb

2. Recommended for specified jitter performance. Slew rate can go lower, but jitter performance could degrade if the minimum slew

rate specification is not met (see the Si5395-94-92 Family Reference Manual).

3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20= ((0.8 – 0.2) x V_{IN_Vpp_se}) / SR.

4. Standard, Non-standard and Pulsed CMOS refer to different formats of CMOS each with a voltage swing of 1.8V, 2.5V or 3.3V

+/-5%.

• Standard CMOS refers to the industry standard LVCMOS signal.

• Non-standard CMOS refers to a signal that has been attenuated/level-shifted in order to comply with the specified non-stand-

ard VIL and VIH specifications.

• Pulsed CMOS refers to a signal that has been attenuated/level-shifted and has a low/high duty cycle and must be dc coupled.

A typical application example is a low-frequency video frame sync pulse.

Refer to the Si5395-94-92 Family Reference Manual for the recommended connections/termination for the different modes.

5. CMOS signals that exceed 3.3 V + 5% can be used as inputs as long as a resistive attenuation network is used to guarantee that

the input voltage at the pin does not violate the device's input ratings. Please refer to the Si5395-94-92 Family Reference Manual

for the recommended connections/termination for this mode.

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Rev. 1.1 | 27

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.4. Serial and Control Input Pin Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDIO/V_DDS= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Si5395 Serial and Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1/SDO, SCLK, A0/CSb, FINC, FDEC, SDA/SDIO)

0.3 ×

V_DDIO

V_IL

V_IH

—

V

1

Input Voltage

0.7 ×

V_DDIO

—

1

C_IN

R_IN

PW

T_UR

Input Capacitance

Input Resistance

Minimum Pulse Width

Update Rate

—

2

—

pF

kΩ

ns

µs

20

—

RSTb, FINC and FDEC

FINC and FDEC

100

1

Si5394/92 Serial and Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1/SDO, SCLK, A0/CSb, SDA/SDIO)

0.3 ×

V_DDIO

V_IL

V_IH

—

V

1

Input Voltage

0.7 ×

V_DDIO

—

1

C_IN

R_IN

PW

Input Capacitance

Input Resistance

Minimum Pulse Width

Note:

—

2

—

pF

kΩ

ns

20

—

RSTb

100

1. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD. See the Si5395-94-92 Family Reference Manual for

more details on the proper register settings.

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Rev. 1.1 | 28

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.5. Differential Clock Output Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C

Parameter

Si5395/94/92

Symbol

Test Condition

Min

Typ

Max

Unit

0.0001

733.33

825

—

720

800.00

1028

720

MHz

MultiSynth not used

f_OUT

Output Frequency

MultiSynth used

MultiSynth used:

f_OUT< 400 MHz

MultiSynth used:

0.0001

48

—

52

%

Duty Cycle¹

DC

45

25

—

55

75

%

400 MHz < f_OUT<= 720

MHz

MultiSynth not used:

f_OUT< 1028 MHz

V_DDO= 3.3 V,

LVDS

350

630

450

780

530

950

mVpp_se

2.5 V, 1.8 V

Output Voltage Swing²

VOUT

V_DDO= 3.3 V,

2.5 V

LVPECL

LVDS

LVPECL

LVDS

1.1

1.9

1.2

2.0

1.3

2.1

V

V_DDO= 3.3 V

Common Mode Voltage^{2, 3}

(100 Ω load line-to-line)

VCM

V_DDO= 2.5 V

V_DDO= 1.8 V

1.1

1.2

1.3

V

sub-LVDS

0.8

—

0.9

0

1.0

75

V

f_OUT= 712.5 MHz

Output-to-Output Skew

(Same MultiSynth)

T_SKS

ps

(LVDS)

Measured from positive to

negative output pins (LVDS)

Out-Outb Skew on one output

TSK_OUT

—

0

50

ps

f_OUT> 100 MHz (20% to

80%)

Rise and Fall Times²

t_r/t_f

ZO

100

200

Differential Output Impedance

—

100

–101

–96

–99

–97

–72

–88

—

Ω

10 kHz sinusoidal noise

100 kHz sinusoidal noise

500 kHz sinusoidal noise

1 MHz sinusoidal noise

Si5395

dBc

Power Supply Noise Rejec-

tion³

PSRR

Output-to-Output Crosstalk⁴

XTALK

Si5394/92

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Rev. 1.1 | 29

Si5395/94/92 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

1. Duty cycle can vary depending on frequency plan (output frequency and divide ratios).

2. Output amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each out-

put driver can be programmed independently. Note that the maximum LVDS single-ended amplitude can be up to 110 mV higher

than the TIA/EIA-644 maximum. Refer to the Si5395-94-92 Family Reference Manual for more suggested output settings. Not all

combinations of voltage amplitude and common mode voltages settings are possible.

OUTx

Vcm

Vpp_se

Vpp_diff = 2*Vpp_se

OUTxb

Differential Output Test Configuration

0.1 uF

IDDO

50

OUT

100 Ω

OUTb

50

0.1 uF

3. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude meas-

ured.

4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25

MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on

crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk.

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Rev. 1.1 | 30

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.6. LVCMOS Clock Output Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

Test Condition

Min

0.0001

48

Typ

—

Max

250

52

Unit

MHz

%

f_OUT

Output Frequency

f_OUT<100 MHz

—

Duty Cycle

DC

100 MHz < f_OUT< 250 MHz

44

—

56

%

V_DDO= 3.3 V

I_OH= –10 mA V_DDOx 0.85

I_OH= –12 mA V_DDOx 0.85

I_OH= –17 mA V_DDOx 0.85

V_DDO= 2.5 V

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

Output Voltage High^{1, 2, 3}

V_OH

I_OH= –6 mA

I_OH= –8 mA

V_DDOx 0.85

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

I_OH= –11 mA V_DDOx 0.85

V_DDO= 1.8 V

I_OH= –4 mA

I_OH= –5 mA

V_DDOx 0.85

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

V_DDOx 0.85

V_DDO= 3.3 V

I_OL= 10 mA

I_OL= 12 mA

I_OL= 17 mA

V_DDOx 0.15

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

—

V_DDO= 2.5 V

Output Voltage Low^{1, 2, 3}

V_OL

I_OL= 6 mA

I_OL= 8 mA

I_OL= 11 mA

V_DDOx 0.15

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

—

V_DDO= 1.8 V

I_OL= 4 mA

I_OL= 5 mA

V_DDO= 3.3V

V_DDOx 0.15

600

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

400

450

550

ps

Rise and Fall Times³

t_r/t_f

V_DDO= 2.5 V

V_DDO= 1.8 V

(20% to 80%)

—

600

750

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Rev. 1.1 | 31

Si5395/94/92 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Note:

1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the

Si5395-94-92 Family Reference Manual for more details on register settings.

2. I_OL/I_OHis measured at V_OL/V_OHas shown in the DC test configuration.

DC Test Configuration

I_DDO

I_OL/I_OH

Zs

V_OL/V_OH

3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 Ω PCB trace. A 4.7 pF capacitive

load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, at 156.25 MHz.

LVCMOS Output Test Configuration

Trace length 5

inches

499

50 Scope Input

50

I_DDO

OUTx

56

4.7pF

499

OUTxb

50

4.7pF

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Rev. 1.1 | 32

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.7. Output Status Pin Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDIO/V_DDS= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Si5395 Status Output Pins (LOLb, INTRb, SDA/SDIO¹, SDO)

V_DDIO²x

0.85

V_OH

I_OH= –2 mA

—

V

Output Voltage

V_DDIO²x

0.15

V_OL

Si5394/92 Status Output Pins (INTRb, SDA/SDIO1¹, SDO)

V_OHI_OH= –2 mA

I_OL= 2 mA

—

V_DDIO²x

0.85

—

V

Output Voltage

V_DDIO²x

0.15

V_OL

I_OL= 2 mA

—

Si5394 Status Output Pins (LOLb, LOS_XAXBb)

Si5392 Status Output Pins (LOLb, LOS_XAXBb, LOS0b, LOS1b, LOS2b, LOS3b)

V_OH

V_OL

I_OH= –2 mA

I_OL= 2 mA

V_DDSx 0.85

—

V

Output Voltage

V_DDSx 0.15

Notes:

1. The V_OHspecification does not apply to the open-drain SDA/SDIO output when the serial interface is in I²C mode or is unused

with I2C_SEL pulled high. VOL remains valid in all cases.

2. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD. See the Si5395-94-92 Family Reference Manual for

more details on the proper register settings.

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Rev. 1.1 | 33

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.8. Performance Characteristics

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

f_BW

Test Condition

Min

0.1

—

Typ

—

Max

4000

45

Unit

Hz

PLL Loop Bandwidth Pro-

gramming Range¹

Initial Start-Up Time

t_START

Time from power-up to when Grade

30

ms

the device generates

free-running clocks

A/B/C/D/J/K/L/M

Grade P/E

—

460

280

0.28

71.4

±1

625

300

—

ms

ps

PLL Lock Time²

t_ACQ

With Fastlock enabled, f_IN= 19.44 MHz

f_VCO= 14 GHz

t_{DELAY_frac}

t_{DELAY_int}

t_RANGE

Output Dynamic Delay Ad-

justment

—

ps

—

ms

POR to Serial Interface

Ready³

t_RDY

—

15

1.5

0.3

ms

ns

Single automatic/manual switch between two 8

kHz inputs, DSPLL BW = 40 Hz

Maximum Phase Transient

During a Hitless Switch⁴

t_SWITCH

Single automatic/manual switch between two 2

MHz inputs, DSPLL BW = 400 Hz

Zero Delay Mode

Input-to-Output Delay Varia-

tion⁵

Between reference and feedback input with both

clocks in LVDS differential format at 128 kHz.

t_ZDELAY

—

0.20

0.1

ns

Measured with a frequency plan running a 25

MHz input, 25 MHz output, and a Loop Band-

width of 4 Hz

J_PK

Jitter Peaking

dB

Compliant with G.8262 Options 1 and 2

for 1G, 10G or 25G Synchronous Ethernet

J_TOL

Jitter Tolerance

Pull-in Range

—

3180

—

UI pk-pk

Jitter Modulation Frequency = 10 Hz

ω_P

—

500

75

—

100

90

ppm

fs

f_in= f_out= 312.5 MHz or 156.25 MHz

f_out= 156.25 MHz

69

fs

f_out= 312.5 MHz

69

95

fs

RMS Phase Jitter

(Grade P)⁶

J_GEN

f_out= 100 MHz

f_in= 25 MHz

150

200

80

200

300

—

fs

f_out= 50/25 MHz

fs

f_out= 644.531248

MHz

fs

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Rev. 1.1 | 34

Si5395/94/92 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

—

Typ

82

Max

110

100

105

200

300

—

Unit

fs

f_in= f_out= 312.5 MHz or 156.25 MHz

f_out= 156.25 MHz

—

71

fs

f_out= 312.5 MHz

f_out= 100 MHz

f_out= 50/25 MHz

—

75

fs

RMS Phase Jitter

(Grade E)⁶

J_GEN

—

150

200

85

fs

f_in= 25 MHz

—

fs

f_out= 644.531248

MHz

—

fs

RMS Phase Jitter

(Grade A/B/C/D and

J/K/L/M)⁷

Output divider Integer Mode

—

85

120

170

fs

J_GEN

Output divider Fractional Mode/DCO Mode

115

Note:

1. Actual loop bandwidth might be lower; please refer to CBPro for actual value for your frequency plan.

2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock

time was measured with nominal bandwidth set to 100 Hz, fastlock bandwidth set to 1 kHz, LOL set/clear thresholds of 6/0.6 ppm

respectively, using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time be-

tween the first rising edge of the clock reference and the LOL indicator deassertion.

3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands.

4. Higher input frequencies will typically result in higher Fpfd frequencies, which, in turn, will result in better hitless switching per-

formance. It is recommended to use higher input frequencies for the best hitless switching performance.

5. Zero-Delay-Mode is dependent on frequency configuration. Using Fpfd < 128 kHz will result in higher delay values. Ref clock rise

time must be <200 ps. Initial Start-Up time can be much higher in Zero Delay mode.

6. Grade P and E are calibrated for optimum performance in 56G/112G SerDes applications at frequencies of 312.5 MHz or 156.25

MHz. Specific layout rules must be followed to achieve optimum performance. For more details, refer to 4.9.2 Grades P and E

and the reference manual.

7. Grades A/B/C/D and J/K/L/M are targeted for applications that require more flexibility and set the output divider to Integer or Frac-

tional modes. Integer mode test conditions: f_in= 19.44 MHz; f_out= 155.52 MHz. Fractional mode test conditions: f_in= 19.44 MHz;

f_out= 125 MHz. All outputs are assumed to be LVPECL. For more details, refer to 4.9.1 Grade A/B/C/D and J/K/L/M.

Table 5.9. I²C Timing Specifications (SCL, SDA)

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDS/V_DDIO= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C

Standard Mode

100 kbps

Fast Mode

400 kbps

Parameter

Symbol

Test Condition

Unit

Min

—

Max

100

35

Min

Max

400

35

f_SCL

—

SCL Clock Frequency

SMBus Timeout

—

kHz

ms

25

Hold time (Repeated)

START condition

t_HD:STA

t_LOW

4.0

4.7

4.0

—

0.6

1.3

0.6

—

µs

Low Period of the SCL Clock

HIGH Period of the SCL

Clock

t_HIGH

Setup Time for a Repeated

START Condition

t_SU:STA

4.7

—

0.6

—

µs

t_HD:DAT

t_SU:DAT

Data Hold Time

Data Setup Time

100

250

—

100

—

ns

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Rev. 1.1 | 35

Si5395/94/92 Data Sheet

Electrical Specifications

Standard Mode

100 kbps

Fast Mode

400 kbps

Parameter

Symbol

Test Condition

Unit

Min

Max

Min

Max

Rise Time of both SDA and

SCL Signals

t_r

t_f

—

1000

20

—

300

ns

µs

Fall Time of both SDA and

SCL Signals

—

300

—

300

—

Setup Time for STOP Condi-

tion

t_SU:STO

4.0

0.6

Bus Free Time between a

STOP and START Condition

t_BUF

4.7

—

1.3

—

µs

t_VD:DAT

t_VD:ACK

Data Valid Time

3.45

0.9

Data Valid Acknowledge

Time

—

Figure 5.1. I²C Serial Port Timing Standard and Fast Modes

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Rev. 1.1 | 36

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.10. SPI Timing Specifications (4-Wire)

V_DD= 1.8 V ±5%, V_DDA= 3.3V ±5%, V_DDIO= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

f_SPI

Min

—

40

50

—

5

Typ

—

Max

20

60

—

Unit

MHz

%

SCLK Frequency

SCLK Duty Cycle

SCLK Period

T_DC

T_C

—

ns

T_D1

Delay Time, SCLK Fall to SDO Active

Delay Time, SCLK Fall to SDO

Delay Time, CSb Rise to SDO Tri-State

Setup Time, CSb to SCLK

12.5

10

—

18

15

—

ns

T_D2

ns

T_D3

ns

T_SU1

T_H1

T_SU2

T_H2

ns

Hold Time, SCLK Fall to CSb

5

—

ns

Setup Time, SDI to SCLK Rise

Hold Time, SDI to SCLK Rise

5

—

ns

5

—

ns

T_CS

Delay Time Between Chip Selects (CSb)

95

—

ns

T_D1

T_C

T_SU1

SCLK

CSb

T_H1

T_SU2

T_H2

T_CS

SDI

T_D2

T_D3

SDO

Figure 5.2. 4-Wire SPI Serial Interface Timing

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Rev. 1.1 | 37

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.11. SPI Timing Specifications (3-Wire)

V_DD= 1.8 V ±5%, V_DDA= 3.3V ±5%, V_DDIO= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

f_SPI

Min

—

40

50

—

5

Typ

—

Max

20

60

—

Unit

MHz

%

SCLK Frequency

SCLK Duty Cycle

SCLK Period

T_DC

T_C

—

ns

T_D1

Delay Time, SCLK Fall to SDIO Turn-on

Delay Time, SCLK Fall to SDIO Next-bit

Delay Time, CSb Rise to SDIO Tri-State

Setup Time, CSb to SCLK

12.5

10

—

18

15

—

ns

T_D2

ns

T_D3

ns

T_SU1

T_H1

T_SU2

T_H2

ns

Hold Time, CSb to SCLK Fall

5

—

ns

Setup Time, SDI to SCLK Rise

5

—

ns

Hold Time, SDI to SCLK Rise

5

—

ns

T_CS

Delay Time Between Chip Selects (CSb)

95

—

ns

T_SU1

T_C

SCLK

T_H1

T_D1

T_D2

CSb

T_SU2

T_H2

T_CS

SDIO

T_D3

Figure 5.3. 3-Wire SPI Serial Interface Timing

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Rev. 1.1 | 38

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.12. External Crystal Specifications for Grades A/B/C/D/P

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Full operating range. Jit-

ter performance may be

reduced.

24.97

—

54.06

MHz

f_XTAL

(A/B/C/D)

Crystal Frequency Range

Range for best jitter.

±100 ppm crystal

48

—

8

54

48

MHz

pF

f_XTAL(P)

C_L

Load Capacitance

Crystal Drive Level

—

d_L

—

200

µW

r_ESR

C_O

Equivalent Series Resistance

Shunt Capacitance

Note:

Refer to the Si5395-94-92 Family Reference Manual to determine ESR and shunt

capacitance values.

1. Refer to the Si534x/8x/9x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual for recommended 48

to 54 MHz crystals.

Table 5.13. Internal Reference Specifications for Grade J/K/L/M/E^{1, 2}

Parameter

Initial Accuracy

Symbol

Test Condition

Min

Typ

Max

Unit

—

–8

—

+8

ppm

Inclusive of temperature range

of –40 to 125 °C, aging at 115

°C and reflow

Frequency Characteristics across

Temperature

—

–88

–2

—

+88

+2

ppm

Activity Dip

Overall Accuracy

Note:

Frequency Perturbations

Inclusive of Initial Accuracy,

Frequency Characteristics

Across Temperature and Activi-

ty Dips (all items listed above)

—

–98

—

+98

ppm

1. These devices with integrated reference have been tuned with an internal 48 MHz reference to deliver optimum performance. It is

important to note that connecting an external reference to a device that already has an integrated reference is not allowed. Doing

so could lead to internal damage to the circuits.

2. Clocks that feature the integrated crystal may require a slightly longer settling time compared to the external crystal device. See

the Reference Manual for more details.

Table 5.14. Thermal Characteristics 44-QFN and 44-LGA (Si5392 and Si5394)

Parameter

Symbol

Test Condition

Still Air^{1, 2}

44-QFN

22.3

44-LGA

25.49

Unit

°C/W

Thermal Resistance

Air Flow 1 m/s^{1, 2}

Air Flow 2 m/s^{1, 2}

θ_JA

19.4

22.14

Junction to Ambient

18.4

21.13

Thermal Resistance

Junction to Case

θ_JC

10.9

9.87

°C/W

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Rev. 1.1 | 39

Si5395/94/92 Data Sheet

Electrical Specifications

Parameter

Thermal Resistance

Symbol

θ_JB

Test Condition

44-QFN

9.3

44-LGA

9.52

Unit

°C/W

Junction to Board

Thermal Resistance

Junction to Top Center

Note:

Ψ_JB

9.2

9.58

Ψ_JT

0.23

0.81

°C/W

1. 44-QFN: Based on PCB Dimension: 3" x 4.5" PCB Thickness: 1.6 mm, PCB Land/Via: 36, Number of Cu Layers: 4.

2. 44-LGA: Based on 4 layer PCB with dimension 4" x 4.5", PCB Thickness of 1.6 mm, per JEDEC. PCB Center Land with 16 Via to

top internal plane of PCB.

Table 5.15. Thermal Characteristics 64-QFN and 64-LGA (Si5395)

Parameter

Symbol

Test Condition

Still Air^{1, 2}

64-QFN

22

64-LGA

22.3

Unit

°C/W

Thermal Resistance

Air Flow 1 m/s^{1, 2}

Air Flow 2 m/s^{1, 2}

θ_JA

19.4

18.3

19.4

Junction to Ambient

18.4

Thermal Resistance

Junction to Case

Thermal Resistance

Junction to Board

Thermal Resistance

Junction to Top Center

Note:

θ_JC

9.5

10.9

°C/W

θ_JB

9.4

9.3

9.2

°C/W

Ψ_JB

Ψ_JT

0.2

0.23

°C/W

1. 64-QFN: Based on PCB Dimension: 3" x 4.5" PCB Thickness: 1.6 mm, PCB Land/Via: 36, Number of Cu Layers: 4.

2. 64-LGA: Based on 4 layer PCB with dimension 4" x 4.5", PCB Thickness of 1.6 mm, per JEDEC. PCB Center Land with 16 Via to

top internal plane of PCB.

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Rev. 1.1 | 40

Si5395/94/92 Data Sheet

Electrical Specifications

Table 5.16. Absolute Maximum Ratings ^{1, 2, 3}

Parameter

Symbol

V_DD

Test Condition

Value

Unit

V

–0.5 to 3.8

–1.0 to 3.8

V_DDA

V_DDO

V_DDS

V

DC Supply Voltage

V

4

V_I1

IN0–IN3/FB_IN

V

IN_SEL1, IN_SEL0, RSTb,

OEb, I2C_SEL, FINC, FDEC,

SDI, SCLK, A0/CSb, A1,

SDA/SDIO

Input Voltage Range

V_I2

–0.5 to 3.8

–0.5 to 2.7

V

V_I3

LU

XA/XB

Latch-up Tolerance

JESD78 Compliant

ESD Tolerance

HBM

T_STG

T_JCT

100 pF, 1.5 kΩ

2.0

–55 to 150

125

kV

°C

Storage Temperature Range

Maximum Junction Temperature in Operation

Soldering Temperature

T_PEAK

260

°C

s

(Pb-free profile)⁵

Soldering Temperature Time at T_PEAK

T_P

20–40

(Pb-free profile)⁵

Note:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to

the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

2. 64-QFN/LGA and 44-QFN/LGA packages are RoHS compliant.

3. For detailed packaging information, go to the Silicon Labs RoHS information page.

4. The minimum voltage at these pins can be as low as –1.0 V when an ac input signal of 8 kHz or greater is applied. See Table

5.3 Input Clock Specifications on page 26 for single-ended ac-coupled f_IN< 250 MHz.

5. The device is compliant with JEDEC J-STD-020.

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Rev. 1.1 | 41

Si5395/94/92 Data Sheet

Typical Application Schematic

6. Typical Application Schematic

312.5 MHz

4~6

Backplane

Clock

PHYs

25/50/100 MHz

Si5395 Jitter

Attenuator

Switch

SoC

156.25 MHz

4

Figure 6.1. Typical 56G SerDes Application

Telecom or

Ethernet

Backplane

Redundant

Timing Cards

Wander Filtering

Hitless Switching

Holdover

LAN / WAN

SyncE Line Card

Tx Timing Path

Hitless Switching

Jitter Filtering

10GbE

PHY

25/50GbE

A

B

Frequency Translation

BITS A

BITS B

Si5348

155.52 MHz

156.25 MHz

161.1328125 MHz

A

B

Si5395

TCXO/

OCXO

8 kHz

19.44 MHz

25 MHz

25/50GbE

PHY

Rx Timing Path

Line

Recovered

Clocks

8 kHz

19.44 MHz

25 MHz

LAN / WAN

SyncE Line Card

Tx Timing Path

Hitless Switching

Jitter Filtering

Frequency Translation

10GbE

25/50GbE

PHY

155.52 MHz

156.25 MHz

161.1328125 MHz

A

B

Si5395

25/50GbE

PHY

Rx Timing Path

Line

Recovered

Clocks

8 kHz

19.44 MHz

25 MHz

Figure 6.2. SyncE Line Card

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Rev. 1.1 | 42

Si5395/94/92 Data Sheet

Detailed Block Diagrams

7. Detailed Block Diagrams

Si5395/94/92

3

XA

XB

Integrated Reference

(J/K/L/M/E)

OSC

IN_SEL[1:0]

PXAXB

÷

IN0

IN0b

IN1

P_0n

P_0d

P_1n

P_1d

P_2n

P_2d

÷

DSPLL

IN1b

LPF

PD

IN2

IN2b

IN3/FB_IN

IN3/FB_INb

M_n

M_d

P_3n

P_3d

÷

5

Optional

External

Feedback

VDDO0

OUT0A

÷R_0A

Multi

Synth

N_0n

N_0d

OUT0

÷

÷R₀

VDDO1

OUT1

Multi

Synth

N_1n

N_1d

÷R₁

÷R₂

÷R₃

÷R₄

÷R₅

÷R₆

÷R₇

÷R₈

÷R₉

Multi

Synth N^2d

VDDO2

OUT2

N_2n

Multi

Synth

N_3n

N_3d

VDDO3

OUT3

÷

Multi

Synth

N_4n

N_4d

VDDO4

OUT4

VDDO5

OUT5

I2C_SEL

VDDO6

OUT6

SDA/SDIO

A1/SDO

SCLK

SPI/

NVM

I²C

VDDO7

OUT7

A0/CSb

VDDO8

OUT8

INTRb

Status

Monitors

LOLb

OUT9

OUT9A

9A

÷R

VDDO9

Figure 7.1. Si5392/94/95 Block Diagram

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Rev. 1.1 | 43

Si5395/94/92 Data Sheet

Typical Operating Characteristics

8. Typical Operating Characteristics

The phase noise plots below were taken under the following conditions: V_DD= 1.8 V; V_DDA= 3.3 V; V_DDS= 3.3 V, 1.8 V; T_A= 25 °C.

Figure 8.1. Input = 25 MHz; Output = 156.25 MHz, 2.5 V LVDS (Si539x P-Grade)

Figure 8.2. Input = 25 MHz; Output = 156.25 MHz, 2.5 V LVDS (Si539x E-Grade)

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Rev. 1.1 | 44

Si5395/94/92 Data Sheet

Typical Operating Characteristics

Figure 8.3. Input = 25 MHz; Output = 312.5 MHz, 2.5 V LVDS (Integer Mode)

Figure 8.4. Input = 25 MHz; Output = 155.52 MHz, 2.5 V LVDS (Fractional Mode)

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Rev. 1.1 | 45

Si5395/94/92 Data Sheet

Pin Descriptions

9. Pin Descriptions

Si5395 (64-QFN and 64-LGA)

Top View

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

IN1

IN1b

FINC

LOLb

3

IN_SEL0

IN_SEL1

RSVD

VDD

4

OUT6

5

OUT6b

VDDO6

OUT5

6

RSTb

7

X1/NC

XA/NC

XB/NC

X2/NC

OEb

8

OUT5b

VDDO5

I2C_SEL

OUT4

GND

Pad

9

10

11

INTRb 12

OUT4b

VDDO4

OUT3

13

14

15

VDDA

IN2

IN2b

OUT3b

VDDO3

SCLK 16

Si5394 (44-QFN and 44-LGA)

Top View

Si5392 (44-QFN and 44-LGA)

Top View

1

2

33

32

31

30

29

28

27

26

25

24

23

1

2

33

IN1

IN1b

IN1

IN1b

INTRb

VDD

OUT2

INTRb

32

VDD

3

31

30

29

28

27

26

25

24

23

LOS1b

LOS0b

VDDS

IN_SEL0

4

OUT2b

VDDO2

LOS_XAXBb

LOLb

X1/NC

XA/NC

XB/NC

X2/NC

VDDA

X1/NC

XA/NC

XB/NC

X2/NC

VDDA

5

GND

Pad

GND

Pad

6

LOS_XAXBb

LOLb

7

VDDS

8

OUT1

9

VDDA

IN2

VDDA

IN2

10

11

10

11

OUT1b

VDDO1

OUT1b

VDDO1

IN2b

Note: Grades A/B/C/D require external references so these pins can be connected to those references (XTAL, XO, VCXO, and so on).

Note that connecting an external reference to a device that already has an internal reference is not recommended and could lead to

internal damage to the circuits.

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Rev. 1.1 | 46

Si5395/94/92 Data Sheet

Pin Descriptions

Table 9.1. Si5395/94/92 Pin Descriptions

Pin Number

Si5394

Pin Type¹

Si5392

Pin Name

Function

Si5395

Inputs

XA/NC

8

5

6

4

7

5

6

4

7

I

Crystal Input for Grade A/B/C/D/P. Input pins for external crys-

tal (XTAL). Alternatively these pins can be driven with an external

reference clock (REFCLK). An internal register bit selects XTAL

or REFCLK mode. Default is XTAL mode.

XB/NC

X1/NC

X2/NC

9

7

NC (No-Connect) for Grades J/K/L/M/E. These devices have an

integrated reference and these pins cannot be connected to an

external reference. They should be left floating to avoid damage

or interference to the internal reference.

XTAL Shield for Grade A/B/C/D/P. Connect these pins directly

to the XTAL ground pins. X1, X2 and the XTAL ground pins

should be separated from the PCB ground plane. Refer to the

Si5395-94-92 Family Reference Manual for layout guidelines.

10

NC (No-Connect) for Grades J/K/L/M/E or external reference

clocks. These pins should be left disconnected for Grades

J/K/L/M/E with integrated reference or when connecting XA/XB

pins to an external reference clock (REFCLK)

IN0

IN0b

63

64

1

43

44

1

43

44

1

I

Clock Inputs. These pins accept an input clock for synchronizing

the device. They support both differential and single-ended clock

signals. Refer to for input termination options. These pins are

high-impedance and must be terminated externally. The negative

side of the differential input must be grounded through a capaci-

tor when accepting a single-ended clock.

IN1

IN1b

2

IN2

14

15

61

10

11

41

10

11

41

IN2b

IN3/FB_IN

Clock Input 3/External Feedback Input. By default these pins

are used as the fourth clock input (IN3/IN3b). They can also be

used as the external feedback input (FB_IN/FB_INb) for the op-

tional zero delay mode. See 4.9.13 Zero Delay Mode for details

on the optional zero delay mode.

IN3b/FB_INb

62

42

I

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Rev. 1.1 | 47

Si5395/94/92 Data Sheet

Pin Descriptions

Table 9.2. Si5395/94/92 Pin Descriptions

Pin Number

Si5394

Pin Type¹

Si5392

Pin Name

Function

Si5395

Outputs

OUT0Ab

OUT0A

OUT0

20

21

24

23

28

27

31

30

35

34

38

37

42

41

45

44

51

50

54

53

56

55

59

58

—

20

19

25

24

31

30

36

35

—

20

19

25

24

—

O

OUT0b

OUT1

OUT1b

OUT2

OUT2b

OUT3

OUT3b

OUT4

Output Clocks. These output clocks support a programmable

signal swing and common mode voltage. Desired output signal

format is configurable using register control. Termination recom-

mendations are provided in the Si5395-94-92 Family Reference

Manual. Unused outputs should be left unconnected.

OUT4b

OUT5

OUT5b

OUT6

OUT6b

OUT7

OUT7b

OUT8

OUT8b

OUT9

OUT9b

OUT9A

OUT9Ab

Serial Interface

I²C Select². This pin selects the serial interface mode as I²C

(I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally pulled

up by a ~ 20 kΩ resistor to the voltage selected by the

IO_VDD_SEL register bit.

I2C_SEL

39

18

38

13

38

13

I

Serial Data Interface²

This is the bidirectional data pin (SDA) for the I²C mode, or the

bidirectional data pin (SDIO) in the 3-wire SPI mode, or the input

data pin (SDI) in 4-wire SPI mode. When in I²C mode, this pin is

an open-drain output and must be pulled up using an external re-

sistor of at least 1 kΩ. No pull-up resistor is needed when in SPI

mode as the output is a push-pull driver. Tie low when unused.

SDA/SDIO

I/O

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Rev. 1.1 | 48

Si5395/94/92 Data Sheet

Pin Descriptions

Pin Number

Si5394

Pin Type¹

Pin Name

Function

Si5395

Si5392

Address Select 1/Serial Data Output²

In I²C mode, this pin is open-drain and functions as the A1 ad-

dress input pin. It does not have an internal pull-up or pull-down

resistor. In 4-wire SPI mode this output is a push-pull driver and

functions as the serial data output (SDO) pin. It drives high to the

voltage selected by the IO_VDD_SEL bit. Leave disconnected

when unused.

A1/SDO

17

15

I/O

Serial Clock Input²

This pin functions as the serial clock input for both I²C and SPI

SCLK

16

19

14

16

14

16

I

modes. When in I²C mode, this pin must be pulled-up using an

external resistor of at least 1 kΩ. No pull-up resistor is needed

when in SPI mode. Tie high or low when unused.

Address Select 0/Chip Select²

This pin functions as the hardware controlled address A0 in I²C

mode. In SPI mode, this pin functions as the chip select input (ac-

tive low). This pin is internally pulled-up by a ~20 kΩ resistor and

can be left unconnected when not in use.

A0/CSb

Control/Status

Interrupt²

INTRb

12

33

17

33

17

O

This pin is asserted low when a change in device status has oc-

curred. It should be left unconnected when not in use.

Device Reset²

Active low input that performs power-on reset (POR) of the de-

vice. Resets all internal logic to a known state and forces the de-

vice registers to their default values. Clock outputs are disabled

during reset. This pin is internally pulled-up and can be left un-

connected when not in use.

RSTb

OEb

6

I

Output Enable²

11

47

—

12

—

27

12

—

27

I

This pin disables all outputs when held high. This pin is internally

pulled low and can be left unconnected when not in use.

Loss of Lock (Si5395)²

O

This output pin indicates when the DSPLL is locked (high) or out-

of-lock (low). It can be left unconnected when not in use.

LOLb

Loss of Lock (Si5394/92)³

This output pin indicates when the DSPLL is locked (high) or out-

of-lock (low). It can be left unconnected when not in use.

Loss of Signal for IN0³

LOS0b

LOS1b

LOS2b

—

30

31

35

O

This pin indicate a loss of clock at the IN0 pin when low.

Loss of Signal for IN1³

This pin indicate a loss of clock at the IN1 pin when low.

Loss of Signal for IN2³

This pin indicate a loss of clock at the IN2 pin when low.

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Rev. 1.1 | 49

Si5395/94/92 Data Sheet

Pin Descriptions

Pin Number

Si5394

Pin Type¹

Pin Name

LOS3b

Function

Si5395

Si5392

Loss of Signal for IN3³

—

36

O

This pin indicate a loss of clock at the IN3 pin when low.

Loss of Signal on XA/XB Pins³

LOS_XAXBb

—

28

—

O

I

This pin indicates a loss of signal at the XA/XB pins when low.

Frequency Increment Pin²

This pin is used to step-up the output frequency of a selected out-

put. The affected output and its frequency change step size is

register configurable. This pin is internally pulled low and can be

left unconnected when not in use.

FINC

48

—

Frequency Decrement Pin²

This pin is used to step-down the output frequency of a selected

output. The affected output driver and its frequency change step

size is register configurable. This pin is internally pulled low and

can be left unconnected when not in use.

FDEC

25

—

I

Input Reference Select²

IN_SEL0

IN_SEL1

3

4

3

I

The IN_SEL[1:0] pins are used in manual pin controlled mode to

select the active clock input as shown in Table 4.1 Manual Input

Selection Using IN_SEL[1:0] Pins on page 13. These pins are in-

ternally pulled low.

37

Reserved

RSVD

5

—

These pins are connected to the die. Leave disconnected.

No Connect

NC

—

22

These pins are not connected to the die. Leave disconnected.

Power

32

46

60

—

13

21

32

39

40

8

21

32

39

40

8

P

Core Supply Voltage

The device operates from a 1.8 V supply. A 1.0 µF bypass capac-

itor should be placed very close to this pin. See the Si5395-94-92

Family Reference Manual for power supply filtering recommenda-

tions.

VDD

Core Supply Voltage 3.3 V

This core supply pin requires a 3.3 V power source. A 1 µF by-

pass capacitor should be placed very close to this pin. See the

Si5395-94-92 Family Reference Manual for power supply filtering

recommendations.

VDDA

—

9

P

—

26

—

26

29

P

Status Output Voltage

The voltage on this pin determines VOL/VOH on the Si5392/94

LOLb and LOL_XAXBb. It also determines the levels on the

LOS0b, LOS1b, LOS2b, and LOS3b outputs of the Si5392. Con-

nect to either 3.3 V or 1.8 V. A 1.0 µF bypass capacitor should be

placed very close to this pin. This voltage must match the IO op-

erating voltage selected for the frequency plan in CBPro.

VDDS

—

34

P

silabs.com | Building a more connected world.

Rev. 1.1 | 50

Si5395/94/92 Data Sheet

Pin Descriptions

Pin Number

Pin Type¹

Pin Name

Function

Si5395

22

Si5394

18

Si5392

18

23

—

VDDO0

VDDO1

VDDO2

VDDO3

VDDO4

VDDO5

VDDO6

VDDO7

VDDO8

VDDO9

P

26

23

29

33

34

—

Output Clock Supply Voltage

36

—

Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTn, OUTn outputs. For

unused outputs, leave VDDO pins unconnected. An alternative

option is to connect the VDDO pin to a power supply and disable

the output driver to minimize current consumption.

40

—

43

—

49

—

52

—

57

—

Ground Pad

This pad provides connection to ground and must be connected

for proper operation. Use as many vias as practical, and keep the

via length to an internal ground plane as short as possible.

GND PAD

—

P

Note:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.

4. Refer to the Si5395-94-92 Family Reference Manual for more information on register setting names.

5. All status pins except I²C and SPI are push-pull.

silabs.com | Building a more connected world.

Rev. 1.1 | 51

Si5395/94/92 Data Sheet

Package Outlines

10. Package Outlines

10.1 Si5395 A/B/C/D/P (External Reference) 9x9 mm 64-QFN Package Diagram

The following figure illustrates the package details for the Si5395 A/B/C/D/P. The table lists the values for the dimensions shown in the

illustration.

Figure 10.1. 64-Pin Quad Flat No-Lead (QFN)

Table 10.1. Package Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

A

A1

b

0.02

0.25

D

9.00 BSC

5.20

D2

e

5.10

5.30

0.50 BSC

9.00 BSC

5.20

E

E2

L

5.10

0.30

—

5.30

0.50

0.10

0.08

0.10

0.40

aaa

bbb

ccc

ddd

—

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Rev. 1.1 | 52

Si5395/94/92 Data Sheet

Package Outlines

10.2 Si5395 J/K/L/M/E (Internal Reference) 9x9 mm 64-LGA Package Diagram

The following figure illustrates the package details for the Si5395 J/K/L/M/E. The table lists the values for the dimensions shown in the

illustration.

Figure 10.2. 64-Pin LGA

Table 10.2. Package Dimensions

Dimension

Min

Nom

1

Max

A

A1

A2

b

0.9

1.1

0.26 REF

0.70 REF

0.25

0.2

0.8

0.3

0.9

b1

D

0.85

9 BSC

0.5 BSC

1.0 BSC

0.365

0.080 REF

0.1

E

e

e1

L

0.315

0.415

L1

aaa

bbb

ccc

ddd

0.2

0.1

0.08

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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Rev. 1.1 | 53

Si5395/94/92 Data Sheet

Package Outlines

10.3 Si5394 and Si5392 A/B/C/D/P (External Reference) 7x7 mm 44-QFN Package Diagram

The following figure illustrates the package details for the Si5394 and Si5392. The table lists the values for the dimensions shown in the

illustration.

Figure 10.3. 44-Pin Quad Flat No-Lead (QFN)

Table 10.3. Package Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

A

A1

b

0.02

0.25

D

7.00 BSC

5.20

D2

e

5.10

5.30

0.50 BSC

7.00 BSC

5.20

E

E2

L

5.10

0.30

—

5.30

0.50

0.10

0.08

0.10

0.40

aaa

bbb

ccc

ddd

—

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Rev. 1.1 | 54

Si5395/94/92 Data Sheet

Package Outlines

10.4 Si5394 and Si5392 J/K/L/M/E (Internal Reference) 7x7 mm 44-LGA Package Diagram

The following figure illustrates the package details for the Si5394J and Si5392J. The table lists the values for the dimensions shown in

the illustration.

Figure 10.4. 44-Pin LGA

Table 10.4. Package Dimensions

Dimension

Min

Nom

—

Max

A

A1

A2

b

—

1.10

0.26 REF

0.7 REF

0.25

0.20

5.10

0.30

5.30

D

7.00 BSC

5.20

D2

e

0.50 BSC

7.00 BSC

5.20

E

E2

L

5.10

0.35

—

5.30

0.45

0.10

0.20

—

0.40

aaa

bbb

ccc

ddd

eee

—

0.08

—

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Rev. 1.1 | 55

Si5395/94/92 Data Sheet

PCB Land Pattern

11. PCB Land Pattern

The following figure illustrates the PCB land pattern details for the devices. The table lists the values for the dimensions shown in the

illustration.

Si5395

Si5394 and Si5392

Figure 11.1. PCB Land Pattern

silabs.com | Building a more connected world.

Rev. 1.1 | 56

Si5395/94/92 Data Sheet

PCB Land Pattern

Table 11.1. PCB Land Pattern Dimensions

Dimension

Si5395 (Max)

8.90

Si5394/92 (Max)

C1

C2

E

6.90

0.50

0.30

0.85

5.30

8.90

0.50

X1

Y1

X2

Y2

0.30

0.85

5.30

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication

Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electropolished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

4. While the same land pattern design can be used for both QFN and LGA package types, the stencil design will need to match the

respective ground pads as shown in the Package outline.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Rev. 1.1 | 57

Si5395/94/92 Data Sheet

Top Marking

12. Top Marking

Figure 12.1. Top Marking

Table 12.1. Top Marking Explanation

Line

Characters

Description

Base part number and Device Grade for Any-frequency, Any-output, Jitter

Cleaning Clock (single PLL):

f = 5: 12-output Si5395: 64-QFN

f = 4: 4-output Si5394: 44-QFN

f = 2: 2-output Si5392: 44-QFN

1

Si539fg-

g = Device Grade (A/B/C/D/P/J/K/L/M/E). See 3. Ordering Guide for more infor-

mation.

– = Dash character.

R = Product revision. (Refer to 3. Ordering Guide for latest revision).

xxxxx = Customer specific NVM sequence number. Optional NVM code as-

signed for custom, factory pre-programmed devices.

2

3

Rxxxxx-GM

Characters are not included for standard, factory default configured devices.

See 3. Ordering Guide for more information.

-GM = Package (QFN) and temperature range (–40 to +85 °C)

YYWW = Characters correspond to the year (YY) and work week (WW) of

package assembly.

YYWWTTTTTT

TTTTTT = Manufacturing trace code.

Pin 1 indicator; left-justified

Circle w/ 1.6 mm (64-QFN) or 1.4

mm (44-QFN) diameter

4

CC

CC = TW = Taiwan; Country of Origin (ISO Abbreviation)

silabs.com | Building a more connected world.

Rev. 1.1 | 58

Si5395/94/92 Data Sheet

Revision History

13. Revision History

Revision 1.1

June, 2019

• Added Integrated reference options J/K/L/M/E.

Revision 1.0

April, 2019

• Updated Figure 4.3. Crystal Resonator and External Reference Clock Connection Options

• Updated section 4.9.2 Grade P section to support up to 3 time domains for Si5395, 2 domains for Si5394 and 1 domain for Si5392

(previous version only specified 2 domains for Si5395)

• Table 5.2 DC Characteristics

• Core supply current IDD/IDDA limits clarified for each device

• Output Buffer supply conditions clarified

• Total power dissipation numbers updated

• Updated test configuration diagrams

• Table 5.3 Input clock specifications

• Updated Input voltage section of "LVCMOS / Pulsed CMOS DC-Coupled Input Buffer" to include standard CMOS

• Table 5.5 Differential Clock Output Specifications

• Clarified duty cycle specs for when MultiSynth is used/not used

• Increased max Rise and Fall times from 150ps to 200ps based on final characterization

• Table 5.6. LVCMOS Clock Output Specifications

• Updated Min and Max limits for duty cycle

• Updated test configuration diagrams

• Table 5.8. Performance Characteristics

• Updated Initial startup time for P-grade devices

• Updated P-grade jitter numbers to include more domains and finalize test conditions

• Updated Table 5.10. SPI Timing Specifications (4-Wire) table and timing diagram

• Updated Table 5.11. SPI Timing Specifications (3-Wire)

• Changed NC/XA, NC/XB, NC/X1, NC/X2 to XA, XB, X1, X2 respectively since integrated crystal devices are getting their own data

sheet

Revision 0.96

June, 2018

• Preliminary data sheet.

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Rev. 1.1 | 59

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without

further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior

notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance

of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license to

design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required

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型号：	SI5394P-A10073-GMR
厂家：	SILICON
描述：	Processor Specific Clock Generator, 外围集成电路
文件：	总60页 (文件大小：1618K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SI5394P-A10073-GMR [SILICON]

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