SI5XX-EVB [SILICON]
EVALUATION BOARD FOR Si53X XOS AND Si55X VCXOS; 评估板用于Si53X XOS和Si55X压控石英振荡器
| 型号： | SI5XX-EVB |
| 厂家： | 
SILICON |
| 描述： | EVALUATION BOARD FOR Si53X XOS AND Si55X VCXOS |
| 文件： | 总8页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5xx-EVB
EVALUATION BOARD FOR Si53X XOS AND Si55X VCXOS
Description
Features
This document describes the operation of the Silicon Evaluation of Silicon Laboratories' Si55x/53x family
Laboratories Si5xx-EVB evaluation board to evaluate
both Silicon Laboratories' Si55x VCXOs and Si53x XOs.
The Si55x and Si53x devices use Silicon Laboratories'
AC-coupled differential output clocks
Voltage control (V ) input port (for Si55x devices)
C
Jumper selection for multi-frequency outputs
Jumper selection for output enable
®
advanced DSPLL circuitry to provide a low-jitter clock
at high frequencies. The Si55x/Si53x IC-based device is
factory configurable for a wide variety of user
specifications including frequency, supply voltage,
output, and tuning slope. Specific configurations are
factory programmed into the Si55x/Si53x at time of
shipment, thereby eliminating the long lead times
associated with custom oscillators. Si55x/Si53x
samples should be ordered at the same time as the
Si5xx-EVB since the EVB does not come with the
device. This allows end users maximum flexibility.
Silicon Laboratories can solder down samples when
ordering an EVB; please specify when ordering.
Functional Block Diagram
Power Input
Configuration
Jumpers
CLK+
Si5xx
Device
VC
Input
RC Filter
(no-pop)
Output
Bias
DC
Block
CLK–
Rev. 0.14 2/06
Copyright © 2006 by Silicon Laboratories
Si5xx-EVB
Si5xx-EVB
1.2. Voltage Control for VCXOs
1. Functional Description
The voltage control (V ) input of the Si55x device is
C
The Si5xx-EVB provides access to all signals for
configuring and operating the device. This board allows
evaluation of the Si55x VCXO device either by itself
(open-loop) or within a prototype PLL (closed-loop). The
performance of the Si53x XO device can also be
evaluated on this board (the Vc port is not used for XO
devices).
conveniently accessible through an SMA jack (J3) but
can also be driven (and observed) through 100 mil-
centered posts (JP4). For prototyping purposes, two
0603 solder pads are located near the device V input
C
(R3 and C3). A traditional PLL might use these as a
single-time-constant low-pass filter (RC filter). The EVB
is shipped with a 0 Ω resistor soldered at R3; C3 is left
open. The voltage control input is not used for XO
devices.
Table 1. Jumper Control
Part Type
JP1
JP2
JP3
JP4
1.3. Output Clock
Si530
Si532
Si534
Si550
Si552
Si554
Notes:
N/A
N/A
N/A
N/A
OE
OE
N/A
Freq Sel
N/A
Because the Si55x/Si53x devices can support an
LVPECL buffer type (in addition to LVDS and CMOS),
pulldown resistors (R1 and R2) are available for proper
output biasing. For LVPECL buffers, biasing can be
achieved through a variety of equivalent circuits; the
Si5xx-EVB allows for 130 Ω pulldown resistors. After
the output biasing, the high-speed outputs are dc-
blocked for connection to differently biased inputs, such
as standard test equipment or a phase detector EVB.
Please review “1.4. Preparing the EVB” for non-LVPECL
devices.
Freq Sel1 Freq Sel2
OE
N/A
N/A
N/A
N/A
OE
V
V
V
C
C
C
Freq Sel
OE
Freq Sel1 Freq Sel2
1. With jumper(s) installed, signal(s) are driven low.
2. With jumper(s) not installed, signal(s) are pulled high.
1.1. Power Supply
1.4. Preparing the EVB
The Si55x/Si53x devices support operation from
nominal voltages of 1.8, 2.5, and 3.3 V. Review the
device data sheet and part number for allowed
configurations of output buffer type and device power
supply.
By default, the evaluation board is set up to accept
LVPECL configured devices. This configuration uses
130 Ω pull-down resistors to bias the LVPECL output
stage. If an LVDS, CMOS, or CML based device is to
be installed, the output biasing resistors, R1 and R2,
should be removed.
2
Rev. 0.14
Si5xx-EVB
2. Schematics
D
G N
3
V D D
6
D N C
9
Rev. 0.14
3
Si5xx-EVB
3. Bill of Materials
Item Quantity Reference
Description
CAP,SM,0.1UF,16V,20%,X7R,0402
CAP,SM,0.1UF,16V,20%,X7R,0603
CAP,SM,10UF,10V,10%,TANTALUM,3216 TA010TCM106KAR
CAP,SM,100PF,50V,10%,C0G,0603 C0603C0G500-101KNE
Manufacturer's #
C0402X7R160-104KNE
C0603X7R160-104KNE
Manufacturer
VENKEL
VENKEL
VENKEL
VENKEL
1
2
3
4
5
6
7
8
9
2
2
1
1
4
3
1
1
2
C1,C2
C5
C4
C6
JP1,JP2,JP3,JP4 CONN,HEADER,2X1
J1,J2,J3
J4
R3
TSW-150-07-T-D or TSW-150-07-T-S SAMTEC
901-10003
1729018
CR0603-16W-000T
CR0603-16W-1500FT
AMPHENOL
PHOENIX CONTACT
VENKEL
CONN,SMA SIDE MOUNT
CONN,POWER,2 POSITION
RES,SM,0 OHM,0603
R1,R2
RES,SM,150,1%,0603
VENKEL
No Load
11
10
1 C3
1 U1
CAP,SM,0.1UF,16V,20%,X7R,0603
Si5XX
C0603X7R160-104KNE
Si5XX
VENKEL
SILICON LABORATORIES
4
Rev. 0.14
Si5xx-EVB
4. Layout
Figure 2. Assembly Drawing
Figure 3. Layer 1 Primary
Figure 4. Layer 2 Secondary
Rev. 0.14
5
Si5xx-EVB
DOCUMENT CHANGE LIST
Revision 0.13 to Revision 0.14
Updated "Bill of Materials‚" on page 4.
Updated Figure 2, “Assembly Drawing,” on page 5.
6
Rev. 0.14
Si5xx-EVB
NOTES:
Rev. 0.14
7
Si5xx-EVB
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: VCXOinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
8
Rev. 0.14
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