SI8234 [SILICON]
0.5 AND 4.0 AMP ISODRIVERS;
| 型号： | SI8234 |
| 厂家： | 
SILICON |
| 描述： | 0.5 AND 4.0 AMP ISODRIVERS 驱动 |
| 文件： | 总57页 (文件大小：907K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si823x
0.5 AND 4.0 AMP ISODRIVERS (2.5 AND 5 KVRMS
)
Features
Two completely isolated drivers 60 ns propagation delay (max)
in one package
Independent HS and LS inputs or
Up to 5 kVRMS input-to-output
isolation
PWM input versions
Transient immunity >45 kV/µs
Up to 1500 VDC peak driver-to-
driver differential voltage
HS/LS and dual driver versions
Overlap protection and
programmable dead time
AEC-Q100 qualification
Up to 8 MHz switching frequency
0.5 A peak output (Si8230/1/2/7)
Wide operating range
–40 to +125 °C
RoHS-compliant packages
4.0 A peak output
(Si8233/4/5/6/8)
High electromagnetic immunity
SOIC-16 wide body
SOIC-16 narrow body
LGA-14
Applications
Power delivery systems
Motor control systems
Lighting control systems
Plasma displays
Isolated dc-dc power supplies
Solar and industrial inverters
Safety Approval
UL 1577 recognized
Up to 5000 Vrms for 1 minute
CSA component notice 5A
approval
VDE certification conformity
IEC 60747-5-5 (VDE 0884 Part 5)
EN 60950-1 (reinforced
insulation)
CQC certification approval
GB4943.1
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
Ordering Information:
Description
See page 39.
The Si823x isolated driver family combines two independent, isolated
drivers into a single package. The Si8230/1/3/4 are high-side/low-side
drivers, and the Si8232/5/6/7/8 are dual drivers. Versions with peak
output currents of 0.5 A (Si8230/1/2/7) and 4.0 A (Si8233/4/5/6/8) are
available. All drivers operate with a maximum supply voltage of 24 V.
The Si823x drivers utilize Silicon Labs' proprietary silicon isolation
technology, which provides up to 5 kV
withstand voltage per UL1577
RMS
and fast 60 ns propagation times. Driver outputs can be grounded to the
same or separate grounds or connected to a positive or negative voltage.
The TTL level compatible inputs with >400 mV hysteresis are available in
individual control input (Si8230/2/3/5/6/7/8) or PWM input (Si8231/4)
configurations. High integration, low propagation delay, small installed
size, flexibility, and cost-effectiveness make the Si823x family ideal for a
wide range of isolated MOSFET/IGBT gate drive applications.
Rev. 1.7 4/15
Copyright © 2015 by Silicon Laboratories
Si823x
Si823x
2
Rev. 1.7
Si823x
TABLE OF CONTENTS
Section
Page
1. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1. Typical Operating Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.2. Typical Operating Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3. Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . . . . . . . .21
3.4. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.5. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.6. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.7. Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.8. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . .28
4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.1. High-Side/Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.2. Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.3. Dual Driver with Thermally Enhanced Package (Si8236) . . . . . . . . . . . . . . . . . . . . .31
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
8. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
9. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
10. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
11. Package Outline: 14 LD LGA (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
12. Land Pattern: 14 LD LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
13. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .50
14. Land Pattern: 14 LD LGA with Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
15. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
15.1. Si823x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . .52
15.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .52
15.3. Si823x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . .53
15.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . .53
15.5. Si823x Top Marking (14 LD LGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
15.6. Top Marking Explanation (14 LD LGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Rev. 1.7
3
Si823x
1. Top-Level Block Diagrams
VDDI
VDDA
VIA
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDI
VDDB
UVLO
VOB
UVLO
DISABLE
GNDB
VIB
GNDI
Si8230/3
Figure 1. Si8230/3 Two-Input High-Side/Low-Side Isolated Drivers
VDDI
VDDA
PWM
LPWM
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
DT
PROTECTION
VDDI
VDDI
VDDB
VDDI
UVLO
VOB
UVLO
DISABLE
GNDB
LPWM
GNDI
Si8231/4
Figure 2. Si8231/4 Single-Input High-Side/Low-Side Isolated Drivers
4
Rev. 1.7
Si823x
VDDI
VDDA
VIA
VOA
UVLO
GNDA
VDDI
VDDI
UVLO
VDDI
VDDB
DISABLE
VOB
UVLO
GNDB
VIB
GNDI
Si8232/5/6/7/8
Figure 3. Si8232/5/6/7/8 Dual Isolated Drivers
Rev. 1.7
5
Si823x
2. Electrical Specifications
Table 1. Electrical Characteristics1
2.7 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Specifications
Si8230/1/2/3/4/5/6
Si8237/8
4.5
2.7
—
—
5.5
5.5
Input-side Power Supply
Voltage
VDDI
V
V
Voltage between VDDA and
VDDA, VDDB GNDA, and VDDB and GNDB
(See “6. Ordering Guide” )
6.5
—
24
Driver Supply Voltage
Si8230/2/3/5/6/7/8
—
—
2
3
5
mA
mA
Input Supply Quiescent
Current
IDDI(Q)
Si8231/4
3.5
IDDA(Q),
Output Supply Quiescent
Current
Current per channel
IDDB(Q)
—
—
—
—
3.5
6
3.0
—
mA
mA
mA
IDDI
Input freq = 500 kHz, no load
Input Supply Active Current
Output Supply Active Current
IDDA
IDDB
Current per channel with
Input freq = 500 kHz, no load
—
IVIA, IVIB,
IPWM
–10
—
+10
µA dc
Input Pin Leakage Current
IDISABLE
VIH
–10
2.0
—
—
—
+10
—
µA dc
V
Input Pin Leakage Current
Logic High Input Threshold
Logic Low Input Threshold
Input Hysteresis
VIL
—
0.8
—
V
VIHYST
Si8230/1/2/3/4/5/6/7/8
IOA, IOB = –1 mA
400
450
mV
(VDDA
/VDDB)
— 0.04
VOAH,
VOBH
—
—
V
Logic High Output Voltage
Logic Low Output Voltage
VOAL, VOBL
IOA, IOB = 1 mA
Si8230/1/2/7, Figure 4
Si8233/4/5/6/8, Figure 4
Si8230/1/2/7, Figure 5
Si8233/4/5/6/8, Figure 5
Si8230/1/2/7
—
—
—
—
—
—
—
—
0.5
4.0
0.25
2.0
5.0
1.0
0.04
—
V
A
A
A
A
IOA(SCL),
IOB(SCL)
Output Short-Circuit Pulsed
Sink Current
—
—
IOA(SCH),
IOB(SCH)
Output Short-Circuit Pulsed
Source Current
—
—
RON(SINK)
Output Sink Resistance
Si8233/4/5/6/8
—
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k..
6
Rev. 1.7
Si823x
Table 1. Electrical Characteristics1 (Continued)
2.7 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Condition
Si8230/1/2/7
Min
—
Typ
15
Max
—
Unit
RON(SOURCE)
Output Source Resistance
Si8233/4/5/6/8
—
2.7
—
VDDI rising
(Si8230/1/2/3/4/5/6)
VDDIUV+
VDDIUV–
3.60
3.30
4.0
4.45
4.15
V
V
VDDI Undervoltage Threshold
VDDI Undervoltage Threshold
VDDI falling
(Si8230/1/2/3/4/5/6)
3.70
VDDIHYS
VDDIUV+
VDDIUV–
VDDIHYS
(Si8230/1/2/3/4/5/6)
VDDI rising (Si8237/8)
VDDI falling (Si8237/8)
(Si8237/8)
—
2.15
2.10
—
250
2.3
—
2.5
2.40
—
mV
V
VDDI Lockout Hysteresis
VDDI Undervoltage Threshold
VDDI Undervoltage Threshold
VDDI Lockout Hysteresis
2.22
75
V
mV
VDDAUV+
VDDBUV+
,
VDDA, VDDB Undervoltage
Threshold
VDDA, VDDB rising
See Figure 37 on page 27.
See Figure 38 on page 27.
See Figure 39 on page 27.
See Figure 40 on page 27.
5.20
7.50
9.60
12.4
5.80
8.60
11.1
13.8
6.30
9.40
12.2
14.8
V
V
V
V
5 V Threshold
8 V Threshold
10 V Threshold
12.5 V Threshold
VDDAUV–
,
VDDA, VDDB Undervoltage
Threshold
VDDA, VDDB falling
VDDBUV–
See Figure 37 on page 27.
See Figure 38 on page 27.
See Figure 39 on page 27.
See Figure 40 on page 27.
4.90
7.20
9.40
11.6
5.52
8.10
10.1
12.8
6.0
V
V
V
V
5 V Threshold
8 V Threshold
10 V Threshold
12.5 V Threshold
8.70
10.9
13.8
VDDAHYS
,
VDDA, VDDB
Lockout Hysteresis
UVLO voltage = 5 V
UVLO voltage = 8 V
—
—
—
280
600
—
—
—
mV
mV
mV
VDDBHYS
VDDAHYS
,
VDDA, VDDB
Lockout Hysteresis
VDDBHYS
VDDAHYS
,
VDDA, VDDB
Lockout Hysteresis
UVLO voltage = 10 V or 12.5 V
1000
VDDBHYS
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k..
Rev. 1.7
7
Si823x
Table 1. Electrical Characteristics1 (Continued)
2.7 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
AC Specifications
Minimum Pulse Width
Symbol
Test Condition
Min
Typ
Max
Unit
—
—
—
10
30
—
—
60
ns
ns
ns
tPHL, tPLH
PWD
CL = 200 pF
Propagation Delay
Pulse Width Distortion
5.60
|t
- t
|
PLH PHL
Minimum Overlap Time2
TDD
DT
DT = VDDI, No-Connect
Figure 42, RDT = 100 k
Figure 42, RDT = 6 k
—
—
—
—
—
0.4
900
70
—
—
—
20
12
ns
ns
Programmed Dead Time3
ns
ns
ns
CL = 200 pF (Si8230/1/2/7)
CL = 200 pF (Si8233/4/5/6/8)
—
tR,tF
Output Rise and Fall Time
—
Shutdown Time from
Disable True
tSD
—
—
—
—
—
—
60
60
40
ns
ns
µs
Restart Time from
Disable False
tRESTART
tSTART
Time from VDD_ = VDD_UV+
to VOA, VOB = VIA, VIB
Device Start-up Time
VIA, VIB, PWM = VDDI or 0 V
VCM = 1500 V (see Figure 6)
Common Mode
Transient Immunity
CMTI
20
45
—
kV/µs
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k..
8
Rev. 1.7
Si823x
2.1. Test Circuits
Figures 4, 5, and 6 depict sink current, source current, and common-mode transient immunity test circuits,
respectively.
VDDA = VDDB = 15 V
VDDI
VDD
10
IN
OUT
Si823x
INPUT
SCHOTTKY
+
8 V
VSS
100 µF
_
1 µF
1 µF
CER
10 µF
EL
Measure
50 ns
RSNS
0.1
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 4. IOL Sink Current Test Circuit
VDDA = VDDB = 15 V
VDDI
VDD
10
IN
OUT
Si823x
INPUT
SCHOTTKY
1 µF
+
5.5 V
VSS
100 µF
_
1 µF
CER
10 µF
EL
Measure
RSNS
0.1
50 ns
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 5. IOH Source Current Test Circuit
Rev. 1.7
9
Si823x
12 V
Supply
Si823x
VDDA
VDDI
Input Signal
Switch
INPUT
VOA
5V
DISABLE GNDA
Isolated
Supply
DT
VDDB
VOB
Oscilloscope
100k
GNDI
GNDB
Isolated
Ground
High Voltage
Differential
Probe
Output
Input
Vcm Surge
Output
High Voltage
Surge Generator
Figure 6. Common Mode Transient Immunity Test Circuit
10
Rev. 1.7
Si823x
Table 2. Regulatory Information1,2,3,4
CSA
The Si823x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
RMS
RMS
RMS
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
60601-1: Up to 125 V
reinforced insulation working voltage; up to 380 V
basic insulation working voltage.
RMS
RMS
VDE
The Si823x is certified according to IEC 60747-5-5. For more details, see File 5006301-4880-0001.
60747-5-5: Up to 891 V for basic insulation working voltage.
peak
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
RMS
UL
The Si823x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 V
isolation voltage for basic protection.
RMS
CQC
The Si823x is certified under GB4943.1-2011. For more details, see certificates CQC13001096106 and
CQC13001096108.
Rated up to 600 V
reinforced insulation working voltage; up to 1000 V
basic insulation working voltage.
RMS
RMS
Notes:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
2. Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
3. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
4. For more information, see "6. Ordering Guide" on page 39.
Rev. 1.7
11
Si823x
Table 3. Insulation and Safety-Related Specifications
Value
WBSOIC-16
14 LD
LGA with
Pad
Test
Condition
14 LD
LGA
Parameter
Symbol
Unit
WBSOIC-16
NBSOIC-16
2.5 kV
5 kV
RMS
2.5 kV
RMS
RMS
1.0 kV
RMS
Nominal Air Gap
(Clearance)
L(1O1)
L(1O2)
8.0
8.0/4.01
8.0/4.01
0.014
3.5
3.5
1.75
1.75
mm
mm
mm
1
Nominal External Tracking
8.0
1
(Creepage)
Minimum Internal Gap
(Internal Clearance)
0.014
0.014
0.014
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
600
600
600
V
mm
0.019
0.019
0.021
0.021
Erosion Depth
Resistance
12
12
12
12
R
10
10
10
10
IO
2
(Input-Output)
Capacitance
(Input-Output)
C
1.4
4.0
1.4
4.0
1.4
4.0
1.4
4.0
pF
pF
IO
2
3
C
Input Capacitance
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline:
16-Pin Wide Body SOIC” , “9. Package Outline: 16-Pin Narrow Body SOIC” , “11. Package Outline: 14 LD LGA
(5 x 5 mm)” , and “13. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm)” . VDE certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-16 and 8.5 mm minimum for the WB SOIC-16 package. UL
does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance
and creepage limits as 3.9 mm minimum for the NB SOIC 16 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si823x is converted into a 2-terminal device. Pins 1–8 (1-7, 14 LD LGA)
are shorted together to form the first terminal and pins 9–16 (8-14, 14 LD LGA) are shorted together to form the
second terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 4. IEC 60664-1 (VDE 0884 Part 5) Ratings
Specification
14 LD
Parameter
Test Condition
WB
NB
14 LD
LGA
LGA
SOIC-16 SOIC-16
with Pad
Basic Isolation Group
Material Group
I
I
I
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-IV
I-III
I-III
I-IV
I-III
I-II
I-II
I-IV
I-III
I-II
I-II
I-IV
I-III
I-II
I-I
RMS
RMS
RMS
RMS
Installation Classification
12
Rev. 1.7
Si823x
Table 5. IEC 60747-5-5 Insulation Characteristics*
Characteristic
NB SOIC-16 14 LD LGA
SOIC-16 14 LD LGA with Pad
Parameter
Symbol
Test Condition
Unit
WB
Maximum Working Insulation
Voltage
V
891
560
373
V peak
V peak
IORM
Method b1
(V
x 1.875 = V
100%
,
PR
IORM
V
Production Test,
t = 1 sec,
1671
1050
700
Input to Output Test Voltage
Transient Overvoltage
PR
m
Partial Discharge < 5
pC)
V
t = 60 sec
6000
2
4000
2
2650
2
V peak
IOTM
Pollution Degree (DIN VDE
0110, Table 1)
Insulation Resistance at T ,
9
9
9
S
R
>10
>10
>10
S
V
= 500 V
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si823x provides a climate classification of
40/125/21.
Table 6. IEC Safety Limiting Values1
14 LD
LGAwith Unit
Pad
WB
NB
14 LD
Parameter Symbol
Case
Test Condition
SOIC-16 SOIC-16 LGA
T
150
50
150
50
150
50
150
100
1.2
°C
mA
W
S
Temperature
= 100 °C/W (WB SOIC-16),
105 °C/W (NB SOIC-16, 14 LD LGA),
50 °C/W (14 LD LGA with Pad)
JA
Safety Input
Current
I
S
V
= 5.5 V,
DDI
V
= V
= 24 V,
DDA
DDB
T = 150 °C, T = 25 °C
J
A
Device Power
Dissipation
P
1.2
1.2
1.2
D
2
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figures 7 and 8.
2. The Si82xx is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle
square wave.
Rev. 1.7
13
Si823x
Table 7. Thermal Characteristics
Parameter
14 LD
LGA with
Pad
WB
SOIC-16
NB
SOIC-16
14 LD
LGA
Symbol
Unit
IC Junction-to-Air
Thermal Resistance
100
105
105
50
°C/W
JA
Table 8. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
—
Max
+150
+125
+150
6.0
Unit
°C
°C
°C
V
2
Storage Temperature
T
STG
Ambient Temperature under Bias
Junction Temperature
T
A
T
J
Input-side Supply Voltage
VDDI
–0.6
–0.6
–0.5
Driver-side Supply Voltage
VDDA, VDDB
30
V
Voltage on any Pin with respect to Ground
V
VDD + 0.5
V
IO
Peak Output Current (t
(0.5 Amp versions)
= 10 µs, duty cycle = 0.2%)
PW
I
—
0.5
A
OPK
Peak Output Current (t
(4.0 Amp versions)
= 10 µs, duty cycle = 0.2%)
PW
I
—
—
—
4.0
260
A
OPK
Lead Solder Temperature (10 sec.)
°C
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
6500
V
V
V
V
V
V
V
V
RMS
RMS
RMS
RMS
RMS
RMS
RMS
RMS
Maximum Isolation (Output to Output) (1 sec)
WB SOIC-16
—
—
—
—
—
—
—
2500
4500
2500
3850
650
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16
Maximum Isolation (Output to Output) (1 sec)
NB SOIC-16
Maximum Isolation (Input to Output) (1 sec)
14 LD LGA without Thermal Pad
Maximum Isolation (Output to Output) (1 sec)
14 LD LGA without Thermal Pad
Maximum Isolation (Input to Output) (1 sec)
14 LD LGA with Thermal Pad
1850
0
Maximum Isolation (Output to Output) (1 sec)
14 LD LGA with Thermal Pad
—
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. VDE certifies storage temperature from –40 to 150 °C.
14
Rev. 1.7
Si823x
60
50
40
30
20
10
0
VDDI = 5.5 V
VDDA, VDDB = 24 V
0
50
100
150
200
Case Temperature (ºC)
Figure 7. WB SOIC-16, NB SOIC-16, 14 LD LGA Thermal Derating Curve, Dependence of Safety
Limiting Values with Case Temperature per DIN EN 60747-5-5
120
VDDI = 5.5 V
VDDA, VDDB = 24 V
100
80
60
40
20
0
0
50
100
150
200
Case Temperature (ºC)
Figure 8. 14 LD LGA with Pad Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5
Rev. 1.7
15
Si823x
3. Functional Description
The operation of an Si823x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is
modulated instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si823x channel is shown in
Figure 9.
Transmitter
Receiver
Driver
VDD
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
Dead
time
control
B
MODULATOR
DEMODULATOR
A
0.5 to 4 A
peak
Gnd
Figure 9. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 10 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 10. Modulation Scheme
16
Rev. 1.7
Si823x
3.1. Typical Operating Characteristics (0.5 Amp)
The typical performance characteristics depicted in Figures 11 through 22 are for information purposes only. Refer
to Table 1 on page 6 for actual specification limits.
10
7
Duty Cycle = 50%
8
6
4
2
0
1MHz
6
5
4
3
2
1
0
CL = 100 pF
1 Channel Switching
Tfall
500kHz
100kHz
Trise
50 kHz
VDD=12V, 25°C
CL = 100 pF
9
14
19
24
VDDA Supply Voltage (V)
9
12
15
18
21
24
VDDA Supply (V)
Figure 14. Supply Current vs. Supply Voltage
Figure 11. Rise/Fall Time vs. Supply Voltage
30
25
5
4
H-L
20
3
VDDA = 15V,
f = 250kHz, CL = 0 pF
Duty Cycle = 50%
2 Channels Switching
L-H
2
1
15
VDD=12V, 25°C
CL = 100 pF
10
-50
0
50
Temperature (°C)
100
9
12
15
18
21
24
VDDA Supply (V)
Figure 15. Supply Current vs. Temperature
Figure 12. Propagation Delay vs. Supply
Voltage
40
35
Trise
4
30
Duty Cycle = 50%
CL = 0 pF
1 Channel Switching
3.5
3
25
1MHz
20
15
10
5
Tfall
500kHz
100kHz
2.5
2
1.5
1
VDD=12V, 25°C
50 kHz
0
0.0
0.5
1.0
Load (nF)
1.5
2.0
9
14
19
24
VDDA Supply Voltage (V)
Figure 16. Rise/Fall Time vs. Load
Figure 13. Supply Current vs. Supply Voltage
Rev. 1.7
17
Si823x
50
45
40
35
30
25
20
15
4ϳϱ
ϰϱϬ
ϰϮϱ
ϰϬϬ
ϯϳϱ
ϯϱϬ
ϯϮϱ
ϯϬϬ
Ϯϳϱ
L-H
H-L
VDD=12V, Vout=VDD-5V
VDD=12V, 25°C
10
0.0
0.5
1.0
Load (nF)
1.5
2.0
10
15
20
25
6XSSO\ꢀ9ROWDJHꢀꢁ9ꢂ
Figure 17. Propagation Delay vs. Load
Figure 20. Output Source Current vs. Supply
Voltage
30
ϴϱϬ
ϴϮϱ
ϴϬϬ
ϳϳϱ
ϳϱϬ
7Ϯϱ
ϳϬϬ
ϲϳϱ
ϲϱϬ
ϲϮϱ
ϲϬϬ
25
20
15
10
L-H
H-L
VDD=12V, Load = 200pF
ϱϳϱ
VDD=12V, Vout=5V
-40
-20
0
20
40
60
80
100
120
ϱϱϬ
-40
-10
20
50
80
110
Temperature (°C)
7HPSHUDWXUHꢀꢁ°&ꢂ
Figure 18. Propagation Delay vs. Temperature
Figure 21. Output Sink Current vs. Temperature
ϭϭϮϱ
ϭϬϬϬ
ϴϳϱ
ϰϮ5
ϰϬϬ
3ϳϱ
ϯϱϬ
ϯϮ5
ϯϬϬ
ϳϱϬ
ϲϮϱ
VDD=12V, Vout=5V
ϱϬϬ
VDD=12V, Vout=VDD-5V
10
12
14
16
18
20
22
24
Ϯϳϱ
6XSSO\ꢀ9ROWDJHꢀꢁ9ꢂ
-40
-10
20
50
80
110
7HPSHUDWXUHꢀꢁ°&ꢂ
Figure 19. Output Sink Current vs. Supply
Voltage
Figure 22. Output Source Current vs.
Temperature
18
Rev. 1.7
Si823x
3.2. Typical Operating Characteristics (4.0 Amp)
The typical performance characteristics depicted in Figures 23 through 34 are for information purposes only. Refer
to Table 1 on page 6 for actual specification limits.
10
14
12
10
8
Duty Cycle = 50%
CL = 100 pF
1 Channel Switching
1MHz
8
6
4
2
0
Tfall
500kHz
6
Trise
100kHz
50 kHz
4
2
0
9
14
19
24
VDD=12V, 25°C
CL = 100 pF
VDDA Supply Voltage (V)
Figure 26. Supply Current vs. Supply Voltage
9
12
15
18
21
24
VDDA Supply (V)
10
8
Figure 23. Rise/Fall Time vs. Supply Voltage
30
6
VDDA = 15V,
f = 250kHz, CL = 0 pF
4
25
Duty Cycle = 50%
2 Channels Switching
2
L-H
0
20
-50
0
50
100
Temperature (°C)
H-L
15
Figure 27. Supply Current vs. Temperature
VDD=12V, 25°C
CL = 100 pF
10
40
35
9
12
15
18
21
24
VDDA Supply (V)
Trise
30
Figure 24. Propagation Delay vs. Supply
Voltage
25
20
15
10
5
Tfall
14
12
10
8
Duty Cycle = 50%
CL = 0 pF
1 Channel Switching
1MHz
VDD=12V, 25°C
0
500kHz
0
1
2
3
4
5
6
7
8
9
10
6
4
Load (nF)
100kHz
50 kHz
2
Figure 28. Rise/Fall Time vs. Load
0
9
14
19
24
VDDA Supply Voltage (V)
Figure 25. Supply Current vs. Supply Voltage
Rev. 1.7
19
Si823x
50
45
40
35
30
25
20
15
10
4
3.75
3.5
3.25
3
H-L
L-H
2.75
2.5
2.25
2
VDD=12V, Vout=VDD-5V
VDD=12V, 25°C
10
15
20
25
0
1
2
3
4
5
6
7
8
9
10
Supply Voltage (V)
Load (nF)
Figure 32. Output Source Current vs. Supply
Voltage
Figure 29. Propagation Delay vs. Load
30
7
6.75
6.5
H-L
25
20
15
10
6.25
6
L-H
5.75
5.5
5.25
5
4.75
4.5
4.25
VDD=12V, Load = 200pF
VDD=12V, Vout=5V
4
-40
-10
20
50
80
110
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 33. Output Sink Current vs. Temperature
Figure 30. Propagation Delay vs. Temperature
3.5
3.25
3
9
8
7
6
5
2.75
2.5
2.25
VDD=12V, Vout=5V
VDD=12V, Vout=VDD-5V
4
2
10
12
14
16
18
20
22
24
-40
-10
20
50
80
110
Supply Voltage (V)
Temperature (°C)
Figure 31. Output Sink Current vs. Supply
Voltage
Figure 34. Output Source Current vs.
Temperature
20
Rev. 1.7
Si823x
3.3. Family Overview and Logic Operation During Startup
The Si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations.
3.3.1. Products
Table 9 shows the configuration and functional overview for each product in this family.
Table 9. Si823x Family Overview
Part Number
Configuration
Overlap
Protection
Programmable
Dead Time
Inputs
Peak Output
Current (A)
Si8230
Si8231
High-Side/Low-Side
High-Side/Low-Side
Dual Driver
VIA, VIB
PWM
0.5
0.5
0.5
4.0
4.0
4.0
Si8232/7
Si8233
—
—
VIA, VIB
VIA, VIB
PWM
High-Side/Low-Side
High-Side/Low-Side
Dual Driver
Si8234
Si8235/6/8
—
—
VIA, VIB
3.3.2. Device Behavior
Table 10 consists of truth tables for the Si8230/3, Si8231/4, and Si8232/5/6 families.
Table 10. Si823x Family Truth Table1
Si8230/3 (High-Side/Low-Side) Truth Table
Inputs
Output
VDDI State Disable
Notes
VIA
VIB
VOA
VOB
Output transition occurs after internal dead time
expires.
L
L
L
Powered
Powered
Powered
Powered
L
L
L
L
L
L
L
Output transition occurs after internal dead time
expires.
H
L
H
L
L
Output transition occurs after internal dead time
expires.
H
H
H
L
Invalid state. Output transition occurs after internal
dead time expires.
H
Output returns to input state within 7 µs of VDDI
power restoration.
2
2
X
X
Unpowered
Powered
X
H
L
L
L
L
X
X
Device is disabled.
Si8231/4 (PWM Input High-Side/Low-Side) Truth Table
Output
PWM Input
VDDI State Disable
Notes
VOA
VOB
Output transition occurs after internal dead time
expires.
H
L
Powered
Powered
L
L
H
L
Output transition occurs after internal dead time
expires.
L
H
Output returns to input state within 7 µs of VDDI
power restoration.
2
X
Unpowered
Powered
X
H
L
L
L
L
X
Device is disabled.
Notes:
1. This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see "3.7.2.
Undervoltage Lockout" on page 26 for more information.
2. Note that an input can power the input die through an internal diode if its source has adequate current.
Rev. 1.7
21
Si823x
Table 10. Si823x Family Truth Table1 (Continued)
Si8232/5/6/7/8 (Dual Driver) Truth Table
Output
Inputs
VDDI State Disable
Notes
VIA
VIB
VOA
VOB
Output transition occurs immediately
(no internal dead time).
L
L
Powered
Powered
Powered
Powered
L
L
L
L
L
L
Output transition occurs immediately
(no internal dead time).
L
H
H
H
L
L
H
H
H
L
Output transition occurs immediately
(no internal dead time).
Output transition occurs immediately
(no internal dead time).
H
H
Output returns to input state within 7 µs of VDDI
power restoration.
2
2
X
X
Unpowered
Powered
X
H
L
L
L
L
X
X
Device is disabled.
Notes:
1. This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see "3.7.2.
Undervoltage Lockout" on page 26 for more information.
2. Note that an input can power the input die through an internal diode if its source has adequate current.
22
Rev. 1.7
Si823x
3.4. Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these
supplies must be placed as close to the VDD and GND pins of the Si823x as possible. The optimum values for
these capacitors depend on load current and the distance between the chip and the regulator that powers it. Low
effective series resistance (ESR) capacitors, such as Tantalum, are recommended.
3.5. Power Dissipation Considerations
Proper system design must assure that the Si823x operates within safe thermal limits across the entire load
range.The Si823x total power dissipation is the sum of the power dissipated by bias supply current, internal
parasitic switching losses, and power dissipated by the series gate resistor and load. Equation 1 shows total
Si823x power dissipation.
Rp
Rn
2
--------------------
Rp + Rg
--------------------
Rn + Rg
PD = VDDIIDDI + 2IDD2VDD2 + fQTLVDD2
where:
+ fQTLVDD2
+ 2fCintVDD2
PD is the total Si823x device power dissipation (W)
IDDI is the input-side maximum bias current (3 mA)
IDD2 is the driver die maximum bias current (2.5 mA)
Cint is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)
VDDI is the input-side VDD supply voltage (2.7 to 5.5 V)
VDD2 is the driver-side supply voltage (10 to 24 V)
f is the switching frequency (Hz)
QTLis the total highside bootstrap charge (see Section 2.2 of AN486)
RG is the external gate resistor
RP is the RDSONof the driver pull-up switch: (Rp=15 for the 0.5A driver; Rp=2.7 for the 4.0A driver)
Rn is the RDSONof the driver pull-down switch: (Rn=5 for the 0.5A driver and 1 for the 4.0A driver)
Equation 1.
Power dissipation example for 0.5 A driver using Equation 1 with the following givens:
V
V
= 5.0 V
= 12 V
DDI
DD2
f = 350 kHz
R = 22
G
Q = 25 nC
G
15
15 + 22
5
Pd = 0.015 + 0.060 + 350 10325 10–912
+ 350 10325 10–912
-------------------
---------------
5 + 22
+ 2350 10375 10–12144= 145 mW
From which the driver junction temperature is calculated using Equation 2, where:
Pd is the total Si823x device power dissipation (W)
ja is the thermal resistance from junction to air (105 °C/W in this example)
TA is the ambient temperature
Rev. 1.7
23
Si823x
Tj = Pd ja + TA
= (0.145)(105) + 20
= 35.2 °C
The maximum power dissipation allowable for the Si823x is a function of the package thermal resistance, ambient
temperature, and maximum allowable junction temperature, as shown in Equation 2:
T
jmax – TA
---------------------------
PDmax
where:
ja
P
T
Dmax = Maximum Si823x power dissipation (W)
jmax = Si823x maximum junction temperature (150 °C)
TA = Ambient temperature (°C)
ja = Si823x junction-to-air thermal resistance (105 °C/W)
f = Si823x switching frequency (Hz)
Equation 2.
Substituting values for P
T
, T , and into Equation 2 results in a maximum allowable total power
Dmax jmax A ja
dissipation of 1.19 W. Maximum allowable load is found by substituting this limit and the appropriate data sheet
values from Table 1 on page 6 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and
Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V.
1.4 10–3
–11
CL(MAX) = -------------------------- – 7.5 10
f
Equation 3.
1.4 10–3
–10
CL(MAX) = -------------------------- – 3.7 10
f
Equation 4.
Equation 3 and Equation 4 are graphed in Figure 35 where the points along the load line represent the package
dissipation-limited value of CL for the corresponding switching frequency.
24
Rev. 1.7
Si823x
1 6 ,0 0 0
1 4 ,0 0 0
1 2 ,0 0 0
1 0 ,0 0 0
8 ,0 0 0
6 ,0 0 0
4 ,0 0 0
2 ,0 0 0
0
0 .5 A D rive r (p F )
4 A D rive r (p F )
F re q u e n c y (K h z )
Figure 35. Max Load vs. Switching Frequency
Rev. 1.7
25
Si823x
3.6. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si823x VDD lines. Care must be taken to
minimize parasitic inductance in these paths by locating the Si823x as close to the device it is driving as possible.
In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and
ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for
power devices and small signal components provides the best overall noise performance.
3.7. Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 36, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low
when input side power supply (VDDI) is not present.
3.7.1. Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period
tSTART. Following this, the outputs follow the states of inputs VIA and VIB.
3.7.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. The input (control) side, Driver A and Driver B, each have
their own undervoltage lockout monitors.
The Si823x input side enters UVLO when VDDI < VDDI
, and exits UVLO when VDDI > VDDI
. The driver
UV+
UV–
outputs, VOA and VOB, remain low when the input side of the Si823x is in UVLO and their respective VDD supply
(VDDA, VDDB) is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA
unconditionally enters UVLO when VDDA falls below VDDA
and exits UVLO when VDDA rises above
UV–
VDDA
.
UV+
UVLO+
VDDHYS
UVLO-
VDDI
UVLO+
UVLO-
VDDHYS
VDDA
VIA
DISABLE
tSD
tRESTART
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
VOA
Figure 36. Device Behavior during Normal Operation and Shutdown
26
Rev. 1.7
Si823x
3.7.3. Undervoltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 37
through 40, upon power up, the Si823x is maintained in UVLO until VDD rises above VDD . During power down,
UV+
the Si823x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDD
–
UV+
VDD
).
HYS
VDDUV+ (Typ)
VDDUV+ (Typ)
3.5
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
8.5
9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5
Supply Voltage (VDD - VSS) (V)
Supply Voltage (VDD - VSS) (V)
Figure 37. Si823x UVLO Response (5 V)
Figure 39. Si823x UVLO Response (10 V)
VDDUV+ (Typ)
VDDUV+ (Typ)
11.3 11.8 12.3 12.8 13.3 13.8 14.3 14.8 15.3
6.0
6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Supply Voltage (VDD - VSS) (V)
Supply Voltage (VDD - VSS) (V)
Figure 40. Si823x UVLO Response (12.5 V)
Figure 38. Si823x UVLO Response (8 V)
Rev. 1.7
27
Si823x
3.7.4. Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB
causes the corresponding output to go high. For PWM input versions (Si8231/4), VOA is high and VOB is low when
the PWM input is high, and VOA is low and VOB is high when the PWM input is low.
3.7.5. Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of VIA
and VIB. Device operation terminates within tSD after DISABLE = V and resumes within tRESTART after
IH
DISABLE = V . The DISABLE input has no effect if VDDI is below its UVLO level (i.e., VOA, VOB remain low).
IL
3.8. Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si8230/1/3/4) include programmable overlap protection to prevent outputs VOA and
VOB from being high at the same time. These devices also include programmable dead time, which adds a user-
programmable delay between transitions of VOA and VOB. When enabled, dead time is present on all transitions,
even after overlap recovery. The amount of dead time delay (DT) is programmed by a single resistor (RDT)
connected from the DT input to ground per Equation 5. Note that the dead time pin can be tied to VDDI or left
floating to provide a nominal dead time at approximately 400 ps.
DT 10 RDT
where:
DT= dead time (ns)
and
RDT= dead time programming resistor (k
Equation 5.
The device driving VIA and VIB should provide a minimum dead time of TDD to avoid activating overlap protection.
Input/output timing waveforms for the two-input drivers are shown in Figure 41, and dead time waveforms are
shown in Figure 42.
Ref
A
B
C
D
E
Description
VIA/
PWM
Normal operation: VIA high, VIB low.
Normal operation: VIB high, VIA low.
Contention: VIA = VIB = high.
VIB
Recovery from contention: VIA transitions low.
Normal operation: VIA = VIB = low.
Normal operation: VIA high, VIB low.
Contention: VIA = VIB = high.
VOA
VOB
F
G
H
I
Recovery from contention: VIB transitions low.
Normal operation: VIB transitions high.
A
B
C
D
E
F
G
H
I
Figure 41. Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers
28
Rev. 1.7
Si823x
OVERLAP
OVERLAP
VOB
VIA/
PWM
VIA/
PWM
VIB
50%
VIB
DT
DT
DT
DT
90%
VOA
VOA
10%
DT
DT
90%
VOB
VOB
10%
B. Dead Time Operation During Overlap
A. Typical Dead Time Operation
Figure 42. Dead Time Waveforms for High-Side/Low-Side Two-Input Drivers
Rev. 1.7
29
Si823x
4. Applications
The following examples illustrate typical circuit configurations using the Si823x.
4.1. High-Side/Low-Side Driver
Figure 43A shows the Si8230/3 controlled using the VIA and VIB input signals, and Figure 43B shows the Si8231/4
controlled by a single PWM signal.
VDD2
C3
VDD2
C3
D1
D1
VDDI
1 µF
VDDI
1 µF
VDDI
GNDI
VDDI
GNDI
C1
1 µF
C2
0.1 µF
1500 V max
1500 V max
C1
1 µF
C2
0.1 µF
VDDA
VDDA
CB
CB
Q1
Q1
OUT1
OUT2
VIA
VIB
PWMOUT
CONTROLLER
I/O
PWM
DT
VOA
VOA
GNDA
GNDA
DT
RDT
RDT
CONTROLLER
Si8230/3
Si8231/4
VDDB
VDDB
C4
0.1 µF
C5
10 µF
C4
0.1 µF
C5
10 µF
I/O
DISABLE
DISABLE
GNDB
VOB
GNDB
VOB
VDDB
Q2
Q2
A
B
Figure 43. Si823x in Half-Bridge Application
For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver
for Q1, which has a maximum drain voltage of 1500 V. The boot-strap start up time will depend on the CB cap
chosen. See “AN486: High-Side Bootstrap Design Using Si823x ISODrivers in Power Delivery Systems”. VOB is
connected as a conventional low-side driver, and, in most cases, VDD2 is the same as VDDB. Note that the input
side of the Si823x requires VDD in the range of 4.5 to 5.5 V (2.7 to 5.5 V for Si8237/8), while the VDDA and VDDB
output side supplies must be between 6.5 and 24 V with respect to their respective grounds. It is recommended
that bypass capacitors of 0.1 and 1 µF value be used on the Si823x input side and that they be located as close to
the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass capacitors, located as close to the
chip as possible, be used on the Si823x output side to reduce high-frequency noise and maximize performance.
30
Rev. 1.7
Si823x
4.2. Dual Driver
Figure 44 shows the Si823x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be
referenced to a common ground or to different grounds with as much as 1500 V dc between them.
VDDI
VDDI
Q1
C1
C2
VOA
1 µF
0.1 µF
GNDI
VDDA
VDDA
GNDA
VIA
VIB
PH1
PH2
C3
0.1 µF
C4
10 µF
Si8232/5/7/8
CONTROLLER
I/O
VDDB
VDDB
GNDB
C5
0.1 µF
C6
10 µF
DISABLE
Q2
VOB
Figure 44. Si8232/5/7/8 in a Dual Driver Application
Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse
without damaging the driver. That is, the voltage at VOA can be higher or lower than that of VOB by VDD without
damaging the driver. Therefore, a dual driver in a low-side high side/low side drive application can use either VOA
or VOB as the high side driver. Similarly, a dual driver can operate as a dual low-side or dual high-side driver and is
unaffected by static or dynamic voltage polarity changes.
4.3. Dual Driver with Thermally Enhanced Package (Si8236)
The thermal pad of the Si8236 must be connected to a heat spreader to lower thermal resistance. Generally, the
larger the thermal shield’s area, the lower the thermal resistance. It is recommended that thermal vias also be used
to add mass to the shield. Vias generally have much more mass than the shield alone and consume less space,
thus reducing thermal resistance more effectively. While the heat spreader is not generally a circuit ground, it is a
good reference plane for the Si8236 and is also useful as a shield layer for EMI reduction.
2
With a 10mm thermal plane on the outer layers (including 20 thermal vias), the thermal impedance of the Si8236
was measured at 50 °C/W. This is a significant improvement over the Si8235 which does not include a thermal
pad. The Si8235’s thermal resistance was measured at 105 °C /W. In addition, note that the GNDA and GNDB pins
for the Si8236 are connected together through the thermal pad.
Rev. 1.7
31
Si823x
5. Pin Descriptions
SOIC-16 (Narrow)
SOIC-16 (Wide)
1
2
16
15
14
16
15
14
13
12
11
10
9
1
2
VIA
VIB
VIA
VIB
VDDA
VOA
GNDA
NC
VDDA
VOA
GNDA
NC
3
4
5
6
7
8
3
4
5
6
7
8
VDDI
GNDI
DISABLE
DT
VDDI
GNDI
DISABLE
DT
Si8230
Si8233
Si823013
Si8233 12
NC
NC
11
10
9
VDDB
VOB
GNDB
VDDB
VOB
GNDB
NC
NC
VDDI
VDDI
Table 11. Si8230/3 Two-Input HS/LS Isolated Driver (SOIC-16)
Pin
1
Name
VIA
Description
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
2
VIB
3
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDI Input-side ground terminal.
4
5
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the
dead time between output transitions of VOA and VOB. Defaults to 400 ps dead time when con-
nected to VDDI or left open (see "3.8. Programmable Dead Time and Overlap Protection" on
page 28).
7
NC
No connection.
8
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB Ground terminal for Driver B.
9
10
11
12
13
14
15
16
VOB Driver B output (low-side driver).
VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
NC
No connection.
No connection.
GNDA Ground terminal for Driver A.
VOA Driver A output (high-side driver).
VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
32
Rev. 1.7
Si823x
SOIC-16 (Narrow)
SOIC-16 (Wide)
1
2
16
15
14
13
12
11
10
9
1
2
16
15
14
PWM
NC
PWM
NC
VDDA
VOA
GNDA
NC
VDDA
VOA
GNDA
NC
3
4
5
6
7
8
3
4
5
6
7
8
VDDI
GNDI
VDDI
GNDI
DISABLE
DT
Si8231
Si8234
Si823113
Si8234 12
DISABLE
DT
NC
NC
11
10
9
VDDB
VOB
GNDB
VDDB
VOB
GNDB
NC
NC
VDDI
VDDI
Table 12. Si8231/4 PWM Input HS/LS Isolated Driver (SOIC-16)
Description
Pin
1
Name
PWM PWM input.
2
NC
No connection.
3
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDI Input-side ground terminal.
4
5
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the
dead time between output transitions of VOA and VOB. Defaults to 400 ps dead time when con-
nected to VDDI or left open (see "3.8. Programmable Dead Time and Overlap Protection" on
page 28).
7
NC
No connection.
8
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB Ground terminal for Driver B.
9
10
11
12
13
14
15
16
VOB Driver B output (low-side driver).
VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
NC
No connection.
No connection.
GNDA Ground terminal for Driver A.
VOA Driver A output (high-side driver).
VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 1.7
33
Si823x
SOIC-16 (Narrow)
SOIC-16 (Wide)
1
2
16
15
16
15
14
13
12
11
10
9
1
2
VIA
VIA
VIB
VDDA
VOA
GNDA
NC
VDDA
VOA
GNDA
NC
VIB
Si8232 14
Si823513
Si8237
3
4
5
6
7
8
3
4
5
6
7
8
VDDI
GNDI
VDDI
Si8232
Si8235
Si8237
Si8238
GNDI
DISABLE
DISABLE
Si8238 12
NC
NC
11
10
9
VDDB
VOB
GNDB
VDDB
VOB
GNDB
NC
NC
NC
NC
VDDI
VDDI
Table 13. Si8232/5/7/8 Dual Isolated Driver (SOIC-16)
Description
Pin
1
Name
VIA
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
2
VIB
3
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for Si8237/8).
GNDI Input-side ground terminal.
4
5
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
NC
NC
No connection.
No connection.
7
8
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for Si8237/8).
GNDB Ground terminal for Driver B.
9
10
11
12
13
14
15
16
VOB
Driver B output.
VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
NC
No connection.
No connection.
GNDA Ground terminal for Driver A.
VOA Driver A output.
VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
34
Rev. 1.7
Si823x
LGA-14 (5 x 5 mm)
1
2
3
4
14
13
12
11
10
GNDI
VIA
VDDA
VOA
GNDA
NC
VIB
VDDI
Si8233
DISABLE 5
VDDB
6
7
8
DT
VOB
7
VDDI
GNDB
Table 14. Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA)
Pin
GNDI
VIA
Name
Description
1
2
3
4
5
Input-side ground terminal.
Non-inverting logic input terminal for Driver A.
VIB
Non-inverting logic input terminal for Driver B.
VDDI
DISABLE
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps
dead time when connected to VDDI or left open (see"3.8. Programmable Dead Time
and Overlap Protection" on page 28).
VDDI
GNDB
VOB
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
8
9
Driver B output (low-side driver).
VDDB
NC
10
11
12
13
14
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
VOA
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 1.7
35
Si823x
LGA-14 (5 x 5 mm)
1
2
3
4
14
13
12
11
10
GNDI
PWM
NC
VDDA
VOA
GNDA
NC
VDDI
Si8234
DISABLE 5
VDDB
6
7
8
DT
VOB
7
VDDI
GNDB
Table 15. Si8234 PWM Input HS/LS Isolated Driver (14 LD LGA)
Pin
GNDI
PWM
NC
Name
Description
1
2
3
4
5
Input-side ground terminal.
PWM input.
No connection.
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps
dead time when connected to VDDI or left open (see "3.8. Programmable Dead Time
and Overlap Protection" on page 28).
VDDI
GNDB
VOB
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
8
9
Driver B output (low-side driver).
VDDB
NC
10
11
12
13
14
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
VOA
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
36
Rev. 1.7
Si823x
LGA-14 (5 x 5 mm)
1
2
3
4
5
14
13
12
11
10
GNDI
VIA
VDDA
VOA
GNDA
NC
VIB
Si8235
VDDI
DISABLE
VDDB
6
7
7
8
NC
VOB
VDDI
GNDB
Table 16. Si8235 Dual Isolated Driver (14 LD LGA)
Pin
GNDI
VIA
Name
Description
Input-side ground terminal.
1
2
3
4
5
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
VIB
VDDI
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
NC
6
7
No connection.
VDDI
GNDB
VOB
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
8
9
Driver B output (low-side driver).
VDDB
NC
10
11
12
13
14
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
VOA
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 1.7
37
Si823x
LGA-14 (5 x 5 mm)
1
2
3
4
14
13
GNDI
VIA
VDDA
VOA
12
11
10
7
GNDA
NC
VIB
Si8236
VDDI
DISABLE 5
VDDB
6
NC
VOB
7
8
VDDI
GNDB
Table 17. Si8236 Dual Isolated Driver (14 LD LGA)
Pin
GNDI
VIA
Name
Description
Input-side ground terminal.
1
2
3
4
5
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
VIB
VDDI
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
NC
6
7
8
No connection.
VDDI
GNDB
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B. GNDA and GNDB pins for the Si8236 are connected together
through the thermal pad.
VOB
VDDB
NC
9
Driver B output (low-side driver).
10
11
12
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
Ground terminal for Driver A.GNDA and GNDB pins for the Si8236 are connected together
through the thermal pad.
VOA
13
14
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
38
Rev. 1.7
Si823x
6. Ordering Guide
Table 18. Ordering Part Numbers1,2
Legacy
Ordering Part
Number (OPN)
Peak
Current Voltage
UVLO
Isolation
Rating
Temperature Package Ordering Part
Inputs Configuration
Range
Type
Number (OPN)
2.5 kV Only
Wide Body (WB) Package Options
High Side/
Low Side
Si8230BB-D-IS VIA, VIB
Si8230-A-IS
High Side/
Low Side
0.5 A
8 V
Si8231BB-D-IS
Si8232BB-D-IS
Si8234CB-D-IS
PWM
VIA,VIB
PWM
Si8231-A-IS
Si8232-A-IS
N/A
Dual Driver
SOIC-16
Wide
Body
High Side/
Low Side
10 V
2.5 kVrms –40 to +125 °C
High Side/
Low Side
Si8233BB-D-IS
VIA,VIB
Si8233-B-IS
Si8234-B-IS
4.0 A
High Side/
Low Side
8 V
Si8234BB-D-IS
Si8235BB-D-IS
PWM
VIA,VIB
Dual Driver
Si8235-B-IS
N/A
Si8230AB-D-IS VIA, VIB
Si8231AB-D-IS PWM
High Side/
Low Side
0.5 A
4.0 A
5 V
5 V
N/A
SOIC-16
Wide
Body
Si8232AB-D-IS VIA,VIB
Si8233AB-D-IS VIA,VIB
Dual Driver
N/A
2.5 kVrms –40 to +125 °C
N/A
High Side/
Low Side
Si8234AB-D-IS
PWM
N/A
Si8235AB-D-IS VIA,VIB
Dual Driver
N/A
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
Rev. 1.7
39
Si823x
Table 18. Ordering Part Numbers1,2 (Continued)
Legacy
Temperature Package Ordering Part
Ordering Part
Number (OPN)
Peak
Current Voltage
UVLO
Isolation
Rating
Inputs Configuration
Range
Type
Number (OPN)
2.5 kV Only
Narrow Body (NB) Package Options
High Side/
Si8230BB-D-IS1 VIA,VIB
Low Side
High Side/
Low Side
0.5 A
8 V
Si8231BB-D-IS1
PWM
Si8232BB-D-IS1 VIA,VIB
Si8233BB-D-IS1 VIA,VIB
Dual Driver
SOIC-16
–40 to +125 °C Narrow
Body
2.5 kVrms
High Side/
Low Side
N/A
High Side/
Low Side
Si8234BB-D-IS1
PWM
4.0 A
8 V
Si8235BB-D-IS1 VIA,VIB
Si8235BA-D-IS1 VIA,VIB
Si8230AB-D-IS1 VIA,VIB
Dual Driver
Dual Driver
1.0 kVrms
N/A
N/A
N/A
N/A
N/A
N/A
High Side/
Low Side
Si8231AB-D-IS1
PWM
0.5 A
4.0 A
5 V
5 V
SOIC-16
Si8232AB-D-IS1 VIA,VIB
Si8233AB-D-IS1 VIA,VIB
Dual Driver
2.5 kVrms –40 to +125 °C Narrow
Body
High Side/
Low Side
Si8234AB-D-IS1
PWM
Si8235AB-D-IS1 VIA,VIB
Dual Driver
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
40
Rev. 1.7
Si823x
Table 18. Ordering Part Numbers1,2 (Continued)
Legacy
Ordering Part
Number (OPN)
Peak
Current Voltage
UVLO
Isolation
Rating
Temperature Package Ordering Part
Inputs Configuration
Range
Type
Number (OPN)
2.5 kV Only
LGA Package Options
Si8233CB-D-IM
10 V
8 V
5 V
8 V
5 V
N/A
Si8233-B-IM
N/A
Si8233BB-D-IM VIA,VIB
Si8233AB-D-IM
High Side/
Low Side
LGA-14
5x5 mm
Si8234BB-D-IM
PWM
Si8234AB-D-IM
2.5 kVrms
Si8234-B-IM
N/A
4.0 A
8 V
–40 to +125 °C
Si8235BB-D-IM
Si8235AB-D-IM
Si8235-B-IM
N/A
5 V
8 V
5 V
Si8236BA-D-IM
VIA,VIB
LGA-14
5x5 mm
with
Thermal
Pad
Si8236-B-IM
Dual Driver
1.0 kVrms
Si8236AA-D-IM
N/A
5 kV Ordering Options
High Side/
Low Side
Si8230BD-D-IS VIA, VIB
High Side/
Low Side
0.5 A
Si8231BD-D-IS
PWM
SOIC-16
Wide
Body
Si8232BD-D-IS VIA, VIB
Si8233BD-D-IS VIA, VIB
Dual Driver
8 V
5.0 kVrms –40 to +125 °C
N/A
High Side/
Low Side
High Side/
Low Side
4.0 A
Si8234BD-D-IS
PWM
Si8235BD-D-IS VIA, VIB
Si8230AD-D-IS VIA, VIB
Dual Driver
N/A
N/A
N/A
N/A
N/A
N/A
High Side/
Low Side
Si8231AD-D-IS
PWM
0.5 A
4.0 A
5 V
5 V
SOIC-16
Wide
Body
Si8232AD-D-IS VIA, VIB
Si8233AD-D-IS VIA, VIB
Dual Driver
5.0 kVrms –40 to +125 °C
High Side/
Low Side
Si8234AD-D-IS
PWM
Si8235AD-D-IS VIA, VIB
3 V VDDI Ordering Options
Notes:
Dual Driver
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
Rev. 1.7
41
Si823x
Table 18. Ordering Part Numbers1,2 (Continued)
Legacy
Temperature Package Ordering Part
Ordering Part
Number (OPN)
Peak
Current Voltage
UVLO
Isolation
Rating
Inputs Configuration
Range
Type
Number (OPN)
2.5 kV Only
Si8237AB‐D‐IS1 VIA, VIB
Si8237BB‐D‐IS1 VIA, VIB
Si8238AB‐D‐IS1 VIA, VIB
Si8238BB‐D‐IS1 VIA, VIB
Si8237AD‐D‐IS VIA, VIB
Si8237BD‐D‐IS VIA, VIB
Si8238AD‐D‐IS VIA, VIB
Si8238BD‐D‐IS VIA, VIB
Notes:
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
5 V
0.5 A
SOIC-16
Narrow
Body
8 V
2.5 kVrms
5.0 kVrms
5 V
4.0 A
8 V
40 to +125 °C
N/A
5 V
0.5 A
SOIC-16
Wide
Body
8 V
5 V
4.0 A
8 V
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
42
Rev. 1.7
Si823x
7. Package Outline: 16-Pin Wide Body SOIC
Figure 45 illustrates the package details for the Si823x in a 16-Pin Wide Body SOIC. Table 19 lists the values for
the dimensions shown in the illustration.
Figure 45. 16-Pin Wide Body SOIC
Rev. 1.7
43
Si823x
Table 19. Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
10.30 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
aaa
bbb
ccc
ddd
eee
fff
—
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for
small body, lead-free components.
44
Rev. 1.7
Si823x
8. Land Pattern: 16-Pin Wide Body SOIC
Figure 46 illustrates the recommended land pattern details for the Si823x in a 16-pin wide-body SOIC. Table 20
lists the values for the dimensions shown in the illustration.
Figure 46. 16-Pin SOIC Land Pattern
Table 20. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.7
45
Si823x
9. Package Outline: 16-Pin Narrow Body SOIC
Figure 47 illustrates the package details for the Si823x in a 16-pin narrow-body SOIC (SO-16). Table 21 lists the
values for the dimensions shown in the illustration.
Figure 47. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 21. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
Dimension
Min
Max
A
A1
A2
b
L
0.40
1.27
0.10
1.25
0.31
0.17
L2
0.25 BSC
h
0.25
0°
0.50
8°
0.51
0.25
θ
c
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
46
Rev. 1.7
Si823x
10. Land Pattern: 16-Pin Narrow Body SOIC
Figure 48 illustrates the recommended land pattern details for the Si823x in a 16-pin narrow-body SOIC. Table 22
lists the values for the dimensions shown in the illustration.
Figure 48. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 22. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.7
47
Si823x
11. Package Outline: 14 LD LGA (5 x 5 mm)
Figure 49 illustrates the package details for the Si823x in an LGA outline. Table 23 lists the values for the
dimensions shown in the illustration.
Figure 49. Si823x LGA Outline
Table 23. Package Diagram Dimensions
Dimension
MIN
0.74
0.25
NOM
0.84
MAX
0.94
0.35
A
b
0.30
D
5.00 BSC
4.15 BSC
0.65 BSC
5.00 BSC
3.90 BSC
0.75
D1
e
E
E1
L
0.70
0.05
—
0.80
0.15
0.10
0.10
0.08
0.15
0.08
L1
aaa
bbb
ccc
ddd
eee
0.10
—
—
—
—
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
48
Rev. 1.7
Si823x
12. Land Pattern: 14 LD LGA
Figure 50 illustrates the recommended land pattern details for the Si823x in a 14-pin LGA. Table 24 lists the values
for the dimensions shown in the illustration.
Figure 50. 14-Pin LGA Land Pattern
Table 24. 14-Pin LGA Land Pattern Dimensions
Dimension
(mm)
4.20
0.65
0.80
0.40
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05 mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.7
49
Si823x
13. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm)
Figure 51 illustrates the package details for the Si8236 ISOdriver in an LGA outline. Table 25 lists the values for the
dimensions shown in the illustration.
Figure 51. Si823x LGA Outline with Thermal Pad
Table 25. Package Diagram Dimensions
Dimension
MIN
0.74
0.25
NOM
0.84
MAX
0.94
0.35
A
b
0.30
D
5.00 BSC
4.15 BSC
0.65 BSC
5.00 BSC
3.90 BSC
0.75
D1
e
E
E1
L
0.70
0.05
1.40
4.15
—
0.80
0.15
1.50
4.25
0.10
0.10
0.08
0.15
0.08
L1
P1
P2
aaa
bbb
ccc
ddd
eee
0.10
1.45
4.20
—
—
—
—
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
50
Rev. 1.7
Si823x
14. Land Pattern: 14 LD LGA with Thermal Pad
Figure 52 illustrates the recommended land pattern details for the Si8236 in a 14-pin LGA with thermal pad.
Table 26 lists the values for the dimensions shown in the illustration.
Figure 52. 14-Pin LGA with Thermal Pad Land Pattern
Table 26. 14-Pin LGA with Thermal Pad Land Pattern Dimensions
Dimension
(mm)
4.20
1.50
4.25
0.65
0.80
0.40
C1
C2
D2
E
X1
Y1
Notes:
General:
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05 mm.
Solder Mask Design:
4. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design:
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly:
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.7
51
Si823x
15. Top Markings
15.1. Si823x Top Marking (16-Pin Wide Body SOIC)
Si823YUV
YYWWTTTTTT
e4
TW
15.2. Top Marking Explanation (16-Pin Wide Body SOIC)
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2, 7 = 0.5 A
Base Part Number
Ordering Options
3, 4, 5, 8 = 4.0 A
Line 1 Marking:
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
See Ordering Guide for more
information.
B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
Line 2 Marking:
Line 3 Marking:
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order form.
“e4” Pb-Free Symbol
Circle = 1.5 mm Diameter
(Center Justified)
Country of Origin
ISO Code Abbreviation
TW = Taiwan
52
Rev. 1.7
Si823x
15.3. Si823x Top Marking (16-Pin Narrow Body SOIC)
Si823YUV
YYWWTTTTTT
e4
15.4. Top Marking Explanation (16-Pin Narrow Body SOIC)
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2, 7 = 0.5 A
3, 4, 5, 8 = 4.0 A
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
Base Part Number
Ordering Options
Line 1 Marking:
Line 2 Marking:
See Ordering Guide for more
information.
B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
Manufacturing Code from Assembly Purchase Order
form.
TTTTTT = Mfg Code
Rev. 1.7
53
Si823x
15.5. Si823x Top Marking (14 LD LGA)
Si823Y
UV-IM
TTTTTT
YYWW
15.6. Top Marking Explanation (14 LD LGA)
Line 1 Marking:
Base Part Number
Ordering Options
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2 = 0.5 A
See Ordering Guide for more
information.
3, 4, 5, 6 = 4.0 A
Line 2 Marking:
Ordering options
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
A = 1.0 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
I = –40 to +125 °C ambient temperature range
M = LGA package type
Line 3 Marking:
Line 4 Marking:
TTTTTT
Manufacturing Code from Assembly
Pin 1 identifier
Circle = 1.5 mm diameter
YYWW
Manufacturing date code
54
Rev. 1.7
Si823x
Updated Table 8 on page 14.
Added junction temperature spec.
DOCUMENT CHANGE LIST
Updated Table 2 on page 11 with new notes.
Added Table 17 and pinout.
Revision 0.11 to Revision 0.2
Updated all specs to reflect latest silicon revision.
Updated Figures 19, 20, 21, and 22 to reflect correct
Updated Table 1 on page 6 to include new UVLO
y-axis scaling.
options.
Updated Figure 44 on page 31.
Updated Table 8 on page 14 to reflect new maximum
Updated "4.3. Dual Driver with Thermally Enhanced
package isolation ratings
Package (Si8236)" on page 31.
Added Figures 34, 35, and 36.
Updated "7. Package Outline: 16-Pin Wide Body
Updated Ordering Guide to reflect new package
SOIC" on page 43.
offerings.
Updated Table 19, “Package Diagram Dimensions,”
Added "3.7.3. Undervoltage Lockout (UVLO)" on
on page 44.
page 27 to describe UVLO operation.
Change references to 1.5 kV
rated devices to
RMS
Revision 0.2 to Revision 0.3
1.0 kV
throughout.
RMS
Moved Sections 2, 3, and 4 to after Section 5.
Updated Tables 14, 15, and 17.
Updated "3.5. Power Dissipation Considerations" on
page 23.
Removed Si8230, Si8231, and Si8232 from pinout and
Revision 1.2 to Revision 1.3
from title.
Updated and added Ordering Guide footnotes.
Updated UVLO specifications in Table 1 on page 6.
Added Si8237/8 throughout.
Updated Table 1 on page 6.
Updated Figure 4 on page 9.
UpdatedFigure 5 on page 9.
Added Figure 6 on page 10.
Added PWD and Output Supply Active Current
specifications in Table 1.
Updated and added typical operating condition
graphs in "3.1. Typical Operating Characteristics
(0.5 Amp)" on page 17 and "3.2. Typical Operating
Characteristics (4.0 Amp)" on page 19.
Updated Table 10 on page 21.
Created Notes 1 and 2.
Updated "3.8. Programmable Dead Time and
Overlap Protection" on page 28.
Revision 0.3 to Revision 1.0
Removed references to Figures 26A and 26B.
Updated Table 18 on page 39.
Updated Tables 2, 3, 4, and 5.
Updated “6. Ordering Guide” .
Added 5 V UVLO ordering options
Added Device Marking sections.
Added Si8235-BA-C-IS1 ordering part number.
Added table note.
Revision 1.3 to Revision 1.4
Revision 1.0 to Revision 1.1
Updated "6. Ordering Guide" on page 39.
Updated “ 3 V VDDI Ordering Options” .
Updated " Features" on page 1.
Updated CMTI specification.
Updated Table 1 on page 6.
Updated CMTI specification.
Revision 1.4 to Revision 1.5
Updated Table 1, input and output supply current.
Updated Table 5, “IEC 60747-5-5 Insulation
Characteristics*,” on page 13.
Added references to AEC-Q100 qualified
throughout.
Updated "4.2. Dual Driver" on page 31.
Updated "6. Ordering Guide" on page 39.
Changed all 60747-5-2 references to 60747-5-5.
Added references to CQC throughout.
Updated pin descriptions throughout.
Corrected dead time default to 400 ps from 1 ns.
Updated Table 18, Ordering Part Numbers.
Removed moisture sensitivity level table notes.
Replaced pin descriptions on page 1 with chip
graphics.
Revision 1.1 to Revision 1.2
Updated "6. Ordering Guide" on page 39.
Updated moisture sensitivity level (MSL) for all package
types.
Rev. 1.7
55
Si823x
Revision 1.5 to Revision 1.6
Updated Table 18, Ordering Part Numbers.
Added Revision D Ordering Part Numbers.
Removed all Ordering Part Numbers of previous
revisions.
Revision 1.6 to Revision 1.7
Updated Table 2 on page 11
Added CQC certificate numbers.
Updated Table 3 on page 12
Updated Erosion Depth.
Updated Table 5 on page 13
Updated VPR for WBSOIC-16.
Updated Table 8 on page 14
Removed Io and added Peak Output Current
specifications.
Updated Equation 1 example on page 23.
Updated Figure 43 on page 30.
Updated Figure 44 on page 31.
Updated Ordering Guide Table 18 on page 39.
Removed Note 2.
56
Rev. 1.7
Si823x
CONTACT INFORMATION
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400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-
intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
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tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-
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Rev. 1.7
57
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