SI8422AB-B-IS [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO8, ROHS COMPLIANT, SOIC-8;
| 型号： | SI8422AB-B-IS |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO8, ROHS COMPLIANT, SOIC-8 光电二极管 |
| 文件： | 总37页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
LOW-POWER, SINGLE AND DUAL-CHANNEL
DIGITAL ISOLATORS
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.6–5.5 V
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
Precise timing (typical)
11 ns propagation delay max
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient immunity 45 kV/µs
AEC-Q100 qualification
Up to 5000 VRMS isolation
High electromagnetic immunity
Ultra low power (typical)
5 V Operation:
< 2.6 mA/channel at 1 Mbps
< 6.8 mA/channel at 100 Mbps
2.70 V Operation:
Wide temperature range
< 2.3 mA/channel at 1 Mbps
< 4.6 mA/channel at 100 Mbps
–40 to 125 °C at 150 Mbps
RoHS compliant packages
SOIC-16 wide body
SOIC-8 narrow body
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated ADC, DAC
Motor control
Power inverters
Isolated switch mode supplies
Communication systems
Safety Regulatory Approvals
Ordering Information:
UL 1577 recognized
Up to 5000 VRMS for 1 minute
VDE certification conformity
IEC 60747-5-5
See page 29.
(VDE0884 Part 5)
EN60950-1 (reinforced insulation)
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering
substantial data rate, propagation delay, power, size, reliability, and external BOM
advantages when compared to legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges and
throughout device service life for ease of design and highly uniform performance.
All device versions have Schmitt trigger inputs for high noise immunity and only
require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case
propagation delays of less than 10 ns. Ordering options include a choice of
isolation ratings (up to 5 kV) and a selectable fail-safe operating mode to control
the default output state during power loss. All products are safety certified by UL,
CSA, and VDE, and products in wide-body packages support reinforced insulation
withstanding up to 5 kVRMS
.
Rev. 1.3 3/14
Copyright © 2014 by Silicon Laboratories
Si8410/20/21 / Si8422/23
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
2
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2. Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
12. Top Marking: 8-Pin Narrow-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Rev. 1.3
3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Symbol
Test Condition
, V rising
Min
Typ
Max
Unit
Parameter
VDD Undervoltage Threshold
VDDUV+
V
2.15
45
2.3
75
2.5
95
V
DD1
DD2
VDD Negative-Going Lockout
Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
All inputs rising
All inputs falling
1.6
1.1
0.40
2.0
—
—
—
1.9
1.4
0.50
—
V
V
V
0.45
—
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
µA
L
1
Output Impedance
Z
50
O
DC Supply Current (All inputs 0 V or at Supply)
Si8410Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
DD1
DD2
DD1
DD2
mA
mA
mA
mA
mA
Si8420Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
DD1
DD2
DD1
DD2
Si8421Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
DD1
DD2
DD1
DD2
Si8422Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
DD1
DD2
DD1
DD2
Si8423Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
DD1
DD2
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
1 Mbps Supply Current (All inputs = 500 kHz square wave, C = 15 pF on all outputs)
L
Si8410Ax, Bx
V
V
—
—
2.0
1.1
3.0
1.7
mA
mA
mA
mA
mA
DD1
DD2
Si8420Ax, Bx
V
V
—
—
3.5
1.9
5.3
2.9
DD1
DD2
Si8421Ax, Bx
V
V
—
—
2.8
2.8
4.2
4.2
DD1
DD2
Si8422Ax, Bx
V
V
—
—
2.8
2.8
4.2
4.2
DD1
DD2
Si8423Ax, Bx
V
V
—
—
3.4
1.9
5.1
2.9
DD1
DD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, C = 15 pF on all outputs)
L
Si8410Bx
V
V
—
—
2.1
1.5
3.1
2.1
mA
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
3.6
2.6
5.4
3.6
DD1
DD2
Si8421Bx
V
V
—
—
3.2
3.2
4.5
4.5
DD1
DD2
Si8422Bx
V
V
—
—
3.2
3.2
4.5
4.5
DD1
DD2
Si8423Bx
V
V
—
—
3.4
2.5
5.1
3.5
DD1
DD2
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
5
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
100 Mbps Supply Current (All inputs = 50 MHz square wave, C = 15 pF on all outputs)
L
Si8410Bx
V
V
—
—
2.1
5.0
3.1
6.3
mA
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
3.7
9.8
5.4
12.3
DD1
DD2
Si8421Bx
V
V
—
—
6.8
6.8
8.5
8.5
DD1
DD2
Si8422Bx
V
V
—
—
6.8
6.8
8.5
8.5
DD1
DD2
Si8423Bx
V
V
—
—
3.4
9.2
5.1
11.5
DD1
DD2
mA
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
—
1.0
250
35
Mbps
ns
—
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
—
—
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Si841xBx, Si842xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
0
—
—
150
6.0
11
Mbps
ns
—
t
, t
See Figure 1
See Figure 1
4.0
8.0
ns
PHL PLH
Pulse Width Distortion
PWD
—
1.5
3.0
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.5
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
—
—
—
2.0
2.0
350
4.0
4.0
—
ns
ns
ps
r
L
Output Fall Time
t
C = 15 pF
f
L
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 6
Common Mode Transient
Immunity
CMTI
V = V or 0 V
20
—
45
15
—
kV/µs
µs
I
DD
3
Start-up Time
t
40
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing
Rev. 1.3
7
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 2. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
, V rising
Min
2.15
45
Typ
2.3
75
Max
2.5
95
Unit
V
VDD Undervoltage Threshold
VDDUV+ V
DD1
DD2
VDD Negative-Going Lockout
Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
All inputs rising
All inputs falling
1.6
1.1
0.40
2.0
—
—
—
1.9
1.4
0.50
—
V
V
V
0.45
—
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
3.1
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
µA
L
1
Output Impedance (Si8410/20)
Z
50
O
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
DD1
DD2
DD1
DD2
mA
mA
mA
mA
mA
Si8420Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
DD1
DD2
DD1
DD2
Si8421Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
DD1
DD2
DD1
DD2
Si8422Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
DD1
DD2
DD1
DD2
Si8423Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
DD1
DD2
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, C = 15 pF on all outputs)
L
Si8410Ax, Bx
V
V
—
—
2.0
1.1
3.0
1.7
mA
mA
mA
mA
mA
DD1
DD2
Si8420Ax, Bx
V
V
—
—
3.5
1.9
5.3
2.9
DD1
DD2
Si8421Ax, Bx
V
V
—
—
2.8
2.8
4.2
4.2
DD1
DD2
Si8422Ax, Bx
V
V
—
—
2.8
2.8
4.2
4.2
DD1
DD2
Si8423Ax, Bx
V
V
—
—
3.4
1.9
5.1
2.9
DD1
DD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, C = 15 pF on all outputs)
L
Si8410Bx
V
V
—
—
2.0
1.3
3.0
1.8
mA
mA
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
3.5
2.3
5.3
3.2
DD1
DD2
Si8421Bx
V
V
—
—
3.0
3.0
4.4
4.4
DD1
DD2
Si8422Bx
V
V
—
—
3.0
3.0
4.4
4.4
DD1
DD2
Si8423Bx
V
V
—
—
3.4
2.2
5.1
3.1
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
9
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100 Mbps Supply Current (All inputs = 50 MHz square wave, C = 15 pF on all outputs)
L
Si8410Bx
V
V
—
—
2.0
3.6
3.0
4.5
mA
mA
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
4.5
7.0
5.3
8.8
DD1
DD2
Si8421Bx
V
V
—
—
5.3
5.3
6.6
6.6
DD1
DD2
Si8422Bx
V
V
—
—
5.3
5.3
6.6
6.6
DD1
DD2
Si8423Bx
V
V
—
—
3.4
6.6
5.1
8.3
DD1
DD2
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
—
—
1.0
250
35
Mbps
ns
—
—
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
25
ns
|t
– t
|
PLH
PHL
2
Propagation Delay Skew
Channel-Channel Skew
Si841xBx, Si842xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
0
—
—
150
6.0
11
Mbps
ns
—
4.0
—
t
, t
See Figure 1
See Figure 1
8.0
1.5
ns
PHL PLH
Pulse Width Distortion
PWD
3.0
ns
|t
– t
|
PLH
PHL
2
Propagation Delay Skew
Channel-Channel Skew
Notes:
t
—
—
2.0
0.5
3.0
1.5
ns
ns
PSK(P-P)
t
PSK
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
All Models
Output Rise Time
t
C = 15 pF
—
—
—
20
2.0
2.0
350
45
4.0
4.0
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
Peak Eye Diagram Jitter
tJIT(PK)
CMTI
See Figure 6
ps
Common Mode Transient
Immunity
V = V or 0 V
—
kV/µs
I
DD
3
Start-up Time
t
—
15
40
µs
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
11
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 3. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Symbol
Test Condition
, V rising
Min
Typ
Max
Unit
Parameter
VDD Undervoltage Threshold
VDDUV+
V
2.15
45
2.3
75
2.5
95
V
DD1
DD2
VDD Negative-Going Lockout
Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
All inputs rising
All inputs falling
1.6
1.1
0.40
2.0
—
—
—
1.9
1.4
0.50
—
V
V
V
V
V
V
V
0.45
—
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
IH
V
—
0.8
—
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.
2.3
OH
DD1 DD2
4
Low Level Output Voltage
Input Leakage Current
V
—
—
—
0.2
—
0.4
±10
—
V
µA
OL
I
L
2
Output Impedance
Z
50
O
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
mA
mA
mA
DD1
DD2
DD1
DD2
Si8420Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
DD1
DD2
DD1
DD2
Si8421Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
DD1
DD2
DD1
DD2
Si8422Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
DD1
DD2
DD1
DD2
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Si8423Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, C = 15 pF on all outputs)
L
Si8410Ax, Bx
V
V
—
—
2.0
1.1
3.0
1.7
mA
mA
mA
mA
mA
DD1
DD2
Si8420Ax, Bx
V
V
—
—
3.5
1.9
5.3
2.9
DD1
DD2
Si8421Ax, Bx
V
V
—
—
2.8
2.8
4.2
4.2
DD1
DD2
Si8422Ax, Bx
V
V
—
—
2.8
2.8
4.2
4.2
DD1
DD2
Si8423Ax, Bx
V
V
—
—
3.3
1.8
5.0
2.8
DD1
DD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, C = 15 pF on all outputs)
L
Si8410Bx
V
V
—
—
2.0
1.1
3.0
1.7
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
3.5
2.1
5.3
3.0
DD1
DD2
Si8421Bx
V
V
—
—
2.9
2.9
4.3
4.3
DD1
DD2
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
13
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Si8422Bx
V
V
—
—
2.9
2.9
4.3
4.3
mA
DD1
DD2
Si8423Bx
V
V
—
—
3.4
2.0
5.1
2.9
mA
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
V
V
—
—
2.0
2.0
3.0
3.0
mA
mA
mA
mA
mA
DD1
DD2
Si8420Bx
V
V
—
—
3.5
5.5
5.3
6.9
DD1
DD2
Si8421Bx
V
V
—
—
4.6
4.6
5.8
5.8
DD1
DD2
Si8422Bx
V
V
—
—
4.6
4.6
5.8
5.8
DD1
DD2
Si8423Bx
V
V
—
—
3.4
5.2
5.1
6.5
DD1
DD2
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
—
—
1.0
250
35
Mbps
ns
—
—
—
t
, t
See Figure 1
See Figure 1
ns
PHL PLH
Pulse Width Distortion
PWD
25
ns
|t
- t
|
PLH PHL
3
Propagation Delay Skew
Channel-Channel Skew
Si841xBx, Si842xBx
Maximum Data Rate
Notes:
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
0
—
150
Mbps
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
14
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Minimum Pulse Width
Propagation Delay
—
4.0
—
—
6.0
11
ns
ns
ns
t
, t
See Figure 1
See Figure 1
8.0
1.5
PHL PLH
Pulse Width Distortion
PWD
3.0
|t
- t
|
PLH PHL
3
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.5
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
Output Fall Time
t
C = 15 pF
—
—
2.0
2.0
4.0
4.0
ns
ns
r
L
t
C = 15 pF
f
L
Peak Eye Diagram Jitter
tJIT(PK)
CMTI
See Figure 6
—
350
45
—
—
ps
Common Mode Transient
Immunity
V = V or 0 V
20
kV/µs
I
DD
4
Start-up Time
t
—
15
40
µs
SU
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Table 4. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
—
Typ
—
—
—
—
—
—
—
—
—
—
Max
150
125
150
6.0
Unit
C°
C°
°C
V
2
Storage Temperature
T
STG
Operating Temperature
Junction Temperature
T
A
T
J
Supply Voltage
V
, V
–0.5
–0.5
–0.5
—
DD1
DD2
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s) NB SOIC-8
Maximum Isolation Voltage (1 s) WB SOIC-16
Notes:
I
10
mA
C°
O
—
260
4500
6500
—
V
RMS
RMS
—
V
1. Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
Rev. 1.3
15
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 5. Recommended Operating Conditions
Symbol
Min
Typ
Max
Unit
Parameter
Ambient Operating Temperature*
Supply Voltage
T
–40
2.70
2.70
25
—
—
125
5.5
5.5
C°
V
A
V
DD1
V
V
DD2
*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating
channels, and supply voltage.
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
RMS
RMS
RMS
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
60601-1: Up to 125 V
reinforced insulation working voltage; up to 380 V
basic insulation working voltage.
RMS
RMS
VDE
The Si84xx is certified according to IEC 60747-5-5. For more details, see File 5006301-4880-0001.
60747-5-5: Up to 891 V for basic insulation working voltage.
peak
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
RMS
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 V isolation voltage for basic insulation.
RMS
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "6. Ordering Guide" on page 29.
16
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 7. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
Unit
WB
NB
SOIC-16 SOIC-8
1
L(IO1)
L(IO2)
8.0 min 4.9 min
8.0 min 4.01 min
mm
mm
mm
Nominal Air Gap (Clearance)
1
Nominal External Tracking (Creepage)
0.014
600
0.008
600
Minimum Internal Gap (Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
V
RMS
0.019
0.040
mm
Erosion Depth
1,2
1,2
2
R
10
10
Resistance (Input-Output)
IO
2
C
2.0
4.0
1.0
4.0
pF
pF
Capacitance (Input-Output)
IO
3
C
Input Capacitance
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline:
16-Pin Wide Body SOIC”, “9. Package Outline: 8-Pin Narrow Body SOIC”. VDE certifies the clearance and creepage
limits as 8.5 mm minimum for the WB SOIC-16 package and 4.7 mm minimum for the NB SOIC-8 package. UL does
not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and
creepage limits as 3.9 mm minimum for the NB SOIC-8 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 (1–4, NB SOIC-8)
are shorted together to form the first terminal and pins 9–16 (5–8, NB SOIC-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 5) Ratings
Specification
Parameter
Test Conditions
NB SOIC8
WB SOIC 16
Basic Isolation Group
Material Group
I
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-III
I-II
I-II
I-IV
I-IV
I-III
I-III
RMS
RMS
RMS
RMS
Installation Classification
Rev. 1.3
17
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 9. IEC 60747-5-5 Insulation Characteristics for Si84xxxx*
Characteristic
Parameter
Symbol
Test Condition
Unit
WB
SOIC-16
NB SOIC-8
Maximum Working Insulation
Voltage
V
891
560
Vpeak
IORM
Method b1
(V
x 1.875 = V , 100%
IORM
PR
1671
1050
Input to Output Test Voltage
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
V
t = 60 sec
6000
2
4000
2
Vpeak
Transient Overvoltage
IOTM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at T ,
9
9
S
R
>10
>10
S
V
= 500 V
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Max
WB SOIC- NB SOIC-
Parameter
Symbol
Test Condition
Unit
16
8
Case Temperature
T
I
150
220
150
160
°C
S
Safety Input, Output, or
Supply Current
= 140 °C/W (NB SOIC-8), 100 °C
(WB SOIC-16),
mA
S
JA
V = 5.5 V, T = 150 °C, T = 25 °C
I
J
A
2
Device Power Dissipation
P
150
150
mW
D
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 2 and 3.
2. The Si84xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
18
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 11. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-8
Unit
IC Junction-to-Air Thermal Resistance
100
140
ºC/W
JA
500
460
VDD1, VDD2 = 2.70 V
375
360
VDD1, VDD2 = 3.3 V
250
220
VDD1, VDD2 = 5.5 V
125
0
0
50
100
150
200
Case Temperature (ºC)
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5
400
320
VDD1, VDD2 = 2.70 V
300
270
V
DD1, VDD2 = 3.3 V
200
100
0
160
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Case Temperature (ºC)
Figure 3. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5
Rev. 1.3
19
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
2. Functional Description
2.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in
Figure 4.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 5 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 5. Modulation Scheme
20
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
2.2. Eye Diagram
Figure 6 illustrates an eye-diagram taken on an Si8422. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8422 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited.
Figure 6. Eye Diagram
Rev. 1.3
21
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present.
Table 12. Si84xx Logic Operation Table
1,4
1,2,3
1,2,3
1,4
Comments
V Input
VDDI State
VDDO State
V Output
I
O
H
L
P
P
P
P
P
H
Normal operation.
L
5
6
X
UP
H (Si8422/23) Upon transition of VDDI from unpowered to
L (Si8410/20/21)
6
powered, V returns to the same state as V in
O
I
less than 1 µs.
5
X
P
UP
Undetermined Upon transition of VDDO from unpowered to
powered, V returns to the same state as V
O
I
within 1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 2.72.60 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See "6. Ordering Guide" on page 29 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN).
22
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this,
the outputs follow the states of inputs.
3.2. Under Voltage Lockout
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage
lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters
UVLO when V
falls below V
and exits UVLO when V
rises above V . Side B operates
DD1
DD1(UVLO–)
DD1
DD1(UVLO+)
the same as Side A with respect to its V
supply.
DD2
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
OUTPUT
Figure 7. Device Behavior during Normal Operation
Rev. 1.3
23
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 16 and Table 7 on page 17 detail the
working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.)
requirements before starting any design that uses a digital isolator.
3.3.1. Supply Bypass
The Si841x/2x family requires a 0.1 µF bypass capacitor between V
and GND1 and V
and GND2. The
DD1
DD2
capacitor should be placed as close as possible to the package. To enhance the robustness of a design, it is further
recommended that the user also add 1 µF bypass capacitors and include 100 resistors in series with the inputs
and outputs if the system is excessively noisy.
3.3.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
3.3.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3.4. Fail-Safe Operating Mode
Si84xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input
supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 12 on
page 22 and "6. Ordering Guide" on page 29 for more information.
24
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
3.5. Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 1, 2, and 3 for actual specification limits.
30
25
20
15
10
5
30
25
20
15
10
5
5V
5V
3.3V
3.3V
2.70V
2.70V
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 11. Si8410 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 8. Si8410 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
30
25
30
25
20
20
5V
5V
15
15
3.3V
3.3V
10
10
2.70V
2.70V
5
5
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 9. Si8420 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 12. Si8420 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
30
25
30
25
5V
20
5V
15
20
3.3V
10
15
10
5
3.3V
5
2.70V
0
2.70V
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
Data Rate (Mbps)
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 10. Si8421 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Figure 13. Si8422 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Rev. 1.3
25
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
30
25
20
5V
15
3.3V
10
2.70V
5
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 14. Si8423 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
30
25
20
5V
15
3.3V
10
2.70V
5
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 15. Si8423 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
10
Falling Edge
9
8
7
6
5
Rising Edge
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 16. Propagation Delay
vs. Temperature
26
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
4. Pin Descriptions (Wide-Body SOIC)
GND2
NC
GND1
NC
GND2
NC
GND2
NC
GND1
NC
GND1
NC
GND2
NC
GND1
NC
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
VDD1
A1
VDD2
B1
VDD1
A1
VDD1
A1
VDD2
B1
VDD2
B1
VDD1
A1
VDD2
B1
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RF
RCVR
NC
RF
RCVR
RF
XMITR
NC
A2
NC
B2
A2
NC
B2
A2
NC
B2
XMITR
NC
GND1
NC
NC
NC
NC
NC
NC
GND1
NC
NC
GND1
NC
NC
GND1
NC
NC
GND2
GND2
GND2
GND2
Si8410 WB SOIC-16
Si8420/23 WB SOIC-16
Si8421 WB SOIC-16
Si8422 WB SOIC-16
Name
SOIC-16 Pin# SOIC-16 Pin#
Type
Description
Si8410
Si842x
GND1
NC*
1
1
Ground
Side 1 ground.
NC
2, 5, 6, 8,10,
11, 12, 15
2, 6, 8,10,
11, 15
No Connect
V
3
4
3
4
Supply
Digital I/O
Digital I/O
Ground
Side 1 power supply.
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 ground.
DD1
A1
A2
NC
7
5
GND1
GND2
B2
7
9
9
Ground
Side 2 ground.
NC
13
14
16
12
13
14
16
Digital I/O
Digital I/O
Supply
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
Side 2 ground.
B1
V
DD2
GND2
Ground
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
Rev. 1.3
27
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
5. Pin Descriptions (Narrow-Body SOIC)
VDD1
VDD2
VDD1
VDD2
B1
I
s
o
l
a
t
I
s
o
l
a
t
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B1
A1
A2
A1
A2
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
B2
B2
i
i
o
n
o
n
GND2
GND1
GND2
GND1
Si8422 NB SOIC-8
Si8423 NB SOIC-8
Name
SOIC-8 Pin#
Si842x
Type
Description
V
1
4
2
3
7
6
8
5
Supply
Ground
Side 1 power supply.
Side 1 ground.
DD1
GND1
A1
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Side 1 digital input or output.
Side 1 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
A2
B1
B2
V
DD2
GND2
Ground
Side 2 ground.
28
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
6. Ordering Guide
Table 13. Ordering Guide1,2,3
Numberof Numberof Maximum Default
Inputs Inputs DataRate Output
VDD1 Side VDD2 Side (Mbps)
Ordering Part
Number (OPN)
Isolation
Rating
Temp
Range
Package
Type
State
High
High
High
Si8422AB-D-IS
Si8422BB-D-IS
Si8423AB-D-IS
Si8423BB-D-IS
1
1
2
1
1
0
1
150
1
2.5 kVrms –40 to 125 °C
NB SOIC-8
2
1
1
2
2
1
1
1
0
0
0
0
0
1
1
1
150
1
High
Low
Low
Low
Low
Low
Low
High
4
Si8410AD-D-IS
Si8410BD-D-IS
Si8420AD-D-IS
Si8420BD-D-IS
Si8421AD-D-IS
Si8421BD-D-IS
4
4
4
4
4
150
1
150
1
5.0 kVrms –40 to 125 °C WB SOIC-16
150
1
Si8422AD-D-IS
Si8422BD-D-IS
Si8423AD-D-IS
Si8423BD-D-IS
Notes:
1
2
2
1
0
0
150
1
High
High
High
150
1. All devices >1 kVRMS are AEC-Q100 qualified.
2. “Si” and “SI” are used interchangeably.
3. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
4. Refer to Si8410/20/21 data sheet for information regarding 2.5 kV rated versions of these products.
Rev. 1.3
29
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
7. Package Outline: 16-Pin Wide Body SOIC
Figure 17 illustrates the package details for the Si84xx Digital Isolator. Table 14 lists the values for the dimensions
shown in the illustration.
Figure 17. 16-Pin Wide Body SOIC
Table 14. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
2.65
0.3
A
A1
D
E
E1
b
0.1
10.3 BSC
10.3 BSC
7.5 BSC
0.31
0.51
0.33
c
0.20
e
1.27 BSC
h
0.25
0.4
0°
0.75
1.27
7°
L
30
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
8. Land Pattern: 16-Pin Wide-Body SOIC
Figure 18 illustrates the recommended land pattern details for the Si84xx in a 16-pin wide-body SOIC. Table 15
lists the values for the dimensions shown in the illustration.
Figure 18. 16-Pin SOIC Land Pattern
Table 15. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.3
31
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
9. Package Outline: 8-Pin Narrow Body SOIC
Figure 19 illustrates the package details for the Si84xx. Table 16 lists the values for the dimensions shown in the
illustration.
Figure 19. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 16. Package Diagram Dimensions
Millimeters
Symbol
Min
Max
A
A1
A2
B
1.35
1.75
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0
6.20
0.50
1.27
8
L
32
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
10. Land Pattern: 8-Pin Narrow Body SOIC
Figure 20 illustrates the recommended land pattern details for the Si84xx in an 8-pin narrow-body SOIC. Table 17
lists the values for the dimensions shown in the illustration.
Figure 20. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 17. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.3
33
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
11. Top Marking: 16-Pin Wide Body SOIC
Si84XYSV
YYWWTTTTTT
e4
TW
Figure 21. Isolator Top Marking
Table 18. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of reverse channels (1, 0)
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
1,2
(See Ordering Guide for more
information).
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing code from assembly house.
“e4” Pb-Free Symbol.
Circle = 1.7 mm Diameter
(Center-Justified)
Country of Origin ISO Code
Abbreviation
TW = Taiwan.
Notes:
1. The Si8422 has one reverse channel.
2. The Si8423 has zero reverse channels.
34
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
12. Top Marking: 8-Pin Narrow-Body SOIC
Si84XYSV
YYWWRF
e3
AIXX
Figure 22. Isolator Top Marking
Table 19. Top Marking Explanations
Line 1 Marking:
Base Part Number
Ordering Options
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of reverse channels (1, 0)
S = Speed Grade
1,2
(See Ordering Guide for more
information).
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to
the year and workweek of the mold date.
R = Product (OPN) Revision
F = Wafer Fab
Circle = 1.1 mm Diameter
Left-Justified
“e3” Pb-Free Symbol.
First two characters of the manufacturing code.
A = Assembly Site
I = Internal Code
Last four characters of the manufacturing code.
XX = Serial Lot Number
Notes:
1. The Si8422 has one reverse channel.
2. The Si8423 has zero reverse channels.
Rev. 1.3
35
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
Updated “ Features” on page 1.
Updated transient immunity
Removed Block Diagram from page 1.
Added chip graphics on page 1.
Added Peak Eye Diagram jitter in Tables 1, 2, and 3.
Updated transient immunity
Moved Table 12 to page 22.
Added "3. Device Operation" on page 22.
Added "3.4. Fail-Safe Operating Mode" on page 24.
Moved “Typical Performance Characteristics” to
page 25.
Deleted RF Radiated Emissions section.
Deleted RF Magnetic and Common-Mode Transient
Immunity section.
Updated MSL rating to MSL2A.
Revision 1.0 to Revision 1.1
Numerous text edits.
Added notes to Tables 18 and 19.
Revision 1.1 to Revision 1.2
Updated Timing Characteristics in Tables 1, 2, and 3.
Revision 1.2 to Revision 1.3
Added references to AEC-Q100 qualified throughout.
Changed all 60747-5-2 references to 60747-5-5.
Updated Table 13 “Ordering Guide”.
Added table Notes 1 and 2.
Removed references to moisture sensitivity levels.
Added Revision D ordering information.
Removed older revisions.
Updated "11. Top Marking: 16-Pin Wide Body SOIC"
on page 34.
36
Rev. 1.3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
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Rev. 1.3
37
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