SI8440AA-C-IS [SILICON]
Interface Circuit,;
| 型号： | SI8440AA-C-IS |
| 厂家： | 
SILICON |
| 描述： | Interface Circuit, |
| 文件： | 总32页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8440/41/42/45
ULTRA LOW POWER QUAD-CHANNEL DIGITAL ISOLATOR
Features
Pin Assignments
High-speed operation:
DC – 150 Mbps
Low propagation delay:
<10 ns typical
Wide Operating Supply Voltage:
2.75–5.5 V
Precise timing:
2 ns pulse width distortion
1 ns channel-channel matching
2 ns pulse width skew
Up to 2500 VRMS isolation
Wide Body SOIC
VDD1
VDD2
GND2
B1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Transient Immunity: 25 kV/µs
Tri-state outputs with ENABLE
control
DC correct
No start-up initialization required
<30 µs startup time
High temperature operation:
125 °C at 150 Mbps
Wide body and narrow body SOIC-
16 packages
GND1
A1
Ultra low power
5 V Operation:
A2
B2
I< 1.25 mA per channel at 1 Mbps
I< 2 mA per channel at 10 Mbps
I< 6 mA per channel at 100 Mbps
2.75 V Operation:
I< 1.25 mA per channel at 1 Mbps
I< 2 mA per channel at 10 Mbps
I< 4 mA per channel at 100 Mbps
A3
A4
B3
B4
EN1/NC
EN2/NC
GND2
GND1
Top View
Narrow Body SOIC
Applications
VDD1
VDD2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND2
B1
GND1
A1
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power factor correction systems
A2
B2
A3
A4
B3
Safety Regulatory Approvals*
B4
UL recognition: 2500 VRMS for 1
Minute per UL1577
VDE certification conformity
IEC 60747-5-2
EN1/NC
EN2/NC
GND2
GND1
(VDE0884 Part 2)
CSA component acceptance notice
Top View
Description
Silicon Lab's family of ultra low power digital isolators are CMOS devices
that employ an RF coupler to transmit digital information across an isolation
barrier. Very high speed operation at low power levels is achieved. These
parts are available in 16-pin wide body and narrow body SOIC packages.
Two speed grade options (1 and 150 Mbps) are available and achieve typical
propagation delay of less than 10 ns.
Block Diagram
Si8440/45
Si8441
Si8442
A1
A2
A3
A4
NC
A1
A2
A3
A4
A1
A2
B1
B2
B1
B2
B1
B2
B3
B4
B3
B4
A3
B3
A4
B4
EN2/NC EN1
EN2
EN1
EN2
*Note: Pending.
Rev. 0.64 1/09
Copyright © 2009 by Silicon Laboratories
Si8440/41/42/45
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si8440/41/42/45
2
Rev. 0.64
Si8440/41/42/45
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Performance Characteristics* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.4. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.5. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . .23
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 0.64
3
Si8440/41/42/45
1. Electrical Specifications
Table 1. Electrical Characteristics1
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
—
4.8
0.2
—
2
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Enable Input High Current
Enable Input Low Current
V
IH
V
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
µA
µA
µA
L
I
V
= V
ENx IH
ENH
I
V
= V
IL
2
—
ENL
ENx
DC Supply Current (All inputs 0 V or at Supply)
Si8440Ax, Bx and Si8445Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
3
6
3
4
6
12
6
mA
mA
mA
DD1
DD2
DD1
DD2
Si8441Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
3
5
4
4
6
10
8
DD1
DD2
DD1
DD2
Si8442Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
2
4
4
4
4
8
8
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8440Ax, Bx
V
V
—
—
4
4
7
7
mA
mA
mA
DD1
DD2
Si8441Ax, Bx
V
V
—
—
4
4
7
7
DD1
DD2
Si8442Ax, Bx
V
V
—
—
4
4
6
6
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
V
V
—
—
5
20
10
30
mA
mA
DD1
DD2
Si8441Bx
V
V
—
—
9
16
14
24
DD1
DD2
4
Rev. 0.64
Si8440/41/42/45
Table 1. Electrical Characteristics1 (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Si8442Bx
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
13
13
20
20
mA
DD1
DD2
Timing Characteristics
Si844xA
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
—
—
1
Mbps
ns
—
—
—
250
35
t
, t
See Figure 2
See Figure 2
ns
PHL PLH
PWD
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Si844xB
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
5
—
—
8
150
6
Mbps
ns
t
, t
See Figure 2
See Figure 2
15
3
ns
PHL PLH
PWD
—
—
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
For All Models
t
—
—
—
—
10
3
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
20
2
2
—
—
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
Immunity
CMTI
V = V or 0 V
25
kV/µs
I
DD
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
9
9
—
—
—
ns
ns
µs
en1
Enable to Data Tri-State
en2
3
Start-up Time
t
30
SU
Notes:
1. Electrical specification values are preliminary. Various specifications will be adjusted to reflect actual performance as
final product characterization data becomes available.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 0.64
5
Si8440/41/42/45
ENABLE
OUTPUTS
ten1
ten2
Figure 1. ENABLE Timing Diagram
1.4 V
Typical
Input
tPLH
tPHL
90%
90%
10%
1.4 V
10%
Typical
Output
tr
tf
Figure 2. Propagation Delay Timing
6
Rev. 0.64
Si8440/41/42/45
Table 2. Electrical Characteristics1
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
—
3.1
0.2
—
2
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Enable Input High Current
Enable Input Low Current
V
IH
V
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
µA
µA
µA
L
I
V
= V
ENx IH
ENH
I
V
= V
IL
2
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8440Ax, Bx and Si8445Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
3
6
3
4
6
12
6
mA
mA
mA
DD1
DD2
DD1
DD2
Si8441Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
3
5
4
4
6
10
8
DD1
DD2
DD1
DD2
Si8442Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
2
4
4
4
4
8
8
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8440Ax, Bx
V
V
—
—
4
4
7
7
mA
mA
mA
DD1
DD2
Si8441Ax, Bx
V
V
—
—
4
4
7
7
DD1
DD2
Si8442Ax, Bx
V
V
—
—
4
4
6
6
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
V
V
—
—
4
13
8
20
mA
mA
mA
DD1
DD2
Si8441Bx
V
V
—
—
7
12
11
18
DD1
DD2
Si8442Bx
V
V
—
—
10
10
15
15
DD1
DD2
Rev. 0.64
7
Si8440/41/42/45
Table 2. Electrical Characteristics1 (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si844xA
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
—
—
1
Mbps
ns
—
—
—
250
35
t
,t
See Figure 2
See Figure 2
ns
PHL PLH
PWD
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Si844xB
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
5
—
—
8
150
6
Mbps
ns
t
, t
See Figure 2
See Figure 2
15
3
ns
PHL PLH
PWD
—
—
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
For All Models
t
—
—
—
—
10
3
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
20
2
2
—
—
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
CMTI
V = V or 0 V
25
kV/µs
I
DD
Immunity at Logic Low Output
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
9
9
—
—
—
ns
ns
µs
en1
en2
Enable to Data Tri-State
3
Start-up Time
t
30
SU
Notes:
1. Electrical specification values are preliminary. Various specifications will be adjusted to reflect actual performance as
final product characterization data becomes available.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 0.64
Si8440/41/42/45
Table 3. Electrical Characteristics1
(VDD1 = 2.75 V, VDD2 = 2.75 V, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
—
2.3
0.2
—
2
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Enable Input High Current
Enable Input Low Current
V
IH
V
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
µA
µA
µA
L
I
V
= V
ENx IH
ENH
I
V
= V
IL
2
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8440Ax, Bx and Si8445Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
3
6
3
4
6
12
6
mA
mA
mA
DD1
DD2
DD1
DD2
Si8441Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
3
5
4
4
6
10
8
DD1
DD2
DD1
DD2
Si8442Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2
2
4
4
4
4
8
8
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8440Ax, Bx
V
V
—
—
4
4
7
7
mA
mA
mA
DD1
DD2
Si8441Ax, Bx
V
V
—
—
4
4
7
7
DD1
DD2
Si8442Ax, Bx
V
V
—
—
4
4
6
6
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440Bx, Si8445Bx
V
V
—
—
4
12
8
20
mA
mA
mA
DD1
DD2
Si8441Bx
V
V
—
—
7
10
11
18
DD1
DD2
Si8442Bx
V
V
—
—
9
9
15
15
DD1
DD2
Rev. 0.64
9
Si8440/41/42/45
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.75 V, VDD2 = 2.75 V, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si844xA
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
—
—
1
Mbps
ns
—
—
—
250
35
t
,t
See Figure 2
See Figure 2
ns
PHL PLH
PWD
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Si844xB
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
5
—
—
8
150
6
Mbps
ns
t
, t
See Figure 2
See Figure 2
15
3
ns
PHL PLH
PWD
—
—
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
For All Models
t
—
—
—
—
10
3
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
20
2
2
—
—
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
CMTI
V = V or 0 V
25
kV/µs
I
DD
Immunity at Logic Low Output
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
15
15
30
—
—
—
ns
ns
µs
en1
Enable to Data Tri-State
en2
3
Start-up Time
t
SU
Notes:
1. Electrical specification values are preliminary. Various specifications will be adjusted to reflect actual performance as
final product characterization data becomes available.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 0.64
Si8440/41/42/45
Table 4. Absolute Maximum Ratings
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
—
Max
150
125
6
Unit
ºC
ºC
V
Storage Temperature
Ambient Temperature Under Bias
Supply Voltage
T
STG
T
A
V
, V
DD2
DD1
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
O
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s)
L
10
mA
ºC
—
260
—
3600
V
RMS
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum ratings for extended periods may degrade performance.
Table 5. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
–40
Typ
25
—
Max
125
5.5
Unit
ºC
V
Ambient Operating Temperature*
Supply Voltage
T
150 Mbps, 15 pF, 5 V
A
V
2.75
2.75
DD1
DD2
V
—
5.5
V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice. For more details, see File 232873.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
*Note: Pending. All 2.5 kVRMS rated devices are production tested to >3.6 kVRMS for 1 sec. For more information, see
"6. Ordering Guide" on page 25.
Rev. 0.64
11
Si8440/41/42/45
Table 7. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
Unit
WB
NB
SOIC-16 SOIC-16
Minimum Air Gap (Clearance)
L(IO1)
L(IO2)
7.7
8.1
5.0
4.6
mm
mm
mm
V
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
0.008
>175
0.008
>175
Tracking Resistance (Comparative Tracking
Index)
CTI
DIN IEC
60112/VDE 0303
Part 1
1
12
12
Resistance (Input-Output)
R
10
10
IO
1
Capacitance (Input-Output)
C
f = 1 MHz
2
2
pF
pF
IO
2
Input Capacitance
C
4.0
4.0
I
Notes:
1. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
2. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0884 Part 2) Ratings
Parameter
Test Conditions
Material Group
Specification
Basic isolation group
IIIa
I-IV
I-III
I-II
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
RMS
RMS
RMS
Installation Classification
12
Rev. 0.64
Si8440/41/42/45
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter
Symbol
Test Condition
Characteristic
Unit
Maximum Working Insulation Voltage
VIORM
560
V peak
Method a
After Environmental Tests
Subgroup 1
896
(VIORM x 1.6 = VPR, tm = 60 sec,
Partial Discharge < 5 pC)
Method b1
VPR
V peak
Input to Output Test Voltage
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
1050
After Input and/or Safety Test
Subgroup 2/3
(VIORM x 1.2 = VPR, tm = 60 sec,
672
Partial Discharge < 5 pC)
Highest Allowable Overvoltage (Transient
Overvoltage, tTR = 10 sec)
4000
V peak
VTR
Pollution Degree (DIN VDE 0110, Table 1)
Insulation Resistance at TS, VIO = 500 V
2
RS
>109
*Note: This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is
ensured by protective circuits. The Si84xx provides a climate classification of 40/125/21.
Table 10. IEC Safety Limiting Values1
Max
Parameter
Symbol
Test Condition
Min Typ
Unit
WB
NB
SOIC-16 SOIC-16
Case Temperature
T
I
—
—
—
—
150
220
150
210
°C
S
Safety input, output, or
supply current
= 100 °C/W (WB SOIC-16),
105 °C/W (NB SOIC-16),
mA
S
JA
V = 5.5 V, T = 150 °C, T = 25 °C
I
J
A
Device Power
Dissipation
P
—
—
275
275
mW
D
2
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 3.
2. The Si8440 is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 0.64
13
Si8440/41/42/45
Table 11. Thermal Characteristics
Typ
Parameter
Symbol
Test Condition
Min
Max
Unit
WB
NB
SOIC-16 SOIC-16
IC Junction-to-Case Ther-
mal Resistance
Thermocouple located at
center of package
—
—
30
45
—
—
ºC/W
ºC/W
JC
IC Junction-to-Air Thermal
Resistance
100
105
JA
500
450
400
300
200
100
0
370
220
0
50
100
150
200
Temperature (ºC)
Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
500
430
400
350
300
210
200
100
0
0
50
100
150
200
Temperature (ºC)
Figure 4. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
14
Rev. 0.64
Si8440/41/42/45
2. Typical Performance Characteristics*
6
14
12
10
8
5.5
5V
5V
5
3.3V
2.75V
4.5
4
3.3V
2.75V
6
3.5
3
4
2
2.5
2
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 5. Si8440/45 Typical VDD1 Supply
Current vs. Data Rate 5, 3.3, and 2.75 V
Operation
Figure 7. Si8441 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.75 V Operation
30
25
5V
5V
25
20
20
3.3V
3.3V
15
15
10
2.75V
2.75V
10
5
0
5
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 6. Si8440/45 Typical VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.75 V
Operation (15 pF Load)
Figure 8. Si8441 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.75 V Operation
(15 pF Load)
20
5V
15
3.3V
10
2.75V
5
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 9. Si8442 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.75 V
Operation (15 pF Load)
Rev. 0.64
15
Si8440/41/42/45
11
10.5
Falling Edge
10
9.5
9
8.5
8
Rising Edge
7.5
7
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 10. Propagation Delay
vs. Temperature 5 V Operation
11
10.5
10
Falling Edge
9.5
9
8.5
8
Rising Edge
7.5
7
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 11. Propagation Delay
vs. Temperature 3.3 V Operation
11
10.5
10
Falling Edge
9.5
9
Rising Edge
8.5
8
7.5
7
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 12. Propagation Delay
vs. Temperature 2.75 V Operation
16
Rev. 0.64
Si8440/41/42/45
3. Application Information
3.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in
Figure 13.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 13. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 14 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 14. Modulation Scheme
Rev. 0.64
17
Si8440/41/42/45
3.2. Eye Diagram
Figure 15 illustrates an eye-diagram taken on an Si8440. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8440 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 15. Eye Diagram
18
Rev. 0.64
Si8440/41/42/45
4. Layout Recommendations
Dielectric isolation is a set of specifications produced by the safety regulatory agencies from around the world that
describes the physical construction of electrical equipment that derives power from a high-voltage power system
such as 100–240 V systems or industrial power systems. The dielectric test (or HIPOT test) given in the safety
AC
specifications places a very high voltage between the input power pins of a product and the user circuits and the
user touchable surfaces of the product. For the IEC relating to products deriving their power from the 220–240 V
power grids, the test voltage is 2500 V (or 3750 V —the peak equivalent voltage).
AC
DC
There are two terms described in the safety specifications:
Creepage—the distance along the insulating surface an arc may travel.
Clearance—the distance through the shortest path through air that an arc may travel.
Figure 16 illustrates the accepted method of providing the proper creepage distance along the surface. For a
220–240 V application, this distance is 8 mm and the wide body SOIC package must be used. There must be no
AC
copper traces within this 8 mm exclusion area, and the surface should have a conformal coating such as solder
resist. The digital isolator chip must straddle this exclusion area.
IEC Specified
Creepage
Distance
Figure 16. Creepage Distance
4.1. Supply Bypass
The Si844x requires a 1 µF bypass capacitor between V
be placed as close as possible to the package.
and GND1 and V
and GND2. The capacitor should
DD1
DD2
Rev. 0.64
19
Si8440/41/42/45
4.2. Input and Output Characteristics
The Si844x inputs and outputs are standard CMOS drivers/receivers. Table 12 details powered and unpowered
operation of the Si84xx.
Table 12. Si84xx Operation Table
V
EN
VDDI
VDDO
V
Comments
I
O
1,2,3,4
1,5,6
1,5,6
1,2
1,2
Input
State
State
Input
Output
H
L
H or NC
H or NC
L
P
P
P
P
P
P
H
L
Enabled, normal operation
X
X
P
Hi-Z
L
Disabled
H or NC
UP
Upon the transition of VDDI from unpowered to
powered, V returns to the same state as V in
O
I
less than 1 µs.
X
X
L
UP
P
P
Hi-Z
L
Disabled
X
UP
Upon the transition of VDDI from unpowered to
powered, V returns to the same state as V in
O
I
less than 1 µs, if EN is in either the H or NC state.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si84xx is
operating in noisy environments.
4. No Connect (NC) replaces EN1 on Si8440/45. No Connect replaces EN2 on the Si8445. No Connects are not internally
connected and can be left floating, tied to VDD, or tied to GND.
5. "Powered" state (P) is defined as 2.75 V < VDD < 5.5 V.
6. "Unpowered" state (UP) is defined as VDD = 0 V.
20
Rev. 0.64
Si8440/41/42/45
4.3. Enable Inputs
Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic
operation is summarized for each isolator product in Table 13. These inputs are internally pulled-up to local VDD by
a 3 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To
minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are
unused, it is recommended they be connected to an external logic level, especially if the Si84xx is operating in a
noisy environment.
Table 13. Enable Input Truth Table
P/N
EN1*
—
—
H
EN2*
H
Operation
Outputs B1, B2, B3, B4 are enabled.
Si8440
L
Outputs B1, B2, B3, B4 are disabled and in high impedance state.
Output A4 enabled.
Si8441
Si8442
Si8445
X
L
X
Output A4 disabled and in high impedance state.
Outputs B1, B2, B3 are enabled.
X
H
X
L
Outputs B1, B2, B3 are disabled and in high impedance state.
Outputs A3 and A4 are enabled.
H
X
L
X
Outputs A3 and A4 are disabled and in high impedance state.
Outputs B1 and B2 are enabled.
X
H
X
L
Outputs B1 and B2 are disabled and in high impedance state.
Outputs B1, B2, B3, B4 are enabled.
—
—
*Note: X = not applicable; H = Logic High; L = Logic Low.
Rev. 0.64
21
Si8440/41/42/45
4.4. RF Radiated Emissions
The Si8440 family uses a RF carrier frequency of approximately 700 MHz. This results in a small amount of
radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but due to a small
amount of RF energy driving the isolated ground planes which can act as a dipole antenna.
The unshielded Si8440 evaluation board passes FCC requirements. Table 14 shows measured emissions
compared to FCC requirements.
Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less
efficient antenna.
Table 14. Radiated Emissions*
Frequency
(GHz)
Measured
(dBµV/m)
FCC Spec
(dBµV/m) to Spec (dB)
Compared
2.094
2.168
4.210
4.337
6.315
6.505
8.672
70.0
68.3
61.9
60.7
58.3
60.7
45.6
74.0
74.0
74.0
74.0
74.0
74.0
74.0
–4.0
–5.7
–12.1
–13.3
–15.7
–13.3
–28.4
*Note: Data table to be updated pending final characterization.
22
Rev. 0.64
Si8440/41/42/45
4.5. RF Immunity and Common Mode Transient Immunity
The Si8440 family has very high common mode transient immunity while transmitting data. This is typically
measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements
show no failures up to 25 kV/µs. During a high surge event the output may glitch low for up to 20–30 ns, but the
output corrects immediately after the surge event.
The Si844x family passes the industrial requirements of CISPR24 for RF immunity of 3 V/m using an unshielded
evaluation board. As shown in Figure 17, the isolated ground planes form a parasitic dipole antenna, while
Figure 18 shows the RMS common mode voltage versus frequency above which the Si844x becomes susceptible
to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage below the
envelope specified in Figure 18. The PCB should be laid-out to not act as an efficient antenna for the RF frequency
of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or
otherwise shielded.
GND1
GND2
Isolator
Dipole
Antenna
Figure 17. Dipole Antenna
5
4
3
2
1
0
500
1000
Frequency (MHz)
1500
2000
Figure 18. RMS Common Mode Voltage vs. Frequency
(Data to be Updated Pending Final Characterization)
Rev. 0.64
23
Si8440/41/42/45
5. Pin Descriptions
VDD1
VDD2
GND2
B1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
A1
A2
B2
B3
A3
A4
B4
EN1/NC
EN2/NC
GND2
GND1
Top View
Narrow and Wide Body SOIC
Name
SOIC-16 Pin#
Type
Description
V
1
2
Supply
Side 1 power supply.
DD1
GND1
A1
Ground
Side 1 ground.
3
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital Input
Ground
Side 1 digital input.
A2
4
Side 1 digital input.
A3
5
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 active high enable. NC on Si8440/45.
Side 1 ground.
A4
6
EN1/NC*
GND1
GND2
EN2/NC*
B4
7
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Input
Digital I/O
Digital I/O
Side 2 active high enable. NC on Si8445.
Side 2 digital input or output.
Side 2 digital input or output.
B3
B2
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B1
GND2
Ground
Supply
Side 2 ground.
V
Side 2 power supply.
DD2
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
24
Rev. 0.64
Si8440/41/42/45
6. Ordering Guide
Si84XYSV-R-TPn
Isolator Product
Data channel count
Reverse channel count
Max Data Rate (A = 1 Mbps, B = 150 Mbps)
Insulation Rating (A = 1 kV, B = 2.5 kV)
Product Revision
Temp Range (I = –40 to +125 ºC)
Package Type (S = SOIC)
Package Extension (1 = Narrow Body)
Figure 19. Ordering Part Number (OPN) Convention
Table 15. Ordering Guide
Ordering Part Number of Number of Maximum Isolation Temp Range
Package
Type
Legacy Part
Equivalent
Number (OPN)
Inputs
Inputs
Data Rate Rating
VDD1 Side VDD2 Side (Mbps)
Si8440AA-C-IS
Si8440BA-C-IS
Si8441AA-C-IS
Si8441BA-C-IS
Si8442AA-C-IS
Si8442BA-C-IS
Si8445BA-C-IS
Si8440AA-C-IS1
Si8440BA-C-IS1
Si8441AA-C-IS1
Si8441BA-C-IS1
Si8442AA-C-IS1
Si8442BA-C-IS1
Si8445BA-C-IS1
4
4
3
3
2
2
4
4
4
3
3
2
2
4
0
0
1
1
2
2
0
0
0
1
1
2
2
0
1
150
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150
1
1 kVrms –40 to 125 °C WB SOIC-16
150
150
1
150
1
150
1
1 kVrms –40 to 125 °C NB SOIC-16
150
150
Rev. 0.64
25
Si8440/41/42/45
Table 15. Ordering Guide (Continued)
Ordering Part Number of Number of Maximum Isolation Temp Range
Package
Type
Legacy Part
Equivalent
Number (OPN)
Inputs
Inputs
Data Rate Rating
VDD1 Side VDD2 Side (Mbps)
Si8440AB-C-IS
Si8440BB-C-IS
4
4
0
0
1
Si8440-A-IS
150
Si8440-B-IS,
Si8440-C-IS
Si8441AB-C-IS
Si8441BB-C-IS
3
3
1
1
1
Si8441-A-IS
150
Si8441-B-IS,
Si8441-C-IS
2.5 kVrms –40 to 125 °C WB SOIC-16
Si8442AB-C-IS
Si8442BB-C-IS
2
2
2
2
1
Si8442-A-IS
150
Si8442-B-IS,
Si8442-C-IS
Si8445BB-C-IS
Si8440AB-C-IS1
Si8440BB-C-IS1
Si8441AB-C-IS1
Si8441BB-C-IS1
Si8442AB-C-IS1
Si8442BB-C-IS1
Si8445BB-C-IS1
4
4
4
3
3
2
2
4
0
0
0
1
1
2
2
0
150
1
Si8445-B-IS
—
—
—
—
—
—
—
150
1
150
1
2.5 kVrms –40 to 125 °C NB SOIC-16
150
150
Note: All packages are Pb-free and RoHS compliant. Moisture sensitivity level is MSL3 with peak reflow temperature of 260
°C according to the JEDEC industry standard classifications, and peak solder temperature.
26
Rev. 0.64
Si8440/41/42/45
7. Package Outline: 16-Pin Wide Body SOIC
Figure 20 illustrates the package details for the Quad-Channel Digital Isolator. Table 16 lists the values for the
dimensions shown in the illustration.
Figure 20. 16-Pin Wide Body SOIC
Table 16. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
2.65
0.3
A
A1
D
E
E1
b
0.1
10.3 BSC
10.3 BSC
7.5 BSC
0.31
0.51
0.33
c
0.20
e
1.27 BSC
h
0.25
0.4
0°
0.75
1.27
7°
L
Rev. 0.64
27
Si8440/41/42/45
8. Package Outline: 16-Pin Narrow Body SOIC
Figure 21 illustrates the package details for the Si84xx in a 16-pin narrow-body SOIC (SO-16). Table 17 lists the
values for the dimensions shown in the illustration. All packages are Pb-free and RoHS compliant. Moisture
sensitivity level is MSL3 with peak reflow temperature of 260 °C according to the JEDEC industry classification and
peak solder temperature.
Figure 21. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 17. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
28
Rev. 0.64
Si8440/41/42/45
Table 17. Package Diagram Dimensions (Continued)
L2
h
0.25 BSC
0.25
0°
0.50
8°
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-
012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-
STD-020C specification for Small Body Components.
Rev. 0.64
29
Si8440/41/42/45
9. Top Marking
Si84XYSV
YYWWTTTTTT
e3
TW
Figure 22. Si8440/41/42/45 Top Marking
Table 18. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
(See Ordering Guide for more
information).
A = 1 kV; B = 2.5 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by Assembly House. Corresponds to the year
and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing Code from Assembly House
“e3” Pb-Free Symbol
Circle = 1.5 mm Diameter
(Center-Justified)
Country of Origin ISO Code
Abbreviation
TW = Taiwan
30
Rev. 0.64
Si8440/41/42/45
DOCUMENT CHANGE LIST
Revision 0.62 to Revision 0.63
Rev 0.63 is the first revision of this document that
applies to the new series of ultra low power isolators
featuring pinout and functional compatibility with
previous isolator products.
Updated “1. Electrical Specifications”.
Updated “6. Ordering Guide”.
Added “9. Top Marking”.
Revision 0.63 to Revision 0.64
Updated all specs to reflect latest silicon.
Rev. 0.64
31
Si8440/41/42/45
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: PowerProducts@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
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