SI8442-C-ISR [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO16, ROHS COMPLIANT, SOIC-16;型号: | SI8442-C-ISR |
厂家: | SILICON |
描述: | Analog Circuit, 1 Func, CMOS, PDSO16, ROHS COMPLIANT, SOIC-16 光电二极管 接口集成电路 |
文件: | 总28页 (文件大小:642K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si8440/41/42/45
QUAD-CHANNEL DIGITAL ISOLATOR
Features
Pin Assignments
ꢀ High-speed operation:
ꢀ 2500 V
isolation
RMS
DC – 150 Mbps
ꢀ Transient Immunity: >25 kV/µs
Wide Body SOIC
ꢀ Low propagation delay:
ꢀ Tri-state outputs with ENABLE
VDD1
VDD2
GND2
B1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
<10 ns
control
GND1
A1
ꢀ Wide Operating Supply Voltage:
ꢀ DC correct
2.375–5.5 V
ꢀ No start-up initialization required
ꢀ <10 µs Startup Time
A2
B2
ꢀ Low power: I1 + I2 <
12 mA/channel at 100 Mbps
B3
A3
A4
ꢀ High temperature operation:
125 °C at 100 Mbps
ꢀ Precise timing:
B4
2 ns pulse width distortion
1 ns channel-channel matching
2 ns pulse width skew
EN1/NC
GND1
EN2/NC
GND2
100 °C at 150 Mbps
ꢀ Wide body SOIC-16 package
Top View
Applications
ꢀ Isolated switch mode supplies ꢀ Motor control
ꢀ Isolated ADC, DAC
ꢀ Power factor correction systems
Safety Regulatory Approvals
ꢀ UL recognition:2500 V
for 1 ꢀ VDE certification conformity
RMS
ꢁ DIN EN 60747-5-2 (VDE0884
Minute per UL1577
Part 2):2003-01
ꢀ CSA component acceptance
ꢁ DIN EN60950(VDE0805):
2001-12;EN60950:2000
ꢁ VIORM = 560 VPEAK
notice #5A
Description
Silicon Lab's family of digital isolators are CMOS devices that employ
an RF coupler to transmit digital information across an isolation
barrier. Very high speed operation at low power levels is achieved.
These parts are available in a 16-pin wide body SOIC package. Three
speed grade options (1, 10, 150 Mbps) are available and achieve
typical propagation delay of less than 10 ns.
Block Diagram
Si8440/45
Si8441
Si8442
A1
A2
A3
A4
NC
A1
A2
A3
A4
A1
A2
B1
B2
B1
B2
B1
B2
B3
B4
B3
B4
A3
B3
A4
B4
EN2/NC EN1
EN2
EN1
EN2
Rev. 0.51 10/06
Copyright © 2006 by Silicon Laboratories
Si8440/41/42/45
Si8440/41/42/45
2
Rev. 0.51
Si8440/41/42/45
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . .22
4.5. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
7. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Rev. 0.51
3
Si8440/41/42/45
1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Enable Input High Current
Enable Input Low Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
µA
µA
µA
L
I
V
= V
IH
4
ENH
ENx
I
V
= V
IL
20
—
ENL
ENx
DC Supply Current (All inputs 0 V or at Supply)
Si8440/45-A,-B,-C, V
Si8440/45-A,-B,-C, V
Si8440/45-A,-B,-C, V
Si8440/45-A,-B,-C, V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
—
—
—
—
8
12
12
22
12
14
17
21
19
15
15
20
20
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
7
15
7
Si8441-A,-B,-C, V
Si8441-A,-B,-C, V
Si8441-A,-B,-C, V
Si8441-A,-B,-C, V
Si8442-A,-B,-C, V
Si8442-A,-B,-C, V
Si8442-A,-B,-C, V
Si8442-A,-B,-C, V
9
DD1
11
14
13
10
10
13
13
DD2
DD1
DD2
DD1
DD2
DD1
DD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8440/45-B,-C, V
Si8440/45-B,-C, V
—
—
—
—
—
—
11
10
12
14
13
13
17
15
18
20
18
18
mA
mA
mA
mA
mA
mA
DD1
DD2
Si8441-B,-C, V
Si8441-B,-C, V
Si8442-B,-C, V
Si8442-B,-C, V
DD1
DD2
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440-C, V
Si8440-C, V
Si8441-C, V
Si8441-C, V
Si8442-C, V
Si8442-C, V
—
—
—
—
—
—
12
27
16
27
22
22
17
32
23
34
29
29
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
4
Rev. 0.51
Si8440/41/42/45
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si844x-A
Maximum Data Rate
Minimum Pulse Width
0
—
—
40
—
1
1000
75
Mbps
ns
—
25
—
1
Propagation Delay
t
, t
ns
PHL PLH
Pulse Width Distortion
PWD
30
ns
1
|t
- t
|
PLH PHL
2
2
2
Propagation Delay Skew
t
—
—
—
—
50
40
ns
ns
PSK
t
PSKCD/OD
3
Channel-Channel Skew
Si844x-B
Maximum Data Rate
Minimum Pulse Width
0
—
—
20
—
10
100
35
Mbps
ns
—
10
—
1
Propagation Delay
t
, t
ns
PHL PLH
Pulse Width Distortion
PWD
7.5
ns
1
|t
- t
|
PLH PHL
Propagation Delay Skew
t
—
—
—
—
25
5
ns
ns
PSK
t
PSKCD/OD
3
Channel-Channel Skew
Si844x-C
Maximum Data Rate
Minimum Pulse Width
0
—
4
—
—
150
6.6
9.5
3
Mbps
ns
1
Propagation Delay
t
, t
6.5
—
ns
PHL PLH
Pulse Width Distortion
PWD
—
ns
1
|t
- t
|
PLH PHL
Propagation Delay Skew
t
—
—
—
—
5.5
3
ns
ns
PSK
t
PSKCD/OD
3
Channel-Channel Skew
Rev. 0.51
5
Si8440/41/42/45
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
For All Models
Output Rise Time
Output Fall Time
C1 = 15 pF
C1 = 15 pF
—
—
25
2
2
—
—
—
ns
ns
Common Mode Transient
Immunity at Logic Low Output
CM
30
kV/µs
L
4
Common Mode Transient
Immunity at Logic High Output
CM
25
30
—
kV/µs
H
4
Enable to Data Valid
t
t
—
—
—
5
5
3
—
—
—
ns
ns
µs
en1
Enable to Data Tri-State
en2
5
Start-up Time
t
SU
Notes:
1. tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the
falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx
signal to the 50% level of the rising edge of the VOx signal.
2. tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any
two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is
the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of
the isolation barrier.
4. CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is
the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-
mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the
range over which the common mode is slewed.
5. Start-up time is the time period from the application of power to valid data at the output.
INPUT
(VIX
50%
ENABLE
)
tPLH
tPHL
OUTPUTS
OUTPUT
(VOX
50%
)
ten1
ten2
Figure 1. ENABLE Timing Diagram
Figure 2. Propagation Delay Timing
6
Rev. 0.51
Si8440/41/42/45
Table 2. Electrical Characteristics
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Enable Input High Current
Enable Input Low Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
3.1
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
µA
µA
µA
L
I
V
= V
IH
4
ENH
ENx
I
V
= V
IL
20
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8440/45-A,-B,-C, V
Si8440/45-A,-B,-C, V
Si8440/45-A,-B,-C, V
Si8440/45-A,-B,-C, V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
—
—
—
—
7
7
12
12
21
11
13
17
20
18
14
14
18
18
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
14
6
Si8441-A,-B,-C, V
Si8441-A,-B,-C, V
Si8441-A,-B,-C, V
Si8441-A,-B,-C, V
Si8442-A,-B,-C, V
Si8442-A,-B,-C, V
Si8442-A,-B,-C, V
Si8442-A,-B,-C, V
8
DD1
11
13
12
9
DD2
DD1
DD2
DD1
DD2
DD1
DD2
9
12
12
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8440/45-B,-C, V
—
—
—
—
—
—
11
9
16
13
17
19
17
17
mA
mA
mA
mA
mA
mA
DD1
DD2
Si8440/45-B,-C, V
Si8441-B,-C, V
Si8441-B,-C, V
Si8442-B,-C, V
Si8442-B,-C, V
11
13
12
12
DD1
DD2
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440-C, V
Si8440-C, V
Si8441-C, V
Si8441-C, V
Si8442-C, V
Si8442-C, V
—
—
—
—
—
—
11
19
13
21
18
18
17
25
20
27
23
23
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
Rev. 0.51
7
Si8440/41/42/45
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si844x-A
Maximum Data Rate
Minimum Pulse Width
0
—
—
40
—
1
1000
75
Mbps
ns
—
25
—
1
Propagation Delay
t
,t
ns
PHL PLH
Pulse Width Distortion
PWD
30
ns
1
|t
- t
|
PLH PHL
2
2
2
Propagation Delay Skew
t
—
—
—
—
50
40
ns
ns
PSK
t
PSKCD/OD
3
Channel-Channel Skew
Si844x-B
Maximum Data Rate
Minimum Pulse Width
0
—
—
20
—
10
100
35
Mbps
ns
—
10
—
1
Propagation Delay
t
, t
ns
PHL PLH
Pulse Width Distortion
PWD
7.5
ns
1
|t
- t
|
PLH PHL
Propagation Delay Skew
t
—
—
—
—
25
5
ns
ns
PSK
t
PSKCD/OD
3
Channel-Channel Skew
Si844x-C
Maximum Data Rate
Minimum Pulse Width
0
—
4
—
—
150
6.6
9.5
3
Mbps
ns
1
Propagation Delay
t
, t
6.5
—
ns
PHL PLH
Pulse Width Distortion
PWD
—
ns
1
|t
- t
|
PLH PHL
Propagation Delay Skew
t
—
—
—
—
5.5
3
ns
ns
PSK
t
PSKCD/OD
3
Channel-Channel Skew
8
Rev. 0.51
Si8440/41/42/45
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
For All Models
Output Rise Time
Output Fall Time
C1 = 15 pF
C1 = 15 pF
—
—
25
2
2
—
—
—
ns
ns
Common Mode Transient
Immunity at Logic Low Output
CM
30
kV/µs
L
4
Common Mode Transient
Immunity at Logic High Output
CM
25
30
—
kV/µs
H
4
Enable to Data Valid
t
t
—
—
—
5
5
3
—
—
—
ns
ns
µs
en1
en2
Enable to Data Tri-State
5
Start-up Time
t
SU
Notes:
1. tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling
edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the
50% level of the rising edge of the VOx signal.
2. tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any
two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is
the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of
the isolation barrier.
4. CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is
the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range
over which the common mode is slewed.
5. Start-up time is the time period from the application of power to valid data at the output.
Rev. 0.51
9
Si8440/41/42/45
Table 3. Electrical Characteristics
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 ºC)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Enable Input High Current
Enable Input Low Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
2.3
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
µA
µA
µA
L
I
V
= V
IH
4
ENH
ENx
I
V
= V
IL
20
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8440/45-A,-B,-C, V
Si8440/45-A,-B,-C, V
Si8440/45-A,-B,-C, V
Si8440/45-A,-B,-C, V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
—
—
—
—
7
6
10
10
17
10
11
12
15
14
12
12
15
15
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
13
6
Si8441-A,-B,-C, V
Si8441-A,-B,-C, V
Si8441-A,-B,-C, V
Si8441-A,-B,-C, V
Si8442-A,-B,-C, V
Si8442-A,-B,-C, V
Si8442-A,-B,-C, V
Si8442-A,-B,-C, V
8
DD1
10
12
11
9
DD2
DD1
DD2
DD1
DD2
DD1
DD2
9
12
12
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8440/45-B,-C, V
—
—
—
—
—
—
10
8
12
12
13
15
14
14
mA
mA
mA
mA
mA
mA
DD1
DD2
Si8440/45-B,-C, V
Si8441-B,-C, V
Si8441-B,-C, V
Si8442-B,-C, V
Si8442-B,-C, V
11
12
11
11
DD1
DD2
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8440-C, V
Si8440-C, V
Si8441-C, V
Si8441-C, V
Si8442-C, V
Si8442-C, V
—
—
—
—
—
—
11
16
13
17
15
15
13
20
16
21
18
18
mA
mA
mA
mA
mA
mA
DD1
DD2
DD1
DD2
DD1
DD2
10
Rev. 0.51
Si8440/41/42/45
Table 3. Electrical Characteristics (Continued)
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si844x-A
Maximum Data Rate
Minimum Pulse Width
0
—
—
40
—
1
1000
75
Mbps
ns
—
25
—
1
Propagation Delay
t
,t
ns
PHL PLH
Pulse Width Distortion
PWD
30
ns
1
|t
- t
|
PLH PHL
2
2
2
Propagation Delay Skew
t
—
—
—
—
50
40
ns
ns
PSK
t
PSKCD/OD
3
Channel-Channel Skew
Si844x-B
Maximum Data Rate
Minimum Pulse Width
0
—
—
20
—
10
100
35
Mbps
ns
—
10
—
1
Propagation Delay
t
, t
ns
PHL PLH
Pulse Width Distortion
PWD
7.5
ns
1
|t
- t
|
PLH PHL
Propagation Delay Skew
t
—
—
—
—
25
5
ns
ns
PSK
t
PSKCD/OD
3
Channel-Channel Skew
Si844x-C
Maximum Data Rate
Minimum Pulse Width
0
—
5
—
—
10
—
100
10
17
7
Mbps
ns
1
Propagation Delay
t
, t
ns
PHL PLH
Pulse Width Distortion
PWD
—
ns
1
|t
- t
|
PLH PHL
Propagation Delay Skew
t
—
—
—
—
12
4
ns
ns
PSK
t
PSKCD/OD
3
Channel-Channel Skew
Rev. 0.51
11
Si8440/41/42/45
Table 3. Electrical Characteristics (Continued)
(VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
For All Models
Output Rise Time
Output Fall Time
C1 = 15 pF
C1 = 15 pF
—
—
25
2
2
—
—
—
ns
ns
Common Mode Transient
Immunity at Logic Low Output
CM
30
kV/µs
L
4
Common Mode Transient
Immunity at Logic High Output
CM
25
30
—
kV/µs
H
4
Enable to Data Valid
t
t
—
—
—
5
5
3
—
—
—
ns
ns
µs
en1
Enable to Data Tri-State
en2
5
Start-up Time
t
SU
Notes:
1. tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling
edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the
50% level of the rising edge of the VOx signal.
2. tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any
two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is
the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of
the isolation barrier.
4. CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is
the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range
over which the common mode is slewed.
5. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 0.51
Si8440/41/42/45
Table 4. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
–40
Typ
25
25
—
Max
125
100
5.5
Unit
ºC
ºC
V
Ambient Operating Temperature*
T
100 Mbps, 15 pF, 5 V
150 Mbps, 15 pF, 5 V
A
0
Supply Voltage
V
2.375
2.375
DD1
DD2
V
—
5.5
V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
—
Max
150
125
6
Unit
ºC
ºC
V
Storage Temperature
Ambient Temperature Under Bias
Supply Voltage
T
STG
T
A
V
, V
DD2
DD1
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
O
Output Current Drive Channel
Lead Solder Temperature (10s)
Maximum Isolation Voltage
L
10
mA
ºC
—
260
—
4000
V
DC
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 6. Package Characteristics
Parameter
Symbol
Test Condition
Min
—
Typ
Max Unit
1
12
Resistance (Input-Output)
R
10
—
—
—
—
Ω
pF
IO
1
Capacitance (Input-Output)
C
f = 1 MHz
—
1.4
4.0
45
IO
2
Input Capacitance
C
—
pF
I
IC Junction-to-Case Thermal Resistance
θ
Thermocouple located
at center of package
—
ºC/W
JC
IC Junction-to-Air Thermal Resistance
θ
—
—
107
—
—
ºC/W
mW
JA
3
Device Power Dissipation
P
250
D
Notes:
1. Device considered a 2-terminal device; Pins 1– 8 shorted together and pins 9–16 shorted together.
2. Input capacitance is from any input data pin to ground.
3. The Si8440-C-IS is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 0.51
13
Si8440/41/42/45
Table 7. Regulatory Information
The Si84xx have been approved by the organizations listed below.
1
2
CSA
UL
VDE
Recognized under 1577 component Approved under CSA Component
Certified according to DIN EN
1
recognition program
Acceptance Notice #5A
60747-5-2 (VDE 0884 Part 2): 2003-
2
01
Basic insulation, 2500 V RMS isola- Reinforced insulation per CSA
Basic insulation, 560 V peak
tion voltage
60950-1-03 and IEC 60950-1,
Maximum Working Voltage:
Basic 477 V
(675 V )
pk
RMS
Reinforced 130 V
(183 V )
pk
RMS
File E257455
File 2500035643
File 5006301-4880-0001
Notes:
1. In accordance with UL1577, each Si84xx is proof tested by applying an insulation test voltage > 3000 V RMS for 1
second (current leakage detection limit = 5 µA).
2. In accordance with DIN EN 60747-5-2, each Si84xx is proof tested by applying an insulation test voltage > 1050 V
peak for 1 second (partial discharge detection limit = 5 pC). A “*” mark branded on the component designates DIN EN
60747-5-2 approval.
Table 8. Insulation and Safety-related Specifications
Parameter
Symbol
Test Condition
Value
Unit
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
1 minute duration
2500
V
RMS
L(IO1) Measured from input terminals to out- 7.7 min
put terminals, shortest distance
through air
mm
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
L(IO2) Measured from input terminals to out-
put terminals, shortest distance path
along body
8.1
mm
Insulation distance through insulation
0.017
min
mm
V
Tracking Resistance (Comparative Tracking
Index)
CTI
DIN IEC 112/VDE 0303 Part 1
>175
Basic Isolation Group
Material Group
IIIa
(DIN VDE 0110, 1/89, Table 1)
14
Rev. 0.51
Si8440/41/42/45
Table 9. DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics
Description
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltages < 150 V
For Rated Mains Voltages < 300 V
For Rated Mains Voltages < 400 V
I-IV
I-III
I-II
RMS
RMS
RMS
Climatic Classification
40/125/21
2
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b1
V
560
V
IORM
PEAK
PEAK
V
1050
V
PR
(V
x 1.875 = V , 100% Production Test, t = 1 sec, Partial Dis-
IORM
PR m
charge < 5 pC)
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1
V
(V
x 1.6 = V , t = 60 sec, Partial Discharge < 5 pC)
896
V
PR
TR
IORM
PR
m
PEAK
After Input and/or Safety Test Subgroup 2/3
(V x 1.2 = V , t = 60 sec, Partial Discharge < 5 pC)
672
V
V
IORM
PR
m
PEAK
PEAK
Highest Allowable Overvoltage (Transient Overvoltage, t = 10 sec)
V
4000
TR
Safety-Limiting Values (Maximum value allowed in the event of a failure;
also see the thermal derating curve, Figure 3)
Case Temperature
T
150
210
ºC
mA
S
Safety input, output, or supply current
I
S
9
Insulation Resistance at T , V = 500 V
R
S
>10
Ω
S
IO
Note: This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is
ensured by protective circuits.
200
175
162
150
2.75 V
125
100
75
5.5 V
3.6 V
50
25
0
0
50
100
150
200
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. 0.51
15
Si8440/41/42/45
Table 10. Si84xx Truth Table (Positive Logic)
1
Vix
ENx
VDDo
Vox
Comments
VDDi State
1
2
1
1
Input
Input
State
Output
3
3
4
H
L
H or NC
H or NC
L
Powered
Powered
Powered
Powered
Powered
H
L
Enabled, normal operation.
Powered
Powered
X
X
Hi-Z
L
Disabled
3
5
H or NC Unpowered
Output returns to input state within 1mS of VDDi
power.
X
X
L
Unpowered Powered
Powered Unpowered
Hi-Z
L
Disabled
X
Output returns to input state within 1µS of VDDo
power if ENx is H or NC. Outputs return to Hi-Z within
8 ns of VDDo if ENx is L.
Notes:
1. Vix and Vox are the respective input and output terminals of a given isolator channel (e.g., channel A1, A2, A3, A4, B1,
B2, B3, B4). ENx is the enable control input located on the same side as the Vox output terminal. VDDi and VDDo are
the power supplies on the input and output side respectively.
2. It is recommended that the enable inputs be connected to an external logic high or low level when the Si84xx is
operating in noisy environments.
3. No Connect (NC) replaces EN1 on Si8440/45. No Connect replaces EN2 on the Si8445. No Connects are not internally
connected and can be left floating, tied to VDD, or tied to GND.
4. "Powered" state is defined as 2.375 V < VDD < 5.5 V.
5. "Unpowered" state is defined as VDD = 0 V.
16
Rev. 0.51
Si8440/41/42/45
2. Typical Performance Characteristics
15
20
18
16
14
12
10
13
5V
5V
11
3.3V
2.5V
3.3V
9
7
2.5V
5
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Data Rate (Mbps)
Data Rate (Mbps)
Figure 4. Si8440/45 Typical VDD1 Supply
Current vs. Data Rate 5, 3.3, and 2.5 V
Operation
Figure 6. Si8441 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
30
30
5V
5V
25
20
15
10
5
25
3.3V
3.3V
20
15
2.5V
2.5V
10
5
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Data Rate (Mbps)
Data Rate (Mbps)
Figure 5. Si8440/45 Typical VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.5 V
Operation (15 pF Load)
Figure 7. Si8441 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
(15 pF Load)
30
25
5V
20
3.3V
15
2.5V
10
5
0
10
20
30
40
50
60
70
80
90
100
Data Rate (Mbps)
Figure 8. Si8442 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.5 V
Operation (15 pF Load)
Rev. 0.51
17
Si8440/41/42/45
10
9
8
Falling Edge
7
6
5
Rising Edge
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 9. Propagation Delay
vs. Temperature 5 V Operation
10
9
Rising Edge
8
Falling Edge
7
6
5
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 10. Propagation Delay
vs. Temperature 3.3 V Operation
15
13
11
9
Rising Edge
Falling Edge
7
5
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 11. Propagation Delay
vs. Temperature 2.5 V Operation
18
Rev. 0.51
Si8440/41/42/45
3. Application Information
3.1. Theory of Operation
The operation of an Si8440 channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si8440 channel is shown in
Figure 12. A channel consists of an RF transmitter and receiver separated by a transformer.
Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying and
applies the resulting waveform to the primary of the transformer. The receiver contains a demodulator that decodes
the input state according to its RF energy content and applies the result to output B via the output driver.
TRANSMITTER
RF
OSCILLATOR
RECEIVER
MODULATOR
DEMODULATOR
A
B
Figure 12. Simplified Channel Diagram
3.2. Eye Diagram
Figure 13 illustrates an eye-diagram taken on an Si8440. The test used an Anritsu (MP1763C) Pulse Pattern
Generator for the data source. The output of the generator's clock and data from an Si8440 were captured on an
oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The
results also show that very low pulse width distortion and very little jitter were exhibited.
Figure 13. Eye Diagram
Rev. 0.51
19
Si8440/41/42/45
4. Layout Recommendations
Dielectric isolation is a set of specifications produced by the safety regulatory agencies from around the world that
describes the physical construction of electrical equipment that derives power from a high-voltage power system
such as 100–240 V systems or industrial power systems. The dielectric test (or HIPOT test) given in the safety
AC
specifications places a very high voltage between the input power pins of a product and the user circuits and the
user touchable surfaces of the product. For the IEC relating to products deriving their power from the 220–240 V
power grids, the test voltage is 2500 V (or 3750 V —the peak equivalent voltage).
AC
DC
There are two terms described in the safety specifications:
ꢀ Creepage—the distance along the insulating surface an arc may travel.
ꢀ Clearance—the distance through the shortest path through air that an arc may travel.
Figure 14 illustrates the accepted method of providing the proper creepage distance along the surface. For a
220–240 V application, this distance is 8 mm and the wide body SOIC package must be used. There must be no
copper traces within this 8 mm exclusion area, and the surface should have a conformal coating such as solder
resist. The digital isolator chip must straddle this exclusion area.
Figure 14. Creepage Distance
4.1. Supply Bypass
The Si844x requires a 0.1 µF bypass capacitor between V
should be placed as close as possible to the package.
and GND1 and V
and GND2. The capacitor
DD1
DD2
4.2. Input and Output Characteristics
The Si844x inputs and outputs are standard CMOS drivers/receivers.
20
Rev. 0.51
Si8440/41/42/45
4.3. Enable Inputs
Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic
operation is summarized for each isolator product in Table 11. These inputs are internally pulled-up to local VDD by
a 9 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To
minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are
unused, it is recommended they be connected to an external logic level, especially if the Si84xx is operating in a
noisy environment.
Table 11. Enable Input Truth Table
P/N
EN1
—
—
H
L
EN2
H
L
Operation
Outputs B1, B2, B3, B4 are enabled.
Si8440
Outputs B1, B2, B3, B4 are disabled and in high impedance state.
Output A4 enabled.
Si8441
Si8442
Si8445
x
x
Output A4 disabled and in high impedance state.
Outputs B1, B2, B3 are enabled.
x
H
L
x
Outputs B1, B2, B3 are disabled and in high impedance state.
Outputs A3 and A4 are enabled.
H
L
x
x
Outputs A3 and A4 are disabled and in high impedance state.
Outputs B1 and B2 are enabled.
x
H
L
x
Outputs B1 and B2 are disabled and in high impedance state.
Outputs B1, B2, B3, B4 are enabled.
—
—
Rev. 0.51
21
Si8440/41/42/45
4.4. RF Immunity and Common Mode Transient Immunity
The Si8440 family has very high common mode transient immunity while transmitting data. This is typically
measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements
show no failures up to 30 kV/µs. During a high surge event the output may glitch low for up to 20–30 ns, but the
output corrects immediately after the surge event.
The Si844x family passes the industrial requirements of CISPR24 for RF immunity of 3 V/m using an unshielded
evaluation board. As shown in Figure 15, the isolated ground planes form a parasitic dipole antenna, while
Figure 16 shows the RMS common mode voltage versus frequency above which the Si844x becomes susceptible
to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage below the
envelope specified in Figure 16. The PCB should be laid-out to not act as an efficient antenna for the RF frequency
of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or
otherwise shielded.
GND1
GND2
Isolator
Dipole
Antenna
Figure 15. Dipole Antenna
5
4
3
2
1
0
500
1000
Frequency (MHz)
1500
2000
Figure 16. RMS Common Mode Voltage vs. Frequency
22
Rev. 0.51
Si8440/41/42/45
4.5. RF Radiated Emissions
The Si8440 family uses a RF carrier frequency of approximately 2.1 GHz. This will result in a small amount of
radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but due to a small
amount of RF energy driving the isolated ground planes which can act as a dipole antenna.
The unshielded Si8440 evaluation board passes FCC requirements. Table 12 shows measured emissions
compared to FCC requirements.
Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less
efficient antenna.
Table 12. Radiated Emissions
Compared
Frequency Measured
FCC Spec
(dBµV/m)
to Spec
(dB)
(GHz)
(dBµV/m)
2.094
2.168
4.210
4.337
6.315
6.505
8.672
70.0
68.3
61.9
60.7
58.3
60.7
45.6
74.0
74.0
74.0
74.0
74.0
74.0
74.0
–4.0
–5.7
–12.1
–13.3
–15.7
–13.3
–28.4
Rev. 0.51
23
Si8440/41/42/45
5. Pin Descriptions
VDD1
VDD2
GND2
B1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
A1
A2
B2
B3
A3
A4
B4
EN1/NC
EN2/NC
GND2
GND1
Top View
Wide Body SOIC
Name
SOIC-16 Pin#
Type
Description
V
1
2
Supply
Ground
Side 1 power supply.
DD1
GND1
A1
Side 1 ground.
3
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital Input
Ground
Side 1 digital input.
A2
4
Side 1 digital input.
A3
5
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 active high enable. NC on Si8440/45.
Side 1 ground.
A4
6
EN1/NC*
GND1
GND2
EN2/NC*
B4
7
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Input
Digital I/O
Digital I/O
Side 2 active high enable. NC on Si8445.
Side 2 digital input or output.
Side 2 digital input or output.
B3
B2
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B1
GND2
Ground
Supply
Side 2 ground.
V
Side 2 power supply.
DD2
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
24
Rev. 0.51
Si8440/41/42/45
6. Ordering Guide
Ordering Part
Number
Number of
Number of Inputs MaximumData
Temperature
Package
Type
Inputs V
V
Side
Rate
DD1
DD2
Side
Si8440-A-IS
Si8440-B-IS
Si8440-C-IS
Si8441-A-IS
Si8441-B-IS
Si8441-C-IS
Si8442-A-IS
Si8442-B-IS
Si8442-C-IS
Si8445-B-IS
4
4
4
3
3
3
2
2
2
4
0
1
10
150
1
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
SOIC-16
0
0
1
1
1
2
2
2
0
10
150
1
10
150
10
Note: All packages are Pb-free and RoHS compliant. Moisture sensitivity level is MSL2 with peak reflow temperature of
260 °C according to the JEDEC industry standard classifications, and peak solder temperature.
Rev. 0.51
25
Si8440/41/42/45
7. Package Outline: Wide Body SOIC
Figure 17 illustrates the package details for the Quad-Channel Digital Isolator. Table 14 lists the values for the
dimensions shown in the illustration.
Figure 17. 16-Pin Wide Body SOIC
Table 14. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
2.65
0.3
A
A1
D
E
E1
b
0.1
10.3 BSC
10.3 BSC
7.5 BSC
0.31
0.51
0.33
c
0.20
e
1.27 BSC
h
0.25
0.4
0°
0.75
1.27
7°
L
θ
26
Rev. 0.51
Si8440/41/42/45
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
ꢀ Added enable high and low typical current
specifications to Tables 1, 2, and 3.
ꢀ Added startup time specifications (with note 5) to
Tables 1, 2, and 3.
ꢀ Rewrote paragraph 1 in section "4.4. RF Immunity
and Common Mode Transient Immunity" on page 22
to reflect 30kV/µs transient immunity capability.
Revision 0.3 to Revision 0.4
ꢀ Added minimum and maximum values to the 5.0 V,
3.3 V, and 2.5 V electrical specifications in Table 1,
Table 2, and Table 3, respectively.
Revision 0.4 to Revision 0.5
ꢀ Updated Block Diagram on page 1.
ꢀ Added Si8445 to various tables.
ꢀ Updated Table 6, “Package Characteristics,” on
page 13.
ꢀ Updated Table 7, “Regulatory Information,” on
page 14.
ꢀ Updated Table 9, “DIN EN 60747-5-2 (VDE 0884
Part 2) Insulation Characteristics,” on page 15.
ꢀ Updated Figure 3, “Thermal Derating Curve,
Dependence of Safety Limiting Values with Case
Temperature per DIN EN 60747-5-2,” on page 15.
ꢀ Added Table 10, “Si84xx Truth Table (Positive
Logic),” on page 16.
ꢀ Added Table 11, “Enable Input Truth Table,” on
page 21.
Revision 0.5 to Revision 0.51
ꢀ Added NC note (Note 3) to Table 10, “Si84xx Truth
Table (Positive Logic),” on page 16.
ꢀ Added NC note (*) to "5. Pin Descriptions" on page
24.
Rev. 0.51
27
Si8440/41/42/45
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28
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