SI8451AB-A-IS1R [SILICON]
Interface Circuit;
| 型号： | SI8451AB-A-IS1R |
| 厂家： | 
SILICON |
| 描述： | Interface Circuit |
| 文件： | 总35页 (文件大小：768K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8450/51/52/55
LOW POWER FIVE-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation
DC to 150 Mbps
Up to 2500 V
isolation
RMS
60-year life at rated working
No start-up initialization required
voltage
Wide Operating Supply Voltage:
Precise timing (typical)
2.70–5.5 V
<10 ns worst case
Ultra-low-power (typical)
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
6 ns minimum pulse width
Transient Immunity 25 kV/µs
5 V Operation:
< 1.6 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps
2.70 V Operation:
Ordering Information:
< 1.4 mA per channel at 1 Mbps
< 4 mA per channel at 100 Mbps
High electromagnetic immunity
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS-compliant packages
SOIC-16 narrow body
See page 28.
Applications
Industrial automation systems
Hybrid electric vehicles
Isolated ADC, DAC
Motor control
Isolated switch mode supplies
Power inverters
Communications systems
Safety Regulatory Approvals
UL 1577 recognized
VDE certification conformity
Up to 2500 VRMS for 1 minute
IEC 60747-5-2
(VDE0884 Part 2)
CSA component notice 5A
approval
IEC 60950-1, 61010-1
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. All products are
safety certified by UL, CSA, and VDE and support withstand voltages
of up to 2.5 kVrms. These devices are available in a 16-pin narrow-
body SOIC package.
Rev. 1.6 4/18
Copyright © 2018 by Silicon Laboratories
Si8450/51/52/55
Si8450/51/52/55
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.1. Enable Pin Causes Outputs to Go Low (Revision A Only) . . . . . . . . . . . . . . . . . . . .25
3.2. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . .25
3.3. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Pin Descriptions (Si8450/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Pin Descriptions (Si8455) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.6
2
Si8450/51/52/55
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
Test Condition
Min
–40
Typ
25
—
Max
125
5.5
Unit
°C
V
T
150 Mbps, 15 pF, 5 V
A
V
2.70
2.70
DD1
DD2
V
—
5.5
V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
—
—
Max
150
125
5.75
6.0
Unit
°C
°C
V
2
Storage Temperature
T
STG
Ambient Temperature Under Bias
T
A
3
Supply Voltage (Revision A)
V
V
, V
, V
DD1
DD1
DD2
DD2
3
Supply Voltage (Revision B)
V
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s)
Notes:
I
10
mA
°C
O
—
260
—
3600
V
RMS
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "6. Ordering Guide" on page 28 for more information.
Rev. 1.6
3
Si8450/51/52/55
Table 3. Electrical Characteristics
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
—
µA
L
1
Output Impedance
Z
85
O
Enable Input High Current
Enable Input Low Current
I
V
= V
IH
2.0
2.0
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
DC Supply Current (All inputs 0 V or at Supply)
Si8450Ax, Bx, Si8455Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.6
2.9
7.0
3.1
2.4
4.4
10.5
4.7
DD1
DD2
DD1
DD2
mA
mA
mA
Si8451Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
DD1
DD2
DD1
DD2
Si8452Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
V
V
—
—
4.3
3.5
6.5
5.3
mA
mA
mA
DD1
DD2
Si8451Ax, Bx
V
V
—
—
4.1
4.0
6.2
6.0
DD1
DD2
Si8452Ax, Bx
V
V
—
—
4.1
4.0
6.2
6.0
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.6
Si8450/51/52/55
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
4.3
4.8
6.5
6.7
mA
mA
mA
DD1
DD2
Si8451Bx
V
V
—
—
4.4
5.0
6.2
7.0
DD1
DD2
Si8452Bx
V
V
—
—
4.6
4.8
6.4
6.7
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
V
V
—
—
4.6
24
6.9
30
mA
mA
mA
DD1
DD2
Si8451Bx
V
V
—
—
8.6
20.4
10.8
25.5
DD1
DD2
Si8452Bx
V
V
—
—
12.6
16.5
15.8
20.6
DD1
DD2
Timing Characteristics
Si845xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
—
—
1.0
250
35
Mbps
ns
—
—
—
t
, t
See Figure 2
See Figure 2
ns
PHL PLH
PWD
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Notes:
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.6
5
Si8450/51/52/55
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si845xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
6.0
9.5
2.5
Mbps
ns
—
3.0
—
t
, t
See Figure 2
See Figure 2
6.0
1.5
ns
PHL PLH
Pulse Width Distortion
PWD
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.8
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
—
3.8
2.8
25
5.0
3.7
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
Immunity
CMTI
V = V or 0 V
kV/µs
I
DD
3
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
5.0
7.0
15
8.0
9.2
40
ns
ns
µs
en1
3
Enable to Data Tri-State
en2
3,4
Start-up Time
t
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.6
Si8450/51/52/55
ENABLE
OUTPUTS
ten1
ten2
Figure 1. ENABLE Timing Diagram
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 2. Propagation Delay Timing
Rev. 1.6
7
Si8450/51/52/55
Table 4. Electrical Characteristics
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
3.1
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
—
µA
L
1
Output Impedance
Z
85
O
Enable Input High Current
Enable Input Low Current
I
V
= V
IH
2.0
2.0
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8450Ax, Bx, Si8455Bx
V
V
V
V
All inputs 0 dc
All inputs 0 dc
All inputs 1 dc
All inputs 1 dc
—
—
—
—
1.6
2.9
7.0
3.1
2.4
4.4
10.5
4.7
DD1
DD2
DD1
DD2
mA
mA
mA
Si8451Ax, Bx
V
V
V
V
All inputs 0 dc
All inputs 0 dc
All inputs 1 dc
All inputs 1 dc
—
—
—
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
DD1
DD2
DD1
DD2
Si8452Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
V
V
—
—
4.3
3.5
6.5
5.3
mA
mA
mA
DD1
DD2
Si8451Ax, Bx
V
V
—
—
4.1
4.0
6.2
6.0
DD1
DD2
Si8452Ax, Bx
V
V
—
—
4.1
4.0
6.2
6.0
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.6
Si8450/51/52/55
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
4.3
4.8
6.5
6.7
mA
mA
mA
DD1
DD2
Si8451Bx
V
V
—
—
4.4
5.0
6.2
7.0
DD1
DD2
Si8452Bx
V
V
—
—
4.6
4.8
6.4
6.7
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
V
V
—
—
4.4
16.8
6.6
21
mA
mA
mA
DD1
DD2
Si8451Bx
V
V
—
—
6.9
14.5
8.6
18.1
DD1
DD2
Si8452Bx
V
V
—
—
9.5
12
11.9
15
DD1
DD2
Timing Characteristics
Si845xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
—
—
1.0
250
35
Mbps
ns
—
—
—
t
,t
See Figure 2
See Figure 2
ns
PHL PLH
PWD
25
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Notes:
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.6
9
Si8450/51/52/55
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si845xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
6.0
9.5
2.5
Mbps
ns
—
3.0
—
t
, t
See Figure 2
See Figure 2
6.0
1.5
ns
PHL PLH
Pulse Width Distortion
PWD
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.8
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
—
4.3
3.0
25
6.1
4.3
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
Immunity
CMTI
V = V or 0 V
kV/µs
I
DD
3
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
5.0
7.0
15
8.0
9.2
40
ns
ns
µs
en1
3
Enable to Data Tri-State
en2
3,4
Start-up Time
t
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.6
Si8450/51/52/55
Table 5. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Symbol
Test Condition
Min
2.0
—
Typ
—
Max
—
Unit
V
V
IH
V
—
0.8
—
V
IL
V
l
= –4 mA
V
,V
– 0.4
2.3
0.2
—
V
OH
OH
DD1 DD2
V
I
= 4 mA
—
0.4
±10
—
V
OL
OL
I
—
—
—
—
µA
L
2
Output Impedance
Z
85
O
Enable Input High Current
Enable Input Low Current
I
V
= V
IH
2.0
2.0
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8450Ax, Bx, Si8455Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.6
2.9
7.0
3.1
2.4
4.4
10.5
4.7
DD1
DD2
DD1
DD2
mA
mA
mA
Si8451Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
DD1
DD2
DD1
DD2
Si8452Ax, Bx
V
V
V
V
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
DD1
DD2
DD1
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
V
V
—
—
4.3
3.5
6.5
5.3
mA
mA
mA
DD1
DD2
Si8451Ax, Bx
V
V
—
—
4.1
4.0
6.2
6.0
DD1
DD2
Si8452Ax, Bx
V
V
—
—
4.1
4.0
6.2
6.0
DD1
DD2
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.6
11
Si8450/51/52/55
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
4.3
4.8
6.5
6.7
mA
mA
mA
DD1
DD2
Si8451Bx
V
V
—
—
4.4
5.0
6.2
7.0
DD1
DD2
Si8452Bx
V
V
—
—
4.6
4.8
6.4
6.7
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
V
V
—
—
4.3
13.3
6.5
16.6
mA
mA
mA
DD1
DD2
Si8451Bx
V
V
—
—
6.2
11.7
7.8
14.6
DD1
DD2
Si8452Bx
V
V
—
—
8.0
9.9
10
12.4
DD1
DD2
Timing Characteristics
Si845xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
—
—
1.0
250
35
Mbps
ns
—
—
—
t
,t
See Figure 2
See Figure 2
ns
PHL PLH
PWD
25
ns
|t
- t
|
PLH PHL
3
Propagation Delay Skew
Channel-Channel Skew
Notes:
t
—
—
—
—
40
35
ns
ns
PSK(P-P)
t
PSK
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.6
Si8450/51/52/55
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si845xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
6.0
9.5
2.5
Mbps
ns
—
3.0
—
t
, t
See Figure 2
See Figure 2
6.0
1.5
ns
PHL PLH
Pulse Width Distortion
PWD
ns
|t
- t
|
PLH PHL
3
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.5
3.0
1.8
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
—
4.8
3.2
25
6.5
4.6
—
ns
ns
r
L
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Common Mode Transient
Immunity
CMTI
V = V or 0 V
kV/µs
I
DD
4
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
5.0
7.0
15
8.0
9.2
40
ns
ns
µs
en1
4
Enable to Data Tri-State
en2
4,5
Start-up Time
t
SU
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.6
13
Si8450/51/52/55
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 V
60950-1: Up to 130 V
VDE
reinforced insulation working voltage; up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
basic insulation working voltage.
RMS
RMS
RMS
RMS
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 V
for basic insulation working voltage.
peak
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 V isolation voltage for basic insulation.
RMS
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "6. Ordering Guide" on page 28.
Table 7. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
Unit
NB SOIC-16
4.9
1
Nominal Air Gap (Clearance)
L(IO1)
L(IO2)
mm
mm
mm
1
Nominal External Tracking (Creepage)
4.01
Minimum Internal Gap (Internal Clearance)
0.008
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
V
RMS
0.019
mm
Erosion Depth
2
12
Resistance (Input-Output)
R
10
IO
2
Capacitance (Input-Output)
C
2.0
4.0
pF
pF
IO
3
Input Capacitance
C
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in "7. Package Outline:
16-Pin Narrow Body SOIC" on page 30. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the
NB SOIC-16 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA
certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
14
Rev. 1.6
Si8450/51/52/55
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Test Condition
Specification
Basic Isolation Group
Material Group
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-III
I-II
I-II
RMS
RMS
RMS
RMS
Installation Classification
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter
Symbol
Test Condition
Characteristic Unit
V
560
V peak
V peak
Maximum Working Insulation Voltage
Input to Output Test Voltage
IORM
Method b1
(V
x 1.875 = V , 100%
IORM
PR
V
1050
PR
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
V
t = 60 sec
4000
2
V peak
Transient Overvoltage
IOTM
Pollution Degree (DIN VDE 0110, Table 1)
Insulation Resistance at T , V = 500 V
9
R
>10
S
S
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Max
Unit
Parameter
Symbol
Test Condition
Min Typ
NB SOIC-16
150
Case Temperature
T
I
—
—
—
—
°C
S
Safety input, output, or
supply current
= 105 °C/W (NB SOIC-16),
JA
215
mA
S
V = 5.5 V, T = 150 °C, T = 25 °C
I
J
A
Device Power Dissipa-
tion
P
—
—
415
mW
D
2
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 3.
2. The Si845x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.6
15
Si8450/51/52/55
Table 11. Thermal Characteristics
Typ
NB SOIC-16
105
Parameter
Symbol
Unit
IC Junction-to-Air Thermal Resistance
°C/W
JA
500
430
V
DD1, VDD2 = 2.70 V
400
300
200
100
0
360
215
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 3. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
16
Rev. 1.6
Si8450/51/52/55
2. Functional Description
2.1. Theory of Operation
The operation of an Si845x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si845x channel is shown in
Figure 4.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 5 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 5. Modulation Scheme
Rev. 1.6
17
Si8450/51/52/55
2.2. Eye Diagram
Figure 6 illustrates an eye-diagram taken on an Si8450. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8450 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 6. Eye Diagram
18
Rev. 1.6
Si8450/51/52/55
2.3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an
overview of the output states when the Enable pins are active.
Table 12. Si845x Logic Operation Table
1,2
V
EN
VDDI
VDDO
Comments
I
V Output
O
1,2,3,4
1,5,6
1,5,6
1,2
Input
State
State
Input
H
L
H or NC
H or NC
L
P
P
P
P
P
P
H
L
Enabled, normal operation.
7
8
X
P
Hi-Z or L
L
Disabled.
7
X
H or NC
UP
Upon transition of VDDI from unpowered to pow-
ered, V returns to the same state as V in less
O
I
than 1 µs.
7
8
X
L
UP
P
P
Hi-Z or L
Disabled.
7
7
X
X
UP
Undetermined Upon transition of VDDO from unpowered to pow-
ered, V returns to the same state as V within
O
I
1 µs, if EN is in either the H or NC state. Upon tran-
sition of VDDO from unpowered to powered, V
returns to Hi-Z within 1 µs if EN is L.
O
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si845x is
operating in noisy environments.
4. No Connect (NC) replaces EN1 on Si8450. No Connects are not internally connected and can be left floating, tied to
VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
(EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 25 for more details.
Rev. 1.6
19
Si8450/51/52/55
Table 13. Enable Input Truth Table1
Operation
1,2
1,2
P/N
EN1
EN2
H
Si8450
—
—
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
L
Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance
3
state.
Si8451
Si8452
Si8455
H
L
X
X
H
L
Output A5 enabled and follow input state.
3
Output A5 disabled and Logic Low or in high impedance state.
X
X
H
L
Outputs B1, B2, B3, B4 are enabled and follow input state.
Outputs B1, B2, B3, B4 are disabled and Logic Low or in high impedance state.
Outputs A4 and A5 are enabled and follow input state.
3
X
X
H
L
3
Outputs A4 and A5 are disabled and Logic Low or in high impedance state.
X
X
—
Outputs B1, B2, B3 are enabled and follow input state.
3
Outputs B1, B2, B3 are disabled and Logic Low or in high impedance state.
—
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are
internally pulled-up to local VDD by a 3 µA current source allowing them to be connected to an external logic level (high
or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If
EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si845x is
operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
(EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 25 for more details.
20
Rev. 1.6
Si8450/51/52/55
2.4. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 14 and Table 7 on page 14 detail the
working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, etc.)
requirements before starting any design that uses a digital isolator.
The following sections detail the recommended bypass and decoupling components necessary to ensure robust
overall performance and reliability for systems using the Si84xx digital isolators.
2.4.1. Supply Bypass
Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically
quiet environments. However, digital isolators are commonly used in hazardous environments with excessively
noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass
capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as
close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is
recommended that the designer add 50 to 100 resistors in series with the VDD supply voltage source and 50 to
300 resistors in series with the digital inputs/outputs (see Figure 7). For more details, see "3. Errata and Design
Migration Guidelines" on page 25.
All components upstream or downstream of the isolator should be properly decoupled as well. If these components
are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing
damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300 resistors protect
the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are
exceeded). Functional operation should be restricted to the conditions specified in Table 1, “Recommended
Operating Conditions,” on page 3.
2.4.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
2.4.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces. The series termination resistor values should be scaled appropriately while keeping in
mind the recommendations described in “2.4.1. Supply Bypass” above.
V Source 2
R2 (50 – 100 )
V Source 1
R1 (50 – 100 )
C1
VDD1
A1
VDD2
B1
C4
50 – 300
50 – 300
0.1 F
0.1 F
C2
C3
Input/Output
Input/Output
1 F
1 F
Ax
Bx
50 – 300
50 – 300
GND1
GND2
Figure 7. Recommended Bypass Components for the Si84xx Digital Isolator Family
Rev. 1.6
21
Si8450/51/52/55
2.5. Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 3, 4, and 5 for actual specification limits.
35
30
25
20
15
10
5
35
30
25
20
15
10
5
5V
5V
3.3V
3.3V
2.70V
2.70V
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 11. Si8450/55 Typical VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Figure 8. Si8450/55 Typical VDD1 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation
35
35
30
5V
25
30
25
20
15
10
5
5V
3.3V
20
3.3V
15
2.70V
10
5
2.70V
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 12. Si8451 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 9. Si8451 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
35
30
35
30
25
5V
25
20
15
10
5
3.3V
5V
20
15
10
5
3.3V
2.70V
2.70V
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 13. Si8452 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 10. Si8452 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Rev. 1.6
22
Si8450/51/52/55
10
Falling Edge
9
8
7
6
5
Rising Edge
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 14. Propagation Delay
vs. Temperature
23
Rev. 1.6
Si8450/51/52/55
Figure 15. Si84xx Time-Dependent Dielectric Breakdown
24
Rev. 1.6
Si8450/51/52/55
3. Errata and Design Migration Guidelines
The following errata apply to Revision A devices only. See "6. Ordering Guide" on page 28 for more details. No
errata exist for Revision B devices.
3.1. Enable Pin Causes Outputs to Go Low (Revision A Only)
When using the enable pin (EN1, EN2) function on the 5-channel (Si8450/1/2) isolators, the corresponding output
pin states (pin = An, Bn, where n can be 1…5) are driven to a logic low (to ground) when the enable pin is disabled
(EN1 or EN2 = 0). This functionality is different from the legacy 3-channel (Si8430/1) and 4-channel (Si8440/1/2)
isolators. On those devices, the isolator outputs go into a high-impedance state (Hi-Z) when the enable pin is
disabled (EN1 = 0 or EN2 = 0).
3.1.1. Resolution
The enable pin functionality causing the outputs to go low is supported in production for Revision A of the Si845x
devices. Revision B corrects the enable pin functionality (i.e., the outputs will go into the high-impedance state to
match the legacy isolator products). Refer to the Ordering Guide sections of the data sheet(s) for more information.
3.2. Power Supply Bypass Capacitors (Revision A and Revision B)
When using the Si845x isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on
both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V
supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins
(VDD1, VDD2) of the isolator device.
3.2.1. Resolution
For recommendations on resolving this issue, see "2.4.1. Supply Bypass" on page 21. Additionally, refer to "6.
Ordering Guide" on page 28 for current ordering information.
3.3. Latch Up Immunity (Revision A Only)
Latch up immunity generally exceeds ± 200 mA per pin. Exceptions: Certain pins provide < 100 mA of latch-up
immunity. To increase latch-up immunity on these pins, 100 of equivalent resistance must be included in series
with all of the pins listed in Table 14. The 100 equivalent resistance can be comprised of the source driver's
output resistance and a series termination resistor.
3.3.1. Resolution
This issue has been corrected with Revision B of the device. Refer to the Ordering Guide for more information.
Table 14. Affected Ordering Part Numbers (Revision A Only)
Device
Affected Ordering Part Numbers*
Pin#
Name
Pin Type
Revision
2
6
A1
A5
Input
Input or Output
Input
SI8450SV-A-IS/IS1, SI8451SV-A-IS/IS1,
SI8452SV-A-IS/IS1
A
10
14
2
EN2
B2
Output
A1
Input
SI8455SV-A-IS/IS1
A
6
A5
Input
14
B2
Output
*Note: SV = Speed Grade/Isolation Rating (AA, AB, BA, BB).
Rev. 1.6
25
Si8450/51/52/55
4. Pin Descriptions (Si8450/51/52)
VDD1
VDD2
B1
VDD1
A1
VDD1
VDD2
B1
VDD2
B1
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A1
A2
A1
A2
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B2
B2
A2
B2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A3
A4
B3
A3
A4
A5
B3
A3
B3
RF
XMITR
RF
RCVR
RF
RCVR
RF
RF
XMITR
RF
RCVR
B4
B4
A4
B4
XMITR
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
A5
B5
B5
A5
B5
EN2/NC
GND2
NC
EN2
GND2
EN2
EN1
EN1
GND1
GND1
GND1
GND2
Si8450
Si8452
Si8451
Name
SOIC-16 Pin#
Type
Supply
Description
V
1
2
Side 1 power supply.
Side 1 digital input.
DD1
A1
A2
Digital Input
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital Input
Ground
3
Side 1 digital input.
A3
4
Side 1 digital input.
A4
5
Side 1 digital input or output.
Side 1 digital input or output.
A5
6
EN1/NC*
GND1
GND2
EN2
B5
7
Side 1 active high enable. NC on Si8450.
Side 1 ground.
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Input
Digital I/O
Digital I/O
Side 2 active high enable.
Side 2 digital input or output.
Side 2 digital input or output.
B4
B3
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B2
B1
V
Supply
Side 2 power supply.
DD2
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
26
Rev. 1.6
Si8450/51/52/55
5. Pin Descriptions (Si8455)
VDD1
VDD2
GND2
B1
GND1
A1
I
s
o
l
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A2
B2
a
t
RF
XMITR
RF
RCVR
B3
A3
i
o
n
RF
XMITR
RF
RCVR
A4
B4
RF
XMITR
RF
RCVR
A5
B5
GND1
GND2
Si8455
Name
SOIC-16 Pin#
Type
Description*
V
1
2
Supply
Ground
Side 1 power supply.
Side 1 ground.
DD1
GND1
A1
3
Digital Input
Digital Input
Digital Input
Digital Input
Digital Input
Ground
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
Side 1 ground.
A2
4
A3
5
A4
6
A5
7
GND1
GND2
B5
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B4
B3
B2
B1
GND2
Ground
Supply
Side 2 ground.
V
Side 2 power supply.
DD2
*Note: For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15
must also be connected to external ground.
Rev. 1.6
27
Si8450/51/52/55
6. Ordering Guide
These devices are not recommended for new designs. Please see the Si865x data sheet for replacement options.
Table 15. Ordering Guide for Valid OPNs1
Ordering Part
Number
Alternative Part Number of
Number of
Maximum Isolation Package Type
Number
(APN)
Inputs VDD1 Inputs VDD2 Data Rate
Rating
(OPN)
Side
Side
(Mbps)
2
Revision B Devices
Si8450AA-B-IS1
Si8450BA-B-IS1
Si8451AA-B-IS1
Si8451BA-B-IS1
Si8452AA-B-IS1
Si8452BA-B-IS1
Si8455BA-B-IS1
Si8450AB-B-IS1
Si8450BB-B-IS1
Si8451AB-B-IS1
Si8451BB-B-IS1
Si8452AB-B-IS1
Si8452BB-B-IS1
Si8650AB-B-IS1
Si8650BB-B-IS1
Si8651AB-B-IS1
Si8651BB-B-IS1
Si8652AB-B-IS1
Si8652BB-B-IS1
Si8655BB-B-IS1
Si8650AB-B-IS1
Si8650BB-B-IS1
Si8651AB-B-IS1
Si8651BB-B-IS1
Si8652AB-B-IS1
Si8652BB-B-IS1
Si8655BB-B-IS1
5
5
4
4
3
3
5
5
5
4
4
3
3
5
0
0
1
1
2
2
0
0
0
1
1
2
2
0
1
150
1
150
1
1 kVrms
NB SOIC-16
150
150
1
150
1
150
1
2.5 kVrms NB SOIC-16
150
150
Si8455BB-B-IS1
Notes:
1. All packages are RoHS-compliant.
2. Revision A and Revision B devices are supported for existing designs.
28
Rev. 1.6
Si8450/51/52/55
Table 15. Ordering Guide for Valid OPNs1 (Continued)
Ordering Part
Number
Alternative Part Number of
Number of
Maximum Isolation Package Type
Number
(APN)
Inputs VDD1 Inputs VDD2 Data Rate
Rating
(OPN)
Side
Side
(Mbps)
2
Revision A Devices
Si8450AA-A-IS1
Si8450BA-A-IS1
Si8451AA-A-IS1
Si8451BA-A-IS1
Si8452AA-A-IS1
Si8452BA-A-IS1
Si8455BA-A-IS1
Si8450AB-A-IS1
Si8450BB-A-IS1
Si8451AB-A-IS1
Si8451BB-A-IS1
Si8452AB-A-IS1
Si8452BB-A-IS1
Si8650AB-B-IS1
Si8650BB-B-IS1
Si8651AB-B-IS1
Si8651BB-B-IS1
Si8652AB-B-IS1
Si8652BB-B-IS1
Si8655BB-B-IS1
Si8650AB-B-IS1
Si8650BB-B-IS1
Si8651AB-B-IS1
Si8651BB-B-IS1
Si8652AB-B-IS1
Si8652BB-B-IS1
Si8655BB-B-IS1
5
5
4
4
3
3
5
5
5
4
4
3
3
5
0
0
1
1
2
2
0
0
0
1
1
2
2
0
1
150
1
150
1
1 kVrms
NB SOIC-16
150
150
1
150
1
150
1
2.5 kVrms NB SOIC-16
150
150
Si8455BB-A-IS1
Notes:
1. All packages are RoHS-compliant.
2. Revision A and Revision B devices are supported for existing designs.
Rev. 1.6
29
Si8450/51/52/55
7. Package Outline: 16-Pin Narrow Body SOIC
Figure 16 illustrates the package details for the Si845x in a 16-pin narrow-body SOIC (SO-16). Table 16 lists the
values for the dimensions shown in the illustration.
Figure 16. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 16. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
0.25 BSC
30
Rev. 1.6
Si8450/51/52/55
Table 16. Package Diagram Dimensions (Continued)
Dimension
Min
0.25
0°
Max
0.50
8°
h
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012,
Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.6
31
Si8450/51/52/55
8. Land Pattern: 16-Pin Narrow Body SOIC
Figure 17 illustrates the recommended land pattern details for the Si845x in a 16-pin narrow-body SOIC. Table 17
lists the values for the dimensions shown in the illustration.
Figure 17. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 17. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
32
Rev. 1.6
Si8450/51/52/55
9. Top Marking: 16-Pin Narrow Body SOIC
9.1. 16-Pin Narrow Body SOIC Top Marking
Si84XYSV
YYWWTTTTTT
e3
9.2. Top Marking Explanation
Table 18. 16-Pin Narrow Body SOIC Top Marking Table
Si84 = Isolator product series
XY = Channel Configuration
Base Part Number
Ordering Options
X = # of data channels (5, 4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)*
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV
Line 1 Marking:
(See Ordering Guide for more
information).
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
Line 2 Marking:
Manufacturing Code from Assembly Purchase Order
form.
TTTTTT = Mfg code
Circle = 1.2 mm diameter
“e3” Pb-Free Symbol.
*Note: Si8455 has 0 reverse channels.
Rev. 1.6
33
Si8450/51/52/55
Revision 1.3 to Revision 1.4
DOCUMENT CHANGE LIST
Removed wide-body SOIC-16 package information
Revision 0.1 to Revision 0.2
and references throughout document.
Updated all specs to reflect latest silicon.
Updated "2.4.1. Supply Bypass" on page 21.
Added "3. Errata and Design Migration Guidelines"
Added Figure 7, “Recommended Bypass
Components for the Si84xx Digital Isolator Family,”
on page 21.
on page 25.
Added "9. Top Marking: 16-Pin Narrow Body SOIC"
on page 33.
Updated "3.2. Power Supply Bypass Capacitors
(Revision A and Revision B)" on page 25.
Revision 0.2 to Revision 1.0
Revision 1.4 to Revision 1.5
Updated document to reflect availability of Revision
B silicon.
Updated "6. Ordering Guide" on page 28 to include
new title note and “ Alternative Part Number (APN)”
column.
Updated Tables 3,4, and 5.
Updated all supply currents and channel-channel skew.
Updated Table 2.
Updated absolute maximum supply voltage.
Updated Table 7.
Revision 1.5 to Revision 1.6
Deleted references to MSL ratings throughout
document to eliminate redundancy and maintain
compliance with corporate data sheet format
requirements. The MSL ratings are specified in the
Qualification Report for the product.
Updated clearance and creepage dimensions.
Updated Table 12.
Updated Note 7.
Updated Table 13.
Updated Note 3.
Updated "3. Errata and Design Migration Guidelines"
on page 25.
Updated "6. Ordering Guide" on page 28.
Revision 1.0 to Revision 1.1
Updated Tables 3, 4, and 5.
Updated notes in both tables to reflect output
impedance of 85 .
Updated rise and fall time specifications.
Updated CMTI value.
Revision 1.1 to Revision 1.2
Updated document throughout to include MSL
improvements to MSL2A.
Updated "6. Ordering Guide" on page 28.
Updated Note 1 in ordering guide table to reflect
improvement and compliance to MSL2A moisture
sensitivity level.
Revision 1.2 to Revision 1.3
Updated " Features" on page 1.
Moved Tables 1 and 2 to page 3.
Updated Tables 6, 7, 8, and 9.
Updated Table 12 footnotes.
Added Figure 15, “Si84xx Time-Dependent
Dielectric Breakdown,” on page 24.
Rev. 1.6
34
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