SI8622EC-A-ISR [SILICON]
Analog Circuit, CMOS, PDSO8;
| 型号： | SI8622EC-A-ISR |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, CMOS, PDSO8 光电二极管 |
| 文件： | 总36页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8610/20/21/22
LOW-POWER SINGLE AND DUAL-CHANNEL DIGITAL ISOLATORS
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Selectable fail-safe mode
Default high or low output
(ordering option)
Precise timing (typical)
Wide Operating Supply Voltage
2.5–5.5 V
Up to 5000 VRMS isolation
10 ns propagation delay
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
3.5 mA per channel at 100 Mbps
Schmitt trigger inputs
RoHS-compliant packages
SOIC-16 wide body
SOIC-8 narrow body
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated ADC, DAC
Motor control
Power inverters
Ordering Information:
Isolated switch mode supplies
Communications systems
See page 27.
Safety Regulatory Approvals
UL 1577 recognized
Up to 5000 VRMS for 1 minute
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation
delays of less than 10 ns. Ordering options include a choice of isolation ratings
(3.75 and 5 kV) and a selectable fail-safe operating mode to control the default
output state during power loss. All products >1 kVRMS are safety certified by
UL, CSA, and VDE, and products in wide-body packages support reinforced
insulation withstanding up to 5 kVRMS
.
Rev. 1.1 9/11
Copyright © 2011 by Silicon Laboratories
Si8610/20/21/22
Si8610/20/21/22
2
Rev. 1.1
Si8610/20/21/22
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11.1. 16-Pin Wide Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
12. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
12.1. 8-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
12.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.1
3
Si8610/20/21/22
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
–40
2.5
Typ
25
—
Max
125*
5.5
Unit
°C
V
Ambient Operating Temperature*
T
150 Mbps, 15 pF, 5 V
A
V
DD1
Supply Voltage
V
2.5
—
5.5
V
DD2
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
VDDUV+
VDDUV–
Test Condition
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
V
, V
rising
falling
DD1
DD2
DD2
V
, V
V
DD1
VDD Negative-Going Lockout
Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
VT+
VT–
All inputs rising
1.4
1.0
1.67
1.23
1.9
1.4
V
V
Negative-Going Input
Threshold
All inputs falling
Input Hysteresis
V
0.38
2.0
—
0.44
—
0.50
—
V
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
µA
L
1
Output Impedance
Z
50
O
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.1
Si8610/20/21/22
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Supply Current (All inputs 0 V or at Supply)
Si8610Bx, Ex
V = 0(Bx), 1(Ex)
I
V
V
V
V
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
DD1
DD2
DD1
DD2
V = 0(Bx), 1(Ex)
mA
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8620Bx, Ex
V = 0(Bx), 1(Ex)
I
V
V
V
V
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
DD1
DD2
DD1
DD2
V = 0(Bx), 1(Ex)
mA
mA
mA
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8621Bx, Ex
V = 0(Bx), 1(Ex)
I
V
V
V
V
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
DD1
DD2
DD1
DD2
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8622Bx, Ex
V = 0(Bx), 1(Ex)
I
V
V
V
V
—
—
—
—
2.6
3.3
4.0
4.8
4.2
5.3
6.4
7.7
DD1
DD2
DD1
DD2
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8610Bx, Ex
VDD1
—
—
1.2
0.9
2.0
1.5
mA
mA
mA
mA
VDD2
Si8620Bx, Ex
VDD1
VDD2
—
—
2.1
1.6
3.1
2.4
Si8621Bx, Ex
VDD1
VDD2
—
—
1.9
1.9
2.9
2.9
Si8622Bx, Ex
VDD1
VDD2
—
—
3.4
4.2
5.1
6.2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.1
5
Si8610/20/21/22
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8610Bx, Ex
VDD1
—
—
1.2
1.2
2.0
2.0
mA
mA
mA
mA
VDD2
Si8620Bx, Ex
VDD1
VDD2
—
—
2.1
2.2
3.1
3.3
Si8621Bx, Ex
VDD1
VDD2
—
—
2.2
2.2
3.3
3.3
Si8622Bx, Ex
VDD1
VDD2
—
—
3.7
4.4
5.5
6.7
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8610Bx, Ex
VDD1
VDD2
—
—
1.2
4.8
2.0
6.7
mA
mA
mA
mA
Si8620Bx, Ex
VDD1
VDD2
—
—
2.1
8.9
3.1
12.5
Si8621Bx, Ex
VDD1
VDD2
—
—
5.8
5.8
8.1
8.1
Si8622Bx, Ex
VDD1
VDD2
—
—
7.6
8.2
10.6
11.4
Timing Characteristics
Si861x/2x Bx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
150
5.0
13
Mbps
ns
—
5.0
—
t
, t
See Figure 1
See Figure 1
8.0
0.2
ns
PHL PLH
PWD
4.5
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
Notes:
t
—
—
2.0
0.4
4.5
2.5
ns
ns
PSK(P-P)
t
PSK
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.1
Si8610/20/21/22
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
All Models
Symbol
Test Condition
Min
Typ
Max
Unit
CL = 15 pF
See Figure 1
tr
—
2.5
4.0
ns
Output Rise Time
CL = 15 pF
tf
—
—
35
—
2.5
350
50
4.0
—
ns
ps
Output Fall Time
See Figure 1
Peak Eye Diagram Jitter
tJIT(PK)
CMTI
tSU
See Figure 6
Common Mode Transient
Immunity
Startup Time3
VI = VDD or 0 V
—
kV/µs
µs
15
40
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing
Rev. 1.1
7
Si8610/20/21/22
Table 3. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDDUV+ VDD1, VDD2 rising
VDDUV–
VDDHYS
V
DD1, VDD2 falling
V
VDD Negative-Going Lockout
Hysteresis
mV
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
VHYS
VIH
All inputs rising
1.4
1.67
1.23
0.44
—
1.9
1.4
0.50
—
V
V
All inputs falling
1.0
0.38
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance1
2.0
V
VIL
—
—
0.8
—
V
VOH
VOL
IL
loh = –4 mA
lol = 4 mA
VDD1,VDD2 – 0.4
3.1
0.2
—
V
—
—
—
0.4
±10
—
V
µA
ZO
50
DC Supply Current (All inputs 0 V or at supply)
Si8610Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
VDD2
mA
mA
mA
mA
VDD1
VDD2
Si8620Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
VDD2
VDD1
VDD2
Si8621Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
VDD2
VDD1
VDD2
Si8622Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.6
3.3
4.0
4.8
4.2
5.3
6.4
7.7
VDD2
VDD1
VDD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.1
Si8610/20/21/22
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8610Bx, Ex
VDD1
—
—
1.2
0.9
2.0
1.5
mA
mA
mA
mA
VDD2
Si8620Bx, Ex
VDD1
VDD2
—
—
2.1
1.6
3.1
2.4
Si8621Bx, Ex
VDD1
VDD2
—
—
1.9
1.9
2.9
2.9
Si8622Bx, Ex
VDD1
VDD2
—
—
3.4
4.2
5.1
6.2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8610Bx, Ex
VDD1
—
—
1.2
1.0
2.0
1.8
mA
mA
mA
mA
VDD2
Si8620Bx, Ex
VDD1
VDD2
—
—
2.1
1.9
3.1
2.8
Si8621Bx, Ex
VDD1
VDD2
—
—
2.0
2.0
3.0
3.0
Si8622Bx, Ex
VDD1
VDD2
—
—
3.5
4.3
5.3
6.4
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8610Bx, Ex
VDD1
—
—
1.2
3.4
2.0
5.1
mA
mA
mA
mA
VDD2
Si8620Bx, Ex
VDD1
VDD2
—
—
2.1
6.3
3.1
8.8
Si8621Bx, Ex
VDD1
VDD2
—
—
4.4
4.4
6.1
6.1
Si8622Bx, Ex
VDD1
VDD2
—
—
5.9
6.6
8.2
9.3
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.1
9
Si8610/20/21/22
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si861x/2x Bx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
150
5.0
13
Mbps
ns
—
5.0
—
t
PHL, tPLH
See Figure 1
See Figure 1
8.0
0.2
ns
PWD
4.5
ns
|tPLH - tPHL
|
Propagation Delay Skew2
Channel-Channel Skew
All Models
tPSK(P-P)
tPSK
—
—
2.0
0.4
4.5
2.5
ns
ns
CL = 15 pF
See Figure 1
Output Rise Time
tr
—
2.5
4.0
ns
CL = 15 pF
Output Fall Time
tf
—
—
35
—
2.5
350
50
4.0
—
ns
ps
See Figure 1
Peak Eye Diagram Jitter
tJIT(PK)
CMTI
tSU
See Figure 6
Common Mode Transient
Immunity
Start-up Time3
VI = VDD or 0 V
—
kV/µs
µs
15
40
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.1
Si8610/20/21/22
Table 4. Electrical Characteristics
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
VDD1, VDD2 rising
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDDUV+
VDDUV– VDD1, VDD2 falling
VDDHYS
V
VDD Negative-Going Lockout
Hysteresis
mV
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
VHYS
VIH
All inputs rising
All inputs falling
1.6
—
—
1.9
1.4
0.50
—
V
V
1.1
0.40
0.45
—
V
2.0
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance1
VIL
—
—
0.8
—
V
VOH
VOL
IL
loh = –4 mA
lol = 4 mA
VDD1,VDD2 – 0.4
2.3
0.2
—
V
—
—
—
0.4
±10
—
V
µA
ZO
50
DC Supply Current (All inputs 0 V or at supply)
Si8610Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
DD1
DD2
DD1
DD2
I
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
V = 0(Bx), 1(Ex)
mA
mA
mA
mA
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8620Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
DD1
DD2
DD1
DD2
I
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8621Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
DD1
DD2
DD1
DD2
I
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8622Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
DD1
DD2
DD1
DD2
I
2.6
3.3
4.0
4.8
4.2
5.3
6.4
7.7
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.1
11
Si8610/20/21/22
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8610Bx, Ex
VDD1
—
—
1.2
0.9
2.0
1.5
mA
mA
mA
mA
VDD2
Si8620Bx, Ex
VDD1
VDD2
—
—
2.1
1.6
3.1
2.4
Si8621Bx, Ex
VDD1
VDD2
—
—
1.9
1.9
2.9
2.9
Si8622Bx, Ex
VDD1
VDD2
—
—
3.4
4.2
5.1
6.2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8610Bx, Ex
V
V
—
—
1.2
1.0
2.0
1.6
mA
mA
mA
mA
DD1
DD2
Si8620Bx, Ex
V
V
—
—
2.1
1.7
3.1
2.6
DD1
DD2
Si8621Bx, Ex
V
V
—
—
2.0
2.0
2.9
2.9
DD1
DD2
Si8622Bx, Ex
V
V
—
—
3.5
4.2
5.2
6.3
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8610Bx, Ex
V
V
—
—
1.2
2.7
2.0
4.4
mA
mA
mA
mA
DD1
DD2
Si8620Bx, Ex
V
V
—
—
2.1
5.1
3.1
7.1
DD1
DD2
Si8621Bx, Ex
V
V
—
—
3.7
3.7
5.2
5.2
DD1
DD2
Si8622Bx, Ex
V
V
—
—
5.2
6.0
7.3
8.4
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.1
Si8610/20/21/22
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si861x/2x Bx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
150
5.0
14
Mbps
ns
—
5.0
—
t
, t
See Figure 1
See Figure 1
8.0
0.2
ns
PHL PLH
PWD
5.0
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.4
5.0
2.5
ns
ns
PSK(P-P)
t
PSK
CL = 15 pF
tr
tf
—
2.5
4.0
ns
Output Rise Time
See Figure 1
CL = 15 pF
See Figure 1
—
—
35
—
2.5
350
50
4.0
—
ns
ps
Output Fall Time
Peak Eye Diagram Jitter
tJIT(PK)
CMTI
tSU
See Figure 6
Common Mode Transient
Immunity
Start-Up Time3
VI = VDD or 0 V
—
kV/µs
µs
15
40
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a
combination of the value of the on-chip series termination resistor and channel resistance of the output driver
FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately
terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units
operating at the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.1
13
Si8610/20/21/22
Table 5. Regulatory Information*
CSA
The Si861x/2x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
RMS
RMS
RMS
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
60601-1: Up to 125 V
reinforced insulation working voltage; up to 380 V
basic insulation working voltage.
RMS
RMS
VDE
The Si861x/2x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1200 V for basic insulation working voltage.
peak
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
RMS
UL
The Si861x/2x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 V isolation voltage for basic protection.
RMS
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "6. Ordering Guide" on page 27.
Table 6. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
Unit
WB
NB
SOIC-16
SOIC-8
1
Nominal Air Gap (Clearance)
L(IO1)
L(IO2)
8.0
8.0
4.9
4.01
0.011
mm
mm
mm
1
Nominal External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
0.014
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
600
V
RMS
0.019
0.040
mm
Erosion Depth
2
12
12
Resistance (Input-Output)
R
10
10
IO
2
Capacitance (Input-Output)
C
2.0
4.0
2.0
4.0
pF
pF
IO
3
Input Capacitance
C
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline:
16-Pin Wide Body SOIC”, “9. Package Outline: 8-Pin Narrow Body SOIC”. VDE certifies the clearance and creepage
limits as 8.5 mm minimum for the WB SOIC-16 package and 4.7 mm minimum for the NB SOIC-8 package. UL does
not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and
creepage limits as 3.9 mm minimum for the NB SOIC-8 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 (1–4, NB SOIC-8)
are shorted together to form the first terminal and pins 9–16 (5–8, NB SOIC-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
14
Rev. 1.1
Si8610/20/21/22
Table 7. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Test Conditions
Specification
NB SOIC-8
WB SOIC-16
Basic Isolation Group
Material Group
I
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-III
I-II
I-II
I-IV
I-IV
I-III
I-III
RMS
RMS
RMS
RMS
Installation Classification
Table 8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx*
Characteristic
Symbol
Test Condition
Unit
Parameter
WB
NB
SOIC-16
SOIC-8
Maximum Working Insulation
Voltage
V
V
1200
2250
630
Vpeak
IORM
Method b1
(V
x 1.875 = V , 100%
IORM
PR
V
1182
Input to Output Test Voltage
PR
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
t = 60 sec
6000
2
6000
2
Vpeak
Transient Overvoltage
IOTM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at T ,
9
9
S
R
>10
>10
S
V
= 500 V
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of
40/125/21.
Table 9. IEC Safety Limiting Values1
Max
Parameter
Symbol
Test Condition
Min Typ
Unit
WB
NB
SOIC-16
SOIC-8
T
—
—
—
—
150
150
°C
Case Temperature
S
= 140 °C/W (NB SOIC-8),
100 °C (WB SOIC-16),
JA
Safety Input, Output,
or Supply Current
I
220
160
mA
S
V = 5.5 V, T = 150 °C, T = 25 °C
I
J
A
Device Power
Dissipation
P
—
—
150
150
mW
2
D
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 2 and 3.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.1
15
Si8610/20/21/22
Table 10. Thermal Characteristics
Parameter
Symbol
Test Condition
WB SOIC-16 NB SOIC-8
Unit
IC Junction-to-Air Thermal
Resistance
100
140
ºC/W
JA
500
375
250
125
0
460
360
VDD1, VDD2 = 2.5 V
V
DD1, VDD2 = 3.3 V
220
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Case Temperature (ºC)
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
400
320
VDD1, VDD2 = 2.5 V
300
270
V
DD1, VDD2 = 3.3 V
200
100
0
160
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Case Temperature (ºC)
Figure 3. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
16
Rev. 1.1
Si8610/20/21/22
Table 11. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
Max
150
125
7.0
Unit
°C
°C
V
2
Storage Temperature
T
STG
Operating Temperature
Supply Voltage
T
A
V
, V
DD2
DD1
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
Output Current Drive Channel
Lead Solder Temperature (10 s)
I
10
mA
°C
O
—
260
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-8
—
—
—
—
4500
V
RMS
RMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
6500
V
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
Rev. 1.1
17
Si8610/20/21/22
2. Functional Description
2.1. Theory of Operation
The operation of an Si861x/2x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si861x/2x channel is shown in
Figure 4.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 5 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 5. Modulation Scheme
18
Rev. 1.1
Si8610/20/21/22
2.2. Eye Diagram
Figure 6 illustrates an eye-diagram taken on an Si8610. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8610 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited.
Figure 6. Eye Diagram
Rev. 1.1
19
Si8610/20/21/22
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLO–
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present.
Table 12. Si86xx Logic Operation
V
VDDI
VDDO
I
1,2
Comments
V Output
O
1,3,4
1,3,4
1,2
State
State
Input
H
L
P
P
P
P
H
L
Normal operation.
6
L
Upon transition of VDDI from unpowered to powered,
V returns to the same state as V in less than 1 µs.
5
X
UP
P
6
H
O
I
Upon transition of VDDO from unpowered to powered,
V returns to the same state as V within 1 µs, if EN is in
Undetermined either the H or NC state. Upon transition of VDDO from
O
I
5
X
P
UP
unpowered to powered, V returns to Hi-Z with 1 µs if
O
EN is L.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
4. “Unpowered” state (UP) is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See "6. Ordering Guide" on page 27 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data
channels have pull-downs on inputs/outputs.
20
Rev. 1.1
Si8610/20/21/22
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when V
falls below V
and exits UVLO when V rises above
DD1
DD1(UVLO–)
DD1
V
. Side B operates the same as Side A with respect to its V
supply.
DD2
DD1(UVLO+)
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
OUTPUT
Figure 7. Device Behavior during Normal Operation
Rev. 1.1
21
Si8610/20/21/22
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 5 on page 14 and Table 6 on page 14 detail the
working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.)
requirements before starting any design that uses a digital isolator.
3.3.1. Supply Bypass
The Si861x/2x family requires a 0.1 µF bypass capacitor between V
and GND1 and V
and GND2. The
DD1
DD2
capacitor should be placed as close as possible to the package. To enhance the robustness of a design, it is further
recommended that the user also add 1 µF bypass capacitors and include 100 resistors in series with the inputs
and outputs if the system is excessively noisy.
3.3.2. Pin Connections
For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin
15 must also be connected to external ground. No connect pins are not internally connected. They can be left
floating, tied to VDD, or tied to GND.
3.3.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3.4. Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input
supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 12 on
page 20 and "6. Ordering Guide" on page 27 for more information.
22
Rev. 1.1
Si8610/20/21/22
3.5. Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 2, 3, and 4 for actual specification limits.
30.0
25.0
20.0
15.0
10.0
5.0
30.0
25.0
20.0
15.0
10.0
5.0
5V
5V
3.3V
2.5V
3.3V
2.5V
0.0
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 11. Si8610 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 8. Si8610 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
30.0
25.0
20.0
30.0
25.0
20.0
15.0
10.0
5.0
5V
15.0
10.0
5.0
5V
3.3V
3.3V
2.5V
2.2.50V
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 9. Si8620 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 12. Si8620 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
30.0
25.0
20.0
30.0
25.0
20.0
5V 1.2
15.0
3.3V
1.2
2.5V
15.0
10.0
5.0
5V
10.0
3.3V
2.5V
1.2
5.0
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0.0
Data Rate (Mbps)
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 10. Si8621 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Figure 13. Si8622 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Rev. 1.1
23
Si8610/20/21/22
10.0
9.0
8.0
7.0
6.0
5.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120
Temperature (Degrees C)
Figure 14. Propagation Delay
vs. Temperature
24
Rev. 1.1
Si8610/20/21/22
4. Pin Descriptions (Wide-Body SOIC)
GND2
NC
GND2
NC
GND1
NC
GND1
NC
GND2
NC
GND1
NC
GND2
NC
GND1
NC
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
VDD1
A1
VDD1
A1
VDD2
B1
VDD2
B1
VDD1
A1
VDD1
A1
VDD2
B1
VDD2
B1
RF
RCVR
RF
XMITR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
RCVR
RF
XMITR
RF
XMITR
RF
XMITR
RF
RCVR
A2
NC
B2
A2
NC
B2
A2
NC
B2
NC
NC
NC
NC
NC
NC
NC
NC
GND1
NC
NC
GND1
NC
GND1
NC
NC
GND1
NC
NC
GND2
GND2
GND2
GND2
Si8622 WB SOIC-16
Si8621 WB SOIC-16
Si8620 WB SOIC-16
Si8610 WB SOIC-16
Name
SOIC-16 Pin# SOIC-16 Pin#
Type
Description
Si8610
Si862x
GND1
NC*
1
1
Ground
Side 1 ground.
NC
2, 5, 6, 8,10,
11, 12, 15
2, 6, 8,10,
11, 15
No Connect
V
3
4
3
4
Supply
Digital I/O
Digital I/O
Ground
Side 1 power supply.
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 ground.
DD1
A1
A2
NC
7
5
GND1
GND2
B2
7
9
9
Ground
Side 2 ground.
NC
13
14
16
12
13
14
16
Digital I/O
Digital I/O
Supply
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
Side 2 ground.
B1
V
DD2
GND2
Ground
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
Rev. 1.1
25
Si8610/20/21/22
5. Pin Descriptions (Narrow-Body SOIC)
VDD1
VDD2
VDD1
VDD1
VDD2
VDD2
B1
VDD1
VDD2
B1
I
s
o
l
a
t
I
s
o
l
a
t
I
s
o
l
a
t
I
s
o
l
a
t
RF
XMITR
RF
XMITR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
GND2/NC
B1
A1
B1
A1
A2
A1
A2
A1
A2
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
VDD1/NC
B2
B2
B2
i
i
i
i
o
n
o
n
o
n
o
n
GND1
GND2
GND1
GND2
GND1
GND2
GND1
GND2
Si8610 NB SOIC-8
Si8620 NB SOIC-8
Si8622 NB SOIC-8
Si8621 NB SOIC-8
Name
SOIC-8 Pin#
Si861x
SOIC-8 Pin#
Si862x
Type
Description
V
/NC*
1,3
4
1
4
2
3
7
6
8
5
Supply
Ground
Side 1 power supply.
DD1
GND1
Side 1 ground.
A1
A2
B1
B2
2
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Side 1 digital input or output.
Side 1 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
NA
6
NA
8
V
DD2
GND2/NC*
5.7
Ground
Side 2 ground.
*Note: No connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
26
Rev. 1.1
Si8610/20/21/22
6. Ordering Guide
Revision B devices are recommended for all new designs.
Table 13. Ordering Guide for Valid OPNs1
Ordering Part Number of Number of Max Data Default Isolation
Temp (C)
Package
Number (OPN)
Inputs
VDD1 Side VDD2 Side
Inputs
Rate
(Mbps)
Output
State
rating
(kV)
2,3
Revision B Devices
Si8610BC-B-IS
Si8610EC-B-IS
Si8610BD-B-IS
Si8610ED-B-IS
Si8620BC-B-IS
Si8620EC-B-IS
Si8620BD-B-IS
Si8620ED-B-IS
Si8621BC-B-IS
Si8621EC-B-IS
Si8621BD-B-IS
Si8621ED-B-IS
Si8622BC-B-IS
Si8622EC-B-IS
Si8622BD-B-IS
Si8622ED-B-IS
Notes:
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
3.75
3.75
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
3.75
3.75
5.0
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
3.75
3.75
5.0
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
3.75
3.75
5.0
SOIC-8
WB SOIC-16
WB SOIC-16
5.0
1. All packages are RoHS-compliant.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 and narrow-body SOIC-8 packages with peak reflow
temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs.
3. All devices >1 kVRMS are AEC-Q100 qualified.
Rev. 1.1
27
Si8610/20/21/22
Table 13. Ordering Guide for Valid OPNs1 (Continued)
Ordering Part Number of Number of Max Data Default Isolation
Temp (C)
Package
Number (OPN)
Inputs
VDD1 Side VDD2 Side
Inputs
Rate
(Mbps)
Output
State
rating
(kV)
2,3
Revision A Devices
Si8610BC-A-IS
Si8610EC-A-IS
Si8610BD-A-IS
Si8610ED-A-IS
Si8620BC-A-IS
Si8620EC-A-IS
Si8620BD-A-IS
Si8620ED-A-IS
Si8621BC-A-IS
Si8621EC-A-IS
Si8621BD-A-IS
Si8621ED-A-IS
Si8622BC-A-IS
Si8622EC-A-IS
Si8622BD-A-IS
Si8622ED-A-IS
Notes:
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
150 Mbps
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
3.75
3.75
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
3.75
3.75
5.0
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
3.75
3.75
5.0
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
3.75
3.75
5.0
SOIC-8
WB SOIC-16
WB SOIC-16
5.0
1. All packages are RoHS-compliant.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 and narrow-body SOIC-8 packages with peak reflow
temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs.
3. All devices >1 kVRMS are AEC-Q100 qualified.
28
Rev. 1.1
Si8610/20/21/22
7. Package Outline: 16-Pin Wide Body SOIC
Figure 15 illustrates the package details for the Triple-Channel Digital Isolator. Table 14 lists the values for the
dimensions shown in the illustration.
Figure 15. 16-Pin Wide Body SOIC
Table 14. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
2.65
0.3
A
A1
D
E
E1
b
0.1
10.3 BSC
10.3 BSC
7.5 BSC
0.31
0.20
0.51
0.33
c
e
1.27 BSC
h
0.25
0.4
0°
0.75
1.27
7°
L
Rev. 1.1
29
Si8610/20/21/22
8. Land Pattern: 16-Pin Wide-Body SOIC
Figure 16 illustrates the recommended land pattern details for the Si861x/2x in a 16-pin wide-body SOIC. Table 15
lists the values for the dimensions shown in the illustration.
Figure 16. 16-Pin SOIC Land Pattern
Table 15. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
30
Rev. 1.1
Si8610/20/21/22
9. Package Outline: 8-Pin Narrow Body SOIC
Figure 17 illustrates the package details for the Si86xx. Table 16 lists the values for the dimensions shown in the
illustration.
Figure 17. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 16. Package Diagram Dimensions
Millimeters
Symbol
Min
Max
A
A1
A2
B
1.35
1.75
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0
6.20
0.50
1.27
8
L
Rev. 1.1
31
Si8610/20/21/22
10. Land Pattern: 8-Pin Narrow Body SOIC
Figure 18 illustrates the recommended land pattern details for the Si86xx in an 8-pin narrow-body SOIC. Table 17
lists the values for the dimensions shown in the illustration.
Figure 18. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 17. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
32
Rev. 1.1
Si8610/20/21/22
11. Top Marking: 16-Pin Wide Body SOIC
11.1. 16-Pin Wide Body SOIC Top Marking
Si86XYSV
YYWWTTTTTT
e3
TW
11.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
(See Ordering Guide for more
information).
Y = # of reverse channels (1, 0)
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing code from assembly house
“e3” Pb-Free Symbol
Circle = 1.5 mm Diameter
(Center-Justified)
Country of Origin ISO Code
Abbreviation
TW = Taiwan
Rev. 1.1
33
Si8610/20/21/22
12. Top Marking: 8-Pin Narrow Body SOIC
12.1. 8-Pin Narrow Body SOIC Top Marking
Si86XYSV
YYWWRF
e3
AIXX
12.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
(See Ordering Guide for more
information).
Y = # of reverse channels (1, 0)
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to
the year and workweek of the mold date.
R = Product (OPN) Revision
F = Wafer Fab
Circle = 1.1 mm Diameter
Left-Justified
“e3” Pb-Free Symbol.
First two characters of the manufacturing code.
A = Assembly Site
I = Internal Code
Last four characters of the manufacturing code.
XX = Serial Lot Number
34
Rev. 1.1
Si8610/20/21/22
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Added chip graphics on page 1.
Moved Tables 1 and 11 to page 17.
Updated Table 6, “Insulation and Safety-Related
Specifications,” on page 14.
Updated Table 8, “IEC 60747-5-2 Insulation
Characteristics for Si86xxxx*,” on page 15.
Moved Table 12 to page 20.
Moved “Typical Performance Characteristics” to
page 23.
Updated "4. Pin Descriptions (Wide-Body SOIC)" on
page 25.
Updated "5. Pin Descriptions (Narrow-Body SOIC)"
on page 26.
Updated "6. Ordering Guide" on page 27.
Revision 0.2 to Revision 0.3
Added chip graphics on page 1.
Moved Tables 1 and 2 to page 17.
Updated Table 6, “Insulation and Safety-Related
Specifications,” on page 14.
Updated Table 8, “IEC 60747-5-2 Insulation
Characteristics for Si86xxxx*,” on page 15.
Moved Table 12 to page 20.
Moved Table 13 to page 27.
Moved “Typical Performance Characteristics” to
page 23.
Updated "4. Pin Descriptions (Wide-Body SOIC)" on
page 25.
Updated "5. Pin Descriptions (Narrow-Body SOIC)"
on page 26.
Updated "6. Ordering Guide" on page 27.
Revision 0.3 to Revision 1.0
Updated “Table 3. Electrical Characteristics”.
Reordered spec tables to conform to new
convention.
Removed “pending” throughout document.
Revision 1.0 to Revision 1.1
Updated High Level Output Voltage VOH to 3.1 V in
Table 3, “Electrical Characteristics,” on page 8.
Updated High Level Output Voltage VOH to 2.3 V in
Table 4, “Electrical Characteristics,” on page 11.
Rev. 1.1
35
Si8610/20/21/22
CONTACT INFORMATION
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Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
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The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
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36
Rev. 1.1
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