SI8642EC-A-IS1 [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO16, ROHS COMPLIANT, MS-012AC, SOIC-16;
| 型号： | SI8642EC-A-IS1 |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO16, ROHS COMPLIANT, MS-012AC, SOIC-16 光电二极管 |
| 文件： | 总40页 (文件大小：485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8640/41/42/45
LOW-POWER QUAD-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage
2.5–5.5 V
Selectable fail-safe mode
Default high or low output
(ordering option)
Precise timing (typical)
10 ns propagation delay
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
Up to 5000 VRMS isolation
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
3.5 mA per channel at 100 Mbps
Tri-state outputs with ENABLE
Schmitt trigger inputs
RoHS-compliant packages
SOIC-16 wide body
SOIC-16 narrow body
QSOP-16
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated ADC, DAC
Motor control
Power inverters
Isolated switch mode supplies
Communications systems
Safety Regulatory Approvals
Ordering Information:
UL 1577 recognized
VDE certification conformity
IEC 60747-5-2
See page 26.
Up to 5000 VRMS for 1 minute
(VDE0884 Part 2)
EN60950-1
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation
delays of less than 10 ns. Enable inputs provide a single point control for
enabling and disabling output drive. Ordering options include a choice of
isolation ratings (3.75 and 5 kV) and a selectable fail-safe operating mode to
control the default output state during power loss. All products >1 kVRMS are
safety certified by UL, CSA, and VDE, and products in wide-body packages
support reinforced insulation withstanding up to 5 kVRMS
.
Rev. 1.1 9/11
Copyright © 2011 by Silicon Laboratories
Si8640/41/42/45
Si8640/41/42/45
2
Rev. 1.1
Si8640/41/42/45
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11. Land Pattern: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
12. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
12.1. 16-Pin Wide Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
12.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
13. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
13.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
14. Top Marking: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14.1. 16-Pin QSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.1
3
Si8640/41/42/45
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
–40
2.5
Typ
25
—
Max
125
5.5
Unit
ºC
V
Ambient Operating Temperature*
Supply Voltage
T
150 Mbps, 15 pF, 5 V
A
V
DD1
V
2.5
—
5.5
V
DD2
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
VDDUV+
VDDUV–
Test Condition
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
V
, V
rising
falling
DD1
DD2
DD2
V
, V
V
DD1
VDD Negative-Going Lockout
Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
VT+
VT–
All inputs rising
1.4
1.0
1.67
1.23
1.9
1.4
V
V
Negative-Going Input
Threshold
All inputs falling
Input Hysteresis
V
0.38
2.0
—
0.44
—
0.50
—
V
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
—
µA
L
1
Output Impedance
Z
50
O
Enable Input High Current
Enable Input Low Current
Notes:
I
V
= V
IH
2.0
2.0
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.1
Si8640/41/42/45
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Supply Current (All inputs 0 V or at Supply)
Si8640Bx, Ex, Si8645Bx
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
mA
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8641Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
mA
mA
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8642Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8640Bx, Ex, Si8645Bx
V
V
—
—
3.6
2.9
5.0
4.0
mA
mA
mA
DD1
DD2
Si8641Bx, Ex
V
V
—
—
3.4
3.3
4.8
4.6
DD1
DD2
Si8642Bx, Ex
V
V
—
—
3.3
3.3
4.6
4.6
DD1
DD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8640Bx, Ex, Si8645Bx
V
V
—
—
3.6
4.0
5.0
5.6
mA
mA
mA
DD1
DD2
Si8641Bx, Ex
V
V
—
—
3.7
4.1
5.2
5.8
DD1
DD2
Si8642Bx, Ex
V
V
—
—
3.9
3.9
5.4
5.4
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.1
5
Si8640/41/42/45
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8640Bx, Ex, Si8645Bx
Test Condition
Min
Typ
Max
Unit
V
V
—
—
3.6
17.5
5.0
22.8
mA
mA
mA
DD1
DD2
Si8641Bx, Ex
V
V
—
—
7.3
14.3
9.8
18.5
DD1
DD2
Si8642Bx, Ex
V
V
—
—
11
11
14.3
14.3
DD1
DD2
Timing Characteristics
Si864xBx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
150
5.0
13
Mbps
ns
—
5.0
—
t
, t
See Figure 2
See Figure 2
8.0
0.2
ns
PHL PLH
PWD
4.5
ns
|t
– t
|
PLH
PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.4
4.5
2.5
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
ns
ns
r
L
2.5
2.5
4.0
4.0
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Peak Eye Diagram Jitter
t
See Figure 7
—
350
50
—
—
ps
JIT(PK)
Common Mode
CMTI
V = V or 0 V
35
kV/µs
I
DD
Transient Immunity
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
6.0
8.0
15
11
12
40
ns
ns
µs
en1
en2
Enable to Data Tri-State
3
Startup Time
t
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.1
Si8640/41/42/45
ENABLE
OUTPUTS
ten1
ten2
Figure 1. ENABLE Timing Diagram
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 2. Propagation Delay Timing
Rev. 1.1
7
Si8640/41/42/45
Table 3. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDDUV+ V
, V
rising
falling
DD1
DD2
DD2
VDDUV– V
, V
V
DD1
VDD Negative-Going Lockout
Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
All inputs rising
All inputs falling
1.4
1.0
0.38
2.0
—
1.67
1.23
0.44
—
1.9
1.4
0.50
—
V
V
V
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
3.1
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
—
—
µA
L
1
Output Impedance
Z
50
O
Enable Input High Current
Enable Input Low Current
I
V
= V
IH
2.0
2.0
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8640Bx, Ex, Si8645Bx
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
mA
mA
mA
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8641Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8642Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.1
Si8640/41/42/45
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8640Bx, Ex, Si8645Bx
Test Condition
Min
Typ
Max
Unit
V
V
—
—
3.6
2.9
5.0
4.0
mA
mA
mA
DD1
DD2
Si8641Bx, Ex
V
V
—
—
3.4
3.3
4.8
4.6
DD1
DD2
Si8642Bx, Ex
V
V
—
—
3.3
3.3
4.6
4.6
DD1
DD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8640Bx, Ex, Si8645Bx
V
V
—
—
3.6
3.4
5.0
4.7
mA
mA
mA
DD1
DD2
Si8641Bx, Ex
V
V
—
—
3.5
3.6
4.9
5.1
DD1
DD2
Si8642Bx, Ex
V
V
—
—
3.6
3.6
5.0
5.0
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8640Bx, Ex, Si8645Bx
V
V
—
—
3.6
12.3
5.0
15.9
mA
mA
mA
DD1
DD2
Si8641Bx, Ex
V
V
—
—
5.9
10.3
7.9
13.4
DD1
DD2
Si8642Bx, Ex
V
V
—
—
8.2
8.2
10.7
10.7
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.1
9
Si8640/41/42/45
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si864xBx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
150
5.0
13
Mbps
ns
—
5.0
—
t
, t
See Figure 2
See Figure 2
8.0
0.2
ns
PHL PLH
PWD
4.5
ns
|t
– t
|
PLH
PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.4
4.5
2.5
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
ns
ns
r
L
2.5
2.5
4.0
4.0
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Peak eye diagram jitter
t
See Figure 7
—
350
50
—
—
ps
JIT(PK)
Common Mode Transient
CMTI
V = V or 0 V
35
kV/µs
I
DD
Immunity at Logic Low Output
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
6.0
8.0
15
11
12
40
ns
ns
µs
en1
en2
Enable to Data Tri-State
3
Startup Time
t
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.1
Si8640/41/42/45
Table 4. Electrical Characteristics
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
VDDUV+
VDDUV–
Test Condition
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
V
, V
rising
falling
DD1
DD2
DD2
V
, V
V
DD1
VDD Negative-Going Lockout
Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
All inputs rising
1.4
1.0
0.38
2.0
—
1.67
1.23
0.44
—
1.9
1.4
0.50
—
V
V
V
V
V
V
All inputs falling
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
IH
V
—
0.8
—
IL
V
loh = –4 mA
lol = 4 mA
V
,
DD1
– 0.4
2.3
OH
V
DD2
Low Level Output Voltage
Input Leakage Current
V
—
0.2
—
0.4
±10
—
V
OL
I
—
—
—
—
µA
L
1
Output Impedance
Z
50
O
Enable Input High Current
Enable Input Low Current
I
V
= V
IH
2.0
2.0
—
µA
µA
ENH
ENx
I
V
= V
IL
—
ENL
ENx
DC Supply Current (All inputs 0 V or at supply)
Si8640Bx, Ex, Si8645Bx
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
mA
mA
mA
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8641Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8642Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.1
11
Si8640/41/42/45
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8640Bx, Ex, Si8645Bx
Test Condition
Min
Typ
Max
Unit
V
V
—
—
3.6
2.9
5.0
4.0
mA
mA
mA
DD1
DD2
Si8641Bx, Ex
V
V
—
—
3.4
3.3
4.8
4.6
DD1
DD2
Si8642Bx, Ex
V
V
—
—
3.3
3.3
4.6
4.6
DD1
DD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8640Bx, Si8645Bx
V
V
—
—
3.6
3.1
5.0
4.3
mA
mA
mA
DD1
DD2
Si8641Bx, Ex
V
V
—
—
3.5
3.4
4.8
4.8
DD1
DD2
Si8642Bx, Ex
V
V
—
—
3.4
3.4
4.8
4.8
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8640Bx, Ex, Si8645Bx
V
V
—
—
3.6
9.9
5.0
12.8
mA
mA
mA
DD1
DD2
Si8641Bx, Ex
V
V
—
—
5.2
8.5
7.0
11.1
DD1
DD2
Si8642Bx, Ex
V
V
—
—
6.9
6.9
9.0
9.0
DD1
DD2
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.1
Si8640/41/42/45
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si864xBx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
150
5.0
14
Mbps
ns
—
5.0
—
t
, t
See Figure 2
See Figure 2
8.0
0.2
ns
PHL PLH
PWD
5.0
ns
|t
– t
|
PLH
PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.4
5.0
2.5
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 2
—
—
ns
ns
r
L
2.5
2.5
4.0
4.0
Output Fall Time
t
C = 15 pF
f
L
See Figure 2
Peak Eye Diagram Jitter
t
See Figure 7
—
350
50
—
—
ps
JIT(PK)
Common Mode Transient
CMTI
V = V or 0 V
35
kV/µs
I
DD
Immunity at Logic Low Output
Enable to Data Valid
t
t
See Figure 1
See Figure 1
—
—
—
6.0
8.0
15
11
12
40
ns
ns
µs
en1
en2
Enable to Data Tri-State
3
Startup Time
t
SU
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.1
13
Si8640/41/42/45
Table 5. Regulatory Information*
CSA
The Si864x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
RMS
RMS
RMS
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
60601-1: Up to 125 V
reinforced insulation working voltage; up to 380 V
basic insulation working voltage.
RMS
RMS
VDE
The Si864x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1200 V for basic insulation working voltage.
peak
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
RMS
UL
The Si864x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 V isolation voltage for basic protection.
RMS
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "5. Ordering Guide" on page 26.
Table 6. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
Unit
WB
NB
QSOP-16
SOIC-16 SOIC-16
1
Nominal Air Gap (Clearance)
L(IO1)
L(IO2)
8.0
8.0
4.9
3.6
3.6
mm
mm
Nominal External Tracking
4.01
1
(Creepage)
Minimum Internal Gap
(Internal Clearance)
mm
0.014
0.011
0.008
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
600
600
V
RMS
0.019
0.019
0.031
mm
Erosion Depth
2
12
12
12
Resistance (Input-Output)
R
10
10
10
IO
2
Capacitance (Input-Output)
C
2.0
4.0
2.0
4.0
2.0
4.0
pF
pF
IO
3
Input Capacitance
C
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-16 and QSOP-16 packages and 8.5 mm minimum for the WB
SOIC-16 package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA
certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16, 3.6 mm for QSOP-16 packages
and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
14
Rev. 1.1
Si8640/41/42/45
Table 7. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Test Conditions
Specification
NB SOIC-16
WB SOIC-16
Basic Isolation Group
Material Group
I
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-III
I-II
I-II
I-IV
I-IV
I-III
I-III
RMS
RMS
RMS
RMS
Installation Classification
Table 8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx*
Characteristic
Symbol
Test Condition
Unit
Parameter
WB
NB
SOIC-16
SOIC-16
Maximum Working
Insulation Voltage
V
V
1200
2250
630
Vpeak
IORM
Method b1
(V
x 1.875 = V , 100%
IORM
PR
V
1182
Input to Output Test Voltage
PR
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
t = 60 sec
6000
2
6000
2
Vpeak
Transient Overvoltage
IOTM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at T ,
9
9
S
R
>10
>10
S
V
= 500 V
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of
40/125/21.
Table 9. IEC Safety Limiting Values1
Max
Parameter
Symbol
Test Condition
Min Typ
Unit
WB
NB
SOIC-16
SOIC-16
T
—
—
—
—
150
150
°C
Case Temperature
S
= 100 °C/W (WB SOIC-16),
105 °C/W (NB SOIC-16, QSOP-16),
Safety Input,
Output, or Supply
Current
JA
I
220
210
mA
S
V = 5.5 V, T = 150 °C, T = 25 °C
I
J
A
Device Power
Dissipation
P
—
—
275
275
mW
2
D
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3 and 4.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.1
15
Si8640/41/42/45
Table 10. Thermal Characteristics
NB SOIC-16
QSOP-16
Parameter
Symbol
Test Condition
WB SOIC-16
Unit
IC Junction-to-Air Thermal
Resistance
100
105
ºC/W
JA
500
450
370
VDD1, VDD2 = 2.70 V
400
300
200
100
0
VDD1, VDD2 = 3.6 V
220
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
500
430
V
DD1, VDD2 = 2.70 V
400
300
200
100
0
360
VDD1, VDD2 = 3.6 V
210
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 4. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
16
Rev. 1.1
Si8640/41/42/45
Table 11. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
Max
150
125
7.0
Unit
ºC
ºC
V
2
Storage Temperature
T
STG
Ambient Temperature Under Bias
Supply Voltage
T
A
V
, V
DD2
DD1
Input Voltage
V
V
V
+ 0.5
V
I
DD
Output Voltage
V
+ 0.5
V
O
DD
Output Current Drive Channel
Lead Solder Temperature (10 s)
I
10
mA
ºC
O
—
260
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16, QSOP-16
—
—
—
—
4500
V
RMS
RMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
6500
V
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum ratings for extended periods may degrade performance.
2. VDE certifies storage temperature from –40 to 150 °C.
Rev. 1.1
17
Si8640/41/42/45
2. Functional Description
2.1. Theory of Operation
The operation of an Si864x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si864x channel is shown in
Figure 5.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 5. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 6 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 6. Modulation Scheme
18
Rev. 1.1
Si8640/41/42/45
2.2. Eye Diagram
Figure 7 illustrates an eye-diagram taken on an Si8640. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8640 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited.
Figure 7. Eye Diagram
Rev. 1.1
19
Si8640/41/42/45
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 8, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present. Additionally, refer to Table 13 for logic conditions when enable pins are used.
Table 12. Si86xx Logic Operation
V
EN
VDDI
VDDO
I
1,2
Comments
V Output
O
1,2,3,4
1,5,6
1,5,6
1,2
Input
State
State
Input
H
L
H or NC
H or NC
L
P
P
P
P
P
P
H
L
Enabled, normal operation.
7
8
X
Hi-Z
Disabled.
9
Upon transition of VDDI from unpowered to pow-
ered, V returns to the same state as V in less
than 1 µs.
L
7
X
H or NC
L
UP
UP
P
P
9
O
I
H
7
8
X
Hi-Z
Disabled.
Upon transition of VDDO from unpowered to pow-
ered, V returns to the same state as V within
1 µs, if EN is in either the H or NC state. Upon
transition of VDDO from unpowered to powered,
O
I
7
7
X
X
P
UP
Undetermined
V returns to Hi-Z within 1 µs if EN is L.
O
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is
operating in noisy environments.
4. No Connect (NC) replaces EN1 on Si8640/45. No Connect replaces EN2 on the Si8645. No Connects are not internally
connected and can be left floating, tied to VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
9. See "5. Ordering Guide" on page 26 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data
channels have pull-downs on inputs/outputs.
20
Rev. 1.1
Si8640/41/42/45
Table 13. Enable Input Truth1
1,2
1,2
P/N
Operation
EN1
EN2
H
L
Si8640
—
—
H
L
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Outputs B1, B2, B3, B4 are disabled and in high impedance state.
Output A4 enabled and follows the input state.
3
Si8641
Si8642
Si8645
X
3
X
Output A4 disabled and in high impedance state.
X
H
L
Outputs B1, B2, B3 are enabled and follow the input state.
3
X
Outputs B1, B2, B3 are disabled and in high impedance state.
H
L
X
Outputs A3 and A4 are enabled and follow the input state.
3
X
Outputs A3 and A4 are disabled and in high impedance state.
X
H
L
Outputs B1 and B2 are enabled and follow the input state.
3
X
Outputs B1 and B2 are disabled and in high impedance state.
—
—
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. EN1, EN2 logic
operation is summarized for each isolator product in Table 13. These inputs are internally pulled-up to local VDD by a
2 µA current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize
noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is
recommended they be connected to an external logic level, especially if the Si86xx is operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
Rev. 1.1
21
Si8640/41/42/45
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when V
falls below V
and exits UVLO when V
rises above
DD1
DD1(UVLO–)
DD1
V
. Side B operates the same as Side A with respect to its V
supply.
DD1(UVLO+)
DD2
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
OUTPUT
Figure 8. Device Behavior during Normal Operation
22
Rev. 1.1
Si8640/41/42/45
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 5 on page 14 and Table 6 on page 14 detail the
working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.)
requirements before starting any design that uses a digital isolator.
3.3.1. Supply Bypass
The Si864x family requires a 0.1 µF bypass capacitor between V
and GND1 and V
and GND2. The
DD2
DD1
capacitor should be placed as close as possible to the package. To enhance the robustness of a design, it is further
recommended that the user also add 1 µF bypass capacitors and include 100 resistors in series with the inputs
and outputs if the system is excessively noisy.
3.3.2. Pin Connections
For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin
15 must also be connected to external ground. No connect pins are not internally connected. They can be left
floating, tied to VDD, or tied to GND.
3.3.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3.4. Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input
supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 12 on
page 20 and "5. Ordering Guide" on page 26 for more information.
Rev. 1.1
23
Si8640/41/42/45
3.5. Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 2, 3, and 4 for actual specification limits.
30.0
25.0
20.0
15.0
10.0
5.0
30.0
25.0
20.0
15.0
10.0
5.0
5V
5V
3.3V
2.5V
3.3V
2.5V
0.0
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 12. Si8640/45 Typical VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.5 V
Figure 9. Si8640/45 Typical VDD1 Supply
Current vs. Data Rate 5, 3.3, and 2.5 V
Operation
30.0
25.0
20.0
30.0
25.0
20.0
15.0
10.0
5.0
5V
3.3V
2.5V
15.0
10.0
5.0
5V
3.3V
2.5V
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0.0
Data Rate (Mbps)
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Figure 13. Si8641 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
(15 pF Load)
Data Rate (Mbps)
Figure 10. Si8641 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
30.0
25.0
20.0
10.0
9.0
8.0
7.0
6.0
5.0
15.0
10.0
5.0
5V
3.3V
2.5V
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100110120
0.0
Temperature (Degrees C)
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 14. Propagation Delay vs. Temperature
Figure 11. Si8642 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.5 V
Operation (15 pF Load)
24
Rev. 1.1
Si8640/41/42/45
4. Pin Descriptions
VDD1
VDD1
VDD2
GND2
B1
VDD1
VDD2
GND2
B1
VDD2
GND2
B1
GND1
GND1
GND1
I
I
s
o
l
I
s
o
l
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
s
o
l
A1
A2
A1
A2
A1
A2
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B2
B2
B2
a
t
i
o
n
a
t
i
o
n
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
RCVR
RF
RCVR
RF
RF
XMITR
A3
A4
B3
A3
A4
B3
A3
A4
B3
XMITR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B4
B4
B4
EN2/NC
GND2
EN2
GND2
EN2
GND2
NC
EN1
EN1
GND1
GND1
GND1
Si8640/45
Si8641
Si8642
Name
SOIC-16 Pin#
Type
Supply
Ground
Description
V
1
2
Side 1 power supply.
Side 1 ground.
DD1
GND1
A1
3
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital Input
Ground
Side 1 digital input.
A2
4
Side 1 digital input.
A3
5
Side 1 digital input or output.
Side 1 digital input or output.
A4
6
EN1/NC*
GND1
GND2
EN2/NC*
B4
7
Side 1 active high enable. NC on Si8640/45.
Side 1 ground.
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Input
Digital I/O
Digital I/O
Side 2 active high enable. NC on Si8645.
Side 2 digital input or output.
Side 2 digital input or output.
B3
B2
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B1
GND2
Ground
Supply
Side 2 ground.
V
Side 2 power supply.
DD2
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
Rev. 1.1
25
Si8640/41/42/45
5. Ordering Guide
Revision B devices are recommended for all new designs.
Table 14. Ordering Guide for Valid OPNs1
Ordering Part Number Number
Number (OPN) of Inputs of Inputs
Max Data
Rate
(Mbps)
Default
Output
State
Isolation
rating (kV)
Temp (°C)
Package
VDD1
Side
VDD2
Side
2,3
Revision B Devices
Si8640BC-B-IS1
Si8640EC-B-IS1
Si8641BC-B-IS1
Si8641EC-B-IS1
Si8642BC-B-IS1
Si8642EC-B-IS1
Si8645BC-B-IS1
Si8640BD-B-IS
Si8640ED-B-IS
Si8641BD-B-IS
Si8641ED-B-IS
Si8642BD-B-IS
Si8642ED-B-IS
Si8645BD-B-IS
Notes:
4
4
3
3
2
2
4
4
4
3
3
2
2
4
0
0
1
1
2
2
0
0
0
1
1
2
2
0
150
150
150
150
150
150
150
150
150
150
150
150
150
150
Low
High
Low
High
Low
High
Low
Low
High
Low
High
Low
High
Low
3.75
3.75
3.75
3.75
3.75
3.75
3.75
5.0
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
5.0
5.0
5.0
5.0
5.0
5.0
1. All packages are RoHS-compliant.
Moisture sensitivity level is MSL3 for wide-body SOIC-16, narrow-body SOIC-16, and QSOP-16 packages with peak
reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs.
3. All devices >1 kVRMS are AEC-Q100 qualified.
26
Rev. 1.1
Si8640/41/42/45
Table 14. Ordering Guide for Valid OPNs1 (Continued)
Ordering Part Number Number
Number (OPN) of Inputs of Inputs
Max Data
Rate
(Mbps)
Default
Output
State
Isolation
rating (kV)
Temp (°C)
Package
VDD1
Side
VDD2
Side
2,3
Revision A Devices
Si8640BC-A-IS1
Si8640EC-A-IS1
Si8641BC-A-IS1
Si8641EC-A-IS1
Si8642BC-A-IS1
Si8642EC-A-IS1
Si8642BA-A-IU
Si8645BA-A-IU
Si8641BA-A-IU
Si8645BC-A-IS1
Si8640BD-A-IS
Si8640ED-A-IS
Si8641BD-A-IS
Si8641ED-A-IS
Si8642BD-A-IS
Si8642ED-A-IS
Si8645BD-A-IS
Notes:
4
4
3
3
2
2
2
4
3
4
4
4
3
3
2
2
4
0
0
1
1
2
2
2
0
1
0
0
0
1
1
2
2
0
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
Low
High
Low
High
Low
High
Low
Low
Low
Low
Low
High
Low
High
Low
High
Low
3.75
3.75
3.75
3.75
3.75
3.75
1.0
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C NB SOIC-16
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
QSOP-16
QSOP-16
QSOP-16
1.0
1.0
3.75
5.0
–40 to 125 °C NB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
–40 to 125 °C WB SOIC-16
5.0
5.0
5.0
5.0
5.0
5.0
1. All packages are RoHS-compliant.
Moisture sensitivity level is MSL3 for wide-body SOIC-16, narrow-body SOIC-16, and QSOP-16 packages with peak
reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures.
2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs.
3. All devices >1 kVRMS are AEC-Q100 qualified.
Rev. 1.1
27
Si8640/41/42/45
6. Package Outline: 16-Pin Wide Body SOIC
Figure 15 illustrates the package details for the Si864x Digital Isolator. Table 15 lists the values for the dimensions
shown in the illustration.
Figure 15. 16-Pin Wide Body SOIC
Table 15. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
2.65
0.3
A
A1
D
E
E1
b
0.1
10.3 BSC
10.3 BSC
7.5 BSC
0.31
0.51
0.33
c
0.20
e
1.27 BSC
h
0.25
0.4
0°
0.75
1.27
7°
L
28
Rev. 1.1
Si8640/41/42/45
7. Land Pattern: 16-Pin Wide-Body SOIC
Figure 16 illustrates the recommended land pattern details for the Si864x in a 16-pin wide-body SOIC. Table 16
lists the values for the dimensions shown in the illustration.
Figure 16. 16-Pin SOIC Land Pattern
Table 16. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.1
29
Si8640/41/42/45
8. Package Outline: 16-Pin Narrow Body SOIC
Figure 17 illustrates the package details for the Si864x in a 16-pin narrow-body SOIC (SO-16). Table 17 lists the
values for the dimensions shown in the illustration.
Figure 17. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 17. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
0.25 BSC
30
Rev. 1.1
Si8640/41/42/45
Table 17. Package Diagram Dimensions (Continued)
Dimension
Min
0.25
0°
Max
0.50
8°
h
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation
AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.1
31
Si8640/41/42/45
9. Land Pattern: 16-Pin Narrow Body SOIC
Figure 18 illustrates the recommended land pattern details for the Si864x in a 16-pin narrow-body SOIC. Table 18
lists the values for the dimensions shown in the illustration.
Figure 18. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 18. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
32
Rev. 1.1
Si8640/41/42/45
10. Package Outline: 16-Pin QSOP
Figure 19 illustrates the package details for the Si864x in a 16-pin QSOP package. Table 19 lists the values for the
dimensions shown in the illustration.
Figure 19. 16-pin QSOP Package
Table 19. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.20
0.17
0.30
0.25
c
D
4.89 BSC
6.00 BSC
3.90 BSC
0.635 BSC
E
E1
e
L
0.40
0.25
1.27
0.50
L2
h
0.25 BSC
Rev. 1.1
33
Si8640/41/42/45
Table 19. Package Diagram Dimensions (Continued)
Dimension
Min
Max
θ
0°
8°
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification
for Small Body Components.
34
Rev. 1.1
Si8640/41/42/45
11. Land Pattern: 16-Pin QSOP
Figure 20 illustrates the recommended land pattern details for the Si864x in a 16-pin narrow-body SOIC. Table 20
lists the values for the dimensions shown in the illustration.
Figure 20. 16-Pin QSOP PCB Land Pattern
Table 20. 16-Pin QSOP Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
C1
E
0.635
0.40
X1
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05mm is assumed.
Rev. 1.1
35
Si8640/41/42/45
12. Top Marking: 16-Pin Wide Body SOIC
12.1. 16-Pin Wide Body SOIC Top Marking
Si86XYSV
YYWWTTTTTT
e3
TW
12.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (4, 3, 2, 1)
(See Ordering Guide for more
information).
Y = # of reverse channels (2, 1, 0)*
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing code from assembly house
“e3” Pb-Free Symbol
Circle = 1.5 mm Diameter
(Center-Justified)
Country of Origin ISO Code
Abbreviation
TW = Taiwan
*Note: Si8645 has 0 reverse channels.
36
Rev. 1.1
Si8640/41/42/45
13. Top Marking: 16-Pin Narrow Body SOIC
13.1. 16-Pin Narrow Body SOIC Top Marking
Si86XYSV
YYWWTTTTTT
e3
13.2. Top Marking Explanation
Line 1 Marking: Base Part Number
Si86 = Isolator product series
Ordering Options
XY = Channel Configuration
X = # of data channels (4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)*
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
(See Ordering Guide for more
information).
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking: Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the year
and work week of the mold date.
TTTTTT = Mfg code
Circle = 1.2 mm diameter
Manufacturing Code from Assembly Purchase Order form.
“e3” Pb-Free Symbol.
*Note: Si8645 has 0 reverse channels.
Rev. 1.1
37
Si8640/41/42/45
14. Top Marking: 16-Pin QSOP
14.1. 16-Pin QSOP Top Marking
Si86XYSV
YYWWTTTTTT
e3
14.2. Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (4, 3, 2, 1)
(See Ordering Guide for more
information).
Y = # of reverse channels (2, 1, 0)*
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking:
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the year
and work week of the mold date.
TTTTTT = Mfg code
Manufacturing Code from Assembly Purchase Order form.
“e3” Pb-Free Symbol.
Circle = 1.2 mm diameter
*Note: Si8645 has 0 reverse channels.
38
Rev. 1.1
Si8640/41/42/45
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Added chip graphics on page 1.
Moved Tables 1 and 11 to page 17.
Updated Table 6, “Insulation and Safety-Related
Specifications,” on page 14.
Updated Table 8, “IEC 60747-5-2 Insulation
Characteristics for Si86xxxx*,” on page 15.
Moved Table 12 to page 20.
Moved Table 13 to page 21.
Moved “Typical Performance Characteristics” to
page 24.
Updated "4. Pin Descriptions" on page 25.
Updated "5. Ordering Guide" on page 26.
Revision 0.2 to Revision 1.0
Reordered spec tables to conform to new
convention.
Removed “pending” throughout document.
Revision 1.0 to Revision 1.1
Updated High Level Output Voltage VOH to 3.1 V in
Table 3, “Electrical Characteristics,” on page 8.
Updated High Level Output Voltage VOH to 2.3 V in
Table 4, “Electrical Characteristics,” on page 11.
Rev. 1.1
39
Si8640/41/42/45
CONTACT INFORMATION
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400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
40
Rev. 1.1
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