SI8660AB-B-IS1 [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16;
| 型号： | SI8660AB-B-IS1 |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16 光电二极管 |
| 文件： | 总47页 (文件大小：757K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si86xx Data Sheet
1 Mbps, 2.5 kV
Digital Isolators
RMS
KEY FEATURES
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-
tages over legacy isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges and throughout device service life for
ease of design and highly uniform performance. All device versions have Schmitt trigger
inputs for high noise immunity and only require VDD bypass capacitors.
• High-speed operation
• DC to 1 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5 to 5.5 V
• Up to 2500 V
isolation
RMS
All products support Data rates up to 1 Mbps and Enable inputs which provide a single
point control for enabling and disabling output drive. All products are safety certified by
• 60-year life at rated working voltage
• High electromagnetic immunity
UL, CSA, VDE, and CQC and support withstand ratings up to 2.5 kVRMS
.
• Ultra low power (typical)
• 5 V Operation: 1.6 mA per channel at 1
Mbps
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robust-
ness and low defectivity required for automotive applications.
• 2.5 V Operation: 1.5 mA per channel at
1 Mbps
Automotive Applications
Industrial Applications
• Tri-state outputs with ENABLE
• Schmitt trigger inputs
• On-board chargers
• Industrial automation systems
• Battery management systems
• Medical electronics
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
• Charging stations
• Isolated switch mode supplies
• Traction inverters
• Isolated ADC, DAC
• Wide temperature range
• –40 to 125 °C
• Hybrid Electric Vehicles
• Motor control
• Battery Electric Vehicles
• Power inverters
• RoHS-compliant packages
• SOIC-16 wide body
• Communication systems
• SOIC-16 narrow body
• SOIC-8 narrow body
Safety Regulatory Approvals
• UL 1577 recognized
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 61010-1
• IMDS and CAMDS listing support
• VDE certification conformity
• IEC 60747-5-2 (VDE0884 Part 2)
• CQC certification approval
• GB4943.1
silabs.com | Building a more connected world.
Rev. 1.01
Si86xx Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Ordering Guide for Valid OPNs1,2
Ordering Part
Number (OPN)
Number of
Inputs
Number of
Inputs
Max Data
Rate (Mbps)
Default Out-
put State
Isolation
Rating (kV)
Temp (°C)
Package
VDD1 Side
VDD2 Side
Si8610AB-B-IS
Si8620AB-B-IS
Si8621AB-B-IS
Si8630AB-B-IS
Si8630AB-B-IS1
Si8631AB-B-IS
Si8631AB-B-IS1
Si8640AB-B-IS1
Si8640AB-B-IS
Si8641AB-B-IS1
Si8641AB-B-IS
Si8642AB-B-IS1
Si8642AB-B-IS
Si8650AB-B-IS1
Si8651AB-B-IS1
Si8652AB-B-IS1
Si8660AB-B-IS1
Si8661AB-B-IS1
Si8662AB-B-IS1
Si8663AB-B-IS1
Notes:
1
2
1
3
3
2
2
4
4
3
3
2
2
5
4
3
6
5
4
3
0
0
1
0
0
1
1
0
0
1
1
2
2
0
1
2
0
1
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
SOIC-8
SOIC-8
SOIC-8
WB SOIC-16
NB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
NB SOIC-16
WB SOIC-16
NB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
silabs.com | Building a more connected world.
Rev. 1.01 | 2
Si86xx Data Sheet
Ordering Guide
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-
duction steps.
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering Part Number
(OPN)
Number of Number of
Inputs Inputs
VDD1 Side VDD2 Side
Max Data
Rate
(Mbps)
Default
Output
State
Isolation
Rating (kV)
Temp (°C)
Package
Si8621AB-AS
Si8663AB-AS1
1
3
1
3
1
1
Low
Low
2.5
2.5
–40 to 125 °C
–40 to 125 °C
SOIC-8
SOIC-16
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-
tative for further information.
silabs.com | Building a more connected world.
Rev. 1.01 | 3
Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.1 Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.2 Output Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . . 8
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 Pin Descriptions (Si861x/2x Narrow Body SOIC-8) . . . . . . . . . . . . . . . . .30
5.2 Pin Descriptions (Si863x) . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.3 Pin Descriptions (Si864x) . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.4 Pin Descriptions (Si8650/51/52) . . . . . . . . . . . . . . . . . . . . . . . .33
5.5 Pin Descriptions (Si866x) . . . . . . . . . . . . . . . . . . . . . . . . . .34
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Package Outline (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . .35
6.2 Package Outline (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . .37
6.3 Package Outline (8-Pin Narrow Body SOIC). . . . . . . . . . . . . . . . . . . .39
7. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.1 Land Pattern (16-Pin Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . .40
7.2 Land Pattern (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . .41
7.3 Land Pattern (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . .42
8. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . .43
8.2 Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . .44
8.3 Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . .45
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
silabs.com | Building a more connected world.
Rev. 1.01 | 4
Si86xx Data Sheet
Functional Description
2. Functional Description
2.1 Theory of Operation
The operation of an Si86xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si86xx channel is shown in the figure below.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 2.2. Modulation Scheme
silabs.com | Building a more connected world.
Rev. 1.01 | 5
Si86xx Data Sheet
Device Operation
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on
page 8, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to the table below to
determine outputs when power supply (VDD) is not present. Additionally, refer to Table 3.2 Enable Input Truth1 on page 7 for logic
conditions when enable pins are used.
Table 3.1. Si86xx Logic Operation
VO Output1,2
VI
Input1,2
EN
Input1,2,3,4
VDDI
State1,5,6
VDDO
State1,5,6
Comments
H
L
H or NC
H or NC
L
P
P
P
P
P
P
H
L
Enabled, normal operation.
X7
X7
Hi-Z8
L
Disabled.
H or NC
UP
P
Upon transition of VDDI from unpowered to powered, VO re-
turns to the same state as VI in less than 1 µs.
X7
X7
Hi-Z8
L
UP
P
P
Disabled.
X7
UP
Undetermined Upon transition of VDDO from unpowered to powered, VO re-
turns to the same state as VI within 1 µs, if EN is in either the
H or NC state. Upon transition of VDDO from unpowered to
powered, VO returns to Hi-Z within 1 µs if EN is L.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the
enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is operating in noisy
environments.
4. No Connect (NC) replaces EN1 on some devices. No Connects are not internally connected and can be left floating, tied to VDD,
or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
silabs.com | Building a more connected world.
Rev. 1.01 | 6
Si86xx Data Sheet
Device Operation
Table 3.2. Enable Input Truth1
EN11,2 EN21,2
P/N
Operation
Si861x/2x
Si8630
—
—
—
—
H
L
Outputs are enabled and follow input state.
Outputs B1, B2, B3 are enabled and follow input state.
Outputs B1, B2, B3 are disabled and in high impedance state.3
Output A3 enabled and follows input state.
Si8631
H
L
X
X
Output A3 disabled and in high impedance state.3
Outputs B1, B2 are enabled and follow input state.
X
X
H
L
Outputs B1, B2 are disabled and in high impedance state.3
Outputs B1, B2, B3, B4 are enabled and follow the input state.
Si8640
Si8641
—
—
H
L
Outputs B1, B2, B3, B4 are disabled and in high impedance state.3
Output A4 enabled and follows the input state.
H
L
X
X
Output A4 disabled and in high impedance state.3
X
X
H
L
Outputs B1, B2, B3 are enabled and follow the input state.
Outputs B1, B2, B3 are disabled and in high impedance state.3
Outputs A3 and A4 are enabled and follow the input state.
Si8642
H
L
X
X
Outputs A3 and A4 are disabled and in high impedance state.3
Outputs B1 and B2 are enabled and follow the input state.
X
X
H
L
Outputs B1 and B2 are disabled and in high impedance state.3
Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
Si8650
Si8651
—
—
H
L
Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance state.3
Output A5 enabled and follow input state.
H
L
X
X
Output A5 disabled and in high impedance state.3
X
X
H
L
Outputs B1, B2, B3, B4 are enabled and follow input state.
Outputs B1, B2, B3, B4 are disabled and in high impedance state.3
Outputs A4 and A5 are enabled and follow input state.
Si8652
Si866x
H
L
X
X
Outputs A4 and A5 are disabled and in high impedance state.3
Outputs B1, B2, B3 are enabled and follow input state.
X
X
H
L
Outputs B1, B2, B3 are disabled and in high impedance state.3
Outputs are enabled and follow input state.
—
—
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are internally
pulled-up to local VDD by a 2 µA current source allowing them to be connected to an external logic level (high or low) or left
floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused,
it is recommended they be connected to an external logic level, especially if the Si86xx is operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
silabs.com | Building a more connected world.
Rev. 1.01 | 7
Si86xx Data Sheet
Device Operation
3.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
3.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
OUTPUT
Figure 3.1. Device Behavior during Normal Operation
3.3 Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.5 Regulatory Information1 on
page 25 and Table 4.6 Insulation and Safety-Related Specifications on page 25 detail the working voltage and creepage/clearance
capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted
by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1,
60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.
3.3.1 Supply Bypass
The Si86xx family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed
as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series
with the inputs and outputs if the system is excessively noisy.
3.3.2 Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-
chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will
be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
silabs.com | Building a more connected world.
Rev. 1.01 | 8
Si86xx Data Sheet
Electrical Specifications
4. Electrical Specifications
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient Operating Temperature1
Supply Voltage
TA
–40
25
125
ºC
VDD1
VDD2
2.5
2.5
—
—
5.5
5.5
V
V
Note:
1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply
voltage.
Table 4.2. Electrical Characteristics
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
VDDUV+
VDDUV–
VDDHYS
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
V
VDD Undervoltage
Hysteresis
mV
Positive-Going Input Threshold
VT+
VT–
All inputs rising
All inputs falling
1.4
1.0
1.67
1.23
1.9
1.4
V
V
Negative-Going
Input Threshold
Input Hysteresis
VHYS
VIH
0.38
2.0
—
0.44
—
0.50
—
V
V
V
V
High Level Input Voltage
Low Level input voltage
High Level Output Voltage
VIL
—
0.8
—
VOH
loh = –4 mA
lol = 4 mA
VDD1,VDD2
0.4
–
4.8
Low Level Output Voltage
Input Leakage Current
VOL
IL
—
—
—
—
—
0.2
—
0.4
±10
—
V
µA
Ω
Output Impedance1
ZO
50
Εναβλε Ινπυτ Ηιγη Χυρρεντ
Enable Input Low Current
ΙENH
IENL
ςENx = VIH
VENx = VIL
2.0
2.0
—
µA
µA
—
DC Supply Current (All inputs 0 V or at Supply)
Si8610Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
mA
VDD2
VDD1
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 9
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
0.8
1.4
3.3
1.4
Max
1.4
2.2
5.3
2.2
Unit
Si8620Ax
VDD1
VI = 0(Ax)
mA
—
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
VDD2
—
VDD1
VDD2
Si8621Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
mA
mA
mA
mA
mA
mA
VDD2
VDD1
VDD2
Si8630Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.9
1.9
4.6
1.9
1.6
3.0
7.4
3.0
VDD2
VDD1
VDD2
Si8631Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.3
1.7
3.9
3.0
2.1
2.7
5.9
4.5
VDD2
VDD1
VDD2
Si8640Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
VDD2
VDD1
VDD2
Si8641Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.4
2.3
5.2
3.6
2.2
3.7
7.8
5.4
VDD2
VDD1
VDD2
Si8642Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
VDD2
VDD1
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 10
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
1.1
3.1
7.0
3.3
Max
1.8
4.7
9.8
5.0
Unit
Si8650Ax
VDD1
VI = 0(Ax)
mA
—
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
VDD2
—
VDD1
VDD2
Si8651Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.5
2.7
6.6
4.0
2.4
4.1
9.2
6.0
mA
mA
mA
mA
mA
mA
VDD2
VDD1
VDD2
Si8652Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.0
2.4
5.6
5.0
3.0
3.6
7.8
7.5
VDD2
VDD1
VDD2
Si8660Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
VDD2
VDD1
VDD2
Si8661Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
VDD2
VDD1
VDD2
Si8662Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
VDD2
VDD1
VDD2
Si8663Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
VDD2
VDD1
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 11
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all Outputs)
Si8610Ax
VDD1
—
—
1.2
0.9
2.0
1.5
mA
VDD2
Si8620Ax
VDD1
—
—
2.1
1.6
3.1
2.4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD2
Si8621Ax
VDD1
—
—
1.9
1.9
2.9
2.9
VDD2
Si8630Ax
VDD1
—
—
2.8
2.2
3.9
3.1
VDD2
Si8631Ax
VDD1
—
—
2.7
2.6
3.8
3.6
VDD2
Si8640Ax
VDD1
—
—
3.6
2.9
5.0
4.0
VDD2
Si8641Ax
VDD1
—
—
3.4
3.3
4.8
4.6
VDD2
Si8642Ax
VDD1
—
—
3.3
3.3
4.6
4.6
VDD2
Si8650Ax
VDD1
—
—
4.1
3.7
5.7
5.2
VDD2
Si8651Ax
VDD1
—
—
4.2
3.8
5.8
5.3
VDD2
Si8652Ax
VDD1
—
—
4.0
4.0
5.6
5.6
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 12
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
5.0
4.2
Max
7.0
Unit
Si8660Ax
VDD1
mA
—
5.9
VDD2
Si8661Ax
VDD1
—
—
4.9
4.6
6.9
6.4
mA
mA
mA
VDD2
Si8662Ax
VDD1
—
—
5.1
4.7
7.1
6.6
VDD2
Si8663Ax
VDD1
—
—
4.9
4.9
6.8
6.8
VDD2
Timing Characteristics
All Models
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
—
1
Mbps
ns
—
—
250
35
tPHL, tPLH
See Figure 4.2 Propagation
Delay Timing on page 14
ns
Pulse Width Distortion
PWD
See Figure 4.2 Propagation
Delay Timing on page 14
—
—
25
ns
|tPLH – tPHL
|
Propagation Delay Skew2
Channel-Channel Skew
Output Rise Time
tPSK(P-P)
tPSK
tr
—
—
—
—
—
40
35
ns
ns
ns
CL = 15 pF
2.5
4.0
See Figure 4.2 Propagation
Delay Timing on page 14
Output Fall Time
tf
CL = 15 pF
—
2.5
4.0
ns
See Figure 4.2 Propagation
Delay Timing on page 14
Peak eye diagram jitter
tJIT(PK)
CMTI
See Figure 2.2 Modulation
Scheme on page 5
—
350
50
—
—
ps
Common Mode
VI = VDD or 0 V
35
kV/µs
Transient Immunity
VCM = 1500 V (See Figure
4.3 Common-Mode Transient
Immunity Test Circuit on page
15)
Enable to Data Valid
ten1
See Figure 4.1 ENABLE Tim-
ing Diagram on page 14
—
—
6.0
8.0
11
12
ns
ns
Enable to Data Tri-State
ten2
See Figure 4.1 ENABLE Tim-
ing Diagram on page 14
silabs.com | Building a more connected world.
Rev. 1.01 | 13
Si86xx Data Sheet
Electrical Specifications
Parameter
Start-up Time3
Notes:
Symbol
Test Condition
Min
Typ
Max
Unit
tSU
—
15
40
µs
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
ENABLE
OUTPUTS
ten1
ten2
Figure 4.1. ENABLE Timing Diagram
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 4.2. Propagation Delay Timing
silabs.com | Building a more connected world.
Rev. 1.01 | 14
Si86xx Data Sheet
Electrical Specifications
3 to 5 V
Supply
Si86xx
VDD1
VDD2
Input
Signal
Switch
INPUT
OUTPUT
3 to 5 V
Isolated
Supply
Oscilloscope
GND1
GND2
Isolated
Ground
High Voltage
Differential
Probe
Output
Input
Vcm Surge
Output
High Voltage
Surge Generator
Figure 4.3. Common-Mode Transient Immunity Test Circuit
Table 4.3. Electrical Characteristics
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 °C)
Parameter
Symbol
VDDUV+
VDDUV–
VDDHYS
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
1.95
1.88
50
Typ
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
2.24
2.16
70
V
VDD Undervoltage
Hysteresis
mV
Positive-Going Input
Threshold
VT+
VT–
All inputs rising
All inputs falling
1.4
1.0
1.67
1.23
1.9
1.4
V
V
Negative-Going Input
Threshold
Input Hysteresis
VHYS
VIH
0.38
0.44
—
0.50
—
V
V
V
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
2.0
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
—
VOH
VOL
loh = –4 mA
lol = 4 mA
3.1
0.2
0.4
silabs.com | Building a more connected world.
Rev. 1.01 | 15
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
—
Max
±10
—
Unit
µA
Ω
Input Leakage Current
IL
Output Impedance1
ZO
—
50
Enable Input High Current
Enable Input Low Current
IENH
IENL
VENx = VIH
VENx = VIL
—
—
2.0
2.0
—
—
µA
µA
DC Supply Current (All inputs 0 V or at supply)
Si8610Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
mA
mA
mA
mA
mA
mA
VDD2
VDD1
VDD2
Si8620Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
VDD2
VDD1
VDD2
Si8621Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
VDD2
VDD1
VDD2
Si8630Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.9
1.9
4.6
1.9
1.6
3.0
7.4
3.0
VDD2
VDD1
VDD2
Si8631Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.3
1.7
3.9
3.0
2.1
2.7
5.9
4.5
VDD2
VDD1
VDD2
Si8640Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
VDD2
VDD1
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 16
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
1.4
2.3
5.2
3.6
Max
2.2
3.7
7.8
5.4
Unit
Si8641Ax
VDD1
VI = 0(Ax)
mA
—
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
VDD2
—
VDD1
VDD2
Si8642Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
mA
mA
mA
mA
mA
mA
VDD2
VDD1
VDD2
Si8650Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.1
3.1
7.0
3.3
1.8
4.7
9.8
5.0
VDD2
VDD1
VDD2
Si8651Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.5
2.7
6.6
4.0
2.4
4.1
9.2
6.0
VDD2
VDD1
VDD2
Si8652Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.0
2.4
5.6
5.0
3.0
3.6
7.8
7.5
VDD2
VDD1
VDD2
Si8660Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
VDD2
VDD1
VDD2
Si8661Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
VDD2
VDD1
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 17
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
2.2
3.0
7.5
5.6
Max
3.3
Unit
Si8662Ax
VDD1
VI = 0(Ax)
mA
—
4.5
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
10.5
8.4
VDD2
—
VDD1
VDD2
Si8663Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
mA
VDD2
VDD1
VDD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8610Ax
VDD1
—
—
1.2
0.9
2.0
1.5
mA
mA
mA
mA
mA
mA
mA
mA
VDD2
Si8620Ax
VDD1
—
—
2.1
1.6
3.1
2.4
VDD2
Si8621Ax
VDD1
—
—
1.9
1.9
2.9
2.9
VDD2
Si8630Ax
VDD1
—
—
2.8
2.2
3.9
3.1
VDD2
Si8631Ax
VDD1
—
—
2.7
2.6
3.8
3.6
VDD2
Si8640Ax
VDD1
—
—
3.6
2.9
5.0
4.0
VDD2
Si8641Ax
VDD1
—
—
3.4
3.3
4.8
4.6
VDD2
Si8642Ax
VDD1
—
—
3.3
3.3
4.6
4.6
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 18
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
4.1
3.7
Max
5.7
Unit
Si8650Ax
VDD1
mA
—
5.2
VDD2
Si8651Ax
VDD1
—
—
4.2
3.8
5.8
5.3
mA
mA
mA
mA
mA
mA
VDD2
Si8652Ax
VDD1
—
—
4.0
4.0
5.6
5.6
VDD2
Si8660Ax
VDD1
—
—
5.0
4.2
7.0
5.9
VDD2
Si8661Ax
VDD1
—
—
4.9
4.6
6.9
6.4
VDD2
Si8662Ax
VDD1
—
—
5.1
4.7
7.1
6.6
VDD2
Si8663Ax
VDD1
—
—
4.9
4.9
6.8
6.8
VDD2
Timing Characteristics
All Models
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
—
1
Mbps
ns
—
—
250
35
tPHL, tPLH
See Figure 4.2 Propaga-
tion Delay Timing on page
14
ns
Pulse Width Distortion
PWD
See Figure 4.2 Propaga-
tion Delay Timing on page
14
—
—
25
ns
|tPLH – tPHL
|
Propagation Delay Skew2
Channel-Channel Skew
Output Rise Time
tPSK(P-P)
tPSK
tr
—
—
—
—
—
40
35
ns
ns
ns
CL = 15 pF
2.5
4.0
See Figure 4.2 Propaga-
tion Delay Timing on page
14
silabs.com | Building a more connected world.
Rev. 1.01 | 19
Si86xx Data Sheet
Electrical Specifications
Parameter
Output Fall Time
Symbol
Test Condition
Min
Typ
Max
Unit
tf
CL = 15 pF
—
2.5
4.0
ns
See Figure 4.2 Propaga-
tion Delay Timing on page
14
Peak eye diagram jitter
tJIT(PK)
CMTI
See Figure 2.2 Modula-
tion Scheme on page 5
—
350
50
—
—
ps
Common Mode
VI = VDD or 0 V
35
kV/µs
Transient Immunity
VCM = 1500 V (see Figure
4.3 Common-Mode Tran-
sient Immunity Test Cir-
cuit on page 15)
Enable to Data Valid
ten1
ten2
tSU
See Figure 4.1 ENABLE
Timing Diagram on page
14
—
—
—
6.0
8.0
15
11
12
40
ns
ns
µs
Enable to Data Tri-State
See Figure 4.1 ENABLE
Timing Diagram on page
14
Start-Up Time3
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Table 4.4. Electrical Characteristics
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter
Symbol
VDDUV+
VDDUV–
VDDHYS
VT+
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
V
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
0.38
2.0
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
VIH
V
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
lol = 4 mA
VDD1,VDD
2 – 0.4
2.3
—
V
Low Level Output Voltage
Input Leakage Current
VOL
IL
—
—
—
0.2
—
0.4
±10
—
V
µA
Ω
Output Impedance1
ZO
50
silabs.com | Building a more connected world.
Rev. 1.01 | 20
Si86xx Data Sheet
Electrical Specifications
Parameter
Enable Input High Current
Enable Input Low Current
Symbol
IENH
Test Condition
VENx = VIH
Min
—
Typ
2.0
2.0
Max
—
Unit
µA
IENL
VENx = VIL
—
—
µA
DC Supply Current (All inputs 0 V or at supply)
Si8610Ax
VDD1
VI = 0(Ax))
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
mA
mA
mA
mA
mA
mA
VDD2
VDD1
VDD2
Si8620Ax
VDD1
VI = 0(Ax))
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
VDD2
VDD1
VDD2
Si8621Ax
VDD1
VI = 0(Ax))
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
VDD2
VDD1
VDD2
Si8630Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
0.9
1.9
4.6
1.9
1.6
3.0
7.4
3.0
VDD2
VDD1
VDD2
Si8631Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.3
1.7
3.9
3.0
2.1
2.7
5.9
4.5
VDD2
VDD1
VDD2
Si8640Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.0
2.4
6.1
2.5
1.6
3.8
9.2
4.0
VDD2
VDD1
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 21
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
1.4
2.3
5.2
3.6
Max
2.2
3.7
7.8
5.4
Unit
Si8641Ax
VDD1
VI = 0(Ax)
mA
—
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
VDD2
—
VDD1
VDD2
Si8642Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.8
1.8
4.4
4.4
2.9
2.9
6.6
6.6
mA
mA
mA
mA
mA
mA
VDD2
VDD1
VDD2
Si8650Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.1
3.1
7.0
3.3
1.8
4.7
9.8
5.0
VDD2
VDD1
VDD2
Si8651Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.5
2.7
6.6
4.0
2.4
4.1
9.2
6.0
VDD2
VDD1
VDD2
Si8652Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.0
2.4
5.6
5.0
3.0
3.6
7.8
7.5
VDD2
VDD1
VDD2
Si8660Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
VDD2
VDD1
VDD2
Si8661Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
VDD2
VDD1
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 22
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
2.2
3.0
7.5
5.6
Max
3.3
Unit
Si8662Ax
VDD1
VI = 0(Ax)
mA
—
4.5
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
10.5
8.4
VDD2
—
VDD1
VDD2
Si8663Ax
VDD1
VI = 0(Ax)
VI = 0(Ax)
VI = 1(Ax)
VI = 1(Ax)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
mA
VDD2
VDD1
VDD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8610Ax
VDD1
—
—
1.2
0.9
2.0
1.5
mA
mA
mA
mA
mA
mA
mA
mA
VDD2
Si8620Ax
VDD1
—
—
2.1
1.6
3.1
2.4
VDD2
Si8621Ax
VDD1
—
—
1.9
1.9
2.9
2.9
VDD2
Si8630Ax
VDD1
—
—
2.8
2.2
3.9
3.1
VDD2
Si8631Ax
VDD1
—
—
2.7
2.6
3.8
3.6
VDD2
Si8640Ax
VDD1
—
—
3.6
2.9
5.0
4.0
VDD2
Si8641Ax
VDD1
—
—
3.4
3.3
4.8
4.6
VDD2
Si8642Ax
VDD1
—
—
3.3
3.3
4.6
4.6
VDD2
silabs.com | Building a more connected world.
Rev. 1.01 | 23
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
4.1
3.7
Max
5.7
Unit
Si8650Ax
VDD1
mA
—
5.2
VDD2
Si8651Ax
VDD1
—
—
4.2
3.8
5.8
5.3
mA
mA
mA
mA
mA
mA
VDD2
Si8652Ax
VDD1
—
—
4.0
4.0
5.6
5.6
VDD2
Si8660Ax
VDD1
—
—
5.0
4.2
7.0
5.9
VDD2
Si8661Ax
VDD1
—
—
4.9
4.6
6.9
6.4
VDD2
Si8662Ax
VDD1
—
—
5.1
4.7
7.1
6.6
VDD2
Si8663Ax
VDD1
—
—
4.9
4.9
6.8
6.8
VDD2
Timing Characteristics
All Models
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
—
1
Mbps
ns
—
—
250
35
tPHL, tPLH
See Figure 4.2 Propagation Delay
Timing on page 14
ns
Pulse Width Distortion
PWD
See Figure 4.2 Propagation Delay
Timing on page 14
—
—
25
ns
|tPLH - tPHL
|
Propagation Delay Skew2
Channel-Channel Skew
Output Rise Time
tPSK(P-P)
tPSK
tr
—
—
—
—
—
40
35
ns
ns
ns
CL = 15 pF
2.5
4.0
See Figure 4.2 Propagation Delay
Timing on page 14
Output Fall Time
tf
CL = 15 pF
—
2.5
4.0
ns
See Figure 4.2 Propagation Delay
Timing on page 14
silabs.com | Building a more connected world.
Rev. 1.01 | 24
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.2 Modulation Scheme
on page 5
—
350
—
ps
Common Mode
CMTI
VI = VDD or 0 V
35
50
—
kV/µs
Transient Immunity
VCM = 1500 V (see Figure
4.3 Common-Mode Transient Im-
munity Test Circuit on page 15)
Enable to Data Valid
ten1
ten2
tSU
See Figure 4.1 ENABLE Timing Di-
agram on page 14
—
—
—
6.0
8.0
15
11
12
40
ns
ns
µs
Enable to Data Tri-State
See Figure 4.1 ENABLE Timing Di-
agram on page 14
Startup Time3
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Table 4.5. Regulatory Information1
CSA
The Si86xx is certified under CSA Component Acceptance Notice 5A, IEC61010-1 and IEC60950-1. For more details, see File
232873.
VDE
The Si86xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
UL
The Si86xx is certified under UL1577 component recognition program. For more details, see File E257455.
CQC
The Si86xx is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see 5.5 Pin Descriptions (Si866x).
Table 4.6. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
Unit
WB SO-
IC-16
NB SO-
IC-16
NB SOIC-8
Nominal Air Gap (Clearance)1
L(IO1)
L(IO2)
8.0
8.0
4.9
4.9
mm
mm
Nominal External Tracking
(Creepage)1
4.01
4.01
Minimum Internal Gap
(Internal Clearance)
0.014
0.014
0.014
mm
silabs.com | Building a more connected world.
Rev. 1.01 | 25
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Value
Unit
WB SO-
IC-16
NB SO-
IC-16
NB SOIC-8
Tracking Resistance
PTI
600
600
600
VRMS
IEC60112
(Proof Tracking Index)
Erosion Depth
ED
0.019
0.019
0.040
mm
Ω
Resistance (Input-Output)2
Capacitance (Input-Output)2
1012
2.0
1012
2.0
1012
2.0
RIO
ΧIO
CI
f = 1 ΜΗz
pF
pF
Input Capacitance3
4.0
4.0
4.0
Notes:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage
limits as 4.7 mm minimum for the NB SOIC-16 and SOIC-8 packages and 8.5 mm minimum for the WB SOIC-16 package. UL
does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance and cree-
page limits as 3.9 mm minimum for the NB SOIC-16 and SOIC-8 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 (Pins 1-4 for the NB SOIC-8)
are shorted together to form the first terminal and pins 9–16 (Pins 5-8 for the NB SOIC-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 4.7. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Test Conditions
Specification
NB SOIC-16
WB SOIC-16
NB SOIC-8
Basic Isolation Group
Material Group
I
I
Installation Classification
Rated Mains Voltages < 150 VRMS
Rated Mains Voltages < 300 VRMS
Rated Mains Voltages < 400 VRMS
Rated Mains Voltages < 600 VRMS
I-IV
I-III
I-II
I-II
I-IV
I-IV
I-III
I-III
Table 4.8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx*
Parameter
Symbol
Test Condition
Characteristic
WB NB
Unit
SOIC-16
SOIC-16
SOIC-8
630
Maximum Working Insulation Volt-
age
VIORM
1200
2250
Vpeak
Input to Output Test Voltage
VPR
Method b1
1182
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
Transient Overvoltage
VIOTM
t = 60 sec
6000
2
6000
2
Vpeak
Pollution Degree
(DIN VDE 0110, Table 1)
silabs.com | Building a more connected world.
Rev. 1.01 | 26
Si86xx Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Characteristic
Unit
WB
NB
SOIC-16
SOIC-16
SOIC-8
>109
>109
Insulation Resistance at TS, VIO
500 V
=
RS
Ω
Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21.
Table 4.9. IEC Safety Limiting Values1
Parameter
Symbol
Test Condition
Max
Unit
WB
NB
NB
SOIC-16
SOIC-16
SOIC-8
Case Temperature
TS
ΙS
150
220
150
215
150
160
°Χ
Σαϕετψ Ινπυτ, Ουτπυτ, ορ
Συππλψ Χυρρεντ
θJA = 100 °C/W (WB SOIC-16), 105
°C/W (NB SOIC-16),
mA
140 °C/W (NB SOIC-8),
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Device Power
Dissipation2
PD
415
415
150
mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.4 Figure 5.4 on page 28,
Figure 4.5 Figure 5.5 on page 28 and Figure 4.6 Figure 5.6 on page 29.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
Table 4.10. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-16
NB SOIC-8
Unit
IC Junction-to-Air Thermal
Resistance
θJA
100
105
140
ºC/W
silabs.com | Building a more connected world.
Rev. 1.01 | 27
Si86xx Data Sheet
Electrical Specifications
500
450
370
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
400
300
200
100
0
220
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 4.4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
500
430
VDD1, VDD2 = 2.70 V
400
360
VDD1, VDD2 = 3.6 V
300
215
200
VDD1, VDD2 = 5.5 V
100
0
0
50
100
150
200
Temperature (ºC)
Figure 4.5. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
silabs.com | Building a more connected world.
Rev. 1.01 | 28
Si86xx Data Sheet
Electrical Specifications
400
300
200
100
0
320
270
VDD1, VDD2 = 2.5 V
VDD1, VDD2 = 3.3 V
VDD1, VDD2 = 5.5 V
160
0
50
100
150
200
Case Temperature (ºC)
Figure 4.6. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 4.11. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Unit
Storage Temperature2
Ambient Temperature Under Bias
Junction Temperature
Supply Voltage
TSTG
–65
150
ºC
TA
–40
—
125
150
ºC
°C
V
TJ
VDD1, VDD2
–0.5
–0.5
–0.5
—
7.0
Input Voltage
VI
VO
IO
VDD + 0.5
VDD + 0.5
10
V
Output Voltage
V
Output Current Drive Channel
mA
(All devices unless otherwise stated)
Output Current Drive Channel
(All Si86xxxA-x-xx devices)
IO
—
—
22
mA
Latchup Immunity3
100
V/ns
Lead Solder Temperature (10 s)
—
—
260
ºC
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16, SOIC-8
4500
VRMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
—
6500
VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. Latchup immunity specification is for slew rate applied across GND1 and GND2.
silabs.com | Building a more connected world.
Rev. 1.01 | 29
Si86xx Data Sheet
Pin Descriptions
5. Pin Descriptions
5.1 Pin Descriptions (Si861x/2x Narrow Body SOIC-8)
VDD1
VDD1
VDD1
VDD2
VDD2
VDD2
B1
I
s
o
l
a
t
I
s
o
l
a
t
I
s
o
l
a
t
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
GND2/NC
B1
A1
A2
A1
A2
A1
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
VDD1/NC
B2
B1
B2
i
i
i
o
n
o
n
o
n
GND2 GND1
GND2 GND1
GND2
GND1
Si8621 NB SOIC-8
Si8610 NB SOIC-8
Si8620 NB SOIC-8
Figure 5.1. Si861x/2x Narrow Body SOIC-8 Pin Descriptions
Table 5.1. Si861x/2x Narrow Body SOIC-8 Pin Descriptions
Name
SOIC-8 Pin#
SOIC-8 Pin#
Type
Description
Si861x
1,3
4
Si862x
VDD1/NC*
GND1
A1
1
4
2
3
7
6
8
5
Supply
Ground
Side 1 power supply.
Side 1 ground.
2
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Side 1 digital input or output.
Side 1 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
A2
NA
6
B1
B2
NA
8
VDD2
GND2/NC*
5, 7
Ground
Side 2 ground.
Note: No connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
silabs.com | Building a more connected world.
Rev. 1.01 | 30
Si86xx Data Sheet
Pin Descriptions
5.2 Pin Descriptions (Si863x)
VDD1
VDD1
VDD2
GND2
B1
VDD2
GND2
B1
GND1
GND1
I
s
o
l
I
s
o
l
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A1
A2
A1
A2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B2
B2
a
t
i
o
n
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
A3
NC
B3
A3
NC
B3
NC
NC
EN2
GND2
EN2
GND2
NC
EN1
GND1
GND1
Si8630
Si8631
Figure 5.2. Si863x Pin Descriptions
Table 5.2. Si863x Pin Descriptions
Name
VDD1
GND1
A1
SOIC-16 Pin#
Type
Description
1
21
3
Supply
Ground
Side 1 power supply.
Side 1 ground.
Digital Input
Digital Input
Digital I/O
NA
Side 1 digital input.
Side 1 digital input.
Side 1 digital input or output.
No Connect.
A2
4
A3
5
NC
6
EN1/NC2
GND1
GND2
EN2
7
Digital Input
Ground
Side 1 active high enable. NC on Si8630
Side 1 ground.
81
91
10
11
12
13
14
151
16
Ground
Side 2 ground.
Digital Input
NA
Side 2 active high enable.
No Connect.
NC
B3
Digital I/O
Digital Output
Digital Output
Ground
Side 2 digital input or output.
Side 2 digital output.
Side 2 digital output.
Side 2 ground.
B2
B1
GND2
VDD2
Notes:
Supply
Side 2 power supply.
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be
connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
silabs.com | Building a more connected world.
Rev. 1.01 | 31
Si86xx Data Sheet
Pin Descriptions
5.3 Pin Descriptions (Si864x)
VDD1
VDD1
VDD1
VDD2
GND2
B1
VDD2
GND2
B1
VDD2
GND2
GND1
GND1
GND1
I
I
s
o
l
I
s
o
l
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
s
o
l
B1
A1
A2
A1
A2
A1
A2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B2
B2
B2
a
t
i
o
n
a
t
i
o
n
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
A3
A4
B3
A3
A4
B3
A3
A4
B3
XMITR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
B4
B4
B4
EN2
GND2
EN2
GND2
EN2
GND2
NC
EN1
EN1
GND1
GND1
GND1
Si8640
Si8641
Si8642
Figure 5.3. Si864x Pin Descriptions
Table 5.3. Si864x Pin Descriptions
Name
VDD1
GND1
A1
SOIC-16 Pin#
Type
Description
1
21
3
Supply
Ground
Side 1 power supply.
Side 1 ground.
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital Input
Ground
Side 1 digital input.
Side 1 digital input.
A2
4
A3
5
Side 1 digital input or output.
Side 1 digital input or output.
A4
6
EN1/NC2
GND1
GND2
EN2
B4
7
Side 1 active high enable. NC on Si8640.
Side 1 ground.
81
91
10
11
12
13
14
151
16
Ground
Side 2 ground.
Digital Input
Digital I/O
Digital I/O
Digital Output
Digital Output
Ground
Side 2 active high enable.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 digital output.
B3
B2
B1
Side 2 digital output.
GND2
VDD2
Side 2 ground.
Supply
Side 2 power supply.
Notes:
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be
connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
silabs.com | Building a more connected world.
Rev. 1.01 | 32
Si86xx Data Sheet
Pin Descriptions
5.4 Pin Descriptions (Si8650/51/52)
VDD1
VDD1
A1
VDD1
VDD2
B1
VDD2
B1
VDD2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B1
A1
A2
A1
A2
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B2
A2
B2
B2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B3
A3
B3
A3
A4
A5
B3
A3
A4
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
A4
B4
B4
B4
XMITR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
A5
B5
A5
B5
B5
EN2
GND2
EN2
GND2
EN2
GND2
NC
EN1
GND1
EN1
GND1
GND1
Si8650
Si8651
Si8652
Figure 5.4. Si865x Pin Descriptions
Table 5.4. Si865x Pin Descriptions
Name
SOIC-16 Pin#
Type
Description
VDD1
A1
1
2
Supply
Digital Input
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital Input
Ground
Side 1 power supply.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
A2
3
A3
4
A4
5
Side 1 digital input or output.
Side 1 digital input or output.
A5
6
EN1/NC*
GND1
GND2
EN2
B5
7
Side 1 active high enable. NC on Si8650.
Side 1 ground.
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital Input
Digital I/O
Digital I/O
Digital Output
Digital Output
Digital Output
Supply
Side 2 active high enable.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 digital output.
B4
B3
B2
Side 2 digital output.
B1
Side 2 digital output.
VDD2
Side 2 power supply.
Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
silabs.com | Building a more connected world.
Rev. 1.01 | 33
Si86xx Data Sheet
Pin Descriptions
5.5 Pin Descriptions (Si866x)
VDD1
VDD1
A1
A2
A3
A4
A5
A6
VDD1
VDD1
VDD2
B1
B2
B3
B4
B5
B6
VDD2
B1
B2
B3
B4
B5
B6
VDD2
B1
VDD2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
RCVR
RF
XMITR
RF
XMITR
B1
A1
A2
A1
A2
A1
A2
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B2
s
o
l
a
t
i
o
n
B2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A3
A4
A5
A6
B3
A3
A4
A5
A6
B3
A3
A4
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
B4
B4
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
A5
B5
B5
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RF
RCVR
RF
A6
B6
B6
XMITR
XMITR
GND1
GND2 GND1
GND2 GND1
GND2 GND1
GND2
Si8660
Si8661
Si8662
Si8663
Figure 5.5. Si866x Pin Descriptions
Table 5.5. Si866x Pin Descriptions
Name
VDD1
A1
SOIC-16 Pin#
Type
Description
1
2
Supply
Digital Input
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital I/O
Ground
Side 1 power supply.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
A2
3
A3
4
A4
5
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 ground.
A5
6
A6
7
GND1
GND2
B6
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital I/O
Digital I/O
Digital I/O
Digital Output
Digital Output
Digital Output
Supply
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 digital output.
B5
B4
B3
B2
Side 2 digital output.
B1
Side 2 digital output.
VDD2
Side 2 power supply.
silabs.com | Building a more connected world.
Rev. 1.01 | 34
Si86xx Data Sheet
Package Outlines
6. Package Outlines
6.1 Package Outline (16-Pin Wide Body SOIC)
The figure below illustrates the package details for the Si86xx Digital Isolator. The table below lists the values for the dimensions shown
in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
silabs.com | Building a more connected world.
Rev. 1.01 | 35
Si86xx Data Sheet
Package Outlines
Table 6.1. Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
10.30 BSC
E
10.30 BSC
7.50 BSC
1.27 BSC
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
silabs.com | Building a more connected world.
Rev. 1.01 | 36
Si86xx Data Sheet
Package Outlines
6.2 Package Outline (16-Pin Narrow Body SOIC)
The figure below illustrates the package details for the Si86xx in a 16-pin narrow-body SOIC (SO-16). The table below lists the values
for the dimensions shown in the illustration.
Figure 6.2. 16-pin Small Outline Integrated Circuit (SOIC) Package
silabs.com | Building a more connected world.
Rev. 1.01 | 37
Si86xx Data Sheet
Package Outlines
Table 6.2. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
E
6.00 BSC
3.90 BSC
1.27 BSC
E1
e
L
0.40
1.27
L2
h
0.25 BSC
0.25
0°
0.50
8°
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.01 | 38
Si86xx Data Sheet
Package Outlines
6.3 Package Outline (8-Pin Narrow Body SOIC)
The figure below illustrates the package details for the Si86xx. The table below lists the values for the dimensions shown in the illustra-
tion.
Figure 6.3. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 6.3. Package Diagram Dimensions
Symbol
Millimeters
Min
1.35
Max
1.75
A
A1
A2
B
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
silabs.com | Building a more connected world.
Rev. 1.01 | 39
Si86xx Data Sheet
Land Patterns
7. Land Patterns
7.1 Land Pattern (16-Pin Wide-Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin wide-body SOIC. The table below lists the
values for the dimensions shown in the illustration.
Figure 7.1. 16-Pin SOIC Land Pattern
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
silabs.com | Building a more connected world.
Rev. 1.01 | 40
Si86xx Data Sheet
Land Patterns
7.2 Land Pattern (16-Pin Narrow Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin narrow-body SOIC. The table below lists
the values for the dimensions shown in the illustration.
Figure 7.2. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 7.2. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
silabs.com | Building a more connected world.
Rev. 1.01 | 41
Si86xx Data Sheet
Land Patterns
7.3 Land Pattern (8-Pin Narrow Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in an 8-pin narrow-body SOIC. The table below lists
the values for the dimensions shown in the illustration.
Figure 7.3. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 7.3. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
silabs.com | Building a more connected world.
Rev. 1.01 | 42
Si86xx Data Sheet
Top Markings
8. Top Markings
8.1 Top Marking (16-Pin Wide Body SOIC)
Si86XYSV
YYWWRTTTTT
e4
CC
Figure 8.1. 16-Pin Wide Body SOIC
Table 8.1. Top Marking Explanation (16-Pin Wide Body SOIC)
Line 1 Marking: Base Part Number
Si86 = Isolator product series
XY = Channel Configuration
Ordering Options
X = # of data channels (5, 4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)
(See 1. Ordering Guide for more information).
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
Line 2 Marking: YY = Year
Assigned by assembly subcontractor. Corresponds to the year
and work week of the mold date.
WW = Workweek
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Line 3 Marking: Circle = 1.7 mm Diameter
“e4” Pb-free symbol
(Center-Justified)
Country of Origin ISO Code Abbreviation
CC = Country of Origin ISO Code Abbreviation
• TW = Taiwan
• TH = Thailand
silabs.com | Building a more connected world.
Rev. 1.01 | 43
Si86xx Data Sheet
Top Markings
8.2 Top Marking (16-Pin Narrow Body SOIC)
Si86XYSV
YYWWRTTTTT
e3
Figure 8.2. 16-Pin Narrow Body SOIC
Table 8.2. Top Marking Explanation (16-Pin Narrow Body SOIC)
Line 1 Marking: Base Part Number
Si86 = Isolator product series
XY = Channel Configuration
Ordering Options
X = # of data channels (5, 4, 3, 2, 1)
Y = # of reverse channels (2, 1, 0)
(See 1. Ordering Guide for more information.)
S = Speed Grade (max data rate) and operating mode:
A = 1 Mbps (default output = low)
B = 150 Mbps (default output = low)
D = 1 Mbps (default output = high)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
“e3” Pb-Free Symbol
Line 2 Marking: Circle = 1.2 mm Diameter
YY = Year
Assigned by the assembly subcontractor. Corresponds to the
year and work week of the mold date.
WW = Work Week
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
silabs.com | Building a more connected world.
Rev. 1.01 | 44
Si86xx Data Sheet
Top Markings
8.3 Top Marking (8-Pin Narrow Body SOIC)
Si86XYSV
YYWWRT
e3
TTTT
Figure 8.3. 8-Pin Narrow Body SOIC
Table 8.3. Top Marking Explanation (8-Pin Narrow Body SOIC)
Line 1 Marking: Base Part Number
Si86 = Isolator Product Series
XY = Channel Configuration
S = Speed Grade (max data rate)
V = Insulation rating
Ordering Options
(See 1. Ordering Guide for more information).
Line 2 Marking: YY = Year
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
WW = Workweek
R = Product Revision
T = First character of the manufacturing code
Line 3 Marking: Circle = 1.1 mm Diameter
“e3” Pb-Free Symbol.
TTTT = Last four characters of the manufactur- Last four characters of the manufacturing code.
ing code
silabs.com | Building a more connected world.
Rev. 1.01 | 45
Si86xx Data Sheet
Revision History
9. Revision History
January 2018
• Updated data sheet format.
• Added new table to Ordering Guide for Automotive-Grade OPN options
Updated Table 4.5 Regulatory Information1 on page 25.
• Added CQC certificate numbers.
•
• Updated 1. Ordering Guide.
• Removed references to moisture sensitivity levels.
• Removed note 2.
silabs.com | Building a more connected world.
Rev. 1.01 | 46
Smart.
Connected.
Energy-Friendly.
Products
www.silabs.com/products
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®,
EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
Gecko®, ISOmodem®, Micrium, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri and others are trademarks or registered
trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other
products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
相关型号：
©2020 ICPDF网 联系我们和版权申明