SI8661BC-A-IS1 [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO16, ROHS COMPLIANT, MS-012AC, SOIC-16;型号: | SI8661BC-A-IS1 |
厂家: | SILICON |
描述: | Analog Circuit, 1 Func, CMOS, PDSO16, ROHS COMPLIANT, MS-012AC, SOIC-16 光电二极管 |
文件: | 总36页 (文件大小:451K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si8660/61/62/63
LOW POWER SIX-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage
2.5–5.5 V
Selectable fail-safe mode
Default high or low output
(ordering option)
Precise timing (typical)
10 ns propagation delay
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
Up to 5000 VRMS isolation
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
3.5 mA per channel at 100 Mbps
Schmitt trigger inputs
RoHS-compliant packages
SOIC-16 wide body
SOIC-16 narrow body
Applications
Ordering Information:
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated ADC, DAC
Motor control
Power inverters
See page 26.
Isolated switch mode supplies
Communication systems
Safety Regulatory Approvals
UL 1577 recognized
Up to 5000 VRMS for 1 minute
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation
delays of less than 10 ns. Ordering options include a choice of isolation ratings
(3.75 and 5 kV) and a selectable fail-safe operating mode to control the default
output state during power loss. All products >1 kVRMS are safety certified by
UL, CSA, and VDE, and products in wide-body packages support reinforced
insulation withstanding up to 5 kVRMS
.
Rev. 1.3 3/12
Copyright © 2012 by Silicon Laboratories
Si8660/61/62/63
Si8660/61/62/63
2
Rev. 1.3
Si8660/61/62/63
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2. Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.1. Si866x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10.2. Top Marking Explanation (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .33
10.3. Si866x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . .34
10.4. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.3
3
Si8660/61/62/63
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
Test Condition
Min
–40
2.5
Typ
25
—
Max
125
5.5
Unit
°C
V
T
150 Mbps, 15 pF, 5 V
A
V
DD1
DD2
V
2.5
—
5.5
V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
VDDUV+
VDDUV–
Test Condition
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
V
, V
rising
falling
DD1
DD2
DD2
V
, V
V
DD1
VDD Negative-Going
Lockout Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
VT+
VT–
All inputs rising
1.4
1.0
1.67
1.23
1.9
1.4
V
V
Negative-Going
Input Threshold
All inputs falling
Input Hysteresis
V
0.38
2.0
—
0.44
—
0.50
—
V
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
4.8
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
µA
L
1
Output Impedance
Z
50
O
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4
Rev. 1.3
Si8660/61/62/63
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Supply Current (All inputs 0 V or at Supply)
Si8660Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
mA
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8661Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
mA
mA
mA
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8662Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8663Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
V
V
—
—
5.0
4.2
7.0
5.9
mA
mA
mA
mA
DD1
DD2
Si8661Bx, Ex
V
V
—
—
4.9
4.6
6.9
6.4
DD1
DD2
Si8662Bx, Ex
V
V
—
—
5.1
4.7
7.1
6.6
DD1
DD2
Si8663Bx, Ex
V
V
—
—
4.9
4.9
6.8
6.8
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
5
Si8660/61/62/63
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
5.0
5.9
7.0
8.3
mA
mA
mA
mA
DD1
DD2
Si8661Bx, Ex
V
V
—
—
5.2
6.1
7.3
8.5
DD1
DD2
Si8662Bx, Ex
V
V
—
—
5.6
5.9
7.9
8.2
DD1
DD2
Si8663Bx, Ex
V
V
—
—
5.7
5.7
8.0
8.0
DD1
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
V
V
—
—
5.0
26.2
7.0
34.1
mA
mA
mA
mA
DD1
DD2
Si8661Bx, Ex
V
V
—
—
8.8
23
11.8
29.8
DD1
DD2
Si8662Bx, Ex
V
V
—
—
12.8
19.4
16.6
25.2
DD1
DD2
Si8663Bx, Ex
V
V
—
—
16.4
16.4
21.3
21.3
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.3
Si8660/61/62/63
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
5.0
13
Mbps
ns
—
5.0
—
t
, t
See Figure 1
See Figure 1
8.0
0.2
ns
PHL PLH
Pulse Width Distortion
PWD
4.5
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.4
4.5
2.5
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 1
—
—
ns
ns
r
L
2.5
2.5
4.0
4.0
Output Fall Time
t
C = 15 pF
f
L
See Figure 1
Peak Eye Diagram Jitter
t
See Figure 6
—
350
50
—
—
ps
JIT(PK)
Common Mode
CMTI
V = V or 0 V
35
kV/µs
I
DD
Transient Immunity
3
Startup Time
t
—
15
40
µs
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing
Rev. 1.3
7
Si8660/61/62/63
Table 3. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDDUV+ V
, V
rising
falling
DD1
DD2
DD2
VDDUV– V
, V
V
DD1
VDD Negative-Going Lockout
Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
All inputs rising
All inputs falling
1.4
1.0
0.38
2.0
—
1.67
1.23
0.44
—
1.9
1.4
0.50
—
V
V
V
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
3.1
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
µA
L
1
Output Impedance
Z
50
O
DC Supply Current (All inputs 0 V or at supply)
Si8660Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
mA
mA
mA
mA
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8661Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8662Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8663Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
8
Rev. 1.3
Si8660/61/62/63
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
5.0
4.2
7.0
5.9
mA
mA
mA
mA
DD1
DD2
Si8661Bx, Ex
V
V
—
—
4.9
4.6
6.9
6.4
DD1
DD2
Si8662Bx, Ex
V
V
—
—
5.1
4.7
7.1
6.6
DD1
DD2
Si8663Bx, Ex
V
V
—
—
4.9
4.9
6.8
6.8
DD1
DD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
V
V
—
—
5.0
5.0
7.0
7.0
mA
mA
mA
mA
DD1
DD2
Si8661Bx, Ex
V
V
—
—
5.0
5.3
7.0
7.4
DD1
DD2
Si8662Bx, Ex
V
V
—
—
5.3
5.2
7.4
7.3
DD1
DD2
Si8663Bx, Ex
V
V
—
—
5.2
5.2
7.3
7.3
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
9
Si8660/61/62/63
Table 3. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 ºC)
Parameter
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
5.0
18.3
7.0
23.8
mA
mA
mA
mA
DD1
DD2
Si8661Bx, Ex
V
V
—
—
7.4
16.4
9.9
21.3
DD1
DD2
Si8662Bx, Ex
V
V
—
—
10
14.1
13
18.3
DD1
DD2
Si8663Bx, Ex
V
V
—
—
12.3
12.3
15.9
15.9
DD1
DD2
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
150
5.0
13
Mbps
ns
—
5.0
—
t
, t
See Figure 1
See Figure 1
8.0
0.2
ns
PHL PLH
PWD
4.5
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.4
4.5
2.5
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 1
—
—
ns
ns
r
L
2.5
2.5
4.0
4.0
Output Fall Time
t
C = 15 pF
f
L
See Figure 1
Peak Eye Diagram Jitter
t
See Figure 6
—
350
50
—
—
ps
JIT(PK)
Common Mode Transient
Immunity
CMTI
V = V or 0 V
35
kV/µs
I
DD
3
Startup Time
t
—
15
40
µs
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.3
Si8660/61/62/63
Table 4. Electrical Characteristics
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
Symbol
VDDUV+
VDDUV–
Test Condition
Min
1.95
1.88
50
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDD Undervoltage Threshold
VDD Undervoltage Threshold
V
, V
rising
falling
DD1
DD2
DD2
V
, V
V
DD1
VDD Negative-Going Lockout
Hysteresis
VDD
mV
HYS
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
All inputs rising
1.4
1.0
0.38
2.0
—
1.67
1.23
0.44
—
1.9
1.4
0.50
—
V
V
All inputs falling
V
V
HYS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
V
V
IH
V
—
0.8
—
V
IL
V
loh = –4 mA
lol = 4 mA
V
,V
– 0.4
2.3
0.2
—
V
OH
DD1 DD2
V
—
0.4
±10
—
V
OL
I
—
—
µA
L
1
Output Impedance
Z
50
O
DC Supply Current (All inputs 0 V or at supply)
Si8660Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
mA
mA
mA
mA
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8661Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8662Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Si8663Bx, Ex
V
V
V
V
V = 0(Bx), 1(Ex)
—
—
—
—
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
DD1
DD2
DD1
DD2
I
V = 0(Bx), 1(Ex)
I
V = 1(Bx), 0(Ex)
I
V = 1(Bx), 0(Ex)
I
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
11
Si8660/61/62/63
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
5.0
4.2
7.0
5.9
mA
mA
mA
mA
DD1
DD2
Si8661Bx, Ex
V
V
—
—
4.9
4.6
6.9
6.4
DD1
DD2
Si8662Bx, Ex
V
V
—
—
5.1
4.7
7.1
6.6
DD1
DD2
Si8663Bx, Ex
V
V
—
—
4.9
4.9
6.8
6.8
DD1
DD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
V
V
—
—
5.0
4.6
7.0
6.4
mA
mA
mA
mA
DD1
DD2
Si8661Bx, Ex
V
V
—
—
5.0
4.9
6.9
6.9
DD1
DD2
Si8662Bx, Ex
V
V
—
—
5.2
4.9
7.2
6.9
DD1
DD2
Si8663Bx, Ex
V
V
—
—
5.0
5.0
7.0
7.0
DD1
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.3
Si8660/61/62/63
Table 4. Electrical Characteristics (Continued)
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 ºC)
Parameter
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8660Bx, Ex
Symbol
Test Condition
Min
Typ
Max
Unit
V
V
—
—
5.0
14.7
7.0
19.1
mA
mA
mA
mA
DD1
DD2
Si8661Bx, Ex
V
V
—
—
6.7
13.4
9.1
17.4
DD1
DD2
Si8662Bx, Ex
V
V
—
—
8.7
11.7
11.3
15.2
DD1
DD2
Si8663Bx, Ex
V
V
—
—
10.3
10.3
13.4
13.4
DD1
DD2
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
0
—
—
150
5.0
14
Mbps
ns
—
5.0
—
t
, t
See Figure 1
See Figure 1
8.0
0.2
ns
PHL PLH
PWD
5.0
ns
|t
- t
|
PLH PHL
2
Propagation Delay Skew
Channel-Channel Skew
All Models
t
—
—
2.0
0.4
5.0
2.5
ns
ns
PSK(P-P)
t
PSK
Output Rise Time
t
C = 15 pF
See Figure 1
—
—
ns
ns
r
L
2.5
2.5
4.0
4.0
Output Fall Time
t
C = 15 pF
f
L
See Figure 1
Peak Eye Diagram Jitter
t
See Figure 6
—
350
50
—
—
ps
JIT(PK)
Common Mode
CMTI
V = V or 0 V
35
kV/µs
I
DD
Transient Immunity
3
Startup Time
t
—
15
40
µs
SU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
13
Si8660/61/62/63
Table 5. Regulatory Information*
CSA
The Si866x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
RMS
RMS
RMS
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
60601-1: Up to 125 V
reinforced insulation working voltage; up to 380 V
basic insulation working voltage.
RMS
RMS
VDE
The Si866x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1200 V for basic insulation working voltage.
peak
60950-1: Up to 600 V
age.
reinforced insulation working voltage; up to 1000 V
basic insulation working volt-
RMS
RMS
UL
The Si866x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 V isolation voltage for basic protection.
RMS
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "5. Ordering Guide" on page 26.
Table 6. Insulation and Safety-Related Specifications
Value
Test
Condition
Parameter
Symbol
Unit
WB
SOIC-16
NB
SOIC-16
1
Nominal Air Gap (Clearance)
L(IO1)
L(IO2)
8.0
8.0
4.9
mm
mm
Nominal External Tracking
4.01
1
(Creepage)
Minimum Internal Gap
(Internal Clearance)
mm
0.014
0.011
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
600
V
RMS
mm
Erosion Depth
0.019
0.019
2
12
12
Resistance (Input-Output)
R
10
10
IO
2
Capacitance (Input-Output)
C
2.0
4.0
2.0
4.0
pF
IO
3
Input Capacitance
C
pF
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and
creepage limits as 4.7 mm minimum for the NB SOIC-16 package and 8.5 mm minimum for the WB SOIC-16 package.
UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance
and creepage limits as 3.9 mm minimum for the NB SOIC-16 package and 7.6 mm minimum for the WB SOIC-16
package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
14
Rev. 1.3
Si8660/61/62/63
Table 7. IEC 60664-1 (VDE 0844 Part 2) Ratings
Specification
Test Conditions
Parameter
NB SOIC-16
WB SOIC-16
Basic Isolation Group
Material Group
I
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-III
I-II
I-II
I-IV
I-IV
I-III
I-III
RMS
RMS
RMS
RMS
Installation Classification
Table 8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx*
Characteristic
Symbol
Test Condition
Unit
Parameter
WB
SOIC-16
NB SOIC-16
Maximum Working Insulation
Voltage
V
V
1200
2250
630
Vpeak
IORM
Method b1
(V
x 1.875 = V , 100%
IORM
PR
V
1182
Input to Output Test Voltage
PR
Production Test, t = 1 sec,
m
Partial Discharge < 5 pC)
t = 60 sec
6000
2
6000
2
Vpeak
Transient Overvoltage
IOTM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at T ,
9
9
S
R
>10
>10
S
V
= 500 V
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of
40/125/21.
Table 9. IEC Safety Limiting Values1
Max
WB SOIC-16 NB SOIC-16
Parameter
Symbol
Test Condition
Min Typ
Unit
Case Temperature
T
I
—
—
—
—
150
150
°C
S
Safety Input, Output,
or Supply Current
= 105 °C/W
JA
(NB SOIC-16),
mA
S
220
215
V = 5.5 V, T = 150 °C,
I
J
T = 25 °C
A
Device Power
Dissipation
P
—
—
mW
D
415
415
2
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 2 and 3.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.3
15
Si8660/61/62/63
Table 10. Thermal Characteristics
Parameter
Symbol
Test Condition
WB SOIC-16 NB SOIC-16
100 105
Unit
IC Junction-to-Air Thermal
Resistance
ºC/W
JA
500
450
370
VDD1, VDD2 = 2.70 V
400
300
200
100
0
VDD1, VDD2 = 3.6 V
220
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
500
430
V
DD1, VDD2 = 2.70 V
400
300
200
100
0
360
VDD1, VDD2 = 3.6 V
215
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 3. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
16
Rev. 1.3
Si8660/61/62/63
Table 11. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
Max
150
125
7.0
Unit
°C
°C
V
2
Storage Temperature
T
STG
Ambient Temperature Under Bias
Supply Voltage
T
A
V
, V
DD2
DD1
Input Voltage
V
V
V
+ 0.5
V
I
DD
DD
Output Voltage
V
+ 0.5
V
O
Output Current Drive Channel
Lead Solder Temperature (10 s)
I
10
mA
°C
O
—
260
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16
—
—
—
—
4500
V
RMS
RMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
6500
V
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
Rev. 1.3
17
Si8660/61/62/63
2. Functional Description
2.1. Theory of Operation
The operation of an Si866x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si866x channel is shown in
Figure 4.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 5 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 5. Modulation Scheme
18
Rev. 1.3
Si8660/61/62/63
2.2. Eye Diagram
Figure 6 illustrates an eye-diagram taken on an Si8660. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8660 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited.
Figure 6. Eye Diagram
Rev. 1.3
19
Si8660/61/62/63
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present.
Table 12. Si866x Logic Operation
V
VDDI
VDDO
I
1,2
Comments
V Output
O
1,3,4
1,3,4
1,2
State
State
Input
H
L
P
P
P
P
H
L
Normal operation.
6
L
Upon transition of VDDI from unpowered to powered, V
5
O
X
UP
P
P
6
returns to the same state as V in less than 1 µs.
H
I
Upon transition of VDDO from unpowered to powered, V
5
O
X
UP
Undetermined
returns to the same state as V within 1 µs.
I
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
4. “Unpowered” state (UP) is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See "5. Ordering Guide" on page 26 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data
channels have pull-downs on inputs/outputs.
20
Rev. 1.3
Si8660/61/62/63
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when V
falls below V
and exits UVLO when V rises above
DD1
DD1(UVLO–)
DD1
V
. Side B operates the same as Side A with respect to its V
supply.
DD2
DD1(UVLO+)
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
OUTPUT
Figure 7. Device Behavior during Normal Operation
Rev. 1.3
21
Si8660/61/62/63
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 V ) must be physically
AC
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 V ) by a certain distance
AC
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 5 on page 14 and Table 6 on page 14 detail the
working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.)
requirements before starting any design that uses a digital isolator.
3.3.1. Supply Bypass
The Si866x family requires a 0.1 µF bypass capacitor between V
and GND1 and V
and GND2. The
DD2
DD1
capacitor should be placed as close as possible to the package. To enhance the robustness of a design, it is further
recommended that the user also add 1 µF bypass capacitors and include 100 resistors in series with the inputs
and outputs if the system is excessively noisy.
3.3.2. Pin Connections
For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin
15 must also be connected to external ground. No connect pins are not internally connected. They can be left
floating, tied to VDD, or tied to GND.
3.3.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3.4. Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input
supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 12 on
page 20 and "5. Ordering Guide" on page 26 for more information.
22
Rev. 1.3
Si8660/61/62/63
3.5. Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 2, 3, and 4 for actual specification limits.
30.0
25.0
20.0
15.0
10.0
5.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
5V
5V
3.3V
2.5V
3.3V
2.5V
0.0
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 11. Si8660 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 8. Si8660 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
40.0
35.0
30.0
25.0
30.0
25.0
20.0
20.0
15.0
10.0
5.0
5V
15.0
10.0
5.0
5V
3.3V
2.5V
3.3V
2.5V
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 12. Si8661 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 9. Si8661 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
(15 pF Load)
30.0
25.0
20.0
30.0
25.0
20.0
15.0
10.0
5.0
5V
15.0
10.0
5.0
5V
3.3V
2.5V
3.3V
2.5V
0.0
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
Figure 13. Si8662 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 10. Si8662 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.5 V Operation
(15 pF Load)
Rev. 1.3
23
Si8660/61/62/63
30.0
25.0
20.0
15.0
10.0
5.0
5V
3.3V
2.5V
0.0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 14. Si8663 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.5 V
Operation (15 pF Load)
10.0
9.0
8.0
7.0
6.0
5.0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100110120
Temperature (Degrees C)
Figure 15. Propagation Delay vs. Temperature
24
Rev. 1.3
Si8660/61/62/63
4. Pin Descriptions
VDD1
VDD1
A1
VDD1
VDD1
VDD2
B1
VDD2
B1
VDD2
B1
VDD2
B1
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
RCVR
RF
XMITR
RF
XMITR
A1
A2
A1
A2
A1
A2
I
s
o
l
a
t
I
s
o
l
a
t
I
s
o
l
a
t
I
s
o
l
a
t
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B2
A2
B2
B2
B2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A3
B3
A3
B3
A3
A4
B3
A3
A4
B3
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
RCVR
RF
XMITR
RF
XMITR
A4
B4
A4
B4
B4
B4
i
o
n
i
o
n
i
o
n
i
o
n
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
A5
B5
A5
B5
A5
B5
A5
B5
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RF
RCVR
RF
A6
B6
B6
A6
B6
A6
B6
A6
XMITR
XMITR
GND1
GND2
GND1
GND2
GND1
GND2
GND1
GND2
Si8660
Si8661
Si8662
Si8663
Name
SOIC-16 Pin#
Type
Supply
Description
V
1
2
Side 1 power supply.
Side 1 digital input.
Side 1 digital input.
Side 1 digital input.
DD1
A1
A2
Digital Input
Digital Input
Digital Input
Digital I/O
Digital I/O
Digital I/O
Ground
3
A3
4
A4
5
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 ground.
A5
6
A6
7
GND1
GND2
B6
8
9
Ground
Side 2 ground.
10
11
12
13
14
15
16
Digital I/O
Digital I/O
Digital I/O
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
B5
B4
B3
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
Digital Output Side 2 digital output.
B2
B1
V
Supply
Side 2 power supply.
DD2
Rev. 1.3
25
Si8660/61/62/63
5. Ordering Guide
Revision B devices are recommended for all new designs.
Table 13. Ordering Guide for Valid OPNs1
Ordering Part
Number (OPN)
Number of Number of MaxData Default Isolation
Inputs Inputs Rate Output rating
Temp (°C)
Package
VDD1 Side VDD2 Side (Mbps)
State
(kV)
2,3
Revision B Devices
Si8660BA-B-IS1
Si8660BC-B-IS1
Si8660EC-B-IS1
Si8660BD-B-IS
Si8660ED-B-IS
Si8661BC-B-IS1
Si8661EC-B-IS1
Si8661BD-B-IS
Si8661ED-B-IS
Si8662BC-B-IS1
Si8662EC-B-IS1
Si8662BD-B-IS
Si8662ED-B-IS
Si8663BC-B-IS1
Si8663EC-B-IS1
Si8663BD-B-IS
Si8663ED-B-IS
Notes:
6
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
0
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
Low
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
1.0
3.75
3.75
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
5.0
3.75
3.75
5.0
5.0
3.75
3.75
5.0
5.0
3.75
3.75
5.0
5.0
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 packages.
Moisture sensitivity level is MSL2A for narrow-body SOIC-16 packages.
2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs.
3. All devices >1 kVRMS are AEC-Q100 qualified.
26
Rev. 1.3
Si8660/61/62/63
Table 13. Ordering Guide for Valid OPNs1 (Continued)
Ordering Part
Number (OPN)
Number of Number of MaxData Default Isolation
Inputs Inputs Rate Output rating
Temp (°C)
Package
VDD1 Side VDD2 Side (Mbps)
State
(kV)
2,3
Revision A Devices
Si8660BA-A-IS1
Si8660BC-A-IS1
Si8660EC-A-IS1
Si8660BD-A-IS
Si8660ED-A-IS
Si8661BC-A-IS1
Si8661EC-A-IS1
Si8661BD-A-IS
Si8661ED-A-IS
Si8662BC-A-IS1
Si8662EC-A-IS1
Si8662BD-A-IS
Si8662ED-A-IS
Si8663BC-A-IS1
Si8663EC-A-IS1
Si8663BD-A-IS
Si8663ED-A-IS
Notes:
6
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
0
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
Low
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
1.0
3.75
3.75
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
NB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
NB SOIC-16
NB SOIC-16
WB SOIC-16
WB SOIC-16
5.0
3.75
3.75
5.0
5.0
3.75
3.75
5.0
5.0
3.75
3.75
5.0
5.0
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard
classifications and peak solder temperatures.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 packages.
Moisture sensitivity level is MSL2A for narrow-body SOIC-16 packages.
2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs.
3. All devices >1 kVRMS are AEC-Q100 qualified.
Rev. 1.3
27
Si8660/61/62/63
6. Package Outline: 16-Pin Wide Body SOIC
Figure 16 illustrates the package details for the Si866x Digital Isolator. Table 14 lists the values for the dimensions
shown in the illustration.
Figure 16. 16-Pin Wide Body SOIC
Table 14. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
2.65
0.3
A
A1
D
E
E1
b
0.1
10.3 BSC
10.3 BSC
7.5 BSC
0.31
0.51
0.33
c
0.20
e
1.27 BSC
h
0.25
0.4
0°
0.75
1.27
7°
L
28
Rev. 1.3
Si8660/61/62/63
7. Land Pattern: 16-Pin Wide-Body SOIC
Figure 17 illustrates the recommended land pattern details for the Si866x in a 16-pin wide-body SOIC. Table 15
lists the values for the dimensions shown in the illustration.
Figure 17. 16-Pin SOIC Land Pattern
Table 15. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.3
29
Si8660/61/62/63
8. Package Outline: 16-Pin Narrow Body SOIC
Figure 18 illustrates the package details for the Si866x in a 16-pin narrow-body SOIC (SO-16). Table 16 lists the
values for the dimensions shown in the illustration.
Figure 18. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 16. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
0.25 BSC
30
Rev. 1.3
Si8660/61/62/63
Table 16. Package Diagram Dimensions (Continued)
Dimension
Min
0.25
0°
Max
0.50
8°
h
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012,
Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.3
31
Si8660/61/62/63
9. Land Pattern: 16-Pin Narrow Body SOIC
Figure 19 illustrates the recommended land pattern details for the Si866x in a 16-pin narrow-body SOIC. Table 17
lists the values for the dimensions shown in the illustration.
Figure 19. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 17. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern
SOIC127P600X165-16N for Density Level B (Median Land
Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC)
and a card fabrication tolerance of 0.05 mm is assumed.
32
Rev. 1.3
Si8660/61/62/63
10. Top Markings
10.1. Si866x Top Marking (16-Pin Wide Body SOIC)
Si86XYSV
YYWWTTTTTT
e3
TW
10.2. Top Marking Explanation (16-Pin Wide Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (6, 5, 4, 3, 2, 1)
Y = # of reverse channels (3, 2, 1, 0)
S = Speed Grade
(See Ordering Guide for more
information).
A = 1 Mbps; B = 150 Mbps (default output = low);
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
Line 2 Marking:
Line 3 Marking:
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing code from assembly house.
“e3” Pb-Free Symbol
Circle = 1.5 mm Diameter
(Center-Justified)
Country of Origin ISO Code
Abbreviation
TW = Taiwan
Rev. 1.3
33
Si8660/61/62/63
10.3. Si866x Top Marking (16-Pin Narrow Body SOIC)
Si86XYSV
YYWWTTTTTT
e3
10.4. Top Marking Explanation (16-Pin Narrow Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (6, 5, 4, 3, 2, 1)
Y = # of reverse channels (3, 2, 1, 0)
S = Speed Grade
(See Ordering Guide for more
information).
A = 1 Mbps; B = 150 Mbps (default
output = low);
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking:
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
TTTTTT = Mfg code
Manufacturing Code from Assembly Purchase Order
form.
Circle = 1.2 mm diameter
“e3” Pb-Free Symbol.
34
Rev. 1.3
Si8660/61/62/63
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
Added chip graphics on page 1.
Updated " Features" on page 1.
Moved Tables 1 and 11 to page 17.
Updated Tables 2, 3, and 4.
Updated Table 6, “Insulation and Safety-Related
Specifications,” on page 14.
Updated Table 8, “IEC 60747-5-2 Insulation
Characteristics for Si86xxxx*,” on page 15.
Moved Table 12 to page 20.
Moved “Typical Performance Characteristics” to
page 23.
Updated "3.5. Typical Performance Characteristics"
on page 23.
Updated Table 4, “Pin Descriptions,” on page 25.
Updated "5. Ordering Guide" on page 26.
Removed references to QSOP-16 package.
Revision 1.0 to Revision 1.1
Reordered spec tables to conform to new
convention.
Removed “pending” throughout document.
Revision 1.1 to Revision 1.2
Updated High Level Output Voltage VOH to 3.1 V in
Table 3, “Electrical Characteristics,” on page 8.
Updated High Level Output Voltage VOH to 2.3 V in
Table 4, “Electrical Characteristics,” on page 11.
Revision 1.2 to Revision 1.3
Updated "5. Ordering Guide" on page 26 to include
MSL2A.
Rev. 1.3
35
Si8660/61/62/63
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
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Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
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and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
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36
Rev. 1.3
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