SI88342EC-IS [SILICON]
Analog Circuit,;
| 型号： | SI88342EC-IS |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, |
| 文件： | 总52页 (文件大小：1117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si88x4x Data Sheet
Quad Digital Isolators with DC-DC Converter
KEY FEATURES
The Si88xx integrates Silicon Labs’ proven digital isolator technology with an on-chip
isolated dc-dc converter that provides regulated output voltages of 3.3 or 5.0 V (or >5 V
with external components) at peak output power levels of up to 5 W. These devices pro-
vide up to four digital channels. The dc-dc converter has user-adjustable frequency for
minimizing emissions, a soft-start function for safety, a shut-down option and loop com-
pensation. The device requires only minimal passive components and a miniature trans-
former.
• High-speed isolators with integrated dc-dc
converter
• Fully-integrated secondary sensing
feedback-controlled converter with
dithering for low EMI
• dc-dc converter peak efficiency of 83%
with external power switch
The ultra-low-power digital isolation channels offer substantial data rate, propagation de-
lay, size and reliability advantages over legacy isolation technologies. Data rates up to
100 Mbps max are supported, and all devices achieve propagation delays of only 23 ns
max. Ordering options include a choice of dc-dc converter features, isolation channel
configurations and a failsafe mode. All products are certified by UL, CSA, VDE, and
CQC.
• Up to 5 W isolated power with external
power switch
• Options include dc-dc shutdown, frequency
control, and soft start
• Standard Voltage Conversion
• 3/5 V to isolated 3/5 V
• 24 V to isolated 3/5 V supported
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robust-
ness and low defectivity required for automotive applications.
• Precise timing on digital isolators
• 0–100 Mbps
• 18 ns typical prop delay
Industrial Applications
• Industrial automation systems
• Medical electronics
• Isolated switch mode supplies
• Inverters
Automotive Applications
• Highly-reliable: 100 year lifetime
• Hybrid electric and electric vehicles
• Traction inverters
• High electromagnetic immunity and ultra-
low emissions
• RoHS compliant packages
• SOIC-20 wide body
• Battery management systems
• Vehicle communication busses
• SOIC-24 wide body
• Data Acquisition
• Isolation of up to 5000 V
RMS
• Motor control
• High transient immunity of 100 kV/µs
(typical)
• PLCs, distributed control systems
• AEC-Q100 qualified
• Wide temp range: -40 to +125°C
Safety Regulatory Approvals
• UL 1577 recognized
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• VDE certification conformity
• VDE0884-10
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950
• IMDS and CAMDS listing support
• CQC certification approval
• GB4943.1
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Rev. 1.01
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Digital Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 DC-DC Converter Application Information . . . . . . . . . . . . . . . . . . . . 9
3.3.1 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2 Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.3 Programmable Frequency. . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.4 External Transformer Driver . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.5 VREGA, VREGB . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.6 Output Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.7 Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.8 Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.9 Cycle Skipping . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.10 Low-Voltage Configuration . . . . . . . . . . . . . . . . . . . . . . .11
3.3.11 Low-Voltage to High-Voltage Configuration . . . . . . . . . . . . . . . . .12
3.3.12 High-Voltage to Low-Voltage Configuration . . . . . . . . . . . . . . . . .13
3.3.13 High-Voltage Configuration . . . . . . . . . . . . . . . . . . . . . . .14
3.4 Transformer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. Digital Isolator Device Operation . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3 Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.1 Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.2 Output Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . .18
4.4 Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.5 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . .19
5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 Calculating Total Current Consumption . . . . . . . . . . . . . . . . . . . . .37
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7. Package Outline: 20-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . 43
8. Land Pattern: 20-Pin SOIC
. . . . . . . . . . . . . . . . . . . . . . . . . 45
9. Package Outline: 24-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . 46
10. Land Pattern: 24-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 48
11. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.1 Si88x4x Top Marking (20-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . .49
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Rev. 1.01 | 2
11.2 Top Marking Explanation (20-Pin Wide Body SOIC). . . . . . . . . . . . . . . . .49
11.3 Si88x4x Top Marking (24-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . .50
11.4 Top Marking Explanation (24-Pin Wide Body SOIC). . . . . . . . . . . . . . . . .50
12. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Rev. 1.01 | 3
Si88x4x Data Sheet
Feature List
1. Feature List
• High-speed isolators with integrated dc-dc converter
• Fully-integrated secondary sensing feedback-controlled converter with dithering for low EMI
• dc-dc converter peak efficiency of 83% with external power switch
• Up to 5 W isolated power with external power switch
• Options include dc-dc shutdown, frequency control, and soft start
• Standard Voltage Conversion
• 3/5 V to isolated 3/5 V
• 24 V to isolated 3/5 V supported
• Precise timing on digital isolators
• 0–100 Mbps
• 18 ns typical prop delay
• Highly-reliable: 100 year lifetime
• High electromagnetic immunity and ultra-low emissions
• RoHS compliant packages
• SOIC-20 wide body
• SOIC-24 wide body
• Isolation of up to 5000 VRMS
• High transient immunity of 100 kV/µs (typical)
• AEC-Q100 qualified
• Wide temp range: -40 to +125°C
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Rev. 1.01 | 4
Si88x4x Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Si88x4x Ordering Guide1,2,3,4
Ordering
Part Number
DC-DC
Shutdown
Soft
Start
Frequency
Control
External
Switch
Forward
Digital
Reverse
Digital
Insulation
Rating
Package
Control
Channels
Channels
Available Now
Si88240BC-IS
Si88240EC-IS
Si88241BC-IS
Si88241EC-IS
Si88242BC-IS
Si88242EC-IS
Si88243BC-IS
Si88243EC-IS
Si88244BC-IS
Si88244EC-IS
Si88340EC-IS
Si88341EC-IS
Si88342EC-IS
Si88343EC-IS
Si88344EC-IS
Si88440EC-IS
Si88441EC-IS
Si88442EC-IS
Si88443EC-IS
Si88444EC-IS
Si88640EC-IS
Si88641EC-IS
Si88642EC-IS
Si88643EC-IS
Si88644EC-IS
Sample Now
Si88240BD-IS
Si88240ED-IS
Si88241BD-IS
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
4
3
3
2
2
1
1
0
0
4
3
2
1
0
4
3
2
1
0
4
3
2
1
0
0
0
1
1
2
2
3
3
4
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
3.75 kVRMS
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
Y
Y
Y
N
N
N
N
N
N
N
N
N
4
4
3
0
0
1
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
WB SOIC-20
WB SOIC-20
WB SOIC-20
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Rev. 1.01 | 5
Si88x4x Data Sheet
Ordering Guide
Ordering
Part Number
DC-DC
Shutdown
Soft
Start
Frequency
Control
External
Switch
Forward
Digital
Reverse
Digital
Insulation
Rating
Package
Control
Channels
Channels
Si88241ED-IS
Si88242BD-IS
Si88242ED-IS
Si88243BD-IS
Si88243ED-IS
Si88244BD-IS
Si88244ED-IS
Si88340ED-IS
Si88341ED-IS
Si88342ED-IS
Si88343ED-IS
Si88344ED-IS
Si88440ED-IS
Si88441ED-IS
Si88442ED-IS
Si88443ED-IS
Si88444ED-IS
Si88640ED-IS
Si88642ED-IS
Si88643ED-IS
Si88644ED-IS
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
3
2
2
1
1
0
0
4
3
2
1
0
4
3
2
1
0
4
2
1
0
1
2
2
3
3
4
4
0
1
2
3
4
0
1
2
3
4
0
2
3
4
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
5.0 kVRMS
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-20
WB SOIC-24
WB SOIC-24
WB SOIC-24
WB SOIC-24
Note:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260°C according to the JEDEC industry standard clas-
sifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
4. All Si88xxxEx product options are default output high on input power loss. All Si88xxxBx product options are default low. See
Chapter 4. Digital Isolator Device Operation for more details about default output behavior.
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Rev. 1.01 | 6
Si88x4x Data Sheet
Ordering Guide
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-
duction steps.
Table 2.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering
Part Number
DC-DC
Shutdown
Soft
Start
Frequency
Control
External
Switch
Forward
Digital
Reverse
Digital
Insulation
Rating
Package
Control
Channels
Channels
Available Now
Si88241EC-AS
Sample Now
Si88241ED-AS
Note:
Y
Y
N
N
N
N
N
N
3
3
1
1
3.75 kVRMS
5.0 kVRMS
WB SOIC-20
WB SOIC-20
1. All packages are RoHS-compliant.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-
tative for further information.
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Rev. 1.01 | 7
Si88x4x Data Sheet
Functional Description
3. Functional Description
3.1 Theory of Operation
The Si88xx family of products is capable of transmitting and receiving digital data signals from an isolated power domain to a local
system power domain with up to 5 kV of isolation. Each part has four unidirectional digital isolation channels. In addition, Si88xx prod-
ucts include an integrated controller and switches for a dc-dc converter which regulates output voltage by sensing it on the isolated
side.
3.2 Digital Isolation
The operation of an Si88xx digital channel is analogous to that of a digital buffer, except an RF carrier transmits data across the isola-
tion barrier. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-
up. A simplified block diagram for a single Si88xx channel is shown in the following figure.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor -
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 3.1. Simplified Si88xx Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a silicon dioxide capacitive isolation barrier. In the transmitter,
input A modulates the carrier provided by an RF oscillator using on/off keying. The receiver contains a demodulator that decodes the
input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is
superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic
fields. See Figure 3.2 Modulation Scheme on page 8 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 3.2. Modulation Scheme
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Si88x4x Data Sheet
Functional Description
3.3 DC-DC Converter Application Information
The Si88xx isolated dc-dc converter is based on a modified fly-back topology and uses an external transformer and Schottky rectifying
diode for low cost and high operating efficiency. The PWM controller operates in closed-loop, peak current mode control and generates
isolated output voltages with 2 W average output power at 5.0 V. Options are available for 24 Vdc input or output operation and exter-
nally configured switching frequency.
The dc-dc controller modulates a pair of internal primary-side power switches (see Figure 3.3 Si883xx Block Diagram: 3 V–5 V Input to
3 V–5 V Output on page 11) to generate an isolated voltage at external diode D1 cathode. Closed-loop feedback is provided by a
compensated error amplifier, which compares the voltage at the VSNS pin to an internal voltage reference. The resulting error voltage
is fed back through the isolation barrier via an internal feedback path to the controller, thus completing the control loop.
For higher input supply voltages than 5 V, an external FET Q2 is modulated by a driver pin ESW as shown in (see Figure 3.6 Si886xx
Block Diagram: 24 V Input to 5 V Output on page 14). A shunt resistor based voltage sense pin RSN provides current sensing capa-
bility to the controller.
Additional features include an externally-triggered shutdown of the converter functionality using the SH pin and a programmable soft
start configured by a capacitor connected to the SS pin. The Si88xx can be used in low- or high-voltage configurations. These features
and configurations are explained in more detail below.
3.3.1 Shutdown
This feature allows the operation of the dc-dc converter to be shut down when asserted high. This function is provided by pin 6 (labeled
“SH” on the Si882xx) and pin 7 (labeled “SH_FC” on the Si883xx and Si886xx). This feature is not available on the Si884xx. Pin 6 or pin
7 provide the exact same functionality and shut down the dc-dc converter when asserted high. For normal operation, pins 6 and 7
should be connected to ground.
3.3.2 Soft-Start
The dc-dc controller has an internal timer that controls the power conversion start-up to limit inrush current. There is also the Soft Start
option where users can program the soft start up by an external capacitor connected to the SS pin. This feature is available on the
Si883xx and the Si886xx.
3.3.3 Programmable Frequency
The frequency of the PWM modulator is set to a default of 250 kHz for Si882xx/4xx. Users can program their desired frequency within a
given band of 200 kHz to 800 kHz by controlling the time constant of an external RC connected to the SH_FC and SS pins for Si883xx/
6xx.
3.3.4 External Transformer Driver
The dc-dc controller has internal switches (VSW) for driving the transformer with up-to a 5.5 V voltage supply. For higher voltages on
the primary side, a driver output (ESW) is provided that can drive an external NMOS power transistor for driving the transformer. When
this configuration is used, a shunt resistor based voltage sense pin (RSN) provides current sensing to the controller.
3.3.5 VREGA, VREGB
For supporting voltages greater than 5.5 V, an internal voltage regulator (VREGA, VREGB) needs to be used in conjunction with an
external NPN transistor, a resistor and a capacitor to provide regulated voltage to the IC.
3.3.6 Output Voltage Control
The isolated output voltage (VOUT) is sensed by a resistor divider that provides feedback to the controller through the VSNS pin. The
voltage error is encoded and transmitted back to the primary side controller across the isolation barrier, which in turn changes the duty
cycle of the transformer driver. The equation for VOUT is as follows:
R1
R2
VOUT = VSNS × 1 +
+ R1 × I
OFFSET
(
)
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Si88x4x Data Sheet
Functional Description
3.3.7 Compensation
The dc-dc converter uses peak current mode control. The loop is compensated by connecting an external resistor in series with a ca-
pacitor from the COMP pin to GNDB. The compensation resistance, RCOMP is fixed at 49.9 kΩ for Si882xx/3xx and 100 kΩ for
Si884xx/6xx to match internal resistance. Capacitance value is given by the following equation, where fC is crossover frequency:
6
CCOMP =
2 × π × f × RCOMP
C
For more details on the calculations involved, please see AN892: Design Guide for Isolated DC/DC Using the Si882xx/883xx.
3.3.8 Thermal Protection
A thermal shutdown circuit is included to protect the system from over-temperature events. The thermal shutdown is activated at a junc-
tion temperature that prevents permanent damage from occurring.
3.3.9 Cycle Skipping
Cycle skipping is included to reduce switching power losses at light loads. This feature is transparent to the user and is activated auto-
matically at light loads. The product options with integrated power switches (Si882xx/3xx) may never experience cycle skipping during
operation even at light loads while the external power switch options (Si884xx/6xx) are likely to have cycle skipping start at light loads.
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Si88x4x Data Sheet
Functional Description
3.3.10 Low-Voltage Configuration
The low-voltage configuration is used for converting 3.0 V to 5.5 V. All product options of the Si882xx and Si883xx are intended for this
configuration.
An advantage of Si88xx devices over other converters that use this same topology is that the output voltage is sensed on the secon-
dary side without requiring additional optocouplers and support circuitry to bias those optocouplers. This allows the dc-dc to operate
with superior line and load regulation while reducing external components and increasing lifetime reliability.
In a typical digital signal isolation application, the dc-dc powers the Si882xx and Si883xx VDDB as shown in the figure below. In addi-
tion to powering the isolated side of the dc-dc can deliver up to 2 W of power to other loads. The dc-dc requires an input capacitor, C2,
blocking capacitor, C1, transformer, T1, rectifying diode, D1, and an output capacitor, C3. Resistors R1 and R2 divide the output volt-
age to match the internal reference of the error amplifier. Type 1 loop compensation made by RCOMP and CCOMP are required at the
COMP pin. Though it is not necessary for normal operation, we recommend that a snubber be used to minimize radiated emissions.
More details can be found in “AN892: Design Guide for Isolated DC-DC Using the Si882xx/883xx”.
Vin
Vout
C1
T1
D1
C3
C2
R1
Si8834x
R2
VDDB
VDDA
UVLO
UVLO
Power
FET
Used in applications
where converter
output is > 5.5 V
VREG
VSNS
VSW
HVREG
Reference
DC-DC
Controller
Power
FET
RFSW
CSS
SH_FC
SS
Error Amp
and
Compensation
Freq. Control
and Shutdown
CCOMP
COMP
Soft Start
Encoder
RCOMP
HF RX
HF TX
HF RX
HF RX
A1
A2
A3
A4
HF TX
HF TX
B1
B2
HF TX
HF RX
HF RX
HF TX
B3
B4
Figure 3.3. Si883xx Block Diagram: 3 V–5 V Input to 3 V–5 V Output
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Rev. 1.01 | 11
Si88x4x Data Sheet
Functional Description
3.3.11 Low-Voltage to High-Voltage Configuration
The low-voltage to high-voltage configuration is used for converting 3.0 V – 5.5 V up to 24 V.
In a typical digital signal isolation application, the dc-dc powers the Si882xx and Si883xx VOUT as shown in the figure below. In addi-
tion to powering the isolated side of the dc-dc, it can deliver up to 2 W of power to other loads. The dc-dc requires an input capacitor,
C2, blocking capacitor, C1, transformer, T1, rectifying diode, D1, and an output capacitor, C3. Resistors R1 and R2 divide the output
voltage to match the internal reference of the error amplifier. To supply VDDB that requires voltage lower than 5.5 V, Q3 transistor is
biased and filtered by R5 and C4. Type 1 loop compensation made by RCOMP and CCOMP are required at the COMP pin. Though it is
not necessary for normal operation, we recommend that a snubber be used to minimize radiated emissions. More details can be found
in AN892: Design Guide for Isolated DC-DC Using the Si882xx/883xx.
Vout
Vin
C1
T1
D1
C3
C2
Si8834x
R5
VDDA
VREGB
VREG
Reference
UVLO
Q3
VDDB
Power
FET
UVLO
VSW
DC-DC
Controller
C4
R
1
Power
FET
VSNS
RFSW
CSS
SH_FC
Error Amp
and
Compensation
Freq. Control
and Shutdown
R2
CCOMP
SS
COMP
Soft Start
Encoder
RCOMP
HF RX
HF TX
HF RX
HF RX
A1
A2
A3
A4
HF TX
HF TX
B1
B2
HF TX
HF RX
HF RX
HF TX
B3
B4
Figure 3.4. Si883xx Block Diagram: 3 V – 5 V Input to up to 24 V Output
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Rev. 1.01 | 12
Si88x4x Data Sheet
Functional Description
3.3.12 High-Voltage to Low-Voltage Configuration
The high-voltage configuration is used for converting up to 24 V to 3.3 V or 5.0 V. All product options of the Si884xx and Si886xx are
intended for this configuration.
Si884xx and Si886xx can be used for dc-dc applications that have primary side voltage greater than 5.5 V. The dc-dc converter uses
the isolated flyback topology. With this topology, the switch and sense resistor are external, allowing higher switching voltages. Digital
isolator supply VDDA of the Si884xx and Si886xx require a supply less than or equal to 5.5 V. If a suitable supply is not available on the
primary side, the VREGA voltage reference with external NPN transistor can supply VDDA. This eliminates the need to design an addi-
tional linear regulator circuit. Like the Si882xx and Si883xx, the output voltage is sensed on the secondary side without requiring addi-
tional optocouplers and support circuitry to bias those optocouplers. This allows the dc-dc to operate with superior line and load regula-
tion.
The figure below shows the block diagram of an Si886xx with external components. Si886xx is different from the Si882xx/883xx as it
has externally-controlled switching frequency and soft start. The dc-dc requires input capacitor C2, transformer T1, switch Q1, sense
resistor R4, rectifying diode D1 and an output capacitor C3. To supply VDDA, Q2 transistor is biased and filtered by R3 and C1. Exter-
nal frequency and soft start behavior is set by CSS and RFSW. Resistors R1 and R2 divide the output voltage to match the internal
reference of the error amplifier. Type 1 loop compensation made by RCOMP and CCOMP are required at the COMP pin. Though it is
not necessary for normal operation, we recommend to use a snubber, to minimize high-frequency emissions. For further details, see
AN901: Design Guide for Isolated DC-DC Using the Si884xx/886xx.
VOUT
Vin
T1
D1
C3
C2
Si8864x
R3
Used in applications
where converter
output is > 5.5 V
VREGA
VDDA
VREGB
VDDB
VREG
Reference
VREG
Reference
Q2
UVLO
UVLO
C1
ESW
RSN
Q1
FET
Driver
DC-DC Controller
Current
Sensing
R
4
GNDP
R
R
1
2
VSNS
COMP
RFSW
CSS
FC_SH
Error Amp
and
Compensation
Freq. Control
and Shutdown
SS
CCOMP
RCOMP
Soft Start
Encoder
HF RX
HF TX
A1
A2
A3
A4
HF TX
HF TX
HF RX
HF RX
B1
B2
HF TX
HF RX
HF RX
HF TX
B3
B4
Figure 3.5. Si886xx Block Diagram: 24 V Input to 5 V Output
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Rev. 1.01 | 13
Si88x4x Data Sheet
Functional Description
3.3.13 High-Voltage Configuration
The high-voltage configuration is used for converting input voltage up to 24 V to output voltage as high as 24 V. All product options of
the Si884xx and Si886xx are intended for this configuration.
Si884xx and Si886xx can be used for dc-dc applications that have primary side voltage greater than 5.5 V. The dc-dc converter uses
the isolated flyback topology. With this topology, the switch and sense resistor are external, allowing higher switching voltages. Digital
isolator supply VDDA of the Si884xx and Si886xx require a supply less than or equal to 5.5 V. If a suitable supply is not available on the
primary side, the VREGA voltage reference with external NPN transistor Q2 can supply VDDA. This eliminates the need to design an
additional linear regulator circuit. Like the Si882xx and Si883xx, the output voltage is sensed on the secondary side without requiring
additional optocouplers and support circuitry to bias those optocouplers. This allows the dc-dc to operate with superior line and load
regulation.
Figure 3.6 Si886xx Block Diagram: 24 V Input to 5 V Output on page 14 shows the block diagram of an Si886xx with external compo-
nents. Si886xx is different from the Si882xx/883xx as it has externally-controlled switching frequency and soft start. The dc-dc requires
input capacitor C2, transformer T1, switch Q1, sense resistor R4, rectifying diode D1 and an output capacitor C3. To supply VDDB, Q3
transistor is biased and filtered by R5 and C4. External frequency and soft start behavior is set by CSS and RFSW. Resistors R1 and
R2 divide the output voltage to match the internal reference of the error amplifier. Type 1 loop compensation made by RCOMP and
CCOMP are required at the COMP pin. Though it is not necessary for normal operation, we recommend to use a snubber, to minimize
high-frequency emissions. For further details, see “AN901: Design Guide for Isolated DC-DC Using the Si884xx/886xx”.
VOUT
Vin
T1
D1
C3
C2
Si8864x
R5
R3
VREGA
VDDA
VREGB
VDDB
VREG
Reference
VREG
Reference
Q2
Q3
UVLO
UVLO
C4
C1
ESW
RSN
Q1
FET
Driver
DC-DC Controller
Current
Sensing
R
4
GNDP
R
1
2
VSNS
COMP
R
RFSW
CSS
FC_SH
Error Amp
and
Compensation
Freq. Control
and Shutdown
SS
CCOMP
Soft Start
Encoder
RCOMP
HF RX
HF TX
A1
A2
A3
A4
HF TX
HF TX
HF RX
HF RX
B1
B2
HF TX
HF RX
HF RX
HF TX
B3
B4
Figure 3.6. Si886xx Block Diagram: 24 V Input to 5 V Output
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Rev. 1.01 | 14
Si88x4x Data Sheet
Functional Description
3.4 Transformer Design
The following table provides a list of transformers and their parametric characteristics that have been validated to work with Si882xx/3xx
products (input voltage 3 to 5 V) and Si884xx/Si886xx products (input voltage of 24 V). It is recommended that users order the trans-
formers from the vendors per the part numbers given below. Refer to AN892 and AN901 for voltage translation applications not listed
below.
To manufacture transformers from your preferred suppliers that may not be listed below, please specify to supplier the parametric char-
acteristics as specified in the table below for a given input voltage and isolation rating.
Table 3.1. Transformer Specifications
Transformer Ordering Part #
Supplier
Input
Voltage
Output
Voltage
Turns
Ratio P:S
Leakage
Inductance
Primary
Inductance
Primary
Resistance
Isolation
Rating
UMEC (http://
www.umec-
usa.com)
UTB02185s
UTB02205s
UTB02240s
UTB02250s
TA7608-AL
4.5 – 5.5 V 3.0 – 5.5V
1.0:4.0
3.0:1.0
1.0:4.0
3.0:1.0
1.0:4.0
100 nH max
800 nH max
100 nH max
600 nH max
60 nH max
2 µH ± 5%
25 µH ± 5%
2 µH ±5%
0.05 Ω max
2.5 kVRMS
UMEC (http://
www.umec-
usa.com)
12V, 24V 3.3 – 5.0V,
15V
0.135 Ω max 2.5 kVRMS
UMEC (http://
www.umec-
usa.com)
4.5 – 5.5V 3.0 – 5.5V
0.05 Ω max
5 kVRMS
UMEC (http://
www.umec-
usa.com)
7 – 24 V
3.3 – 5.5V
25 µH ± 5%
2 µH ± 5%
0.135 Ω max
5 kVRMS
Coilcraft1
(http://
www.coil-
craft.com)
4.5 – 5.5 V 3.0 – 5.5V
4.5 – 5.5V 3.0 – 5.5V
0.033 Ω max 2.5 kVRMS
Coilcraft1
(http://
www.coil-
craft.com)
TA7618-AL
TA7788-AL
UA7902
1.0:4.0
64 nH max
554 nH max
971 nH max
2.0 µH ±5%
25 µH ±5%
25 µH ±5%
0.031 Ω max
0.49 Ω max
0.075 Ω max
5 kVRMS
5 kVRMS
5 kVRMS
Coilcraft1
(http://
www.coil-
craft.com)
12V
12V
5V, 15V
5V, 15V
1.00 :
1.25 : 0.75
Coilcraft1
(http://
3.0:1.0
www.coil-
craft.com)
TDK (http://
www.tdk.com)
P100940_A1
4.5 – 5.5V 3.0 – 5.5V
1.0:4.0
1.0:1.0
40 nH max
2.0 µH ±10%
25 µH ±10%
0.1 Ω max
0.4 Ω max
2.4 kVRMS
2.5 kVRMS
Mentech
TTER09-0457S1
8 - 24 V
15V, 24V
550 nH max
(http://
men-
tech.en.made-
in-china.com/)
Mentech
TTER09-0458S1
8 - 24 V
8 - 24 V
1.0:1.0
550 nH max
25 µH ±10%
0.4 Ω max
5 kVRMS
(http://
men-
tech.en.made-
in-china.com/)
silabs.com | Building a more connected world.
Rev. 1.01 | 15
Si88x4x Data Sheet
Functional Description
Transformer Ordering Part #
Supplier
Input
Voltage
Output
Voltage
Turns
Ratio P:S
Leakage
Inductance
Primary
Inductance
Primary
Resistance
Isolation
Rating
Pulse (http://
www.pulsee-
lectron-
PA4896NL
8 – 24 V
7 – 24 V
1.0:1.0
650 nH max
25 µH ±10%
0.25 Ω max
2.5 kVRMS
ics.com/)
Pulse (http://
www.pulsee-
lectron-
PA4897NL
8 – 24 V
7 – 24 V
1.0:1.0
650 nH max
25 µH ±10%
0.25 Ω max
5 kVRMS
ics.com/)
Notes:
1. AEC-Q200 qualified.
2. For reference design details, see AN892: Design Guide for Isolated DC/DC using the Si882xx/883xx or AN901: Design Guide for
Isolated DC/DC using the Si884xx/886xx.
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Rev. 1.01 | 16
Si88x4x Data Sheet
Digital Isolator Device Operation
4. Digital Isolator Device Operation
Table 4.1. Si88xx Logic Operation
VDDI11 , 2, 3, 4
VDDO11 , 2, 3, 4
VI Input
VO Output
Comments
H
L
P
P
P
P
P
H
L
Normal operation.
L4
H4
X
UP
Upon transition of VDDI from un-
powered to powered, VO returns to
the same state as VI.
X
P
UP
Undetermined
Upon transition of VDDO from un-
powered to powered, VO returns to
the same state as VI.
Note:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. P = powered; UP = unpowered.
3. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. This situation
should be avoided. We recommend that I/O's not be driven high when primary side supply is turned off or when in dc-dc shut-
down mode.
4. See Chapter 2. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). When VDDB is pow-
ered via the primary side and the integrated dc-dc, the default outputs are undetermined as secondary side power is not available
when primary side power shuts off.
4.1 Device Startup
Outputs are held low during power up until VDDx is above the UVLO threshold for time period tSU. Following this, the outputs follow the
states of inputs.
4.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDDx is below
its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter
or exit UVLO independently. For example, Side A unconditionally enters UVLO when VDDA falls below VDDUV– and exits UVLO when
VDDA rises above VDDUV+. Side B operates the same as Side A with respect to its VDD supply.
4.3 Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). and detail the working voltage and cree-
page/clearance capabilities of the Si88xx. These tables also detail the component standards (UL1577, VDE0884-10, CSA 5A), which
are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system speci-
fication (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.
4.3.1 Supply Bypass
The Si88xx family requires a 0.1 µF bypass capacitor between all VDDx and their associated GNDx. The capacitor should be placed as
close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series with
the inputs and outputs if the system is excessively noisy.
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Rev. 1.01 | 17
Si88x4x Data Sheet
Digital Isolator Device Operation
4.3.2 Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-
chip series termination resistor and channel resistance of the output driver FET. When driving high-impedance terminated PCB traces,
output pins should be source-terminated to minimize reflections.
4.4 Fail-Safe Operating Mode
Si88xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)
can either be a logic high or logic low when the output supply is powered. See Table 4.1 Si88xx Logic Operation on page 17 and Table
2.1 Si88x4x Ordering Guide1,2,3,4 on page 5 for more information.
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Rev. 1.01 | 18
Si88x4x Data Sheet
Digital Isolator Device Operation
4.5 Typical Performance Characteristics
The typical performance characteristics are for information only. Refer to Table 5.2 Electrical Characteristics1 on page 24 for specifi-
cation limits. The data below is for all channels switching.
Figure 4.1. Si88240 Typical VDDA Supply Current vs. Data
Rate (5 and 3.3 V Operation)
Figure 4.2. Si88240 Typical VDDB Supply Current vs. Data
Rate (5 and 3.3 V Operation)
Figure 4.4. Si88241 Typical VDDB Supply Current vs. Data
Rate (5 and 3.3 V Operation)
Figure 4.3. Si88241 Typical VDDA Supply Current vs. Data
Rate (5 and 3.3 V Operation)
Figure 4.5. Si88242 Typical VDDA Supply Current vs. Data
Rate (5 and 3.3 V Operation)
Figure 4.6. Si88242 Typical VDDB Supply Current vs. Data
Rate (5 and 3.3 V Operation)
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Rev. 1.01 | 19
Si88x4x Data Sheet
Digital Isolator Device Operation
Figure 4.8. Si88243 Typical VDDB Supply Current vs. Data
Rate (5 and 3.3 V Operation)
Figure 4.7. Si88243 Typical VDDA Supply Current vs. Data
Rate (5 and 3.3 V Operation)
Figure 4.9. Si88244 Typical VDDA Supply Current vs. Data
Rate (5 and 3.3 V Operation)
Figure 4.10. Si88244 Typical VDDB Supply Current vs. Data
Rate (5 and 3.3 V Operation)
Figure 4.11. Propagation Delay vs. Temperature
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Rev. 1.01 | 20
Si88x4x Data Sheet
Digital Isolator Device Operation
Figure 4.12. Efficiency vs. Load Current over Temperature
(3.3 to 3.3 V)
Figure 4.13. Efficiency vs. Load Current over Temperature
(3.3 to 5.0 V)
Figure 4.14. Efficiency vs. Load Current over Temperature
(5.0 to 3.3 V)
Figure 4.15. Efficiency vs. Load Current over Temperature
(5.0 to 5.0 V)
Figure 4.16. Efficiency vs. Load Current over Temperature
(24 V to 5 V)
Figure 4.17. Efficiency vs. Load Current over Temperature
(24 V to 3.3 V)
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Rev. 1.01 | 21
Si88x4x Data Sheet
Digital Isolator Device Operation
Figure 4.18. Efficiency vs. Load Current over Temperature
(12 V to 5 V)
Figure 4.19. Efficiency vs. Load Current over Temperature (7
V to 24 V)
Figure 4.20. 24 V–5 V VOUT Startup vs.Time,
No Load Current
Figure 4.21. 24 V–5 V VOUT Startup vs.Time,
50 mA Load Current
Figure 4.22. 24 V–5 V VOUT Startup vs.Time,
400 mA Load Current
Figure 4.23. 5 V–5 V VOUT Startup vs.Time (No Load)
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Rev. 1.01 | 22
Si88x4x Data Sheet
Digital Isolator Device Operation
Figure 4.24. 5 V–5 V VOUT Startup vs.Time (50 mA Load Cur- Figure 4.25. 5 V–5 V VOUT Startup vs.Time (400 mA Load
rent)
Current)
Figure 4.26. 24 V–5 V VOUT Load Transient Response (10% Figure 4.27. 5 V–5 V VOUT Load Transient Response (10% to
to 90% Load)
90% Load)
Figure 4.28. Typical I-V Curve for VREGA/B
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Rev. 1.01 | 23
Si88x4x Data Sheet
Electrical Specifications
5. Electrical Specifications
Table 5.1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient Operating Tempera-
ture1
TA
–40
25
125
°C
Power Input Voltage
Supply Voltage
VDDP
VDDA
VDDB
3.0
3.0
3.0
—
—
—
5.5
5.5
5.5
V
V
V
Note:
1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply
voltage.
Table 5.2. Electrical Characteristics1
VIN = 24 V; VDDA = 4.3 V (see Figure 5.3 Measurement Circuit for Converter Efficiency and Regulation for Si884xx, Si886xx on page
32) for all Si8844x/64x; VDDA = VDDP = 3.0 to 5.5 V (see Figure 5.2 Measurement Circuit for Converter Efficiency and Regulation for
Si882xx, Si883xx on page 32) for all Si8824x/34x; TA = –40 to 125 °C unless otherwise noted
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC/DC Converter
Switching Frequency
Si8824x,
FSW
225
250
275
kHz
Si8844x
RFSW = 23.3 kΩ
FSW = 1025.5/(RFSW x CSS)
CSS = 220 nF (see Figure
3.6 Si886xx Block Diagram: 24 V
Input to 5 V Output on page 14)
180
200
220
kHz
(1% tolerance on BOM)
RFSW = 9.3 kΩ
FSW = 1025.5/(RFSW x CSS)
Switching Frequency
Si8834x,
FSW
CSS = 220 nF (see Figure
3.6 Si886xx Block Diagram: 24 V
Input to 5 V Output on page 14)
450
810
500
900
550
990
kHz
kHz
Si8864x
(1% tolerance on BOM)
RFSW = 5.18 kΩ,
CSS = 220 nF (see Figure
3.6 Si886xx Block Diagram: 24 V
Input to 5 V Output on page 14)
VSNS voltage
VSNS
Ioffset
ILOAD = 0 A
1.002
–500
1.05
—
1.097
500
V
VSNS current offset
nA
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Rev. 1.01 | 24
Si88x4x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32
Output Voltage
Accuracy2
–5
—
+5
%
ILOAD = 0 mA
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32
ΔVOUT(line)/
ΔVDDP
Line Regulation
Load Regulation
—
—
1
—
—
mV/V
ILOAD = 50 mA
VDDP varies from 4.5 to 5.5 V
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32
ΔVOUT(load)/
VOUT
0.1
%
ILOAD = 50 to 400 mA
ILOAD = 100 mA
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32
Output Voltage Rip-
ple
—
100
—
mV p-p
Si8824x, Si8834x
Si8844x, Si8864x
See Figure 5.3 Measurement
Circuit for Converter Efficiency
and Regulation for Si884xx,
Si886xx on page 32
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32
Turn-on overshoot
ΔVOUT(start)
—
2
—
%
CIN = COUT = 0.1 μF in
parallel with 10 μF, ILOAD = 0 A
Continuous Output
Current
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32
Si8824x, Si8834x
5.0 V to 5.0 V
3.3 V to 3.3 V
3.3 V to 5.0 V
5.0 V to 3.3 V
Si8844x, Si8864x
24.0 to 5.0 V
400
400
250
550
See Figure 5.3 Measurement
Circuit for Converter Efficiency
and Regulation for Si884xx,
Si886xx on page 32
ILOAD(max)
—
—
mA
1000
1500
24.0 to 3.0 V
Cycle-by-cycle aver-
age current limit
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32
ILIM
—
3
—
A
Si8824x, Si8834x
Output short circuited
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Rev. 1.01 | 25
Si88x4x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
No Load Supply Cur-
rent IDDP
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32
IDDPQ_DCD
C3
—
30
—
mA
Si8824x, Si8834x
VDDP = VDDA = 5 V
No Load Supply Cur-
rent IDDA
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32
ID-
—
—
—
5.7
0.8
5.8
—
—
—
mA
mA
mA
Si8824x, Si8834x
DAQ_DCDC4
VDDP = VDDA = 5 V
No Load Supply Cur-
rent IDDP
See Figure 5.3 Measurement
Circuit for Converter Efficiency
and Regulation for Si884xx,
Si886xx on page 32
IDDPQ_DCD
C3
Si8844x, Si8864x
VIN = 24 V
No Load Supply Cur-
rent IDDA
See Figure 5.3 Measurement
Circuit for Converter Efficiency
and Regulation for Si884xx,
Si886xx on page 32
ID-
DAQ_DCDC4
Si8844x, Si8864x
VIN=24V
See Figure 5.2 Measurement
Circuit for Converter Efficiency
and Regulation for Si882xx,
Si883xx on page 32, Figure
5.3 Measurement Circuit for
Converter Efficiency and Regula-
tion for Si884xx, Si886xx on
page 32
Peak Efficiency
η
—
—
—
—
%
Si8824x, Si8834x
Si8844x, Si8864x
78
83
Voltage Regulator
Reference Voltage
IREG = 600 µA
See Figure 4.15 Efficiency vs.
Load Current over Temperature
(5.0 to 5.0 V) on page 21 for typi-
cal I–V curve
VREGA,
VREGB
4.8
V
Si8844x, Si8864x
VREG tempco
KTVREG
IREG
—
–0.4
—
—
mV/°C
µA
VREG input current
350
950
See Figures Figure 4.20 24 V–5
V VOUT Startup vs.Time,
No Load Current on page 22
through Figure 4.25 5 V–5 V
VOUT Startup vs.Time (400 mA
Load Current) on page 23 for
typical soft start times over load
conditions.
Soft Start Time, Full
Load
tSST
—
—
—
—
ms
Si8824x, Si8844x
Si8834x, Si8864x
25
50
Restart Delay from
fault event
tOTP
21
s
Digital Isolator
VDD Undervoltage
Threshold
VDDUV+
VDDUV–
VDDA, VDDB rising
VDDA, VDDB falling
—
—
2.7
2.6
—
—
V
V
VDD Undervoltage
Threshold
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Rev. 1.01 | 26
Si88x4x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Undervoltage
Hysteresis
VDDHYS
—
100
—
mV
Positive-Going Input
Threshold
VT+
All inputs rising
All inputs falling
—
1.7
—
V
Negative-Going Input
Threshold
VT–
VHYS
VIH
—
—
1.2
0.4
—
—
—
—
V
V
V
Input Hysteresis
High Level Input Volt-
age
2.0
Low Level Input Volt-
age
VIL
VOH
VOL
—
—
—
—
0.8
—
V
V
V
High Level Output
Voltage
VDDA,
DDB – 0.4
loh = –4 mA
lol = 4 mA
V
Low Level Output
Voltage
—
0.4
Input Leakage Cur-
rent
IL
-10
—
—
+10
—
µA
Ω
Output Impedance
ZO
50
Supply Current, CLOAD = 15 pF
DC, VDDx = 3.3 V ± 10%
Si88x40ED
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
7.5
3.5
1.5
2.5
10.5
5.5
4.5
4.5
13.5
7.5
7.8
6.5
VDDB
mA
mA
mA
VDDA
VDDB
Si88x41ED
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
6.7
5.0
1.5
2.5
9.7
7.0
4.5
4.5
12.7
9.0
7.8
6.5
VDDB
VDDA
VDDB
Si88x42ED
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
5.2
6.1
1.5
2.5
8.2
8.1
4.5
4.5
11.2
10.1
7.8
VDDB
VDDA
6.5
VDDB
Si88x43ED
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
3.7
7.5
1.5
2.5
6.7
9.5
4.5
4.5
9.7
11.5
7.8
VDDB
mA
VDDA
6.5
VDDB
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Si88x4x Data Sheet
Electrical Specifications
Parameter
Si88x44ED
VDDA
Symbol
Test Condition
Min
Typ
Max
Unit
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
1.9
9.0
1.5
2.5
4.9
11.0
4.5
7.9
13.0
7.8
VDDB
mA
VDDA
4.5
6.5
VDDB
Si88x40BD
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
1.5
2.5
7.5
3.5
4.5
4.5
7.8
6.5
VDDB
mA
mA
mA
mA
mA
10.5
5.5
13.5
7.5
VDDA
VDDB
Si88x41BD
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
1.5
2.5
6.7
5.0
4.5
4.5
9.7
7.0
7.8
6.5
VDDB
12.7
9.0
VDDA
VDDB
Si88x42BD
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
1.5
2.5
5.2
6.1
4.5
4.5
8.2
8.1
7.8
6.5
VDDB
11.2
10.1
VDDA
VDDB
Si88x43BD
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
1.5
2.5
3.7
7.5
4.5
4.5
6.7
9.5
7.8
6.5
VDDB
9.7
VDDA
11.5
VDDB
Si88x44BD
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
1.5
2.5
1.9
9.0
4.5
4.5
7.8
6.5
VDDB
4.9
7.9
VDDA
11.0
13.0
VDDB
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Rev. 1.01 | 28
Si88x4x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
mA
mA
mA
mA
mA
mA
Supply Current, CLOAD = 15 pF
DC, VDDx = 5 V ± 10%
Si88x40ED
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
10.3
3.8
4.0
2.8
13.3
5.8
7.0
4.8
16.3
7.8
VDDB
10.0
6.8
VDDA
VDDB
Si88x41ED
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
9.0
5.0
4.0
2.8
12.0
7.0
7.0
4.8
15.0
9.0
VDDB
10.0
6.8
VDDA
VDDB
Si88x42ED
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
7.8
6.3
4.0
2.8
10.8
8.3
7.0
4.8
12.8
10.3
10.0
6.8
VDDB
VDDA
VDDB
Si88x43ED
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
6.5
7.5
4.0
2.8
9.5
9.5
7.0
4.8
12.5
11.5
10.0
6.8
VDDB
VDDA
VDDB
Si88x44ED
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
4.3
9.0
4.0
2.8
7.3
11.0
7.0
10.3
13.0
10.0
6.8
VDDB
VDDA
4.8
VDDB
Si88x40BD
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
4.0
2.8
7.0
4.8
10.0
6.8
VDDB
10.3
3.8
13.3
5.8
16.3
7.8
VDDA
VDDB
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Si88x4x Data Sheet
Electrical Specifications
Parameter
Si88x41BD
VDDA
Symbol
Test Condition
Min
Typ
Max
Unit
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
4.0
2.8
9.0
5.0
7.0
4.8
10.0
6.8
VDDB
mA
12.0
7.0
15.0
9.0
VDDA
VDDB
Si88x42BD
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
4.0
2.8
7.8
6.3
7.0
4.8
10.0
6.8
VDDB
mA
mA
mA
10.8
8.3
12.8
10.3
VDDA
VDDB
Si88x43BD
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
4.0
2.8
6.5
7.5
7.0
4.8
9.5
9.5
10.0
6.8
VDDB
12.5
11.5
VDDA
VDDB
Si88x44BD
VDDA
All inputs = 0
All inputs = 0
All inputs = 1
All inputs = 1
4.0
2.8
4.3
9.0
7.0
4.8
10.0
6.8
VDDB
7.3
10.3
13.0
VDDA
11.0
VDDB
Timing Characteristics
Data Rate
0
—
—
100
—
Mbps
ns
Minimum Pulse
Width
10
Propagation Delay
Propagation Delay
Propagation Delay
Propagation Delay
tPHL
tPLH
tPHL
tPLH
See Figure 5.1 Propagation De-
lay Timing for Digital Channels
on page 31
12.0
11.0
13.0
10.0
17.0
15.0
18.0
13.0
22.0
20.0
23.0
18.0
ns
ns
ns
ns
VDDx = 3.3 V
See Figure 5.1 Propagation De-
lay Timing for Digital Channels
on page 31
VDDx = 3.3 V
See Figure 5.1 Propagation De-
lay Timing for Digital Channels
on page 31
VDDx = 5.0 V
See Figure 5.1 Propagation De-
lay Timing for Digital Channels
on page 31
VDDx = 5.0 V
silabs.com | Building a more connected world.
Rev. 1.01 | 30
Si88x4x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Pulse Width Distor-
tion
PWD
See Figure 5.1 Propagation De-
lay Timing for Digital Channels
on page 31
—
2.5
5.0
ns
|tPLH – tPHL
|
VDDx = 3.3 V
Pulse Width Distor-
tion
PWD
See Figure 5.1 Propagation De-
lay Timing for Digital Channels
on page 31
—
4.5
7.0
ns
|tPLH – tPHL
|
VDDx = 5.0 V
Propagation Delay
Skew6
tPSK(P-P)
—
—
3.0
2.0
10.0
4.0
ns
ns
Channel-Channel
Skew
tPSK
Output Rise Time
Output Fall Time
tr
tf
CLOAD = 15 pF
CLOAD = 15 pF
VI = VDDx or 0 V
VCM = 1500 V
—
—
40
2.5
2.5
100
—
—
—
ns
ns
Common Mode
Transient Immunity
CMTI
kV/µs
See Figure 5.4 Common-Mode
Transient Immunity Test Circuit
on page 33
Startup Time7
tSU
—
55
—
µs
Note:
1. Over recommended operating conditions as noted in Table 5.1 Recommended Operating Conditions on page 24.
2. VOUT = VSNS x (1 + R1/R2) + R1 x Ioffset
3. VDDP current needed for dc-dc circuits.
4. VDDA current needed for dc-dc circuits.
5. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
6. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
7. Start-up time is the time period from when the UVLO threshold is exceeded to valid data at the output.
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 5.1. Propagation Delay Timing for Digital Channels
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Si88x4x Data Sheet
Electrical Specifications
IIN
C1
D1
T1
DB2440100L
10 µF
R4
100
+
+
VOUT
_
C3
C2
VIN
10 µF
10 µF
C5
_
100 pF
UTB02185S
U1
VSW
IDDB
IDDP
VDDB
VDDP
VDDA
R1
49.9 k
IDDA
VSNS
COMP
R3
49.9 k
R2
13.3 k
SH
C4
GNDA
GNDP
1.5 nF
GNDB
Figure 5.2. Measurement Circuit for Converter Efficiency and Regulation for Si882xx, Si883xx
ILOAD
IIN
IDDP
IDDA
D1
T1
SBRT5A50SA
R8
27.4
R9
82
+
+
C3
C2
VIN
VOUT
22 µF
10 µF
C7
C6
_
_
100 pF
68 pF
UTB02205S
U2
IDDB
Q1
FDT3612
ESW
VDDB
RSNS
R1
49.9 k
R5
0.1
R7
19.6 k
VSNS
GNDP
VREG
COMP
Q2
R3
100 k
R2
13.3 k
MMBT2222LT1
C5
0.1 µF
C4
VDDA
1.5 nF
C8
GNDB
10 µF
SS
SH_FC
C1
R6
18 k
0.22 µF
GNDA
Figure 5.3. Measurement Circuit for Converter Efficiency and Regulation for Si884xx, Si886xx
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Si88x4x Data Sheet
Electrical Specifications
DC-DC Output
Powers B-side
Referenced to
Earth Ground
Si8824x
VSW
VDDB
VDDP/VDDA
Oscilloscope
Forward
Channel
Input
Forward
Channel
Ouput
Reverse
Channel
Measured by
Forward
Channel in
Loopback
Isolated
Supply
+
_
Reverse
Channel
Output
Reverse
Channel
Input
GNDB
GNDA
High Voltage
Differential
Probe
High Voltage Transient Generator
Figure 5.4. Common-Mode Transient Immunity Test Circuit
Table 5.3. Regulatory Information1, 2
CSA
The Si88xx is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number
232873.
60950-1: Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
VDE
The Si88xx is certified according to VDE 0884-10. For more details, see certificate 40018443.
VDE 0884-10: Up to 891 Vpeak for basic insulation working voltage.
UL
The Si88xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si88xx is certified under GB4943.1-2011.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 3.75 and 5.0 kVRMS rated devices, which are production tested to 4.5 and 6.0 kVRMS
for 1 sec, respectively.
2. All certifications are pending.
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Rev. 1.01 | 33
Si88x4x Data Sheet
Electrical Specifications
Table 5.4. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
Unit
WB SOIC-20
WB SOIC-24
8.01
Nominal External Air Gap (Clear-
ance)
CLR
CPG
DTI
mm
mm
mm
8.01
Nominal External Tracking (Cree-
page)
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
Erosion Depth
0.014
PTI or CTI
ED
IEC60112
f = 1 MHz
600
V
mm
Ω
0.019
Resistance (Input-Output)2
Capacitance (Input-Output)2
1012
1.4
RIO
CIO
CI
pF
pF
Input Capacitance3
4.0
Note:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage
limits as 8.5 mm minimum for the WB SOIC-20 and WB SOIC-24 packages. UL does not impose a clearance and creepage mini-
mum for component-level certifications. CSA certifies the clearance and creepage limits as 7.6 mm minimum for the WB SOIC-20
and WB SOIC-24 packages.
2. To determine resistance and capacitance, the Si88xx is converted into a 2-terminal device.
3. Measured from input to ground.
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Si88x4x Data Sheet
Electrical Specifications
Table 5.5. IEC 60664-1 Ratings
Test Condition
Parameter
Specification
WB SOIC-20
WB SOIC-24
Basic Isolation Group
Material Group
I
Installation Classification
Rate Mains Voltages <150 VRMS
Rate Mains Voltages <300 VRMS
Rate Mains Voltages <400 VRMS
Rate Mains Voltages <600 VRMS
I–IV
I–IV
I–III
I–III
Table 5.6. VDE 0884-10 Insulation Characteristics1
Parameter
Symbol
Test Condition
Characteristic
WB SOIC-20
WB SOIC-24
Unit
Maximum Working
Insulation Voltage
VIORM
891
V peak
V peak
Input to Output Test Volt-
age
VPR
Method b1
(VIORM x 1.875 = VPR
100%
1671
,
Production Test,
tm = 1 sec,
Partial Discharge < 5 pC)
Transient Overvoltage
Surge Voltage
VIOTM
t = 60 sec
6000
V peak
Tested per IEC 60065
with surge voltage of 1.2
µs/50 µs
VIOSM
Tested with 4000 V
3077
2
V peak
Pollution Degree
(DIN VDE 0110, Table 1)
>109
Insulation Resistance at
TS, VIO = 500 V
RS
Ω
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si88xx provides a climate classification of 40/125/21.
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Rev. 1.01 | 35
Si88x4x Data Sheet
Electrical Specifications
Table 5.7. IEC Safety Limiting Values1
Parameter
Symbol
Test Condition
WB SOIC-20, WB SO-
Unit
IC-24
Safety Temperature
Safety Input Current
Device Power Dissipation
TS
IS
150
°C
mA
W
θJA = 55 °C/W
(WB SOIC-20),
413
PD
2.27
VDDA = 5.5 V,
TJ = 150 °C, TA = 25 °C
Note:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 5.5 WB SOIC-20/24 Thermal De-
rating Curve (Dependence of Safety Limiting Values per VDE) on page 36.
Table 5.8. Thermal Characteristics
Parameter
Symbol
WB SOIC-20, WB SOIC-24
Unit
IC Junction-to-Air Thermal Re-
sistance
θJA
55
°C/W
Figure 5.5. WB SOIC-20/24 Thermal Derating Curve (Dependence of Safety Limiting Values per VDE)
Table 5.9. Absolute Maximum Ratings1
Parameter
Symbol
TSTG
Min
–65
—
Max
+150
+150
6.0
Unit
°C
°C
V
Storage Temperature
Junction Temperature
Input-side Supply Voltage
TJ
VDDA
VDDP
–0.6
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Si88x4x Data Sheet
Electrical Specifications
Parameter
Symbol
VDDB
VIN
Min
–0.6
–0.5
Max
6.0
Unit
V
Output supply
Voltage on any Pin with respect to
Ground
VDD + 0.5
V
Output Drive Current per Channel
Input Current for VREGA, VREGB
Lead Solder Temperature (10 s)
ESD per AEC-Q100
IO
10
1
mA
mA
°C
IREG
—
—
—
—
—
260
4
HBM
CDM
kV
2
kV
Maximum Isolation (Input to Out-
put) (1 sec)
6500
VRMS
WB SOIC-20, WB SOIC-24
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
5.1 Calculating Total Current Consumption
For calculating dynamic supply current, use the following guidelines:
The dynamic current is calculated as follows:
D
2
IDD ac = C
× V ×
× 1E − 3
(
)
(
)
( )
(
)
L
Where
IDD(ac) is the dynamic component of current, per output channel, in mA
D is the data-rate of that channel, in Mbps
CL is the load capacitance connected to the output, in pF
V is the VDD on the output side, in Volts
For example, for the Si88x42ED-IS, the total current can be calculated as follows:
The average DC IDDA/B is the average of the DC current values at input 0 and input 1, for VDDA and VDDB respectively (max values
used), as stated in the table above for Si88x42ED.
CL, pF VDD, V Data-rate,
MBps
IDD(ac), per
output channel,
mA
Total IDDA(ac),
mA
Total
Average
Average Total IDDA, mA
Total
IDDB, mA
IDDB(ac), DC IDDA, DC IDDB,
mA
mA
mA
20
3.3
10
0.33
0.66
0.66
9.35
8.3
10.01
8.96
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Si88x4x Data Sheet
Pin Descriptions
6. Pin Descriptions
20
19
18
GNDP
VSW
VDDP
VDDA
GNDA
SH
1
2
3
4
5
6
GNDB
20
19
18
1
2
3
4
5
6
GNDP
VSW
VDDP
VDDA
GNDA
SH
GNDB
VDDB
VDDB
DNC/VREGB
DNC/VREGB
17 NC
17 NC
VSNS
16
VSNS
16
15 COMP
15 COMP
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
B1
14
7
8
A1
B1
14
7
8
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A2
13 B2
A2
13 B2
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A3
B3
B4
12
11
9
A3
B3
B4
12
11
9
HF
RCVR
HF
XMTR
HF
XMTR
HF
RCVR
A4
10
A4
10
Si88241
Si88240
20
1
GNDP
VSW
VDDP
VDDA
GNDA
SH
GNDB
20
1
GNDP
VSW
VDDP
VDDA
GNDA
SH
GNDB
19
18
2
3
4
5
6
VDDB
19
18
2
3
4
5
6
VDDB
DNC/VREGB
DNC/VREGB
17 NC
17 NC
VSNS
16
VSNS
16
15 COMP
15 COMP
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
B1
14
7
8
A1
B1
14
7
8
HF
RCVR
HF
XMTR
HF
XMTR
HF
RCVR
A2
13 B2
A2
13 B2
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
A3
B3
B4
12
11
9
A3
B3
B4
12
11
9
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
A4
10
A4
10
Si88243
Si88242
20
19
18
1
2
3
4
5
6
GNDP
VSW
VDDP
VDDA
GNDA
SH
GNDB
VDDB
DNC/VREGB
17 NC
VSNS
16
15 COMP
HF
RCVR
HF
XMTR
A1
B1
14
7
8
HF
RCVR
HF
XMTR
A2
13 B2
HF
RCVR
HF
XMTR
A3
B3
B4
12
11
9
HF
RCVR
HF
XMTR
A4
10
Si88244
Figure 6.1. Si8824x Pin Configurations
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Si88x4x Data Sheet
Pin Descriptions
24
23
22
24
23
22
1
2
3
4
5
6
7
1
2
3
4
5
6
7
GNDP
VSW
VDDP
VDDA
GNDA
NC
GNDB
GNDP
VSW
VDDP
VDDA
GNDA
NC
GNDB
VDDB
VDDB
DNC/VREGB
DNC/VREGB
21 NC
21 NC
VSNS
VSNS
20
20
19 COMP
19 COMP
SH_FC
SS
SH_FC
SS
18
17
18
17
NC
NC
B1
NC
NC
B1
8
8
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
A2
A3
A4
16
A1
A2
A3
A4
9
16
9
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
15 B2
10
15 B2
10
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
B3
B4
14
13
B3
B4
11
12
14
13
11
12
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
Si88340
Si88341
24
23
22
24
23
22
1
2
3
4
5
6
7
1
2
3
4
5
6
7
GNDP
VSW
VDDP
VDDA
GNDA
NC
GNDB
GNDP
VSW
VDDP
VDDA
GNDA
NC
GNDB
VDDB
VDDB
DNC/VREGB
DNC/VREGB
21 NC
21 NC
VSNS
VSNS
20
20
19 COMP
19 COMP
SH_FC
SS
SH_FC
SS
18
17
18
17
NC
NC
B1
NC
NC
B1
8
8
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
A2
A3
A4
A1
A2
A3
A4
16
9
16
9
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
15 B2
10
15 B2
10
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
B3
B4
14
13
B3
B4
14
13
11
12
11
12
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
Si88342
Si88343
24
23
22
1
2
3
4
5
6
7
GNDP
GNDB
VDDB
DNC/VREGB
VSW
VDDP
VDDA
GNDA
NC
21 NC
VSNS
20
19 COMP
SH_FC
SS
18
17
NC
NC
B1
8
HF
RCVR
HF
XMTR
A1
A2
A3
A4
16
9
HF
RCVR
HF
XMTR
15 B2
10
HF
RCVR
HF
XMTR
B3
B4
14
13
11
12
HF
RCVR
HF
XMTR
Si88344
Figure 6.2. Si8834x Pinout Diagrams
silabs.com | Building a more connected world.
Rev. 1.01 | 39
Si88x4x Data Sheet
Pin Descriptions
20
19
18
20
19
18
1
2
3
4
5
6
1
2
3
4
5
6
GNDP
RSN
GNDB
GNDP
RSN
GNDB
VDDB
VDDB
ESW
VDDA
GNDA
VREGA
A1
DNC/VREGB
ESW
VDDA
GNDA
VREGA
A1
DNC/VREGB
17 NC
17 NC
VSNS
VSNS
16
16
15 COMP
15 COMP
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
B1
B1
14
14
7
8
7
8
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A2
13 B2
A2
13 B2
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A3
A3
B3
B4
B3
B4
12
11
12
11
9
9
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
A4
A4
10
10
Si88440
Si88441
20
19
18
1
2
3
4
5
6
GNDP
RSN
GNDB
20
19
18
1
2
3
4
5
6
GNDP
RSN
GNDB
VDDB
VDDB
ESW
VDDA
GNDA
VREGA
A1
DNC/VREGB
ESW
VDDA
GNDA
VREGA
A1
DNC/VREGB
17 NC
17 NC
VSNS
16
VSNS
16
15 COMP
15 COMP
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
B1
14
7
8
B1
14
7
8
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
A2
13 B2
A2
13 B2
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
A3
B3
B4
12
11
9
A3
B3
B4
12
11
9
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
10
A4
A4
10
Si88442
Si88443
20
1
2
3
4
5
6
GNDP
RSN
GNDB
VDDB
19
18
ESW
VDDA
GNDA
VREGA
A1
DNC/VREGB
17 NC
VSNS
16
15 COMP
HF
RCVR
HF
XMTR
B1
14
7
8
HF
RCVR
HF
XMTR
A2
13 B2
HF
RCVR
HF
XMTR
A3
B3
B4
12
11
9
HF
RCVR
HF
XMTR
A4
10
Si88444
Figure 6.3. Si8844x Pinout Diagrams
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Rev. 1.01 | 40
Si88x4x Data Sheet
Pin Descriptions
24
23
22
24
23
22
1
2
3
4
5
6
7
1
2
3
4
5
6
7
GNDP
RSN
GNDB
GNDP
RSN
GNDB
VDDB
VDDB
ESW
DNC/VREGB
ESW
DNC/VREGB
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VSNS
VSNS
20
20
19 COMP
19 COMP
18
17
18
17
NC
NC
B1
NC
NC
B1
8
8
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
A2
A3
A4
16
A1
A2
A3
A4
9
16
9
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
15 B2
10
15 B2
10
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
B3
B4
14
13
B3
B4
11
12
14
13
11
12
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
Si88640
Si88641
24
23
22
24
23
22
1
2
3
4
5
6
7
1
2
3
4
5
6
7
GNDP
RSN
GNDB
GNDP
RSN
GNDB
VDDB
VDDB
ESW
DNC/VREGB
ESW
DNC/VREGB
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VSNS
VSNS
20
20
19 COMP
19 COMP
18
17
18
17
NC
NC
B1
NC
NC
B1
8
8
HF
XMTR
HF
RCVR
HF
XMTR
HF
RCVR
A1
A2
A3
A4
A1
A2
A3
A4
16
9
16
9
HF
XMTR
HF
RCVR
HF
RCVR
HF
XMTR
15 B2
10
15 B2
10
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
B3
B4
14
13
B3
B4
14
13
11
12
11
12
HF
RCVR
HF
XMTR
HF
RCVR
HF
XMTR
Si88642
Si88643
24
23
22
1
2
3
4
5
6
7
GNDP
GNDB
VDDB
DNC/VREGB
RSN
ESW
VDDA
GNDA
VREGA
SH_FC
SS
21 NC
VSNS
20
19 COMP
18
17
NC
NC
B1
8
HF
RCVR
HF
XMTR
A1
A2
A3
A4
16
9
HF
RCVR
HF
XMTR
15 B2
10
HF
RCVR
HF
XMTR
B3
B4
14
13
11
12
HF
RCVR
HF
XMTR
Si88644
Figure 6.4. Si8864x Pinout Diagrams
silabs.com | Building a more connected world.
Rev. 1.01 | 41
Si88x4x Data Sheet
Pin Descriptions
Table 6.1. Si88x4x Pin Descriptions
Description
Pin Name
DC-DC Input Side
VDDP
Power stage primary power supply.
Voltage reference output for external voltage regulator pin.
Power stage ground.
VREGA
GNDP
ESW
Power stage external switch driver output.
Power stage internal switch output.
Soft startup control.
VSW
SS
SH, SH_FC
RSN
Shutdown and Switch frequency control.
Power stage current sense input.
DC-DC Output Side
VSNS
Power stage feedback input.
Power stage compensation.
COMP
DNC/VREGB
Voltage reference output for external voltage regulator pin. This pin has a
Zener connected internally. Use this pin as reference only when output
voltage from dc-dc is > 5.5 V. If output voltage is ≤ 5.5V, this pin should be
read as DNC or Do Not Connect, and should be no connect.
NC
No connect; this pin is not connected to the silicon.
Digital Isolator VDDA Side
VDDA
Primary side signal power supply.
I/O signal channel 1–4.
A1–A4
GNDA
Primary side signal ground.
Digital Isolator VDDB Side
VDDB
B1–B4
GNDB
Secondary side signal power supply.
I/O signal channel 1–4.
Secondary side signal ground.
silabs.com | Building a more connected world.
Rev. 1.01 | 42
Si88x4x Data Sheet
Package Outline: 20-Pin Wide Body SOIC
7. Package Outline: 20-Pin Wide Body SOIC
Figure 7.1 20-Pin Wide Body SOIC on page 43 illustrates the package details for the 20-pin wide-body SOIC package. Table 7.1 20-
Pin Wide Body SOIC Package Diagram Dimensions on page 43 lists the values for the dimensions shown in the illustration.
Figure 7.1. 20-Pin Wide Body SOIC
Table 7.1. 20-Pin Wide Body SOIC Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
12.80 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
—
0.10
silabs.com | Building a more connected world.
Rev. 1.01 | 43
Si88x4x Data Sheet
Package Outline: 20-Pin Wide Body SOIC
Dimension
Min
—
Max
0.33
0.10
0.25
0.10
0.20
bbb
ccc
ddd
eee
fff
—
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AC.
4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.
silabs.com | Building a more connected world.
Rev. 1.01 | 44
Si88x4x Data Sheet
Land Pattern: 20-Pin SOIC
8. Land Pattern: 20-Pin SOIC
Figure 8.1 20-Pin SOIC PCB Land Pattern on page 45 illustrates the PCB land pattern details for the 20-pin SOIC package. Table
8.1 24-Pin SOIC PCB Land Pattern Dimensions on page 45 lists the values for the dimensions shown in the illustration.
Figure 8.1. 20-Pin SOIC PCB Land Pattern
Table 8.1. 24-Pin SOIC PCB Land Pattern Dimensions
Dimension
mm
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Note:
1. This Land Pattern Design is based on IPC-7351 design guidelines for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC), and a card fabrication tolerance of 0.05 mm is assumed.
silabs.com | Building a more connected world.
Rev. 1.01 | 45
Si88x4x Data Sheet
Package Outline: 24-Pin Wide Body SOIC
9. Package Outline: 24-Pin Wide Body SOIC
Figure 9.1 24-Pin Wide Body SOIC on page 46 illustrates the package details for the 24-pin wide-body SOIC package. Table 9.1 24-
Pin Wide Body SOIC Package Diagram Dimensions on page 46 lists the values for the dimensions shown in the illustration.
Figure 9.1. 24-Pin Wide Body SOIC
Table 9.1. 24-Pin Wide Body SOIC Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
15.40 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
bbb
—
0.10
0.33
—
silabs.com | Building a more connected world.
Rev. 1.01 | 46
Si88x4x Data Sheet
Package Outline: 24-Pin Wide Body SOIC
Dimension
Min
—
Max
0.10
0.25
0.10
0.20
ccc
ddd
eee
fff
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AD.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
silabs.com | Building a more connected world.
Rev. 1.01 | 47
Si88x4x Data Sheet
Land Pattern: 24-Pin SOIC
10. Land Pattern: 24-Pin SOIC
Figure 10.1 24-Pin SOIC PCB Land Pattern on page 48 illustrates the PCB land pattern details for the 24-pin SOIC package. Table
10.1 24-Pin SOIC PCB Land Pattern Dimensions on page 48 lists the values for the dimensions shown in the illustration.
Figure 10.1. 24-Pin SOIC PCB Land Pattern
Table 10.1. 24-Pin SOIC PCB Land Pattern Dimensions
Dimension
mm
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Note:
1. This Land Pattern Design is based on IPC-7351 design guidelines for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC), and a card fabrication tolerance of 0.05 mm is assumed.
silabs.com | Building a more connected world.
Rev. 1.01 | 48
Si88x4x Data Sheet
Top Markings
11. Top Markings
11.1 Si88x4x Top Marking (20-Pin Wide Body SOIC)
11.2 Top Marking Explanation (20-Pin Wide Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
Si88x4 = 5 kV rated 4 channel digital isolator with dc-dc
converter
X = 2, 4
See Ordering Guide for more infor-
mation.
• 2 = dc-dc shutdown
• 4 = External FET
Y = Number of reverse channels
Z = E, B
• E = default high
• B = default low
R = C, D
• C = 3.75 kVRMS
• D = 5 kVRMS isolation rating
Line 2 Marking:
Line 3 Marking:
YY = Year
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
WW = Workweek
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order
form.
Circle = 1.5 mm Diameter
(Center Justified)
“e4” Pb-Free Symbol
Country of Origin
TW = Taiwan
ISO Code Abbreviation
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Rev. 1.01 | 49
Si88x4x Data Sheet
Top Markings
11.3 Si88x4x Top Marking (24-Pin Wide Body SOIC)
11.4 Top Marking Explanation (24-Pin Wide Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
Si88x4 = 5kV rated 4 channel digital isolator with dc-dc convert-
er
X = 3, 6
See Ordering Guide for more in-
formation.
• 3 = Full-featured dc-dc with internal FET
• 6 = Full-featured dc-dc with external FET
Y = Number of reverse channels
Z = E, B
• E = default high
• B = default low
R = C, D
• C = 3.75 kVRMS
• D = 5 kVRMS isolation rating
Line 2 Marking:
Line 3 Marking:
YY = Year
Assigned by the Assembly House. Corresponds to the year and
workweek of the mold date.
WW = Workweek
TTTTTT = Mfg Code
Circle = 1.5 mm Diameter
(Center Justified)
Country of Origin
ISO Code Abbreviation
Manufacturing Code from Assembly Purchase Order form.
“e4” Pb-Free Symbol
TW = Taiwan
silabs.com | Building a more connected world.
Rev. 1.01 | 50
Si88x4x Data Sheet
Revision History
12. Revision History
Rev. 1.01
March 2018
• Added Automotive Grade Ordering Guide
• Updated Ordering Guide Table 2.1
• Updated Transformer Table 3.1
• Updated Spec Table 4.2
• Added section 5.1 (Calculating total current)
Rev. 0.6
August 2015
• Reformatted figures
• Corrected typos
• Added text for clarity
silabs.com | Building a more connected world.
Rev. 1.01 | 51
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
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