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SL18860 [SILICON]

3-Channel Clock Distribution Buffer;
SL18860
型号： SL18860
厂家： SILICON    SILICON
描述：

3-Channel Clock Distribution Buffer
文件： 总12页 (文件大小：269K)
中文：  中文翻译
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SL18860DC  
3-Channel Clock Distribution Buffer  
Key Features  
Description  
The SL18860DC product is a high performance 3 output  
clock distribution buffer and provides 3 outputs from a  
single input clock by using SLI proprietary low phase  
noise and low power dissipation circuit design.  
•
Low current consumption  
- 2.7mA-typ (VDD=1.8V and CL=0)  
1.7V to 3.65V power supply operation  
10MHz to 52MHz CLKIN  
Supports LVCMOS and clipped sine wave inputs  
Suports 3 single-ended LVCMOS square wave  
outputs  
OE1/2/3 functions for each CLKOUT1/2/3 outputs  
OE_OSC control pin to enable external TCXO/XO  
Ultra-Low phase noise  
•
•
•
•
The SL18860DC can be used in baseband mobile RF  
applications including WLAN, Bluetooth and DVB-H as an  
input clock reference. The product designed to isolate  
each device driven by their clock outputs to minimize  
interference between these devices.  
•
•
•
•
•
•
Each of the clock buffer outputs can be individually  
disabled by using OE1/2/3 control pins to reduce the  
power consumption if the connected device does not need  
the clock. The device operates from single power supply  
from 1.7V to 3.65V and from -40 ºC to 85 ºC.  
Ultra low standby current  
10-pin TDFN package (1.4x2.0x0.75 mm)  
Industrial -40 ºC to 85 ºC temperature range  
Application  
Benefits  
•
•
•
•
Fast Time-to-market  
Cost Reduction  
Low Power Dissipation  
Low Phase Noise  
•
•
•
Smart Mobile Handsets  
Multi-mode RF Clock Distribution  
Baseband Peripheral Clock Distribution  
Block Diagram  
8
CLKOUT1  
3
9
CLKOUT2  
CLKIN  
4
OE_OSC  
10 CLKOUT3  
CONTROL LOGIC  
6
7
5
2
1
OE1  
OE2  
OE3  
VDD  
VSS  
Rev 1.8, March 16 , 2012  
400 West Cesar Chavez, Austin, TX 78701  
Page 1 of 12  
1+(512) 416-8500  
1+(512) 416-9669  
www.silabs.com  
SL18860DC  
Pin Configuration  
VSS  
VDD  
1
2
3
4
5
10  
9
CLKOUT3  
CLKOUT2  
CLKOUT1  
8
CLKIN  
OE_OSC  
7
OE2  
OE1  
OE3  
6
10-Pin TDFN Package Pinout  
Pin Description  
Pin  
Pin Name Pin Type  
Pin Description  
Number  
1
VSS  
Power  
Power supply ground.  
2
3
4
VDD  
CLKIN  
Power  
Input  
2.25 to 3.65V or 1.8V +/-5% positive power supply  
External clock input pin. VSS to VDD CMOS level.  
OE_OSC  
Output  
Crystal oscillator enable pin. If OE1=OE2=OE3=0 then OE_OSC=0.  
OE_OSC=1 for all the other OE1/2/3 logic states.  
5
6
7
OE3  
OE1  
OE2  
Input  
Input  
Input  
Output enable pin for CLKOUT3. The input has 150kΩ-typ on-chip pull-  
down resistor.  
Output enable pin for CLKOUT1. The input has 150kΩ-typ on-chip pull-  
down resistor.  
Output enable pin for CLKOUT2. The input has 150kΩ-typ on-chip pull-  
down resistor.  
8
9
CLKOUT1  
CLKOUT2  
CLKOUT3  
Output  
Output  
Output  
Clock output-1. Clock frequency is the same as CLKIN.  
Clock output-2. Clock frequency is the same as CLKIN.  
Clock output-3. Clock frequency is the same as CLKIN.  
10  
OE1  
(Input)  
OE2  
(Input)  
OE3  
(Input)  
OE_OSC  
(Output)  
CLKOUT1  
CLKOUT2  
CLKOUT3  
0
1
0
0
0
0
0
1
Hi-Z  
CLOCK  
CLOCK  
…
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
1
1
0
1
CLOCK  
…
Hi-Z  
…
1
…
1
…
1
…
1
…
CLOCK  
CLOCK  
CLOCK  
Table 1. Truth Table for OE1/2/3, OE_OSC and CLKOUT1/2/3  
Rev 1.8, March 16 , 2012  
Page 2 of 12  
SL18860DC  
Absolute Maximum Ratings  
Description  
Condition  
Min  
-0.5  
1.70  
-0.5  
-40  
Max  
4.6  
Unit  
V
Supply voltage, VDD (Absolute)  
Supply voltage, VDD (Operation)  
All Inputs and Outputs  
3.65  
VDD+0.5  
85  
V
V
Ambient Operating Temperature  
Storage Temperature  
In operation, C-Grade  
No power is applied  
°C  
°C  
°C  
°C  
V
-65  
150  
Junction Temperature  
In operation, power is applied  
-
125  
Soldering Temperature  
-
260  
ESD Rating (Human Body Model)  
ESD Rating (Charge Device Model)  
ESD Rating (Machine Model)  
JEDEC22-A114D  
JEDEC22-C101C  
JEDEC22-A115D  
-4,000  
-1,500  
-200  
4,000  
1,500  
200  
V
V
DC Electrical Characteristics (I-Grade)  
Unless otherwise stated VDD= 1.8V+/- 5% and Operation Temperature Range -40 to +85°C  
Description  
Operating Voltage  
Operating Temperature  
Symbol  
VDD  
TA  
Condition  
Operation range, 1.8V+/-5%  
I-Grade  
Min  
1.70  
Typ  
1.80  
25  
Max  
1.90  
Unit  
V
ºC  
V
-40  
85  
Input Low Voltage  
VIL  
CMOS Level, Pins 3,5, 6 and 7  
VSS  
-
0.3VDD  
Input High Voltage  
Output High Voltage  
VIH  
CMOS Level, Pins 3,5, 6 and 7  
IOH=-4mA , Pins 4, 8, 9 and 10  
0.7VDD  
VDD-0.4  
-
-
VDD  
-
V
V
VOH  
Output Low Voltage  
Input Leakage Current  
Input Leakage Current  
VOL  
ILH  
ILL  
IOL=-4mA, Pins 4, 8, 9 and 10  
VIN=VDD, Pins 5, 6 and 7  
VIN=GND, Pins 5, 6 and 7  
-
-
-
-
0.4  
25  
10  
V
-25  
-10  
μA  
μA  
Pull-Down Resistor  
RPD  
IDD1  
Pins 5, 6 and 7  
100  
-
150  
2.7  
250  
-
kΩ  
CLKIN=26MHz,  
Operating Supply Current  
mA  
OE1=OE2=OE3=1  
OE1=OE2=OE3=0  
CLKIN=Low or High  
Operating Supply Current  
IDD2  
-
-
1.0  
µA  
Input Capacitance  
Load Capacitance  
CIN  
CL  
Pins 5, 6 and 7  
-
-
3
5
pF  
pF  
CLKOUT1/2/3, Pins 8, 9 and 10  
10  
20  
Rev 1.8, March 16 , 2012  
Page 3 of 12  
SL18860DC  
AC Electrical Characteristics (I-Grade)  
Unless otherwise stated VDD= 1.8V+/- 5% and Operation Temperature Range -40 to +85°C  
Parameter  
Symbol  
Condition  
Min  
Typ  
Max  
Unit  
Input Clock Range  
CLKIN  
External Clock, CMOS square wave  
External Clock, CMOS square wave  
10  
26.000  
52  
MHz  
Output Clock Range  
CLKOUT  
VINpp  
10  
0.72  
30  
26.000  
52  
-
MHz  
Vpp  
%
CLKOUT1/2/3  
VDD=1.8V  
Input Clock Voltage  
Swing Level  
1
Input Duty Cycle  
DCIN  
CLKIN, Pin 3  
50  
70  
VDD=1.8, CL=10pF, measured from  
10 to 90% of VDD, Pins 4, 8, 9 and  
10  
Output Clock Rise  
Time  
tr  
tf  
-
-
2.0  
2.0  
4.00  
4.00  
ns  
ns  
VDD=1.8, CL=10pF, measured from  
10 to 90% of VDD, Pins 4, 8, 9 and  
10  
Output Clock Fall  
Time  
CLKIN=26MHz and 1 kHz offset  
CLKOUT1/2/3  
Additive Phase Noise  
Additive Phase Noise  
Additive Phase Noise  
APN-1  
APN-2  
APN-3  
-
-
-
-140  
-150  
-159  
-
-
-
dBc/Hz  
dBc/Hz  
dBc/Hz  
CLKIN=26MHz and 10 kHz offset  
CLKOUT1/2/3  
CLKIN=26MHz and 100 kHz offset  
CLKOUT1/2/3  
Time duration until CLKOUT1/2/3  
frequency reaches valid frequency  
after power supply reaches 0.9xVDD  
value  
Power-up Time  
tPU  
-
100  
200  
Ns  
Time from OE raising edge to active  
at outputs CLKOUT1/2/3  
(Asynchronous)  
Output Enable Time  
Output Disable Time  
Output Enable Time  
tOE1  
tOD  
-
-
-
25  
25  
-
-
-
ns  
ns  
Ns  
Time from OE falling edge to Hi-Z at  
outputs CLKOUT1/2/3  
(Asynchronous)  
Active recovery time from standby  
(CLKIN=0 or 1) to active at outputs  
CLKOUT1/2/3  
tOE2  
100  
Rev 1.8, March 16 , 2012  
Page 4 of 12  
SL18860DC  
DC Electrical Characteristics (I-Grade)  
Unless otherwise stated VDD= 2.5V+/- 10% and Operation Temperature Range -40 to +85°C  
Description  
Operating Voltage  
Operating Temperature  
Symbol  
VDD  
TA  
Condition  
Min  
2.25  
Typ  
2.50  
25  
Max  
2.75  
Unit  
V
Operation range, 2.5V+/-10%  
I-Grade  
-40  
85  
ºC  
V
Input Low Voltage  
VIL  
CMOS Level, Pins 3,5, 6 and 7  
VSS  
-
0.3VDD  
Input High Voltage  
Output High Voltage  
VIH  
CMOS Level, Pins 3,5, 6 and 7  
IOH=-4mA , Pins 4, 8, 9 and 10  
0.7VDD  
VDD-0.4  
-
-
VDD  
-
V
V
VOH  
Output Low Voltage  
Input Leakage Current  
Input Leakage Current  
VOL  
ILH  
ILL  
IOL=-4mA, Pins 4, 8, 9 and 10  
VIN=VDD, Pins 5, 6 and 7  
VIN=GND, Pins 5, 6 and 7  
-
-
-
-
0.4  
30  
15  
V
-30  
-15  
μA  
μA  
Pull-Down Resistor  
RPD  
IDD1  
Pins 5, 6 and 7  
100  
-
150  
3.0  
250  
-
kΩ  
CLKIN=26MHz,  
Operating Supply Current  
mA  
OE1=OE2=OE3=1  
OE1=OE2=OE3=0  
CLKIN=Low or High  
Operating Supply Current  
IDD2  
-
-
1.5  
µA  
Input Capacitance  
Load Capacitance  
CIN  
CL  
Pins 5, 6 and 7  
-
-
3
5
pF  
pF  
CLKOUT1/2/3, Pins 8, 9 and 10  
10  
20  
AC Electrical Characteristics (I-Grade)  
Unless otherwise stated VDD= 2.5V+/- 10% and Operation Temperature Range -40 to +85°C  
Parameter  
Symbol  
Condition  
Min  
Typ  
Max  
Unit  
Input Clock Range  
CLKIN  
External Clock, CMOS square wave  
External Clock, CMOS square wave  
10  
26.000  
52  
MHz  
Output Clock Range  
CLKOUT  
VINpp  
10  
26.000  
1.2  
52  
-
MHz  
V
CLKOUT1/2/3  
VDD=2.5V, connect to CLKIN directly  
1.0  
Input Clock Voltage  
Swing Level  
VDD=2.5V, connect to CLKIN through  
AC coupling and bias circuit  
0.6  
30  
-
-
V
Input Duty Cycle  
DCIN  
CLKIN, Pin 3  
50  
70  
%
VDD=1.8, CL=10pF, measured from  
10 to 90% of VDD, Pins 4, 8, 9 and  
10  
Output Clock Rise  
Time  
tr  
-
2.0  
4.00  
ns  
VDD=1.8, CL=10pF, measured from  
10 to 90% of VDD, Pins 4, 8, 9 and  
10  
Output Clock Fall  
Time  
tf  
-
-
2.0  
4.00  
-
ns  
CLKIN=26MHz and 1 kHz offset  
CLKOUT1/2/3  
Additive Phase Noise  
APN-1  
-142  
dBc/Hz  
Rev 1.8, March 16 , 2012  
Page 1 of 12  
www.silabs.com  
400 West Cesar Chavez, Austin, TX 78701  
1+(512) 416-8500  
1+(512) 416-9669  
SL18860DC  
CLKIN=26MHz and 10 kHz offset  
CLKOUT1/2/3  
Additive Phase Noise  
Additive Phase Noise  
Power-up Time  
APN-2  
APN-3  
tPU  
-
-
-
-156  
-164  
100  
-
-
dBc/Hz  
dBc/Hz  
ns  
CLKIN=26MHz and 100 kHz offset  
CLKOUT1/2/3  
Time for CLKOUT1/2/3 frequency to  
reach valid frequency after power  
supply reaches 0.9xVDDvalue  
200  
Time from OE raising edge to active  
at outputs CLKOUT1/2/3  
(Asynchronous)  
Output Enable Time  
Output Disable Time  
Output Enable Time  
tOE1  
tOD  
-
-
-
25  
25  
-
-
-
ns  
ns  
ns  
Time from OE falling edge to Hi-Z at  
outputs CLKOUT1/2/3  
(Asynchronous)  
Active recovery time from standby  
(CLKIN=0 or 1) to active at outputs  
CLKOUT1/2/3  
tOE2  
100  
DC Electrical Characteristics (I-Grade)  
Unless otherwise stated VDD= 3.3V+/- 10% and Operation Temperature Range -40 to +85°C  
Description  
Operating Voltage  
Operating Temperature  
Symbol  
VDD  
TA  
Condition  
Min  
2.95  
Typ  
3.3  
25  
-
Max  
3.65  
Unit  
V
Operation range , 3.3V+/-10%  
I-Grade  
-40  
85  
ºC  
V
Input Low Voltage  
VIL  
CMOS Level, Pins 3.5, 6 and 7  
VSS  
0.3VDD  
Input High Voltage  
Output High Voltage  
VIH  
CMOS Level, Pins 3.5, 6 and 7  
IOH=-4mA , Pins 4, 8, 9 and 10  
0.7VDD  
VDD-0.4  
-
-
VDD  
-
V
V
VOH  
Output Low Voltage  
Input Leakage Current  
Input Leakage Current  
VOL  
ILH  
ILL  
IOL=-4mA, Pins 4, 8, 9 and 10  
VIN=VDD, Pins 5, 6 and 7  
VIN=GND, Pins 5, 6 and 7  
-
-
-
-
0.5  
35  
20  
V
-35  
-20  
μA  
μA  
Pull-Down Resistor  
RPD  
IDD1  
Pins 5, 6 and 7  
100  
-
150  
3.4  
250  
-
kΩ  
CLKIN=26MHz,  
Operating Supply Current  
mA  
OE1=OE2=OE3=1  
OE1=OE2=OE3=0  
CLKIN=Low or High  
Operating Supply Current  
IDD2  
-
-
2.0  
µA  
Input Capacitance  
Load Capacitance  
CIN  
CL  
Pins 5, 6 and 7  
-
-
3
5
pF  
pF  
CLKOUT1/2/3, Pins 8, 9 and 10  
10  
25  
Rev 1.8, March 16 , 2012  
Page 2 of 12  
SL18860DC  
AC Electrical Characteristics (I-Grade)  
Unless otherwise stated VDD= 3.3V+/- 10% and Operation Temperature Range -40 to +85°C  
Parameter  
Symbol  
Condition  
Min  
Typ  
Max  
Unit  
Input Clock Range  
CLKIN  
External Clock, CMOS square wave  
External Clock, CMOS square wave  
10  
26.000  
52  
MHz  
Output Clock Range  
CLKOUT  
VINpp  
10  
26.000  
1.4  
52  
-
MHz  
V
CLKOUT1/2/3  
VDD=3.3V, connect to CLKIN directly  
1.32  
Input Clock Voltage  
Swing Level  
VDD=3.3V, connect to CLKIN through  
AC coupling and bias circuit  
0.6  
30  
-
-
V
Input Duty Cycle  
DCIN  
CLKIN, Pin 3  
50  
70  
%
VDD=1.8, CL=10pF, measured from  
10 to 90% of VDD, Pins 4, 8, 9 and  
10  
Output Clock Rise  
Time  
tr  
tf  
-
-
1.2  
1.2  
2.2  
2.2  
ns  
ns  
VDD=1.8, CL=10pF, measured from  
10 to 90% of VDD, Pins 4, 8, 9 and  
10  
Output Clock Fall  
Time  
CLKIN=26MHz and 1 kHz offset  
CLKOUT1/2/3  
Additive Phase Noise  
Additive Phase Noise  
Additive Phase Noise  
APN-1  
APN-2  
APN-3  
-
-
-
-138  
-157  
-165  
-
-
-
dBc/Hz  
dBc/Hz  
dBc/Hz  
CLKIN=26MHz and 10 kHz offset  
CLKOUT1/2/3  
CLKIN=26MHz and 100 kHz offset  
CLKOUT1/2/3  
Time duration until CLKOUT1/2/3  
frequency reaches valid frequency  
after power supply reaches 0.9xVDD  
value  
Power-up Time  
tPU  
-
100  
200  
ns  
Time from OE raising edge to active  
at outputs CLKOUT1/2/3  
(Asynchronous)  
Output Enable Time  
Output Disable Time  
Output Enable Time  
tOE1  
tOD  
-
-
-
25  
25  
-
-
-
ns  
ns  
ns  
Time from OE falling edge to Hi-Z at  
outputs CLKOUT1/2/3  
(Asynchronous)  
Active recovery time from standby  
(CLKIN=0 or 1) to active at outputs  
CLKOUT1/2/3  
tOE2  
100  
Rev 1.8, March 16 , 2012  
Page 3 of 12  
SL18860DC  
SL18860DC CLKOUT1/2/3  
Phase Noise (dBc/Hz) CL=15pF.  
VDD(V)  
1.8  
100hz  
-115.52  
1Khz  
-139.85  
10Khz  
-150.79  
100Khz  
-159.31  
1Mhz  
-160.52  
5Mhz  
-162.52  
Fig #  
1
2.5  
3.3  
-125.16  
-116.60  
-142.67  
-138.06  
-156.37  
157.41  
-164.02  
-164.88  
-166.45  
-167.21  
-167.02  
-168.57  
2
3
Table 2. Output Phase Noise Summary Table  
Figure 1. Output Phase Noise VDD=1.8V, CL=15pF  
Rev 1.8, March 16 , 2012  
Page 4 of 12  
SL18860DC  
Figure 2. Output Phase Noise VDD=2.5V, CL=15pF  
Figure 3. Output Phase Noise VDD=3.3V, CL=15pF  
Rev 1.8, March 16 , 2012  
Page 5 of 12  
SL18860DC  
Typical Application Circuit  
VDD=1.8V to 3.3V  
R1 (50Ω)  
C1 (10μF)  
C2 (0.1μF)  
2
CLKIN  
(26.000MHz-typ)  
3
4
(26.000MHz-typ)  
(26.000MHz-typ)  
(26.000MHz-typ)  
CLKOUT1  
CLKOUT2  
CLKOUT3  
8
9
OE_OSC  
SL18860DC  
OE1  
OE2  
OE3  
6
7
5
10  
1
VSS  
AC coupling and bias circuit  
Vcc  
R
C1  
VDD  
TCXO  
SL18860  
22nF  
R2  
Rev 1.8, March 16 , 2012  
Page 6 of 12  
SL18860DC  
Package Outline and Package Dimensions  
10-Pin TDFN Package (1.4x2.0x0.75 mm)  
Top View  
Side View  
Bottom View  
Side View  
Rev 1.8, March 16 , 2012  
Page 7 of 12  
SL18860DC  
Ordering Information  
Ordering Number  
Marking  
Shipping Package  
Package  
Temperature  
SL18860DC  
860  
860  
Tube  
10-pin TDFN  
10-pin TDFN  
-40 to 85°C  
-40 to 85°C  
SL18860DCT  
Tape and Reel  
Note:  
The SL18860 is RoHS compliant  
Marking Diagram:  
860  
YWW  
YWW:  
Pin 1  
Y = Last Digit of Year  
WW = Work Week  
The information in this document is believed to be accurate in all respects at the time of publication but is subject to  
change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims  
responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon  
Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon  
Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty,  
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon  
Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories  
products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for  
any other application in which the failure of the Silicon Laboratories product could create a situation where personal  
injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or  
unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and  
damages.  
Rev 1.8, March 16 , 2012  
Page 8 of 12  

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