SL23EP04SC-1HT [SILICON]
PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8;
| 型号： | SL23EP04SC-1HT |
| 厂家： | 
SILICON |
| 描述： | PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总16页 (文件大小：969K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL23EP04
Not Recommended for New Designs
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
Key Features
Description
The SL23EP04 is a low skew, low jitter power
Zero Delay Buffer (ZDB) designed to proto four
(4) clock outputs from one (1) refeinput clock, for
high speed clock distribution appons
10 to 220 MHz operating frequency range
Low output clock skew: 60ps-typ
Low output clock Jitter:
Low part-to-part output skew: 150 ps-typ
The product has an on-chip L and a feedback pin
(FBK) which can be used feedback from any
one of the 4 output clocks. 23EP04 offers X/2,1X
and 2X frequency options at the output with respect to
input reference clok. Refeto the “Product Coniguration
Table” for the details of these options.
3.3V to 2.5V power supply range
Low power dissipation:
- 12 mA-typ at 66MHz and VDD=3.3V
- 10 mA-typ at 66MHz and VDD=2.5V
One input drives 4 outputs
The SL23E1H and -2H High Drive version operates
up to 220 MHand 200MHz at 3.3 and 2.V power
supples respectively. The standard sions -1 and -2
operae up to 167MHz and 135MV and 2.5V
ower supplies respectively with CF utput load.
Multiple configurations and drive options
SpreadThru™ PLL that allows use of SSCG
Available in 8-pin SOIC package
Available in Commercial and Industrial grades
The SL23EP04 enter into Power Down (PD) mode if the
input at CLKIN is DC (GND to VDD). In this state all 4
output clocks are tri-stated and he PLL is turned off,
leading to 8μA-typ r supply current draw.
Applications
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Datacom and Telecom
Benefits
4) distribution of input clock
High-Speed Digital Embeded Sstems
Std High-Drive levels to control
impee level, frequency range and EMI
Low skew, jitter and power dissipation
Block Diagram
FBK
Low Power and
Low Jitter
PLL
CLKA1
CLKA2
CLKIN
(Divider for -2 only)
/2
CLKB1
CLKB2
VDD
GND
Rev 2.1, May 15, 2008
2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500
Page 1 of 15
www.silabs.com
1+(512) 416-9669
SL23EP04
Pin Configuration
CLKIN
CLKA1
CLKA2
GND
1
2
3
4
8
7
6
5
FBK
VDD
CLKB2
CLKB1
8-Pin SOIC
Pin Description
Pin
Pin Name
Pin Type
n Description
Number
1
CLKIN
nput
Reference Frequency Clock Input. Weak pull-down (250kΩ).
2
3
4
5
8
CLK
CLK
GND
Output
Output
Power
Output
Outpt
Power
Input
Buffered Clock Outpt Weak pull-down (250kΩ).
BufferClock utput. Weak pull-down (250kΩ).
PowGroud.
CLKB1
CLKB2
VDD
Bufered Clock Output. Weak pull-down (250kΩ).
Buffered Clock Output. Weak pull-down (250kΩ).
2.5V to 3.3V Power Supply.
FBK
PLL Feedback Input. This pin must be connected to one of the clock outputs.
May 15, 2008
Page 2 of 15
SL23EP04
General Description
High and Low-Drive Product Options
The SL23EP04 is a low skew, low jitter Zero Delay Buffer
with very low operating current.
All SL23EP04 products are offered with the high drive
“-1H” and “-2H” as well as the standard drive “-1” and “-2”
options. These drive options enable the user to control
load levels, frequency range and EMI level. Refer to the
electrical tables for the details of the drive lels.
The product includes an on-chip high performance PLL
that locks into the input reference clock and produces
four (4) output clock drivers tracking the input reference
clock for systems requiring clock distribution.
Skew and Zero Delay
in addition to FBK pin used for internal PLL feedback,
there are two (2) banks with two (2) outputs in each bank,
bringing the number of total available output clocks to
four (4).
All outputs should drive the similar to achieve output-
to-output skew and input-to-output lay secifications as
given in the switching electricables. However, the delay
between input and outputs adjusted by changing
the load at FBK pin relative anks A and B clocks
since FBK pin is the eedack to the internal PLL.
Input and output Frequency Range
The input and output frequency is the same (1x) for
SL23EP04-1 and -1H versions. For SL23EP04-2 and -
2H versions, the output frequency is 1/2x, 1x or 2x of
the CLKIN as given in the “Available SL23EP04
Configurations” Table 1. But, the frequency range
depends on VDD, drive levels and CL (Load
Capacitance) as given in the electrical specifications
tables.
In addition, the input eference clock rise and fall ime
should be simthe output rise and fall time to obtain
the best skeults
PoweSupply Range (VDD)
Te SL23EP04 is designed to oper3.3V (3.63V-
maxto 2.5V (2.25V-min) VDD power supply ange. An
internal on-chip voltage regulator is sed to provide to
PLL constant power suppy of 1.8V internally. This leads
to a consistent and stable PLL electrical performance in
terms of skew, jittepower dissipation. The
When the input clock frequency is DC (from GND to
VDD), this input state is detected by an input level
detection circuitry and all four (4) clock outputs are orced
to Hi-Z. The PLL is shutdown to save power. In thi
shutdown state, the product draws less than 12 μA
(8 μA –typ) supply current.
SL23EP04 I/O is pered by using VDD.
ContacV power supply ZDB called
SL23EP
SpreadThru™ Feature
If a Spread Spectrum Clock (SSC) were to be used as
an input clock, the SL23EP04 is desgned tpass the
modulated Spread Spectrum (SSC) signal from
its reference CLKIN input to ouput clocks. The
same spread spectraracristics at the input are
passed through L and drivers without any
degradation in sprercent (%), spread profile and
modulation frequency
Device
Feedback From
Bank-A or Bank-B
Bank-A
Bank-A Frequency
Reference
Bank-B Frequency
Reference
SL23EP04-1 and 1
SL23EP04-2 and -2H
SL23EP04-2 and -2H
Reference
Reference / 2
Reference
Bank-B
2 x Reference
Table 1. Available SL23EP04 Configurations
May 15, 2008
Page 3 of 15
SL23EP04
Absolute Maximum Ratings (All Products)
Description
Supply voltage, VDD
Condition
Min
-0.5
-0.5
0
Max
Unit
V
V
All Inputs and Outputs
5
70
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
In operation, C-Grade
In operation, I-Grade
°C
°C
°C
°C
C
V
40
-
85
No power is applied
150
Junction Temperature
In operation, power is applied
125
Soldering Temperature
-
260
ESD Rating (Human Body Model)
ESD Rating (Change Device Model)
ESD Rating (Machine Model)
JEDECCC22-A114D
JEDECCC22-C101C
JEDECCC22-A115D
-4000
-1500
-200
400
1500
200
V
V
Operating Conditions (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Operating Voltage
Symbol
VDD
Condition
0%
in
Typ
3.3
-
Max
Unit
V
2.97
3.63
Operating Temperature
Input Capacitance
Output Impedance
Output Impedance
TA
Ambient Temperature
Pins 1 and 8
0
-
70
7
-
°C
pF
Ω
VIH
5
OUT1
ROUT-2
High Drive (-1H an-2H)
Standard Drive (-1 ad -2)
-
28
40
-
-
Ω
DC Electrical Chacteristics (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL5pF and Ambient Temperature range 0 to +70°C
Description
Input LOW ge
Symbol
VINL
Condition
Pins 1 and 8
Min
–
Typ
–
Max
0.8
Unit
V
Input HIGe
Input LOCurrent
VINH
IINL
Pins 1 and 8
2.0
–
–
VDD+0.3
50
V
0 < VIN < 0.8V, Pins 1 and 8
20
µA
2.4V < VIN < VDD
Pins 1 and 8
Inpt HIGH Current
Output LOW Voltage
IINH
VOL
–
20
50
µA
IOL = 8 mA ( -1, -2 drives)
–
–
–
–
0.4
0.4
V
V
IOL = 12 mA (-1H, -2H drives)
May 15, 2008
Page 4 of 15
SL23EP04
DC Electrical Characteristics (C-Grade and VDD=3.3V – Cont.)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Symbol
Condition
Min
2.4
Typ
–
Max
Unit
V
IOH = –8 mA (-1, -2 drives)
IOH = –12 mA (-1H, -2H drives)
–
Output HIGH Voltage
VOH
2.4
–
V
Power Down Supply
Current
Measured when CLKIN= GND to VDD
or floating
IDDPD
IDD1
IDD2
IDD3
–
–
–
–
12
14
1
20
µA
mA
mA
mA
All Outputs CL=0, 33.3 MHz CLKIN
All versions
Power Supply Current
Power Supply Current
Power Supply Current
10
12
14
All Outputs CL=0, 66.6 MHz CLKIN
All versions
All Outputs CL=0, 133.3 MHz CLK
All versions
All Outputs CL=0, 166.6 Mz CLKIN
All versions
Power Supply Current
Pull-down Resistors
IDD4
RPD
–
23
mA
Pin-1, 2, 3, 5, and 6
150
250
350
kΩ
Switching Electrical Characteristics (CGrade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature 0 to +70°C
Description
Symbol
FOUT1
FOUT2
FO
FOUT4
FOUT5
FOUT6
DC1
Condition
Min
10
10
10
10
10
10
30
Typ
Max
220
180
135
180
135
100
70
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
CL=15pf, -1H and -2H versio
CL=22pf, -1H and -2H versions
L=30pf, -1H and -2H vesions
CL=15pf, -1, and -2 versio
CL=22pf, -1 ad -2 verions
CL=30pf, -d -2 versions
Measureat VDD/2, all versions
-
-
-
Output Frequency Range
-
-
-
Input Duty Cycle
50
CL=30pF, Fout=66 MHz, all versions
Meaured at 1.4V
Output D
DC2
DC3
DC5
tr/f1
40
45
45
45
-
50
50
50
50
-
60
55
%
%
%
%
ns
ns
CL=15pF, Fout=66 MHz, all versions
Measured at VDD/2
Output Dy Cycle
Output Duty Cycle
Output Duty Cycle
Output Rise/Fall Time
Output Rise/Fall Time
CL=15pF, Fout=133 MHz, all versions
Measured at VDD/2
55
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
55
CL=30pF, -1 and -2 versions,
measured from 0.8V to 2.0V
2.2
1.5
CL=15pF, -1 and -2 versions,
measured from 0.8V to 2.0V
tr/f2
-
-
May 15, 2008
Page 5 of 15
SL23EP04
Switching Electrical Characteristics (C-Grade and VDD=3.3V – Cont.)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
CL=30pF -1H and -2H version,
Output Rise/Fall Time
Output Rise/Fall Time
tr/f3
tr/f4
-
-
-
-
-
1.5
ns
measured from 0.8V to 2.0V
CL=15pF -1H and -2H version,
measured from 0.8V to 2.0V
-
ns
ps
ps
Output-to-Output Skew
on Same Bank
-1 and -2 measured at VDD/2
and outputs are equally loaded
SKW1
SKW2
60
150
125
Output-to-Output Skew
on Same Bank
-1H and -2H measured at VDD/2
and outputs are equally loaded
Output-to-Output Skew
Between Bank A and B
-1 and -2 measured at VDD/2
and outputs are equally loaded
SKW3
SKW4
SKW5
-
-
-
110
90
25
200
400
ps
ps
ps
Output-to-Output Skew
Between Bank A and B
-1H and -2H measured at VDD/2
and outputs are equally loaded
All versions, measured at VDD/2 and
outputs are equally loadd
Device-to-Device Skew
Input-to-Output Delay
1
All versions, CLKN to FBK ising
edge, measured t VDD/2 and outputs
are equally loaded
Dt
-200
+/-70
200
ps
Fout=66MHz and CL=15pF
Fout=z and CL=15P
Fout=66.6MHz and CL=30pF
Fout=66.6 MHz and CL=15pF
out=166.6MHz and CL=15pF
Fout=66.6 MHz and CL=3F
-
-
-
-
-
-
-
-
-
-
-
-
100
100
100
400
400
400
ps
ps
ps
ps
ps
ps
Cycle-to-Cycle Jitter
CCJ1
(-1 and, -1H Versions)
Cycle-to-Cycle Jitter
(-2 and -2H Versions)
CC
From 0.95VDD and valclock
presented KIN
PLL Lock Time
tLOCK
-
-
1.0
ms
Operatonditions (I-Grade and VDD=3.3V)
Unlesothstated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
escription
Operating Voltage
Symbol
VDD
Condition
VDD+/-10%
Min
Typ
3.3
-
Max
Unit
V
2.97
3.63
Operating Temperatur
Input Capacitance
Output Impedance
Output Impedance
TA
Ambient Temperature
Pins 1 and 8
-40
85
8
-
°C
pF
Ω
VIH
-
-
-
5
ROUT-1
ROUT-2
High Drive (-1H and -2H)
Standard Drive (-1 and -2)
28
40
-
Ω
May 15, 2008
Page 6 of 15
SL23EP04
DC Electrical Characteristics (I-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Symbol
VINL
Condition
Min
–
Typ
–
Max
0.8
Unit
Pins 1 and 8
Pins 1 and 8
V
V
VINH
IINL
2.0
–
–
0.3
50
0 < VIN < 0.8V, Pins 1 and 8
µA
2.4V < VIN < VDD
Pins 1 and 8
Input HIGH Current
Output LOW Voltage
IINH
VOL
–
20
50
µA
IOL = 8 mA ( -1, -2 drives)
–
–
–
–
–
0.4
0.
–
V
V
V
V
IOL = 12 mA ( -1H, -2H drives)
IOH = –8 mA (-1, -2 drives)
IOH = –12 mA ( -1H, -2H drives)
–
2.4
2.4
Output HIGH Voltage
VOH
–
Power Down Supply
Current
Measured when CLKIN= GND to VDD
or floating
IDDPD
IDD1
IDD2
IDD3
–
–
–
–
12
14
16
18
17
20
22
µA
mA
mA
mA
All Outputs CL=033.MHCLKIN
All versions
Power Supply Current
Power Supply Current
Power Supply Current
All Outputs C=0, 66.6 MHz CLKIN
All ve
All OuL=0, 133.3 MH
All versions
All Outputs CL=0, 166.6 MHz CLK
All versions
Power Supply Current
Pull-down Resistors
ID
RPD
–
18
25
mA
Pin-1, 2, 3, 5 and 6
125
250
375
kΩ
Switching Electril Characteristics (I-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pnd Ambient Temperature range -40 to +85°C
Description
Symbol
FOUT
FOUT2
FOUT3
FOUT4
FOUT5
FOUT6
DC1
Condition
Min
10
10
10
10
10
10
30
Typ
Max
220
180
135
180
135
100
70
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
CL=15pf, -1H and -2H versions
CL=22pf, -1H and -2H versions
CL=30pf, -1H and -2H versions
CL=15pf, -1, and -2 versions
CL=22pf, -1 and -2 versions
CL=30pf, -1 and -2 versions
Measured at VDD/2
-
-
-
Output Frequency Range
-
-
-
Input Duty Cycle
50
CL=30pF, Fout=66 MHz, all
versions
Output Duty Cycle
DC2
40
50
60
%
Measured at 1.4V
May 15, 2008
Page 7 of 15
SL23EP04
Switching Electrical Characteristics (I-Grade and VDD=3.3V – Cont.)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
CL=15pF, Fout=66 MHz, all
versions
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
DC3
DC4
DC5
45
45
45
50
5
0
55
55
55
%
Measured at VDD/2
CL=15pF, Fout=133 MHz, all
versions
%
%
Measured at VDD/2
CL=15pF, Fout=166 MHz, all
versions
Measured at VDD/2
CL=30pF, -1 and -2 versions,
measured from 0.8V to 2.0V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
tr/f1
tr/f2
-
-
-
-
-
-
-
2.2
1.5
1.5
1.2
150
ns
ns
ns
ns
ps
CL=15pF, -1 and -2 versions
measured from 0.8V to 2.0V
CL=30pF -1H and -2H ersion,
measured from 0.8V to 2.0V
tr/f3
-
CL=15pF -1H an-2H version,
measured frm 0.8V to 2.0V
tr/f4
-
Output-to-Output Skew
on Same Bank
-1 and -2 measured at VDD/2
puts are equally lo
SKW1
70
-1d -2H measure
VDD/2
Output-to-Output Skew
on Same Bank
SKW2
SKW3
SKW4
-
-
-
60
110
90
125
250
200
ps
ps
ps
and outputs are equally load
Output-to-Output Skew
Between Bank A and B
-1 and -2 measured at VDD/2
and outputs arequly loaded
-1H and -2H measured at
VDD/
Output-to-Output Skew
Between Bank A and B
and oputs re equally loaded
All ersions, measured at
VDDand outputs are equally
loaded
Device-to-Dce Skew
Input-to-tput Delay
SKW5
Dt
-
150
400
200
ps
ps
All versions, CLKIN to FBK
rising edge, measured at
VDD/2 and outputs are equally
loaded
-200
+/-70
Fout=66.6 MHz and CL=15pF
Fout=133.3MHz and CL=15pF
Fout=66.6 MHz and CL=30pF
-
-
-
-
-
-
100
100
100
ps
ps
ps
Cycle-to-Cycle Jitter
(-1 and, -1H Versions)
CCJ1
May 15, 2008
Page 8 of 15
SL23EP04
Switching Electrical Characteristics (I-Grade and VDD=3.3V – Cont.)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Fout=66.6 MHz and CL=15pF
Fout=166.6MHz and CL=15pF
Fout=66.6 MHz and CL=30pF
-
-
-
-
-
-
400
400
ps
Cycle-to-Cycle Jitter
CCJ2
ps
ps
(-1H and -2H Versions)
From 0.95VDD and valid clock
presented at CLKIN
PLL Lock Time
tLOCK
-
1.0
ms
Operating Conditions (C-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 C
Description
Operating Voltage
Symbol
VDD
Condition
VDD+/-10%
Min
Typ
2.5
-
Max
Unit
V
.25
2.75
Operating Temperature
Input Capacitance
Output Impedance
Output Impedance
TA
Ambient Temperature
Pins 1 and 8
-40
85
8
-
°C
pF
Ω
VIH
-
-
-
5
ROUT-1
ROUT-2
High Drive (-1H and -2H)
Standard Drive (-1 and -2)
42
-
Ω
DC Electrical Characteristics (C-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=5pF and Ambient Temperature range 0 to +70°C
Description
Input LOW Voltage
Symbol
VINL
Condition
nd 8
Min
–
Typ
–
Max
Unit
V
0.7
Input HIGH Voltage
Input LOW Current
Input HIGH Current
VINH
INL
Pins 1 and 8
1.7
–
–
VDD+0.3
V
0 < VIN < 0.8V, pins 1 and 8
2.4V < VIN < VDD, ins 1 and 8
IOL = 6 mA, -1 and -
20
20
–
50
50
0.3
0.3
–
µA
µA
V
IINH
–
–
Output LOW Voltage
Output HIGH Vage
VOL
VOH
IOL = , -1H and -2H
IOH 6 mA-1 and -2
IOH = –8 mA, -1H and -2H
–
–
V
2.0
2.0
–
V
–
–
V
Measured when CLKIN= GND
to VDD
Power Doly Current
Power Spply Current
IDDPD
IDD1
–
–
10
8
18
11
µA
All Outputs CL=0, 33.3 MHz
CLKIN
mA
All Outputs CL=0, 66.6 MHz
CLKIN, all versions
Powr Supply Curren
Power Supply Current
IDD2
IDD3
–
–
10
12
14
17
mA
mA
All Outputs CL=0, 133.3 MHz
CLKIN, all versions
All Outputs CL=0, 166.6 MHz
CLKIN, all versions
Power Supply Current
Pull-down Resistors
IDD4
RPD
–
14
20
mA
Pin-1, 2, 3, 5 and 6
150
250
350
kΩ
May 15, 2008
Page 9 of 15
SL23EP04
Switching Electrical Characteristics (C-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Symbol
FOUT1
FOUT2
Condition
Min
10
Typ
Max
170
Unit
CL=15pf, -1H and -2H versions
CL=22pf, -1H and -2H versions
-
-
MHz
MHz
10
FOUT1
FOUT4
FOUT5
FOUT6
DC1
CL=30pf, -1H and -2H versions
CL=15pf, -1 and -2 versions
CL=22pf, -1 and -2 versions
CL=30pf, -1 and -2 versions
Measured at VDD/2, all versions
10
10
10
1
40
100
135
100
75
MHz
MHz
MHz
MHz
%
Output Frequency Range
-
-
Input Duty Cycle
50
60
CL=15pF, Fout=66 MHz, all versio
Measured at VDD/2
Output Duty Cycle
DC2
DC3
DC4
tr/f1
45
45
40
50
50
-
55
55
%
%
CL=15pF, Fout=133 MHz, al versons
Measured at VDD/2
Output Duty Cycle
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
Output Duty Cycle
60
%
CL=30pF, -1 nd -2 versions
Measured at 0.6 to 1.8V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
3.0
2.0
2.0
1.4
175
150
300
ns
ns
ns
ns
ps
ps
ps
CL=1nd -2 versions
Measure0.6 to 1.8V
tr/f2
-
-
CL=30F, -1H and -2H versions
Measured at 0.6 to 1.8V
tr/f3
-
-
CL=15pF, -1H and -H vesions
Measured at 0.6 to 1.8V
tr/f4
-
-
Output-to-Output Skew
on Same Bank
-1 and -2, mred at VDD/2
and outpute eqally loaded
SKW1
SKW2
SKW3
-
80
70
125
Output-to-Output Skew
on Same B
-1H and -2H, measured at VDD/2
and outputs are equally loaded
-
Output-toSkew
BetweeBank A and B
-1 and -2, measured at VDD/2
and outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-1H and -2H, measured at VDD/2
and outputs are equally loaded
4
SKW5
-
-
110
175
250
450
ps
ps
All versions, measured at VDD/2 and
outputs are equally loaded
Device-to-Device Skew
Input-to-Output Delay
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded
Dt
-250
+/-90
250
ps
Fout=66.6 MHz and CL=15pF
Fout=133.3 MHz and CL=15pF
-
-
-
-
150
150
ps
ps
Cycle-to-Cycle Jitter
(-1 and -1H Versions)
CCJ1
May 15, 2008
Page 10 of 15
SL23EP04
Switching Electrical Characteristics (C-Grade and VDD=2.5V-Cont.)
Unless otherwise stated VDD= 2.5+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Fout=66.6 MHz and CL=15pF
Fout=166.6 MHz and CL=15pF
-
-
-
-
400
400
ps
Cycle-to-Cycle Jitter
CCJ2
(-1H and -2H Versions)
ps
From 0.95VDD and valid clock
presented at CLKIN
PLL Lock Time
tLOCK
-
-
ms
Operating Conditions (I-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 +85°C
Description
Operating Voltage
Symbol
VDD
Condition
VDD+/-10%
Min
yp
2.5
-
Max
Unit
V
2.25
2.75
Operating Temperature
Input Capacitance
Output Impedance
Output Impedance
TA
Ambient Temperature
Pins 1 and 8
-40
85
8
-
C
pF
Ω
VIH
-
-
-
5
ROUT-1
ROUT-2
High Drive (-1H and -2H)
Standard Drive (-1 and -2)
36
-
Ω
DC Electrical Characteristics (I-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperatue range -40 to +85°
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Symbol
VINL
Condition
in
–
Typ
–
Max
Unit
V
Pins 1
Pins 1
0.7
VINH
IINL
1.7
–
–
VDD+0.3
V
0 < VI< 0.8V, pins 1 and 8
30
30
–
60
60
0.3
0.3
–
µA
µA
V
IIN
2.4V < VIN < VDD, pins 1 and 8
IOL = 6 mA, -1 and versons
IOL = 8 mA, -1H and -H versions
IOH = –6 1 and -2 versions
IOH = –8 mA, -1H and -2H versions
–
–
Output LOW Voltage
Output HIGH Voltage
VOL
VOH
–
–
V
2.0
2.0
–
V
–
–
V
Power Dopply
Curent
Measured when CLKIN= GND to VDD
or foating
IDDPD
IDD
IDD3
–
–
–
–
15
10
12
14
25
14
17
20
µA
mA
mA
mA
All Outputs CL=0, 33.3 MHz CLKIN
All versions
Power Spply Current
Power Supply Curren
Power Supply Current
All Outputs CL=0, 66.6 MHz CLKIN
All versions
All Outputs CL=0, 133.3 MHz CLKIN
All versions
All Outputs CL=0, 133.3 MHz CLKIN
All versions
Power Supply Current
Pull-down Resistors
IDD4
–
16
24
mA
RPUD
Pin-1, 2, 3, 5 and 6
125
250
375
kΩ
May 15, 2008
Page 11 of 15
SL23EP04
Switching Electrical Characteristics (I-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Description
Symbol
FOUT1
FOUT2
FOU3
Condition
Min
10
10
10
10
10
10
40
Typ
Max
170
100
135
100
75
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
CL=15pf, -1H and -2H versions
CL=22pf, -1H and -2H versions
CL=30pF, -1H and -2H versions
CL=15pf, -1 and -2 versions
CL=22pf, -1 and -2 versions
CL=30pf, -1 and -2 versions
Measured at VDD/2, all versions
-
-
Output Frequency Range
FOUT4
FOUT5
FOUT6
DC1
-
-
Input Duty Cycle
50
6
CL=30pF, Fout=66 MHz, all versio
Measured at VDD/2
Output Duty Cycle
DC2
DC3
DC4
DC5
tr/f1
40
45
45
0
-
50
50
50
-
60
55
%
%
CL=15pF, Fout=66 MHz, all versions
Measured at VDD/2
Output Duty Cycle
CL=15pF, Fout=133 MHzall versions
Measured at VDD/2
Output Duty Cycle
55
%
CL=15pF, Fout=16MHz, all versions
Measured at VDD/2
Output Duty Cycle
60
%
CL=3nd -2 versions
Measur0.6 to 1.8V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
3.2
2.0
2.0
1.5
220
220
220
ns
ns
ns
ns
ps
ps
ps
CL=15F, -1 and -2 versions
Measured at 0.6 to 1.8V
tr/f2
-
-
CL=30pF, -1H and -2H vesions
Measured at 0.6 to 1.8V
tr/f
-
-
CL=15pF, -1nd -2H version
Measured 6 to 1.8V
tr/f4
-
-
Output-to-OutpuSkew
on Same Bak
-1 and -2measured at VDD/2, and
utputs arequally loaded
SKW1
SKW2
W3
-
100
100
100
Output-toSkew
on Same Ba
-1H and -2H, measured at VDD/2 and
outputs are equally loaded
-
Output-toutput Skew
Beween Bank A and B
-1 and -2, measured at VDD/2, and
outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-1H and -2H, measured at VDD/2 and
outputs are equally loaded
SKW4
SKW5
-
-
180
225
375
550
ps
ps
All versions, measured at VDD/2 and
outputs are equally loaded
Device-to-Device Skew
Input-to-Output Delay
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded
Dt
-300
+/-125
300
ps
May 15, 2008
Page 12 of 15
SL23EP04
Switching Electrical Characteristics (I-Grade and VDD=2.5V – Cont.)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C
Fout=66.6 MHz and CL=15pF
Fout=133.3 MHz and CL=15pF
Fout=66.6 MHz and CL=15pF
Fout=166.6 MHz and CL=15pF
From 0.95VDD and valid CLKIN
-
-
-
-
-
-
-
-
150
150
400
1.0
ps
ps
ps
ps
ms
Cycle-to-Cycle Jitter
(-1 and -2 Versions)
CCJ1
Cycle-to-Cycle Jitter
CCJ2
(-1H and -2H Versions)
PLL Lock Time
tLOCK
External Components & Design Considerations
Typical Application Schematic
8
2
FBK
1
7
CLKIN
CLKA1
CL
CL
CLK2
3
VDD
0.1μF
SL23EP04
LKB1
CLKB2
5
6
CL
4
GND
Comments and Recommendations
Decoupling Cpacitor: A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the
capacitothe component side of thPCB as cse to the VDD pin as possible. The PCB trace to the VDD pin and
to the should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD
pi.
Serieermination Resistor: A series termination resistor is recommended if the distance between the output
clocks and the load is ovinch. The nominal impedance of the clock outputs is given in the Operating Condition
Tables. Place the eries ion resistors as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero
Delay” between the CLKIN and the outputs. The FBK pin is connected to PLL internally on-chip for feedback and
should be connected to one of to output clocks externally. For applications requiring zero input/output delay, the load
at the all output pins including the FBK pin must be the same. If any delay adjustment is required, the capacitance at
the FBK pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks
relative to CLKIN. For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
In addition, the rise and fall time of the reference clock at CLKIN pin should be similar to rise and fall times at the
CLKA and CLK B bank outputs.
May 15, 2008
Page 13 of 15
SL23EP04
Package Outline and Package Dimensions
8-Pin SOIC (150 Mil)
8
5
Dimensions re in inhes(milimeters).
Top line: (MINand Bottom line: (Max)
0.150(3.810)
0.157(3.987)
Pin-1 ID
0.230(5.842)
0.244(6.197)
1
4
0.189(4.800)
0.196(4.978)
0.0100(0.254
X 45°
0160(6)
0.0075(0.190)
0.0098(0.249)
0.0040(0.102)
Seating plane
0.050(1.270)
BSC
0.0160(0.406)
0.0350(0.889)
0°
.0040(0.02)
0..249)
.350
02(0.487
Thermharacteristics
Parameter
Symbol
Condition
Min
Typ
157
142
131
42
Max
Unit
°C/W
°C/W
°C/W
°C/W
θ JA
θ JA
θ JA
θ JC
Still air
-
-
-
-
-
-
-
-
Thermal Resistance
Junction to Ambient
1m/s air flow
3m/s air flow
Thermal Resistance
Junction to Case
Independent of air flow
May 15, 2008
Page 14 of 15
SL23EP04
Ordering Information [3]
Ordering Number
Marking
Shipping Package
Package
Temperature
SL23EP04SC-1
SL23EP04SC-1T
SL23EP04SI-1
SL23EP04SC-1
SL23EP04SC-1
SL23EP04SI-1
SL23EP04SI-1
SL23EP04SC-1H
SL23EP04SC-1H
SL23EP04SI-1H
SL23EP04SI-1H
SL23EP04SC-2
SL23EP04SC-2
SL23EP04SI-2
SL23EP04SI-2
SL23EP04SC-2H
SL23EP04SC-2H
SL23EP04SI-2H
SL23EP04SI-
Tube
Tape and Reel
Tube
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pC
8-pi
8-pn SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8pin SOC
-pin SOIC
8-n SOIC
to 70°C
70°C
-40 to 85°C
-40 to 85°C
0 to 70°C
SL23EP04SI-1T
SL23EP04SC-1H
SL23EP04SC-1HT
SL23EP04SI-1H
SL23EP04SI-1HT
SL23EP04SC-2
SL23EP04SC-2T
SL23EP04SI-2
Tape and Reel
Tube
Tape and Reel
Tube
0 to 70°C
-40 to 85°C
-40 to 85°C
0 o 70°C
Tape and Reel
Tube
Tape and Reel
Tue
0 to 70°C
-40 to 85°C
40 to 85°C
0 to 70°C
SL23EP04SI-2T
SL23EP04SC-2H
SL23EP04SC-2HT
SL23EP04SI-2H
SL23EP04SI-2HT
Tapand Reel
Tube
Tape and Reel
Tube
0 to 70°C
-40 to 85°C
-40 to 85°C
Tape and Reel
Notes:
1. The SL23EP04 products arS compliant.
May 15, 2008
Page 15 of 15
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
SW/HW
www.sis.coCBP
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Laboratories intnds to povide customers with the ltest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using
or intendino se the Scon Laboratories products. Chacterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and
"Typical" parmeters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to
make changes ithout further notice and limitatiouct inormation, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the
included informati. Silicon Laboratorieshall hity for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses
granted hereunder to design or fabricate ainteguits. The products are not designed or authorized to be used within any Life Support System without the specific written consent
of Silicon Laboratories. A "Life Support Syste" is any oduct or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Laboratories poducts are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in
weapons of mass destruction including (but not limted to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,
EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,
ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Laborato-
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