SL28SRC01BZI [SILICON]

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型号：	SL28SRC01BZI
厂家：	SILICON
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SL28SRC01

PCI Express Gen 2 & Gen 3 Clock Generator

Features

• SSON input for enabling spread spectrum clock

• Low power PCI Express Gen 2 & Gen 3clock generator

• One100-MHz differential SRC clocks

• Triangular Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• Low power push-pull output buffers (no 50ohm to

ground needed)

• Input frequency of 14.318MHz

• Industrial Temperature -40^oC to 85^oC

• 3.3V power supply

• Integrated 33ohm series termination resistors

• Low jitter (<50pS)

• 16-pin TSSOP package

Pin Configuration

Block Diagram

DOC#: SP-AP-0015 (Rev. 0.2)

400 West Cesar Chavez, Austin, TX 78701

Page 1 of 11

www.silabs.com

1+(512) 416-8500 1+(512) 416-9669

SL28SRC01

Pin Definitions

Pin No.

Name

Type

Description

XIN

14.318 MHz Crystal input.

VDD

VSS

PWR 3.3V power supply

GND Ground

VDD

VSS

PWR 3.3V power supply

GND Ground

SRC1

SRC1#

VSS

O, DIF 100 MHz Differential serial reference clocks.

GND Ground

VDD

VSS

PWR 3.3V power supply

GND Ground

VDD

SSON

PWR 3.3V power supply

3.3V LVTTL input for enabling spread spectrum clock

0 = Disable, 1 = Enable (-0.5% SS)

Extrenal 10K ohm pull-up or pull-down resistor required

VSS

GND Ground

14.318 MHz Crystal output.

XOUT

Table 1. Crystal Recommendations

Frequency

Drive

(max.)

Shunt Cap Motional

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

(Fund)

Cut

Loading Load Cap

(max.)

14.31818 MHz

Parallel 20 pF

0.1 mW

5 pF

0.016 pF

35 ppm

30 ppm

5 ppm

The SL28SRC01 requires a Parallel Resonance Crystal.

Substituting series resonance crystal causes the

SL28SRC01 to operate at the wrong frequency and violates

the ppm specification. For most applications there is a

300-ppm frequency shift between series and parallel crystals

due to incorrect loading.

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, use the total capac-

itance the crystal sees to calculate the appropriate capacitive

loading (CL).

Figure 1. Crystal Capacitive Clarification

Calculating Load Capacitors

Figure 1 shows a typical crystal configuration using the two

trim capacitors. It is important that the trim capacitors are in

series with the crystal. It is not true that load capacitors are in

parallel with the crystal and are approximately equal to the

load capacitance of the crystal.

In addition to the standard external trim capacitors, consider

the trace capacitance and pin capacitance to calculate the

crystal loading correctly. Again, the capacitance on each side

is in series with the crystal. The total capacitance on both side

is twice the specified crystal load capacitance (CL). Trim

DOC#: SP-AP-0015 (Rev. 0.2)

Page 2 of 11

SL28SRC01

capacitors are calculated to provide equal capacitive loading

on both sides.

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2 .

Load Capacitance (each side)

C lo ck C h ip

Ce = 2 * CL - (Cs + Ci)

C i2

C i1

Total Capacitance (as seen by the crystal)

P in

3 to 6 p

CLe

(

)

Ce2 + Cs2 + Ci2

Ce1 + Cs1 + Ci1

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

using standard value trim capacitors

X 2

X 1

C s2

C s1

T ra ce

2 .8 p F

X T A L

Ce..................................................... External trim capacitors

Cs..............................................Stray capacitance (terraced)

Ci ...........................................................Internal capacitance

(lead frame, bond wires, etc.)

C e 1

C e 2

T rim

3 3 p F

Figure 2. Crystal Loading Example

Absolute Maximum Conditions

Parameter

V_DD

Description

Core Supply Voltage

Input Voltage

Condition

Min.

–

Max.

4.6

Unit

V_IN

Relative to V_SS

Non-functional

Functional

–0.5

–65

4.6

V_DC

°C

T_S

Temperature, Storage

150

T_{A (commercial)}

Temperature, Operating

Ambient, Commercial

°C

T_{A (industrial)}

Temperature, Operating

Ambient, Industrial

Functional

-40

°C

T_J

Temperature, Junction

–

150

Ø_JC

Dissipation, Junction to Case JEDEC (JESD 51)

°C/

Ø_JA

Dissipation, Junction to Ambient JEDEC (JESD 51)

–

°C/

ESD_HBM

UL-94

ESD Protection (Human Body JEDEC (JESD 22 - A114)

Model)

2000

Flammability Rating

UL (Class)

V–0

DC Electrical Specifications

Parameter

VDD

Description

Condition

Min.

3.135

2.0

Max.

Unit

3.3V Operating Voltage

3.3V Input High Voltage

3.3V Input Low Voltage

Input High Leakage Current

3.3 ± 5%

3.465

V_IH

V_IL

I_IH

V_DD+ 0.3

V_SS– 0.3

–

0.8

Except internal pull-down resistors, 0 < V_IN

V_DD

A

I_IL

Input Low Leakage Current

3.3V Output High Voltage

3.3V Output Low Voltage

Except internal pull-up resistors, 0 < V_IN< V_DD

–5

2.4

–

A

V_OH

V_OL

I_OZ

I_OH= –1 mA

I_OL= 1 mA

0.4

High-impedance Output

Current

–10

A

DOC#: SP-AP-0015 (Rev. 0.2)

Page 3 of 11

SL28SRC01

DC Electrical Specifications

Parameter

C_IN

Description

Condition

Min.

Max.

Unit

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

1.5

C_OUT

L_IN

–

V_XIH

V_XIL

Xin High Voltage

0.7V_DD

V_DD

0.3V_DD

Xin Low Voltage

–

I_DD3.3V

Dynamic Supply Current

DOC#: SP-AP-0015 (Rev. 0.2)

Page 4 of 11

SL28SRC01

AC Electrical Specifications

Parameter

Crystal

T_DC

Description

Condition

Min.

Max.

Unit

XIN Duty Cycle

XIN Period

The device operates reliably with input

dutycyclesupto30/70buttheREFclock

duty cycle will not be within specification

47.5

52.5

T_PERIOD

When XIN is driven from an external

clock source

69.841

71.0

T_R/T_F

T_CCJ

XIN Rise and Fall Times

XIN Cycle to Cycle Jitter

Long-term Accuracy

Measured between 0.3V_DDand 0.7V_DD

As an average over 1-s duration

Measured at VDD/2 differential

–

10.0

500

250

L_ACC

ppm

Clock Input

T_DC

CLKIN Duty Cycle

Measured at VDD/2

0.5

–

4.0

V/ns

T_R/T_F

T_CCJ

CLKIN Rise and Fall Times

CLKIN Cycle to Cycle Jitter

CLKIN Long Term Jitter

Input Low Voltage

Measured between 0.2V_DDand 0.8V_DD

Measured at VDD/2

250

T_LTJ

Measured at VDD/2

–

350

V_IL

XIN / CLKIN pin

–

0.8

V_IH

Input High Voltage

XIN / CLKIN pin

VDD+0.3

I_IL

Input LowCurrent

XIN / CLKIN pin, 0 < VIN <0.8

XIN / CLKIN pin, VIN = VDD

–

I_IH

Input HighCurrent

–

SRC

T_DC

SRC Duty Cycle

Measured at 0V differential

9.99900

10.0010

T_PERIOD

T_PERIODSS

T_PERIODAbs

100 MHz SRC Period

Measured at 0V differential at 0.1s

Measured at 0V differential at 1 clock

Measured at 0V differential

10.02406 10.02607

100 MHz SRC Period, SSC

100 MHz SRC Absolute Period

9.87400

9.87406

–

10.1260

10.1762

T_PERIODSSAbs100 MHz SRC Absolute Period, SSC

T_CCJ

SRC Cycle to Cycle Jitter

RMS_GEN1

Output PCIe* Gen1 REFCLK phase

jitter

BER = 1E-12 (including PLL BW 8 - 16

MHz, ζ = 0.54, Td=10 ns,

108

3.0

Ftrk=1.5 MHz)

RMS_GEN2

RMS_GEN3

Output PCIe* Gen2 REFCLK phase

jitter

Includes PLL BW 8 - 16 MHz, Jitter

Peaking = 3dB, ζ = 0.54, Td=10 ns),

Low Band, F < 1.5MHz

Output PCIe* Gen2 REFCLK phase

jitter

Includes PLL BW 8 - 16 MHz, Jitter

Peaking = 3dB, ζ = 0.54, Td=10 ns),

Low Band, F < 1.5MHz

3.1

Output phase jitter impact – PCIe*

Gen3

Includes PLL BW 2 - 4 MHz,

CDR = 10MHz)

1.0

L_ACC

T_R/ T_F

T_RFM

V_HIGH

V_LOW

V_OX

SRC Long Term Accuracy

SRC Rising/Falling Slew Rate

Rise/Fall Matching

Measured at 0V differential

–

2.5

–

100

ppm

V/ns

Measured differentially from ±150 mV

Measured single-endedly from ±75 mV

Voltage High

1.15

–

Voltage Low

–0.3

300

Crossing Point Voltage at 0.7V Swing

550

DOC#: SP-AP-0015 (Rev. 0.2)

Page 5 of 11

SL28SRC01

AC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

Unit

T_jphasepll

Phase Jitter

(PLL BW 8-16MHz, 5-16MHz )

RMS value

3.1

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SSStopclock Set-up Time

–

1.8

–

10.0

Test and Measurement Set-up

For SRC Signals

This diagram shows the test load configuration for the differential SRC outputs

Figure 3. 0.7V Differential Load Configuration

Figure 4. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)

DOC#: SP-AP-0015 (Rev. 0.2)

Page 6 of 11

SL28SRC01

Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)

DOC#: SP-AP-0015 (Rev. 0.2)

Page 7 of 11

SL28SRC01

Ordering Information

Part Number

Lead-free

Package Type

Product Flow

SL28SRC01BZI

SL28SRC01BZIT

16-pin TSSOP

16-pin TSSOP–Tape and Reel

Industrial, -40 to 85C

SL 28 SRC01 B Z I T

Packaging Designator for Tape and Reel

Temperature Designator

Package Designator

Z : TSSOP

Revision Number

A = 1^stSilicon

Generic Part Number

Designated Family Number

Company Initials

This device is Pb free and RoHS compliant

DOC#: SP-AP-0015 (Rev. 0.2)

Page 8 of 11

SL28SRC01

Package Diagrams

16-pin TSSOP

DOC#: SP-AP-0015 (Rev. 0.2)

Page 9 of 11

SL28SRC01

Document History Page

Document Title: SL28SRC01 PCI Express Gen 2 & Gen 3 Clock Generator

Orig. of

REV. ECR# Issue Date Change

Description of Change

1.0

1.1

09/13/09

11/06/09

04/25/10

JMA

New datasheet

Updated Figure 4

1454

1. Updated pin 6 definition on page 2

2. Updated revision to be ISO compliant

3. Updated package information

4. Added commercial temperature grade

5. Added clock in features

DOC#: SP-AP-0015 (Rev. 0.2)

Page 10 of 11

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using

or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and

"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to

make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the

included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses

granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent

of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant

personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in

weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

Trademark Information

Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,

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names mentioned herein are trademarks of their respective holders.

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

USA

http://www.silabs.com

SL28SRC01BZI [SILICON]

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