SL28SRC02BZIT [SILICON]
PCI Express Gen 2 & Gen 3 Clock Generator;型号: | SL28SRC02BZIT |
厂家: | SILICON |
描述: | PCI Express Gen 2 & Gen 3 Clock Generator 时钟 PC 光电二极管 外围集成电路 晶体 |
文件: | 总14页 (文件大小:264K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SL28SRC02
PCI Express Gen 2 & Gen 3 Clock Generator
• SSON input for enabling spread spectrum clock
• I2C support with readback capabilities
Features
• Low power PCI Express Gen 2 & Gen 3 clock generator
• Two100-MHz differential SRC clocks
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Low power push-pull output buffers (no 50ohm to
ground needed)
• Input frequency of 14.318MHz
• Industrial Temperature -40oC to 85oC
• 3.3V power supply
• Integrated 33ohm series termination resistors
• Low jitter (<50pS)
• 20-pin TSSOP package
Block Diagram
Pin Configuration
VDD 1
SDATA 2
SCLK 3
VDD 4
20 XIN
19 XOUT
18 VSS
14.318MHz
crystal or clock
Crystal
Oscillator/
clock buffer
SRC1
17 SSON
16 VDD
15 VSS
PLL
SRC1#
VSS 5
SRC2
VDD 6
Control
logic
SRC2#
SSON
VSS 7
14 VDD
13 VDD
12 SRC2#
11 SRC2
SRC1 8
SRC1# 9
VSS 10
.................................................... Document #: Page 1 of 14
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669
www.silabs.com
SL28SRC02
Pin Definitions
Pin No.
Name
Type
Description
1
2
VDD
PWR 3.3V Power supply
SDATA
SCLK
VDD
I/O
I
SMBus compatible SDATA.
SMBus compatible SCLOCK.
3
4
PWR 3.3V power supply
GND Ground
5
VSS
6
VDD
PWR 3.3V power supply
GND Ground
7
VSS
8
SRC1
SRC1#
VSS
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
GND Ground
9
10
11
12
13
14
15
16
17
SRC2
SRC2#
VDD
O, DIF 100 MHz Differential serial reference clocks.
O, DIF 100 MHz Differential serial reference clocks.
PWR 3.3V power supply
VDD
PWR 3.3V power supply
VSS
GND Ground
VDD
PWR 3.3V power supply
SSON
I
3.3V LVTTL input for enabling spread spectrum clock
0 = Disable, 1 = Enable (-0.5% SS)
External 10K ohm pull-up or pull-down resistor required
18
19
20
VSS
XOUT
XIN
GND Ground
O, SE 14.318 MHz Crystal output.
I
14.318 MHz Crystal input.
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
.
Table 1. Command Code Definition
Bit
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
7
....................................................Document #: Page 2 of 14
SL28SRC02
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Data byte 1–8 bits
27:21
28
Slave address–7 bits
Read = 1
36:29
37
Acknowledge from slave
Data byte 2–8 bits
29
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
45:38
46
37:30
38
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
Acknowledge from slave
Stop
....
46:39
47
Data byte 1 from slave–8 bits
Acknowledge
....
....
55:48
56
Data byte 2 from slave–8 bits
Acknowledge
....
....
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
Stop
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Stop
27:21
28
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
....................................................Document #: Page 3 of 14
SL28SRC02
Control Registers
Byte 0: Control Register 0
Bit
7
@Pup
Name
Description
HW
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
5
1
4
0
3
0
2
0
1
0
0
1
Byte 1: Control Register 1
Bit
7
@Pup
Name
Description
1
0
RESERVED
PLL1_SS_DC
RESERVED
6
Select for down or center SS
0 = Down spread, 1 = Center spread
5
4
3
2
1
0
0
0
0
1
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Byte 2: Control Register 2
Bit
7
@Pup
Name
Description
1
1
1
1
1
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
5
4
3
2
1
0
Byte 3: Control Register 3
Bit
7
@Pup
Name
Description
1
1
1
1
1
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
5
4
3
2
1
0
....................................................Document #: Page 4 of 14
SL28SRC02
Byte 4: Control Register 4
Bit
7
@Pup
Name
Description
1
1
RESERVED
SRC1_OE
RESERVED
6
Output enable for SRC1
0 = Output Disabled, 1 = Output Enabled
5
1
SRC2_OE
Output enable for SRC2
0 = Output Disabled, 1 = Output Enabled
4
3
2
1
1
1
1
1
RESERVED
RESERVED
RESERVED
PLL1_SS_EN
RESERVED
RESERVED
RESERVED
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
0
1
RESERVED
RESERVED
Byte 5: Control Register 5
Bit
7
@Pup
Name
Description
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
RESERVED
0
RESERVED
Byte 6: Control Register 6
Bit
7
@Pup
Name
Description
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
RESERVED
0
RESERVED
Byte 7: Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
1
1
1
0
0
0
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
6
5
4
3
2
Vendor ID Bit 2
1
Vendor ID Bit 1
0
Vendor ID Bit 0
....................................................Document #: Page 5 of 14
SL28SRC02
Byte 8: Control Register 8
Bit
7
@Pup
Name
Description
1
0
0
0
0
0
1
1
Device_ID3
Device_ID2
Device_ID1
Device_ID0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
5
4
3
2
1
0
Byte 9: Control Register 9
Bit
7
@Pup
Name
RESERVED
Description
0
0
1
0
RESERVED
RESERVED
RESERVED
6
RESERVED
5
RESERVED
4
TEST _MODE_SEL
Test mode select either REF/N or tri-state
0 = All outputs tri-state, 1 = All output REF/N
3
0
TEST_MODE_ENTRY
Allows entry into test mode
0 = Normal Operation, 1 = Enter test mode(s)
2
1
0
1
0
1
12C_VOUT<2>
12C_VOUT<1>
12C_VOUT<0>
I2C_VOUT[2:0]
000 = 0.30V
001 = 0.40V
010 = 0.50V
011 = 060V
100 = 0.70V
101 = 0.80V (default)
110 = 0.90V
111 = 1.00V
Byte 10: Control Register 10
Bit
7
@Pup
Name
Description
RESERVED
0
0
0
0
0
0
1
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
RESERVED
0
RESERVED
Byte 11: Control Register 11
Bit
7
@Pup
Name
Description
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
6
5
4
3
....................................................Document #: Page 6 of 14
SL28SRC02
Byte 11: Control Register 11 (continued)
2
1
1
1
RESERVED
PCI-E_GEN2
RESERVED
PCI-E_Gen2 Compliant
0 = non Gen2, 1= Gen2 Compliant
0
1
RESERVED
RESERVED
Byte 12: Byte Count
Bit
7
@Pup
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Description
Byte count register for block read operation.
The default value for Byte count is 14. In order to read more than 14 bytes,
the system BIOS needs to change this register to the number of bytes to
be read.
0
0
0
0
1
1
1
1
6
5
4
3
2
1
0
....................................................Document #: Page 7 of 14
SL28SRC02
Table 4. Crystal Recommendations
Frequency
Drive
(max.)
Shunt Cap Motional
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
(Fund)
Cut
Loading Load Cap
(max.)
(max.)
14.31818 MHz
AT
Parallel 20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
The SL28SRC02 requires a Parallel Resonance Crystal.
Substituting series resonance crystal causes the
SL28SRC02 to operate at the wrong frequency and violates
the ppm specification. For most applications there is a
300-ppm frequency shift between series and parallel crystals
due to incorrect loading
a
C lo ck C h ip
C i2
C i1
P in
3 to 6 p
F
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, use the total capac-
itance the crystal sees to calculate the appropriate capacitive
loading (CL).
X 2
X 1
C s2
C s1
T ra ce
2 .8 p F
X T A L
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
C e 1
C e 2
T rim
3 3 p F
Figure 2. Crystal Loading Example
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL - (Cs + Ci)
Total Capacitance (as seen by the crystal)
1
CLe
=
1
1
(
)
+
Ce2 + Cs2 + Ci2
Ce1 + Cs1 + Ci1
Figure 1. Crystal Capacitive Clarification
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires, etc.)
....................................................Document #: Page 8 of 14
SL28SRC02
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Input Voltage
Condition
Min.
–
Max.
4.6
Unit
V
VIN
TS
TA
Relative to VSS
Non-functional
Functional
–0.5
–65
-40
4.6
VDC
°C
Temperature, Storage
150
85
Temperature, Operating
Ambient
°C
TJ
Temperature, Junction
Functional
–
–
150
20
°C
ØJC
Dissipation, Junction to Case Mil-STD-883E Method 1012.1
°C/
W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
60
–
°C/
W
ESDHBM
ESD Protection (Human Body MIL-STD-883, Method 3015
Model)
2000
V
UL-94
MSL
Flammability Rating
At 1/8 in.
V–0
1
Moisture Sensitivity Level
DC Electrical Specifications
Parameter
VDD
Description
Condition
Min.
Max.
Unit
3.3V Operating Voltage
3.3V Input High Voltage
3.3V Input Low Voltage
Input High Voltage
3.3 ± 5%
3.135
3.465
V
V
VIH
2.0
VDD + 0.3
VIL
VSS – 0.3
0.8
–
V
VIHI2C
VILI2C
IIH
SDATA, SCLK
SDATA, SCLK
2.2
–
V
Input Low Voltage
1.0
5
V
Input High Leakage Current
Input Low Leakage Current
3.3V Output High Voltage
3.3V Output Low Voltage
Except internal pull-down resistors, 0 < VIN < VDD
Except internal pull-up resistors, 0 < VIN < VDD
IOH = –1 mA
–
A
A
V
IIL
–5
2.4
–
–
VOH
VOL
IOZ
–
IOL = 1 mA
0.4
10
V
High-impedance Output
Current
–10
A
CIN
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
1.5
5
6
pF
pF
nH
V
COUT
LIN
–
7
VXIH
VXIL
IDD3.3V
Xin High Voltage
0.7VDD
VDD
0.3VDD
40
Xin Low Voltage
0
–
V
Dynamic Supply Current
mA
....................................................Document #: Page 9 of 14
SL28SRC02
AC Electrical Specifications
Parameter
Crystal
TDC
Description
Condition
Min.
Max.
Unit
XIN Duty Cycle
XIN Period
The device operates reliably with input
dutycyclesupto30/70buttheREFclock
duty cycle will not be within specification
47.5
52.5
%
TPERIOD
When XIN is driven from an external
clock source
69.841
71.0
ns
TR/TF
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Measured between 0.3VDD and 0.7VDD
–
–
10.0
500
ns
ps
TCCJ
As an average over 1-s duration
SRC
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
ns
ns
ns
ns
ps
ps
9.99900
10.0010
TPERIOD
TPERIODSS
TPERIODAbs
100 MHz SRC Period
Measured at 0V differential @ 0.1s
Measured at 0V differential @ 0.1s
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential
10.02406 10.02607
100 MHz SRC Period, SSC
100 MHz SRC Absolute Period
9.87400
9.87406
10.1260
10.1762
100
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
TSKEW
TCCJ
SRC1 to SRC2
SRC Cycle to Cycle Jitter
Measured at 0V differential
–
0
50
RMSGEN1
Output PCIe* Gen1 REFCLK phase
jitter
BER = 1E-12 (including PLL BW 8 - 16
MHz, ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz)
108
3.0
ps
ps
RMSGEN2
RMSGEN2
RMSGEN3
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
0
0
0
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
3.1
ps
Output phase jitter impact – PCIe*
Gen3
Includes PLL BW 2 - 4 MHz,
CDR = 10MHz)
1.0
ps
LACC
SRC Long Term Accuracy
SRC Rising/Falling Slew Rate
Rise/Fall Matching
Measured at 0V differential
–
2.5
–
100
8
ppm
V/ns
%
TR / TF
TRFM
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
20
VHIGH
VLOW
VOX
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
Crossing Point Voltage at 0.7V Swing
550
3.1
mV
pS
Tjphasepll
Phase Jitter
RMS value
(PLL BW 8-16MHz, 5-16MHz)
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up
TSS Stopclock Set-up Time
–
1.8
–
ms
ns
10.0
..................................................Document #: Page 10 of 14
SL28SRC02
Test and Measurement Set-up
For SRC Signals
This diagram shows the test load configuration for the differential SRC outputs
Figure 3. 0.7V Differential Load Configuration
Figure 4. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
.................................................. Document #: Page 11 of 14
SL28SRC02
VMAX = 1.15V
VMAX = 1.15V
CLK#
VcrossMAX = 550mV
VcrossMIN = 300mV
VcrossMAX = 550mV
VcrossMIN = 300mV
CLK
VMIN = 0.30V
VMIN = 0.30V
CLK#
Vcross delta = 140mV
Vcross delta = 140mV
CLK#
CLK#
Vcross median +75mV
Vcross median
Vcross median
Vcross median -75mV
CLK
CLK
Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
SL28SRC02BZI
SL28SRC02BZIT
20-pin TSSOP
20-pin TSSOP–Tape and Reel
Industrial, -40 to 85C
Industrial, -40 to 85C
SL 28 SRC02 B Z I T
Packaging Designator for Tape and Reel
Temperature Designator
Package Designator
Z : TSSOP
Revision Number
A = 1st Silicon
Generic Part Number
Designated Family Number
Company Initials
This device is Pb free and RoHS compliant
..................................................Document #: Page 12 of 14
SL28SRC02
Package Diagrams
20-pin TSSOP
..................................................Document #: Page 13 of 14
SL28SRC02
Document History Page
Document Title: SL28SRC02 PCI Express Gen 2 & Gen 3 Clock Generator
Orig. of
REV. Issue Date Change
Description of Change
1.0
1.1
10/28/09
11/06/09
JMA
JMA
New Datasheet
Updated Figure 4
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
..................................................Document #: Page 14 of 14
相关型号:
©2020 ICPDF网 联系我们和版权申明