SST25VF010-20-4C-QA [SILICON]
EEPROM, 1MX1, Serial, CMOS, WSON-8;
| 型号： | SST25VF010-20-4C-QA |
| 厂家： | 
SILICON |
| 描述： | EEPROM, 1MX1, Serial, CMOS, WSON-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 内存集成电路 |
| 文件： | 总24页 (文件大小：687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
SST25VF512 / 010 / 020 / 040512Kb / 1Mb / 2Mb / 4Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
FEATURES:
•
•
Single 2.7-3.6V Read and Write Operations
Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
20 MHz Max Clock Frequency
Superior Reliability
•
Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
– Chip Programming Time (typical):
SST25VF512: 2 seconds
•
•
SST25VF010: 3 seconds
SST25VF020: 5 seconds
SST25VF040: 9 seconds
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
End-of-Write Detection
– Software Status
•
•
•
Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
•
•
•
Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
Software Write Protection
– Write protection through Block-Protection bits in
status register
Packages Available
– 8-lead SOIC (4.9mm x 6mm)
(SST25VF512/010/020 only)
– 8-contact WSON
PRODUCT DESCRIPTION
SST’s serial flash family features a four-wire, SPI-com-
patible interface that allows for a low pin count package
occupying less board space and ultimately lowering total
system costs. SST25VFxxx SPI serial flash memories
are manufactured with SST’s proprietary, high perfor-
mance CMOS SuperFlash Technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST25VFxxx devices significantly
improve performance and reliability, while lowering power
consumption. The SST25VFxxx devices write (Program
or Erase) with a single 2.7-3.6V power supply. It uses
less energy during Erase and Program operations than
alternative flash memory technologies. The total energy
consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to
program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less
than alternative flash memory technologies.
The SST25VF512/010/020 devices are offered in an
8-lead SOIC package. All densities are offered in the
8-contact WSON package. See Figure 1 for the pin
assignments.
©2002 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71192-02-000 4/02
1
539
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Control Logic
Data Latches
Serial Interface
539 ILL B1.4
CE# SCK SI SO WP# HOLD#
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
2
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
PIN DESCRIPTION
1
2
3
4
8
7
6
5
CE#
SO
V
DD
1
2
3
4
8
7
6
5
CE#
SO
V
DD
HOLD#
SCK
SI
HOLD#
SCK
SI
Top View
Top View
WP#
WP#
V
V
SS
SS
539 08-soic ILL P01.4
539 08-wson ILL P01a.6
8-LEAD SOIC
(SST25VF512/010/020 only)
8-CONTACT WSON
FIGURE 1: PIN ASSIGNMENTS
TABLE 1: PIN DESCRIPTION
Symbol Pin Name Functions
To provide the timing of the serial interface.
SCK
Serial Clock
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
SI
Serial Data
Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data
Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE#
WP#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI Flash memory without resetting the device.
Power Supply To provide power supply (2.7-3.6V).
Ground
HOLD# Hold
VDD
VSS
T1.7 539
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
3
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
CE#
MODE 3
MODE 0
MODE 3
MODE 0
SCK
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
SI
DON'T CARE
HIGH-Z
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
SO
539 ILL F34.4
FIGURE 2: SPI PROTOCOL
PRODUCT IDENTIFICATION
DEVICE OPERATION
The SST25VFxxx is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
TABLE 2: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
00000H
BFH
SST25VF512
SST25VF010
SST25VF020
SST25VF040
00001H
00001H
00001H
00001H
48H
49H
43H
44H
The SST25VFxxx supports both Mode 0 (0,0) and Mode 3
(1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 2, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
T2.3 539
MEMORY ORGANIZATION
The SST25VFxxx SuperFlash memory array is organized
in 4 KByte sectors with 32 KByte overlay blocks.
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
4
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Hold Operation
HOLD# pin is used to pause a serial sequence underway
with the SPI Flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
17 for Hold timing.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
SCK
HOLD#
Active
Hold
Active
Hold
Active
539 ILL F44.0
FIGURE 3: HOLD CONDITION WAVEFORM
TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUS-
REGISTER (WRSR) INSTRUCTION
Write Protection
SST25VFxxx provides software Write protection. The Write
Protect pin (WP#) enables or disables the lock-down func-
tion of the status register. The Block-Protection bits (BP1,
BP0, and BPL) in the status register provide Write protec-
tion to the memory array and the status register. See Table
5 for Block-Protection description.
WP#
BPL
Execute WRSR Instruction
Not Allowed
L
L
1
0
X
Allowed
H
Allowed
T3.0 539
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
5
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Status Register
The software status register provides status on whether the
flash memory array is available for any Read or Write oper-
ation, whether the device is Write enabled, and the state of
the memory Write protection. During an internal Erase or
Program operation, the status register may be read only to
determine the completion of an operation in progress.
Table 4 describes the function of each bit in the software
status register.
TABLE 4: SOFTWARE STATUS REGISTER
Default at
Bit Name
Function
Power-up
Read/Write
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
1
WEL
1 = Device is memory Write enabled
0
R
0 = Device is not memory Write enabled
2
3
BP0
BP1
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Reserved for future use
1
1
0
0
R/W
R/W
N/A
R
4:5 RES
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
7
BPL
1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
0
R/W
T4.6 539
Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A “1” for the Busy bit indi-
cates the device is busy with an operation in progress. A “0”
indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the inter-
nal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to “1”, it indicates the device is Write enabled. If the
bit is set to “0” (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automati-
cally reset under the following conditions:
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming
reached its highest memory address
•
•
•
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
6
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Block Protection (BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP1, BP0) bits define the size of the
memory area, as defined in Table 5, to be software pro-
tected against any memory Write (Program or Erase)
operations. The Write-Status-Register (WRSR) instruction
is used to program the BP1 and BP0 bits as long as WP#
is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase
can only be executed if Block-Protection bits are both 0.
After power-up, BP1 and BP0 are set to 1.
WP# pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP1, and BP0 bits. When the
WP# pin is driven high (VIH), the BPL bit has no effect and
its value is “Don’t Care”. After power-up, the BPL bit is
reset to 0.
1
TABLE 5: SOFTWARE STATUS REGISTER BLOCK PROTECTION
Status
Register
Bit
Protected Memory Area
Protection Level
0
BP1 BP0
512 Kbit
1 Mbit
None
2 Mbit
4 Mbit
0
0
1
1
0
1
0
1
None
None
None
1 (1/4 Memory Array)
2 (1/2 Memory Array)
3 (Full Memory Array)
0C000H-0FFFFH 018000H-01FFFFH 030000H-03FFFFH 060000H-07FFFFH
08000H-0FFFFH 010000H-01FFFFH 020000H-03FFFFH 040000H-07FFFFH
00000H-0FFFFH 000000H-01FFFFH 000000H-03FFFFH 000000H-07FFFFH
T5.3 539
1. Default at power-up for BP1 and BP0 is ‘11’.
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit pro-
vides status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
7
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Instructions
Instructions are used to Read, Write (Erase and Program),
and configure the SST25VFxxx. The instruction bus cycles
are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
most significant bit. CE# must be driven low before a
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of a
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
1
TABLE 6: DEVICE OPERATION INSTRUCTIONS
Bus Cycle2
1
2
3
4
5
Cycle Type/Operation3,4
SIN
SOUT
SIN
SOUT
SIN
SOUT
SIN
SOUT SIN SOUT
Read
03H
20H
52H
60H
02H
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
Hi-Z
Hi-Z
Hi-Z
-
X
-
DOUT
Sector-Erase5,6
Block-Erase5,7
Chip-Erase6
Byte-Program6
Auto Address Increment (AAI) Program6,8 AFH
A7-A0
-
A7-A0
-
-
Hi-Z
-
-
-
-
-
-
-
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
Hi-Z DIN
Hi-Z DIN
Hi-Z
A7-A0
Hi-Z
Read-Status-Register (RDSR)
Enable-Write-Status-Register (EWSR)10
Write-Status-Register (WRSR)10
Write-Enable (WREN)
05H
50H
01H
06H
04H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
DOUT
-
Note9
-
-
Note9
-
-
Note9
-
Data
-
-
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-.
-
-
-
-
-
Write-Disable (WRDI)
-
-
-
-
Hi-Z ID Addr11 Hi-Z
X
DOUT
12
Read-ID
90H or Hi-Z
ABH
00H
Hi-Z
00H
T6.16 539
1. AMS = Most Significant Address
AMS = A15 for SST25VF512, A16 for SST25VF010, A17 for SST25VF020, A18 for SST25VF040
Address bits above the most significant bit of each density can be VIL or VIH
2. One bus cycle is eight clock periods.
3. Operation: SIN = Serial In, SOUT = Serial Out
4. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction
must be executed.
7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of
each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s and Device
ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 48H for SST25VF512, 49H for SST25VF010, 43H for SST25VF020, and 44H for SST25VF040
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
8
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Read
The Read instruction outputs the data starting from the
specified address location. The data output stream is con-
tinuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
4 Mbit density, once the data from address location
7FFFFH had been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A23-A0]. CE# must
remain active low for the duration of the Read cycle. See
Figure 4 for the Read sequence.
CE#
MODE 3
MODE 0
0
1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
70
47 48
55 56
63 64
SCK
03
ADD.
ADD.
ADD.
SI
N
OUT
N+1
N+2
N+3
N+4
D
OUT
HIGH IMPEDANCE
D
D
OUT
D
OUT
D
OUT
SO
MSB
539 ILL F10.9
FIGURE 4: READ SEQUENCE
Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a pro-
tected memory area will be ignored.
Program instruction is initiated by executing an 8-bit com-
mand, 02H, followed by address bits [A23-A0]. Following the
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait TBP for the completion of the internal
self-timed Byte-Program operation. See Figure 5 for the
Byte-Program sequence.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39
SCK
02
ADD.
ADD.
ADD.
D
IN
MSB LSB
SI
HIGH IMPEDANCE
SO
539 ILL F08.8
FIGURE 5: BYTE-PROGRAM SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
9
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Auto Address Increment (AAI) Program
The AAI program instruction allows multiple bytes of data to
be programmed without re-issuing the next sequential
address location. This feature decreases total program-
ming time when the entire memory array is to be pro-
grammed. An AAI program instruction pointing to a
protected memory area will be ignored. The selected
address range must be in the erased state (FFH) when ini-
tiating an AAI program instruction.
executed. The user must poll the BUSY bit in the software
status register or wait TBP for the completion of each inter-
nal self-timed Byte-Program cycle. Once the device com-
pletes programming byte, the next sequential address may
be program, enter the 8-bit command, AFH, followed by the
data to be programmed. When the last desired byte had
been programmed, execute the Write-Disable (WRDI)
instruction, 04H, to terminate AAI. See Figure 6 for AAI pro-
gramming sequence.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. The AAI program instruction
is initiated by executing an 8-bit command, AFH, followed
by address bits [A23-A0]. Following the addresses, the data
is input sequentially from MSB (bit 7) to LSB (bit 0). CE#
must be driven high before the AAI program instruction is
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-Enable-
Latch bit (WEL = 0).
T
T
BP
BP
CE#
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Data Byte 2
15 16
23 24
31 32 33 34 35 36 37 38 39
MODE 3
MODE 0
SCK
SI
A[23:16]
AF
A[15:8]
Data Byte 1
AF
A[7:0]
T
BP
CE#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Last Data Byte
0
1
2
3
4 5 6 7
SCK
SI
539 ILL F39.6
AF
04
Write Disable (WRDI)
Instruction to terminate
AAI Operation
FIGURE 6: AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
10
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
the any command sequence. The Sector-Erase instruction
is initiated by executing an 8-bit command, 20H, followed
by address bits [A23-A0]. Address bits [AMS-A12]
(AMS = Most Significant address) are used to determine the
sector address (SAX), remaining address bits can be VIL or
VIH. CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status
register or wait TSE for the completion of the internal self-
timed Sector-Erase cycle. See Figure 7 for the Sector-
Erase sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23 24
31
MODE 0
SCK
ADD.
20
ADD.
ADD.
SI
HIGH IMPEDANCE
SO
539 ILL F06.10
FIGURE 7: SECTOR-ERASE SEQUENCE
Block-Erase
The Block-Erase instruction clears all bits in the selected 32
KByte block to FFH. A Block-Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Block-Erase instruction is
initiated by executing an 8-bit command, 52H, followed by
address bits [A23-A0]. Address bits [AMS-A16] (AMS = Most
significant address) are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
TBE for the completion of the internal self-timed Block-
Erase cycle. See Figure 8 for the Block-Erase sequence.
CE#
0
1
2
3
4
5
6
7
8
15 16
23 24
31
MODE 3
MODE 0
SCK
ADD.
ADD.
52
ADD.
SI
HIGH IMPEDANCE
SO
539 ILL F28.9
FIGURE 8: BLOCK-ERASE SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
11
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
by executing an 8-bit command, 60H. CE# must be driven
high before the instruction is executed. The user may poll
the Busy bit in the software status register or wait TCE for
the completion of the internal self-timed Chip-Erase cycle.
See Figure 9 for the Chip-Erase sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
MODE 0
SCK
60
SI
HIGH IMPEDANCE
539 ILL F07.9
SO
FIGURE 9: CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows read-
ing of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-
Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 10 for the RDSR instruction sequence.
CE#
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK
SI
05
HIGH-IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
STATUS
REGISTER OUT
539 ILL F37.5
FIGURE 10: READ-STATUS-REGISTER (RDSR) SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
12
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE# must be driven high
before the WREN instruction is executed.
CE#
MODE 3
MODE 0
0
1
2
3
4 5 6 7
SCK
06
SI
HIGH IMPEDANCE
SO
539 ILL F35.3
FIGURE 11: WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. CE# must be driven high before
the WRDI instruction is executed.
CE#
MODE 3
MODE 0
0
1
2
3
4 5 6 7
SCK
04
SI
HIGH IMPEDANCE
SO
539 ILL F36.3
FIGURE 12: WRITE DISABLE (WRDI) SEQUENCE
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Enable-Write-
Status-Register instruction does not have any effect and
will be wasted, if it is not followed immediately by the Write-
Status-Register (WRSR) instruction. CE# must be driven
low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
13
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction
with the Enable-Write-Status-Register (EWSR) instruction
to write new values to the BP1, BP0, and BPL bits of the
status register. The Write-Status-Register instruction must
be executed immediately after the execution of the Enable-
Write-Status-Register instruction (very next instruction bus
cycle). This two-step instruction sequence of the EWSR
instruction followed by the WRSR instruction works like
SDP (software data protection) command structure which
prevents any accidental alteration of the status register val-
ues. The Write-Status-Register instruction will be ignored
when WP# is low and BPL bit is set to “1”. When the WP#
is low, the BPL bit can only be set from “0” to “1” to lock-
down the status register, but cannot be reset from “1” to “0”.
When WP# is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, and BP1 bits in the status reg-
ister can all be changed. As long as BPL bit is set to 0 or
WP# pin is driven high (VIH) prior to the low-to-high transi-
tion of the CE# pin at the end of the WRSR instruction, the
BP0, BP1, and BPL bit in the status register can all be
altered by the WRSR instruction. In this case, a single
WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0 and BP1 bit
at the same time. See Table 3 for a summary description of
WP# and BPL functions. CE# must be driven low before
the command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is
executed. See Figure 12 for EWSR and WRSR instruction
sequences.
CE#
MODE 3
MODE 0
0 1 2 3 4 5 6 7
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
STATUS
REGISTER IN
7
6
5
4
3
2
1
0
50
01
SI
MSB
HIGH IMPEDANCE
SO
539 ILL F38.6
FIGURE 13: ENABLE-WRITE-STATUS-REGISTER (EWSR) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Read-ID
The Read-ID instruction identifies the devices as
SST25VFxxx and manufacturer as SST. The device infor-
mation can be read from executing an 8-bit command, 90H
or ABH, followed by address bits [A23-A0]. Following the
Read-ID instruction, the manufacturer’s ID is located in
address 00000H and the device ID is located in address
00001H. Once the device is in Read-ID mode, the manu-
facturer’s and device ID output data toggles between
address 00000H and 00001H until terminated by a low to
high transition on CE#.
CE#
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39
46 47
54 55
62 63
SCK
1
ADD
90 or AB
00
00
SI
HIGH
IMPEDANCE
HIGH IMPEDANCE
SO
BF
Device ID
BF
Device ID
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
539 ILL F19.13
FIGURE 14: READ-ID SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
15
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE:
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 18 and 19
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
TABLE 7: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits
Symbol Parameter
Min
Max Units Test Conditions
IDDR
IDDW
ISB
Read Current
10
30
15
1
mA
mA
µA
µA
µA
V
CE#=0.1 VDD/0.9 VDD@20 MHz, SO=open
CE#=VDD
Program and Erase Current
Standby Current
CE#=VDD, VIN=VDD or VSS
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
ILO
1
VIL
0.8
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
0.7 VDD
VDD-0.2
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
V
T7.9 539
TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VOUT = 0V
Maximum
1
COUT
Output Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T8.0 539
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
16
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T9.1 539
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: AC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits
Symbol
FCLK
Parameter
Min
Max
Units
MHz
ns
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
Serial Clock Rise Time
Serial Clock Fall Time
CE# Active Setup Time
CE# Active Hold Time
CE# Not Active Setup Time
CE# Not Active Hold Time
CE# High Time
20
TSCKH
TSCKL
TSCKR
TSCKF
20
20
ns
5
5
ns
ns
1
TCES
15
10
ns
1
TCEH
ns
1
TCHS
10
ns
1
TCHH
10
ns
TCPH
TCHZ
TCLZ
TDS
100
ns
CE# High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
20
ns
0
5
ns
ns
TDH
THLS
THHS
THLH
THHH
THZ
Data In Hold Time
5
ns
HOLD# Low Setup Time
HOLD# High Setup Time
HOLD# Low Hold Time
HOLD# High Hold Time
HOLD# Low to High-Z Output
HOLD# High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
Sector-Erase
10
10
15
10
ns
ns
ns
ns
20
20
ns
TLZ
ns
TOH
TV
0
ns
20
25
ns
TSE
ms
ms
ms
µs
TBE
Block-Erase
25
TSCE
TBP
Chip-Erase
100
20
Byte-Program
T10.13 539
1. Relative to SCK.
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
17
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
T
T
CPH
CE#
T
CHH
T
CHS
CEH
T
SCKF
T
CES
SCK
T
SCKR
T
T
DS
DH
SI
LSB
MSB
HIGH-Z
HIGH-Z
SO
539 ILL F41.6
FIGURE 15: SERIAL INPUT TIMING DIAGRAM
CE#
T
SCKH
T
SCKL
SCK
T
OH
T
CHZ
T
CLZ
SO
SI
MSB
LSB
T
V
539 ILL F42.3
FIGURE 16: SERIAL OUTPUT TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
18
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
CE#
T
HHS
T
T
HLS
HHH
SCK
T
HLH
T
HZ
T
LZ
SO
SI
HOLD#
539 ILL F43.1
FIGURE 17: HOLD TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
19
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
V
IHT
V
OT
V
IT
INPUT
REFERENCE POINTS
OUTPUT
V
ILT
539 ILL F02.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 18: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
539 ILL F03.0
FIGURE 19: A TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
20
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST25VFxxx
-
XXX
-
XX
-
XX
Package Modifier
A = 8 leads or contacts
Package Type
S = SOIC
Q = WSON
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Operating Frequency
20 = 20 MHz
Device Density
512 = 512 Kbit
010 = 1 Mbit
020 = 2 Mbit
040 = 4 Mbit
Voltage
V = 2.7-3.6V
Valid combinations for SST25VF512
SST25VF512-20-4C-SA SST25VF512-20-4C-QA
Valid combinations for SST25VF010
SST25VF010-20-4C-SA
SST25VF010-20-4C-QA
Valid combinations for SST25VF020
SST25VF020-20-4C-SA
SST25VF020-20-4C-QA
Valid combinations for SST25VF040
SST25VF040-20-4C-QA
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
21
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
PACKAGING DIAGRAMS
Pin #1
Identifier
Side View
7˚
Top View
4 places
0.51
0.33
5.0
4.8
1.27 BSC
End View
45˚
7˚
4 places
4.00
3.80
0.25
0.10
6.20
5.80
1.75
1.35
0.25
0.19
0˚
8˚
1.27
0.40
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
08-soic-5x6-SA-7
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC)
SST PACKAGE CODE: SA
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
22
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Side View
Bottom View
Top View
0.25
0.19
Pin #1
Pin #1
Corner
1.27 BSC
4.00
5.00
BSC
0.076
3.40
0.48
0.35
0.05 Max
6.00
BSC
0.75
0.50
0.8
0.7
Cross Section
0.8
0.7
Note: 1. All linear dimensions are in millimeters (max/min).
8-wson-5x6-QA-5
8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON)
SST PACKAGE CODE: QA
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
23
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash
SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
Advance Information
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2002 Silicon Storage Technology, Inc.
S71192-02-000 4/02 539
24
相关型号：
SST25VF010-20-4C-SAE-DD029
1M X 1 SPI BUS SERIAL EEPROM, PDSO8, 4.90 X 6 MM, MS-012AA, SOIC-8
MICROCHIP
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