SST25VF010A-33-4C-SA [SILICON]
EEPROM, 1MX1, Serial, CMOS, PDSO8, 0.150 INCH, MS-012AA, SOIC-8;
| 型号： | SST25VF010A-33-4C-SA |
| 厂家： | 
SILICON |
| 描述： | EEPROM, 1MX1, Serial, CMOS, PDSO8, 0.150 INCH, MS-012AA, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总25页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 Mbit SPI Serial Flash
SST25VF010A
SST25VF010A1Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
FEATURES:
•
•
Single 2.7-3.6V Read and Write Operations
Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
33 MHz Max Clock Frequency
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption:
– Active Read Current: 7 mA (typical)
– Standby Current: 8 µA (typical)
Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
•
Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
•
•
End-of-Write Detection
– Software Status
Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
Software Write Protection
– Write protection through Block-Protection bits in
status register
Temperature Range
•
•
•
•
•
•
•
•
Fast Erase and Byte-Program:
– Chip-Erase Time: 70 ms (typical)
– Sector- or Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
– Extended: -20°C to +85°C
•
Packages Available
– 8-lead SOIC 150 mil body width
– 8-contact WSON (5mm x 6mm)
PRODUCT DESCRIPTION
SST’s serial flash family features a four-wire, SPI-compati-
ble interface that allows for a low pin-count package occu-
pying less board space and ultimately lowering total system
costs. SST25VF010A SPI serial flash memory is manufac-
tured with SST’s proprietary, high performance CMOS
SuperFlash Technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash memory technologies. The SST25VF010A
device operates with a single 2.7-3.6V power supply.
The SST25VF010A device is offered in both 8-lead SOIC
and 8-contact WSON packages. See Figure 1 for the pin
assignments.
The SST25VF010A device significantly improves perfor-
mance, while lowering power consumption. The total
energy consumed is a function of the applied voltage, cur-
©2004 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71265-00-000
1
6/04
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Control Logic
Data Latches
Serial Interface
1265 B1.0
CE# SCK SI SO WP# HOLD#
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
2
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
PIN DESCRIPTION
1
2
3
4
8
7
6
5
CE#
SO
V
DD
1
2
3
4
8
7
6
5
CE#
SO
V
DD
HOLD#
SCK
SI
HOLD#
SCK
SI
Top View
Top View
WP#
WP#
V
V
SS
SS
1265 08-soic P1.0
1265 08-wson P2.0
8-LEAD SOIC
8-CONTACT WSON
FIGURE 1: PIN ASSIGNMENTS
TABLE 1: PIN DESCRIPTION
Symbol Pin Name
Functions
To provide the timing of the serial interface.
SCK
Serial Clock
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
SI
Serial Data
Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data
Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE#
WP#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the device.
Power Supply To provide power supply (2.7-3.6V).
Ground
HOLD# Hold
VDD
VSS
T1.0 1265
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
3
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
PRODUCT IDENTIFICATION
DEVICE OPERATION
The SST25VF010A is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
TABLE 2: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
00000H
BFH
SST25VF010A
00001H
49H
The SST25VF010A supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 2, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
T2.0 1265
MEMORY ORGANIZATION
The SST25VF010A SuperFlash memory array is orga-
nized in 4 KByte sectors with 32 KByte overlay blocks.
CE#
MODE 3
MODE 3
MODE 0
MODE 0
SCK
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SI
DON'T CARE
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
1265 F02.0
FIGURE 2: SPI PROTOCOL
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
4
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Hold Operation
HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
18 for Hold timing.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
SCK
HOLD#
Active
Hold
Active
Hold
Active
1265 F03.0
FIGURE 3: HOLD CONDITION WAVEFORM
Write Protection
The SST25VF010A provides software Write protection.
The Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protection
bits (BP1, BP0, and BPL) in the status register provide
Write protection to the memory array and the status regis-
ter. See Table 5 for Block-Protection description.
TABLE 3: CONDITIONS TO EXECUTE WRITE-STATUS-
REGISTER (WRSR) INSTRUCTION
WP#
BPL
1
Execute WRSR Instruction
Not Allowed
L
L
0
Allowed
H
X
Allowed
T3.0 1265
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
5
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Status Register
The software status register provides status on whether the
flash memory array is available for any Read or Write oper-
ation, whether the device is Write enabled, and the state of
the memory Write protection. During an internal Erase or
Program operation, the status register may be read only to
determine the completion of an operation in progress.
Table 4 describes the function of each bit in the software
status register.
TABLE 4: SOFTWARE STATUS REGISTER
Default at
Bit
Name Function
Power-up
Read/Write
0
BUSY 1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
1
WEL
1 = Device is memory Write enabled
0
R
0 = Device is not memory Write enabled
2
3
BP0
BP1
RES
AAI
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Reserved for future use
1
1
0
0
R/W
R/W
N/A
R
4:5
6
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
7
BPL
1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
0
R/W
T4.0 1265
Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A “1” for the Busy bit indi-
cates the device is busy with an operation in progress. A “0”
indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the inter-
nal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to “1”, it indicates the device is Write enabled. If the
bit is set to “0” (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automati-
cally reset under the following conditions:
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming
reached its highest memory address
•
•
•
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
6
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Block Protection (BP1, BP0)
TABLE 5: SOFTWARE STATUS REGISTER
1
BLOCK PROTECTION
The Block-Protection (BP1, BP0) bits define the size of the
memory area, as defined in Table 5, to be software pro-
tected against any memory Write (Program or Erase)
operations. The Write-Status-Register (WRSR) instruction
is used to program the BP1 and BP0 bits as long as WP#
is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase
can only be executed if Block-Protection bits are both 0.
After power-up, BP1 and BP0 are set to 1.
Status
Register Bit
BP1 BP0
Protected
Memory Area
Protection Level
0
0
0
1
1
0
1
0
1
None
1 (1/4 Memory Array)
2 (1/2 Memory Array)
3 (Full Memory Array)
018000H-01FFFFH
010000H-01FFFFH
000000H-01FFFFH
Block Protection Lock-Down (BPL)
T5.0 1265
1. Default at power-up for BP1 and BP0 is ‘11’.
WP# pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP1, and BP0 bits. When the
WP# pin is driven high (VIH), the BPL bit has no effect and
its value is “Don’t Care”. After power-up, the BPL bit is
reset to 0.
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit pro-
vides status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
7
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Instructions
Instructions are used to Read, Write (Erase and Program),
and configure the SST25VF010A. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
most significant bit. CE# must be driven low before an
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of an
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
1
TABLE 6: DEVICE OPERATION INSTRUCTIONS
Bus Cycle2
1
2
3
4
5
6
Cycle Type/Operation3,4
SIN
03H
0BH
20H
SOUT
SIN
SOUT
SIN
SOUT
SIN
SOUT SIN SOUT SIN SOUT
Read (20 MHz)
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
A7-A0
A7-A0
A7-A0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
X
-
DOUT
High-Speed-Read (33 MHz)
Sector-Erase5,6
Block-Erase5,7
X
-
X
DOUT
Hi-Z
A23-A16 Hi-Z A15-A8 Hi-Z
52H or Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
D8H
-
-
Chip-Erase6
60H or Hi-Z
C7H
-
-
-
-
-
-
-
-
Byte-Program6
02H
AFH
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
A7-A0
Hi-Z DIN
Hi-Z DIN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Auto Address Increment
(AAI) Program6,8
Hi-Z
Hi-Z
Hi-Z
Hi-Z
A23-A16 Hi-Z A15-A8 Hi-Z
Read-Status-Register
(RDSR)
05H
X
-
DOUT
-
-
-
-
Note9
-
-
Note9
-
-
-
Note9
Note9
Enable-Write-Status-Register 50H
(EWSR)10
-
-
-
-
-
-
Write-Status-Register
(WRSR)10
01H
Data
Hi-Z
-.
Write-Enable (WREN)
Write-Disable (WRDI)
Read-ID
06H
04H
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
90H or Hi-Z
ABH
00H
Hi-Z
00H
Hi-Z ID Addr11 Hi-Z
X
DOUT
DOUT
T6.0 1265
1. AMS = Most Significant Address
AMS = A16 for SST25VF010A
Address bits above the most significant bit of each density can be VIL or VIH
2. One bus cycle is eight clock periods.
3. Operation: SIN = Serial In, SOUT = Serial Out
4. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN)
instruction must be executed.
7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in con-
junction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction
to make both instructions effective.
11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s and
Device ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 49H for SST25VF010A
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
8
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Read (20 MHz)
The Read instruction outputs the data starting from the
specified address location. The data output stream is con-
tinuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
4 Mbit density, once the data from address location
7FFFFH had been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A23-A0]. CE# must
remain active low for the duration of the Read cycle. See
Figure 4 for the Read sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
39
40
47 48
55 56
63 64
70
24
32
MODE 0
SCK
03
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
SI
MSB
N
OUT
N+1
N+2
N+3
N+4
D
OUT
D
D
D
D
OUT
OUT
OUT
SO
MSB
1265 F04.0
FIGURE 4: READ SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
9
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
High-Speed-Read (33 MHz)
The High-Speed-Read instruction supporting up to 33 MHz
is initiated by executing an 8-bit command, 0BH, followed
by address bits [A23-A0] and a dummy byte. CE# must
remain active low for the duration of the High-Speed-Read
cycle. See Figure 5 for the High-Speed-Read sequence.
to high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
4 Mbit density, once the data from address location
07FFFFH has been read, the next output will be from
address location 000000H.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from
the specified address location. The data output stream is
continuous through all addresses until terminated by a low
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
80
71 72
SCK
0B
ADD.
ADD.
ADD.
X
SI
MSB
MSB
N
OUT
N+1
N+2
N+3
D
OUT
N+4
HIGH IMPEDANCE
D
D
D
D
SO
OUT
OUT
OUT
MSB
1265 F05.0
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V or V
)
IH
IL
FIGURE 5: HIGH-SPEED-READ SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
10
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a pro-
tected memory area will be ignored.
Program instruction is initiated by executing an 8-bit com-
mand, 02H, followed by address bits [A23-A0]. Following the
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait TBP for the completion of the internal
self-timed Byte-Program operation. See Figure 6 for the
Byte-Program sequence.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
39
24
32
MODE 0
SCK
02
ADD.
MSB
ADD.
ADD.
D
IN
MSB LSB
SI
MSB
HIGH IMPEDANCE
SO
1265 F06.0
FIGURE 6: BYTE-PROGRAM SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
11
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Auto Address Increment (AAI) Program
The AAI program instruction allows multiple bytes of data to
be programmed without re-issuing the next sequential
address location. This feature decreases total program-
ming time when the entire memory array is to be pro-
grammed. An AAI program instruction pointing to a
protected memory area will be ignored. The selected
address range must be in the erased state (FFH) when ini-
tiating an AAI program instruction.
status register or wait TBP for the completion of each inter-
nal self-timed Byte-Program cycle. Once the device com-
pletes programming byte, the next sequential address may
be program, enter the 8-bit command, AFH, followed by the
data to be programmed. When the last desired byte had
been programmed, execute the Write-Disable (WRDI)
instruction, 04H, to terminate AAI. After execution of the
WRDI command, the user must poll the Status register to
ensure the device completes programming. See Figure 7
for AAI programming sequence.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. The AAI program instruction
is initiated by executing an 8-bit command, AFH, followed
by address bits [A23-A0]. Following the addresses, the data
is input sequentially from MSB (bit 7) to LSB (bit 0). CE#
must be driven high before the AAI program instruction is
executed. The user must poll the BUSY bit in the software
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-Enable-
Latch bit (WEL = 0).
T
T
BP
BP
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16 23 24 31 32 33 34 35 36 37 38 39
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0 1
MODE 0
SCK
SI
A[23:16] A[15:8]
A[7:0]
Data Byte 1
AF
AF
Data Byte 2
T
BP
CE#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
SI
AF
Last Data Byte
04
05
Write Disable (WRDI)
Instruction to terminate
AAI Operation
Read Status Register (RDSR)
Instruction to verify end of
AAI Operation
D
OUT
SO
1265 F07.0
FIGURE 7: AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
12
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
the any command sequence. The Sector-Erase instruction
is initiated by executing an 8-bit command, 20H, followed
by address bits [A23-A0]. Address bits [AMS-A12]
(AMS = Most Significant address) are used to determine the
sector address (SAX), remaining address bits can be VIL or
VIH. CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status
register or wait TSE for the completion of the internal self-
timed Sector-Erase cycle. See Figure 8 for the Sector-
Erase sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
24
MODE 0
SCK
20
ADD.
MSB
ADD.
ADD.
SI
MSB
HIGH IMPEDANCE
SO
1265 F08.0
FIGURE 8: SECTOR-ERASE SEQUENCE
Block-Erase
The Block-Erase instruction clears all bits in the selected 32
KByte block to FFH. A Block-Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Block-Erase instruction is
initiated by executing an 8-bit command, 52H or D8H, fol-
lowed by address bits [A23-A0]. Address bits [AMS-A15]
(AMS = Most significant address) are used to determine
block address (BAX), remaining address bits can be VIL or
VIH. CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status
register or wait TBE for the completion of the internal self-
timed Block-Erase cycle. See Figure 9 for the Block-Erase
sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
24
MODE 0
SCK
52 or D8
ADD.
MSB
ADD.
ADD.
SI
MSB
HIGH IMPEDANCE
SO
1265 F09.0
FIGURE 9: BLOCK-ERASE SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
13
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
by executing an 8-bit command, 60H or C7H. CE# must be
driven high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait TCE
for the completion of the internal self-timed Chip-Erase
cycle. See Figure 10 for the Chip-Erase sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
MODE 0
SCK
60 or C7
SI
MSB
HIGH IMPEDANCE
SO
1265 F10.0
FIGURE 10: CHIP-ERASE SEQUENCE
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows read-
ing of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-
Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 11 for the RDSR instruction sequence.
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
SI
05
HIGH IMPEDANCE
MSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
Status
1265 F11.0
Register Out
FIGURE 11: READ-STATUS-REGISTER (RDSR) SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
14
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE# must be driven high
before the WREN instruction is executed.
CE#
MODE 3
0
1
2
3
4
5
6
7
MODE 0
SCK
06
SI
MSB
HIGH IMPEDANCE
SO
1265 F12.0
FIGURE 12: WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. CE# must be driven high before
the WRDI instruction is executed.
CE#
MODE 3
0
1
2
3
4
5
6
7
MODE 0
SCK
04
SI
MSB
HIGH IMPEDANCE
SO
1265 F13.0
FIGURE 13: WRITE DISABLE (WRDI) SEQUENCE
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Enable-Write-
Status-Register instruction does not have any effect and
will be wasted, if it is not followed immediately by the Write-
Status-Register (WRSR) instruction. CE# must be driven
low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
15
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Write-Status-Register (WRSR)
When WP# is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, and BP1 bits in the status reg-
ister can all be changed. As long as BPL bit is set to 0 or
WP# pin is driven high (VIH) prior to the low-to-high transi-
tion of the CE# pin at the end of the WRSR instruction, the
BP0, BP1, and BPL bit in the status register can all be
altered by the WRSR instruction. In this case, a single
WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0 and BP1 bit
at the same time. See Table 3 for a summary description of
WP# and BPL functions. CE# must be driven low before
the command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is
executed. See Figure 14 for EWSR and WRSR instruction
sequences.
The Write-Status-Register instruction works in conjunction
with the Enable-Write-Status-Register (EWSR) instruction
to write new values to the BP1, BP0, and BPL bits of the
status register. The Write-Status-Register instruction must
be executed immediately after the execution of the Enable-
Write-Status-Register instruction (very next instruction bus
cycle). This two-step instruction sequence of the EWSR
instruction followed by the WRSR instruction works like
SDP (software data protection) command structure which
prevents any accidental alteration of the status register val-
ues. The Write-Status-Register instruction will be ignored
when WP# is low and BPL bit is set to “1”. When the WP#
is low, the BPL bit can only be set from “0” to “1” to lock-
down the status register, but cannot be reset from “1” to “0”.
CE#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
MODE 3
MODE 0
MODE 3
MODE 0
SCK
STATUS
REGISTER IN
50
01
7 6 5 4 3 2 1 0
MSB
SI
MSB
MSB
HIGH IMPEDANCE
SO
1265 F14.0
FIGURE 14: ENABLE-WRITE-STATUS-REGISTER (EWSR) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
16
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
Read-ID
The Read-ID instruction identifies the device as
SST25VF010A and manufacturer as SST. The device
information can be read from executing an 8-bit command,
90H or ABH, followed by address bits [A23-A0]. Following
the Read-ID instruction, the manufacturer’s ID is located in
address 00000H and the device ID is located in address
00001H. Once the device is in Read-ID mode, the manu-
facturer’s and device ID output data toggles between
address 00000H and 00001H until terminated by a low to
high transition on CE#.
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23
31
39
40
47 48
55 56
63
24
32
SCK
90 or AB
00
00
ADD1
MSB
SI
MSB
HIGH
IMPEDANCE
HIGH IMPEDANCE
Device ID
Device ID
BF
BF
SO
MSB
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
1265 F15.0
FIGURE 15: READ-ID SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
17
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 20 and 21
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
Extended
2.7-3.6V
2.7-3.6V
2.7-3.6V
-40°C to +85°C
-20°C to +85°C
TABLE 7: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits
Symbol Parameter
Min
Max Units Test Conditions
IDDR
IDDW
ISB
Read Current
10
30
15
1
mA
mA
µA
µA
µA
V
CE#=0.1 VDD/0.9 VDD@20 MHz, SO=open
CE#=VDD
Program and Erase Current
Standby Current
CE#=VDD, VIN=VDD or VSS
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
ILO
1
VIL
0.8
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
0.7 VDD
VDD-0.2
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
V
T7.0 1265
TABLE 8: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
1
TPU-READ
VDD Min to Read Operation
VDD Min to Write Operation
10
10
µs
µs
1
TPU-WRITE
T8.0 1265
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
18
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
TABLE 9: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
12 pF
1
COUT
Output Pin Capacitance
Input Capacitance
VOUT = 0V
VIN = 0V
1
CIN
6 pF
T9.0 1265
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T10.0 1265
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: AC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits
20 MHz
33 MHz
Symbol
FCLK
Parameter
Min
Max
Min
Max
Units
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
CE# Active Setup Time
CE# Active Hold Time
CE# Not Active Setup Time
CE# Not Active Hold Time
CE# High Time
20
33
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
TSCKH
TSCKL
20
20
13
13
1
TCES
20
12
1
TCEH
20
12
1
TCHS
10
10
1
TCHH
10
10
TCPH
TCHZ
TCLZ
TDS
100
100
CE# High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
20
14
0
5
0
3
TDH
THLS
THHS
THLH
THHH
THZ
Data In Hold Time
5
3
HOLD# Low Setup Time
HOLD# High Setup Time
HOLD# Low Hold Time
HOLD# High Hold Time
HOLD# Low to High-Z Output
HOLD# High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
Sector-Erase
10
10
15
10
10
10
10
10
20
20
14
14
TLZ
TOH
TV
0
0
20
25
12
25
TSE
TBE
Block-Erase
25
25
TSCE
TBP
Chip-Erase
100
20
100
20
Byte-Program
µs
T11.0 1265
1. Relative to SCK.
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
19
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
T
CPH
CE#
SCK
T
CHH
T
T
CHS
CEH
T
SCKF
T
CES
T
T
DH
DS
T
SCKR
LSB
MSB
SI
SO
HIGH-Z
HIGH-Z
1265 F16.0
FIGURE 16: SERIAL INPUT TIMING DIAGRAM
CE#
T
SCKH
T
SCKL
SCK
T
OH
T
CHZ
T
CLZ
SO
SI
MSB
LSB
T
V
1265 F17.0
FIGURE 17: SERIAL OUTPUT TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
20
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
CE#
SCK
T
HHS
T
T
HLS
HHH
T
HLH
T
HZ
T
LZ
SO
SI
HOLD#
1265 F18.0
FIGURE 18: HOLD TIMING DIAGRAM
VDD
V
DD Max
Chip selection is not allowed.
All commands are rejected by the device.
VDD Min
TPU-READ
TPU-WRITE
Device fully accessible
Time
1265 F19.0
FIGURE 19: POWER-UP TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
21
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
V
IHT
V
V
HT
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
V
ILT
1265 F20.0
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VHT (0.7VDD) and VLT (0.3VDD). Input rise and fall times (10% ↔90%) are <5 ns.
Note: VHT - VHIGH Test
V
V
V
LT - VLOW Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 20: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1265 F21.0
FIGURE 21: A TEST LOAD EXAMPLE
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
22
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST25VF010A - XXX
-
XX
-
XXX
Environmental Attribute
E = non-Pb
Package Modifier
A = 8 leads or contacts
Package Type
S = SOIC
Q = WSON
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Operating Frequency
33 = 33 MHz
Device Density
010 = 1 Mbit
Voltage
V = 2.7-3.6V
Product Series
25 = Serial Peripheral Interface flash memory
Valid combinations for SST25VF010A
SST25VF010A-33-4C-SA
SST25VF010A-33-4C-SAE
SST25VF010A-33-4C-QA
SST25VF010A-33-4C-QAE
SST25VF010A-33-4I-SA
SST25VF010A-33-4I-SAE
SST25VF010A-33-4I-QA
SST25VF010A-33-4I-QAE
SST25VF010A-33-4E-SA
SST25VF010A-33-4E-SAE
SST25VF010A-33-4E-QA
SST25VF010A-33-4E-QAE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
23
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
PACKAGING DIAGRAMS
Pin #1
Identifier
SIDE VIEW
TOP VIEW
7˚
4 places
0.51
0.33
5.0
4.8
1.27 BSC
END VIEW
45˚
7˚
0.25
0.10
4 places
4.00
3.80
1.75
1.35
0.25
0.19
0˚
8˚
6.20
5.80
1.27
0.40
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
08-soic-5x6-SA-8
1mm
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 150 MIL BODY WIDTH (4.9MM X 6MM)
SST PACKAGE CODE: SA
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
24
1 Mbit SPI Serial Flash
SST25VF010A
Advance Information
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Pin #1
0.25
0.19
Pin #1
Corner
1.27 BSC
5.00 0.10
4.00 0.10
3.40 0.10
0.076
0.48
0.35
0.70
0.50
0.05 Max
6.00 0.10
0.80
0.70
CROSS SECTION
0.80
0.70
Note: 1. All linear dimensions are in millimeters (max/min).
8-wson-6x5-QA-8
1mm
8-CONTACT VERY-VERY-THIN SMALL OUTLINE NO-LEAD (WSON)
SST PACKAGE CODE: QA
TABLE 12: REVISION HISTORY
Number
Description
Date
00
Jun 2004
•
Initial release
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2004 Silicon Storage Technology, Inc.
S71265-00-000
6/04
25
相关型号：
SST25VF010A-33-4I-QAE
1M X 1 SPI BUS SERIAL EEPROM, DSO8, 5 X 6 MM, ROHS COMPLIANT, WSON-8
MICROCHIP
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