SST29EE512-70-4C-NHE [SILICON]
Flash, 64KX8, 70ns, PQCC32, PLASTIC, MS-016AE, LCC-32;
| 型号： | SST29EE512-70-4C-NHE |
| 厂家： | 
SILICON |
| 描述： | Flash, 64KX8, 70ns, PQCC32, PLASTIC, MS-016AE, LCC-32 |
| 文件： | 总26页 (文件大小：771K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512 Kbit (64K x8) Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
SST29EE / LE / VE512512Kb Page-Write flash memories
Data Sheet
FEATURES:
•
Single Voltage Read and Write Operations
•
•
Latched Address and Data
– 4.5-5.5V for SST29EE512
– 3.0-3.6V for SST29LE512
– 2.7-3.6V for SST29VE512
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption
– Active Current: 20 mA (typical) for 5V and 10 mA
(typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
Fast Page-Write Operation
Automatic Write Timing
– Internal VPP Generation
End of Write Detection
– Toggle Bit
– Data# Polling
•
•
•
•
•
Hardware and Software Data Protection
Product Identification can be accessed via
Software Operation
TTL I/O Compatibility
JEDEC Standard
– Flash EEPROM Pinouts and command sets
Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm, 8mm x 20mm)
– 32-pin PDIP
•
•
•
•
– 128 Bytes per Page, 512 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 2.5 sec (typical)
– Effective Byte-Write Cycle Time: 39 µs (typical)
•
Fast Read Access Time
– 4.5-5.5V operation: 70 and 90 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
PRODUCT DESCRIPTION
The SST29EE/LE/VE512 are 64K x8 CMOS, Page-Write
EEPROMs manufactured with SST’s proprietary, high
performance CMOS SuperFlash technology. The split-
gate cell design and thick oxide tunneling injector attain
better reliability and manufacturability compared with
alternate approaches. The SST29EE/LE/VE512 write
with a single power supply. Internal Erase/Program is
transparent to the user. The SST29EE/LE/VE512 con-
form to JEDEC standard pinouts for byte-wide memories.
The SST29EE/LE/VE512 are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applica-
tions, the SST29EE/LE/VE512 significantly improve per-
formance and reliability, while lowering power
consumption. The SST29EE/LE/VE512 improve flexibil-
ity while lowering the cost for program, data, and configu-
ration storage applications.
To meet high density, surface mount requirements, the
SST29EE/LE/VE512 are offered in 32-lead PLCC and 32-
lead TSOP packages. A 600-mil, 32-pin PDIP package is
also available. See Figures 1, 2, and 3 for pinouts.
Featuring high performance Page-Write, the SST29EE/
LE/VE512 provide a typical Byte-Write time of 39 µsec.
The entire memory, i.e., 64 Kbyte, can be written page-
by-page in as little as 2.5 seconds, when using interface
features such as Toggle Bit or Data# Polling to indicate
the completion of a Write cycle. To protect against inad-
vertent write, the SST29EE/LE/VE512 have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum
of applications, the SST29EE/LE/VE512 are offered with
a guaranteed Page-Write endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
Device Operation
The SST Page-Write EEPROM offers in-circuit electrical
write capability. The SST29EE/LE/VE512 do not require
separate Erase and Program operations. The internally
timed Write cycle executes both erase and program trans-
parently to the user. The SST29EE/LE/VE512 have indus-
try standard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE/LE/
VE512 are compatible with industry standard EEPROM
pinouts and functionality.
©2002 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Small-Sector Flash and SSF are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71060-06-000 2/02
1
301
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
consists of a specific three-byte load sequence that allows
writing to the selected page and will leave the SST29EE/
LE/VE512 protected at the end of the Page-Write. The
page-load cycle consists of loading 1 to 128 Bytes of data
into the page buffer. The internal Write cycle consists of the
TBLCO time-out and the write timer operation. During the
Write operation, the only valid reads are Data# Polling and
Toggle Bit.
Read
The Read operations of the SST29EE/LE/VE512 are con-
trolled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
(Figure 4).
The Page-Write operation allows the loading of up to 128
Bytes of data into the page buffer of the SST29EE/LE/
VE512 before the initiation of the internal Write cycle. Dur-
ing the internal Write cycle, all the data in the page buffer is
written simultaneously into the memory array. Hence, the
Page-Write feature of SST29EE/LE/VE512 allows the
entire memory to be written in as little as 2.5 seconds. Dur-
ing the internal Write cycle, the host is free to perform addi-
tional tasks, such as to fetch data from other locations in
the system to set up the write to the next page. In each
Page-Write operation, all the bytes that are loaded into the
page buffer must have the same page address, i.e. A7
through A16. Any byte not loaded with user data will be writ-
ten to FFH.
Write
The Page-Write to the SST29EE/LE/VE512 should always
use the JEDEC Standard Software Data Protection (SDP)
three-byte command sequence. The SST29EE/LE/VE512
contain the optional JEDEC approved Software Data Pro-
tection scheme. SST recommends that SDP always be
enabled, thus, the description of the Write operations will
be given using the SDP enabled format. The three-byte
SDP Enable and SDP Write commands are identical;
therefore, any time a SDP Write command is issued,
Software Data Protection is automatically assured. The
first time the three-byte SDP command is given, the device
becomes SDP enabled. Subsequent issuance of the same
command bypasses the data protection for the page being
written. At the end of the desired Page-Write, the entire
device remains protected. For additional descriptions,
please see the application notes The Proper Use of
JEDEC Standard Software Data Protection and Protecting
Against Unintentional Writes When Using Single Power
Supply Flash Memories.
See Figures 5 and 6 for the Page-Write cycle timing dia-
grams. If after the completion of the three-byte SDP load
sequence or the initial byte-load cycle, the host loads a sec-
ond byte into the page buffer within a byte-load cycle time
(TBLC) of 100 µs, the SST29EE/LE/VE512 will stay in the
page-load cycle. Additional bytes are then loaded consecu-
tively. The page-load cycle will be terminated if no addi-
tional byte is loaded into the page buffer within 200 µs
(TBLCO) from the last byte-load cycle, i.e., no subsequent
WE# or CE# high-to-low transition after the last rising edge
of WE# or CE#. Data in the page buffer can be changed by
a subsequent byte-load cycle. The page-load period can
continue indefinitely, as long as the host continues to load
the device within the byte-load cycle time of 100 µs. The
page to be loaded is determined by the page address of
the last byte loaded.
The Write operation consists of three steps. Step 1 is the
three-byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
SST29EE/LE/VE512. Steps 1 and 2 use the same timing
for both operations. Step 3 is an internally controlled Write
cycle for writing the data loaded in the page buffer into the
memory array for nonvolatile storage. During both the SDP
three-byte load sequence and the byte-load cycle, the
addresses are latched by the falling edge of either CE# or
WE#, whichever occurs last. The data is latched by the ris-
ing edge of either CE# or WE#, whichever occurs first. The
internal Write cycle is initiated by the TBLCO timer after the
rising edge of WE# or CE#, whichever occurs first. The
Write cycle, once initiated, will continue to completion, typi-
cally within 5 ms. See Figures 5 and 6 for WE# and CE#
controlled Page-Write cycle timing diagrams and Figures
15 and 17 for flowcharts.
Software Chip-Erase
The SST29EE/LE/VE512 provide a Chip-Erase operation,
which allows the user to simultaneously clear the entire
memory array to the “1” state. This is useful when the entire
device must be quickly erased.
The Software Chip-Erase operation is initiated by using a
specific six-byte load sequence. After the load sequence,
the device enters into an internally timed cycle similar to the
Write cycle. During the Erase operation, the only valid read
is Toggle Bit. See Table 4 for the load sequence, Figure 10
for timing diagram, and Figure 19 for the flowchart.
The Write operation has three functional cycles: the Soft-
ware Data Protection load sequence, the page-load cycle,
and the internal Write cycle. The Software Data Protection
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
2
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Write Operation Status Detection
Hardware Data Protection
The SST29EE/LE/VE512 provide two software means to
detect the completion of a Write cycle, in order to optimize
the system Write cycle time. The software detection
includes two status bits: Data# Polling (DQ7) and Toggle Bit
(DQ6). The end of write detection mode is enabled after the
rising WE# or CE# whichever occurs first, which initiates
the internal Write cycle.
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Software Data Protection (SDP)
The SST29EE/LE/VE512 provide the JEDEC approved
optional Software Data Protection scheme for all data alter-
ation operations, i.e., Write and Chip-Erase. With this
scheme, any Write operation requires the inclusion of a
series of three byte-load operations to precede the data
loading operation. The three-byte load sequence is used to
initiate the Write cycle, providing optimal protection from
inadvertent Write operations, e.g., during the system
power-up or power-down. The SST29EE/LE/VE512 are
shipped with the Software Data Protection disabled.
Data# Polling (DQ7)
When the SST29EE/LE/VE512 are in the internal Write
cycle, any attempt to read DQ7 of the last byte loaded dur-
ing the byte-load cycle will receive the complement of the
true data. Once the Write cycle is completed, DQ7 will
show true data. Note that even though DQ7 may have valid
data immediately following the completion of an internal
Write operation, the remaining data outputs may still be
invalid: valid data on the entire data bus will appear in sub-
sequent successive Read cycles after an interval of 1 µs.
See Figure 7 for Data# Polling timing diagram and Figure
16 for a flowchart.
The software protection scheme can be enabled by
applying a three-byte sequence to the device, during a
page-load cycle (Figures 5 and 6). The device will then
be automatically set into the data protect mode. Any
subsequent Write operation will require the preceding
three-byte sequence. See Table 4 for the specific soft-
ware command codes and Figures 5 and 6 for the tim-
ing diagrams. To set the device into the unprotected
mode, a six-byte sequence is required. See Table 4 for
the specific codes and Figure 9 for the timing diagram. If
a Write is attempted while SDP is enabled the device
will be in a non-accessible state for ~ 300 µs. SST rec-
ommends Software Data Protection always be enabled.
See Figure 17 for flowcharts.
Toggle Bit (DQ6)
During the internal Write cycle, any consecutive attempts to
read DQ6 will produce alternating ‘0’s and ‘1’s, i.e., toggling
between 0 and 1. When the Write cycle is completed, the
toggling will stop. The device is then ready for the next
operation. See Figure 8 for Toggle Bit timing diagram and
Figure 16 for a flowchart. The initial read of the Toggle Bit
will typically be a “1”.
The SST29EE/LE/VE512 Software Data Protection is a
global command, protecting (or unprotecting) all pages in
the entire memory array once enabled (or disabled). There-
fore using SDP for a single Page-Write will enable SDP for
the entire array. Single pages by themselves cannot be
SDP enabled or disabled, although the page addressed
during the SDP write will be written.
Data Protection
The SST29EE/LE/VE512 provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.
Single power supply reprogrammable nonvolatile memo-
ries may be unintentionally altered. SST strongly recom-
mends that Software Data Protection (SDP) always be
enabled. The SST29EE/LE/VE512 should be programmed
using the SDP command sequence. SST recommends the
SDP Disable Command Sequence not be issued to the
device prior to writing.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
3
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Please refer to the following Application Notes for more
information on using SDP:
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
•
Protecting Against Unintentional Writes When
Using Single Power Supply Flash Memories
Manufacturer’s ID
Device ID
0000H
BFH
•
The Proper Use of JEDEC Standard Software
Data Protection
SST29EE512
SST29LE512
SST29VE512
0001H
0001H
0001H
5DH
3DH
3DH
Product Identification
T1.2 301
The Product Identification mode identifies the device as the
SST29EE/LE/VE512 and manufacturer as SST. This mode
is accessed via software. For details, see Table 4, Figure
11 for the software ID entry, and Read timing diagram and
Figure 18 for the ID entry command sequence flowchart.
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Software ID Exit (reset) opera-
tion, which returns the device to the Read operation. The
Reset operation may also be used to reset the device to the
Read mode after an inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. See Table 4 for software command
codes, Figure 12 for timing waveform, and Figure 18 for a
flowchart.
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X-Decoder
A
- A
0
15
Address Buffer & Latches
Y-Decoder and Page Latches
I/O Buffers and Data Latches
CE#
Control Logic
OE#
WE#
DQ - DQ
7
0
301 ILL B1.1
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
4
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
4
3
2
1
32 31 30
29
5
A7
A6
A14
A13
A8
6
28
27
26
25
24
23
22
21
7
A5
8
A4
A9
32-lead PLCC
Top View
9
A3
A11
OE#
A10
CE#
DQ7
10
11
12
13
A2
A1
A0
DQ0
14 15 16 17 18 19 20
301 ILL F19.1
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
A11
A9
A8
A13
A14
NC
1
2
3
4
5
6
7
8
32
OE#
A10
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Standard Pinout
Top View
WE#
V
DD
NC
NC
A15
A12
A7
9
V
SS
Die Up
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
A6
A5
A4
A1
A2
A3
301 ILL F01.2
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP
NC
NC
A15
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
WE#
NC
2
3
4
A14
A13
A8
5
32-pin
PDIP
A6
6
A5
7
A9
A4
8
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
A3
9
A2
10
11
12
13
14
15
16
A1
A0
DQ0
DQ1
DQ2
V
SS
301 ILL F02.2
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
5
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
A15-A7
A6-A0
Pin Name
Functions
Row Address Inputs
Column Address Inputs
To provide memory addresses. Row addresses define a page for a Write cycle.
Column Addresses are toggled to load page data
DQ7-DQ0 Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide: 5.0V supply (4.5-5.5V) for SST29EE512
3.0V supply (3.0-3.6V) for SST29LE512
2.7V supply (2.7-3.6V) for SST29VE512
VSS
NC
Ground
No Connection
Unconnected pins.
T2.2 301
TABLE 3: OPERATION MODES SELECTION
Mode
CE# OE# WE# DQ
Address
Read
VIL
VIL
VIH
X
VIL
VIH
X1
VIH
VIL
X
DOUT
AIN
Page-Write
Standby
Write Inhibit
DIN
AIN
High Z
X
VIL
X
X
High Z/ DOUT
High Z/ DOUT
DIN
X
X
VIH
VIL
X
Software Chip-Erase
Product Identification
Software Mode
VIL
VIH
AIN, See Table 4
VIL
VIH
VIL
Manufacturer’s ID (BFH)
Device ID2
See Table 4
SDP Enable Mode
SDP Disable Mode
VIL
VIL
VIH
VIH
VIL
VIL
See Table 4
See Table 4
T3.4 301
1. X can be VIL or VIH, but no other value.
2. Device ID = 5DH for SST29EE512 and 3DH for SST29LE/VE512
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
6
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data
5555H AAH 2AAAH 55H 5555H A0H
Addr2 Data
Software
Data Protect Enable
& Page-Write
Software Chip-Erase3 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry4,5
5555H AAH 2AAAH 55H 5555H 90H
Software ID Exit
5555H AAH 2AAAH 55H 5555H F0H
Alternate
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H
Software ID Entry6
T4.3 301
1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value.”
2. Page-Write consists of loading up to 128 Bytes (A6-A0)
3. The software Chip-Erase function is not supported by the industrial temperature part.
Please contact SST if you require this function for an industrial temperature part.
4. The device does not remain in Software Product ID mode if powered down.
5. With A14-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,
SST29EE512 Device ID = 5DH, is read with A0 = 1
SST29LE/VE512 Device ID = 3DH, is read with A0 = 1
6. Alternate six-byte Software Product ID Command Code
Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code
sequence. For new designs, SST recommends that the three-byte command code sequence be used.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
7
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE FOR SST29EE512
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
4.5-5.5V
4.5-5.5V
-40°C to +85°C
OPERATING RANGE FOR SST29LE512
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
3.0-3.6V
3.0-3.6V
-40°C to +85°C
OPERATING RANGE FOR SST29VE512
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF
See Figures 13 and 14
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
8
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V FOR SST29EE512
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
VDD=VDD Max
IDD
Power Supply Current
Read
Write
30
50
3
mA
mA
mA
CE#=OE#=VIL, WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH, VDD=VDD Max
CE#=OE#=WE#=VIH, VDD=VDD Max
ISB1
ISB2
Standby VDD Current
(TTL input)
Standby VDD Current
(CMOS input)
50
µA
CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
VIL
VIH
VOL
VOH
10
0.8
Input High Voltage
2.0
2.4
V
VDD=VDD Max
Output Low Voltage
Output High Voltage
0.4
V
IOL=2.1 mA, VDD=VDD Min
IOH=-400 µA, VDD=VDD Min
V
T5.1 301
TABLE 6: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST29LE512 AND 2.7-3.6V FOR SST29VE512
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
IDD
Power Supply Current
VDD=VDD Max
Read
Write
12
15
1
mA
mA
mA
CE#=OE#=VIL, WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH, VDD=VDD Max
CE#=OE#=WE#=VIH, VDD=VDD Max
ISB1
ISB2
Standby VDD Current
(TTL input)
Standby VDD Current
(CMOS input)
15
µA
CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
VIL
VIH
VOL
VOH
10
0.8
Input High Voltage
2.0
2.4
V
VDD=VDD Max
Output Low Voltage
Output High Voltage
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
V
T6.2 301
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
9
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
100
5
1
TPU-WRITE
ms
T7.0 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T8.0 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100
T9.5 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
10
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
AC CHARACTERISTICS
TABLE 10: READ CYCLE TIMING PARAMETERS FOR SST29EE512
SST29EE512-70
SST29EE512-90
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
90
TCE
Chip Enable Access Time
Address Access Time
70
70
30
90
90
40
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
20
20
30
30
ns
1
TOHZ
ns
1
TOH
0
0
ns
T10.2 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: READ CYCLE TIMING PARAMETERS FOR SST29LE512
SST29LE512-150
SST29LE512-200
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
150
200
TCE
Chip Enable Access Time
Address Access Time
150
150
60
200
200
100
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
30
30
50
50
ns
1
TOHZ
ns
1
TOH
0
0
ns
T11.1 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: READ CYCLE TIMING PARAMETERS FOR SST29VE512
SST29VE512-200
SST29VE512-250
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
200
250
TCE
Chip Enable Access Time
Address Access Time
200
200
100
250
250
120
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
50
50
50
50
ns
1
TOHZ
ns
1
TOH
0
0
ns
T12.1 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
11
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS
SST29EE512
SST29LE/VE512
Symbol
TWC
TAS
Parameter
Min
Max
Min
Max
Units
ms
ns
Write Cycle (Erase and Program)
Address Setup Time
Address Hold Time
10
10
0
50
0
0
70
0
TAH
ns
TCS
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
ns
TCH
0
0
ns
TOES
TOEH
TCP
0
0
ns
0
0
ns
70
70
35
0
120
120
50
0
ns
TWP
TDS
WE# Pulse Width
ns
Data Setup Time
ns
1
TDH
Data Hold Time
ns
1
TBLC
Byte Load Cycle Time
Byte Load Cycle Time
Software ID Access and Exit Time
Software Chip-Erase
0.05
200
100
0.05
200
100
µs
1
TBLCO
µs
1
TIDA
10
20
10
20
µs
TSCE
ms
T13.6 301
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
12
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
T
T
RC
AA
ADDRESS A
15-0
T
CE
CE#
T
OE
OE#
T
T
OHZ
OLZ
V
IH
WE#
T
CHZ
T
OH
T
CLZ
HIGH-Z
DATA VALID
DATA VALID
DQ
7-0
301 ILL F03.0
FIGURE 4: READ CYCLE TIMING DIAGRAM
Three-Byte Sequence for
Enabling SDP
T
AH
T
AS
ADDRESS A
5555 2AAA 5555
15-0
T
T
CS
CH
CE#
T
T
OEH
OES
OE#
WE#
T
WP
T
BLCO
T
BLC
T
DH
DQ
AA
55
A0
DATA VALID
7-0
T
WC
T
DS
SW0
SW1
SW2
BYTE 0
BYTE 1
BYTE 127
301 ILL F04.1
FIGURE 5: WE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
13
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Three-Byte Sequence for
Enabling SDP
T
AH
T
AS
ADDRESS A
5555 2AAA 5555
15-0
T
CP
T
T
BLCO
BLC
CE#
T
T
OEH
OES
OE#
WE#
T
T
CS
CH
T
DH
DQ
AA
55
A0
DATA VALID
7-0
T
WC
T
DS
SW0
SW1
SW2
BYTE 0
BYTE 1
BYTE 127
301 ILL F05.1
FIGURE 6: CE# CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
ADDRESS A
15-0
T
CE
CE#
T
OES
T
OEH
OE#
T
OE
WE#
DQ
7
D
D
D#
D#
T
+ T
BLCO
WC
301 ILL F06.0
FIGURE 7: DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
14
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
ADDRESS A
15-0
CE#
OE#
T
T
CE
T
OEH
T
OES
OE
WE#
DQ
6
T
+ T
BLCO
WC
TWO READ CYCLES
WITH SAME OUTPUTS
301 ILL F07.0
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
Six-Byte Sequence for Disabling
Software Data Protection
T
WC
ADDRESS A
14-0
5555
2AAA
5555
5555
2AAA
5555
DQ
AA
55
80
AA
55
20
7-0
CE#
OE#
WE#
T
BLCO
T
WP
T
BLC
SW0
SW1
SW2
SW3
SW4
SW5
301 ILL F08.1
FIGURE 9: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
15
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Six-Byte Code for Software Chip-Erase
T
SCE
ADDRESS A
14-0
5555
2AAA
5555
5555
2AAA
5555
DQ
AA
55
80
AA
55
10
7-0
CE#
OE#
WE#
T
BLCO
T
WP
T
BLC
SW0
SW1
SW2
SW3
SW4
SW5
301 ILL F09.2
FIGURE 10: SOFTWARE CHIP-ERASE TIMING DIAGRAM
Three-Byte Sequence
for Software ID Entry
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
T
AA
DQ
AA
55
90
BF
DEVICE ID
7-0
T
IDA
CE#
OE#
WE#
T
WP
T
BLC
DEVICE ID = 5DH for SST29EE512
3DH for SST29LE512/29VE512
SW0
SW1
SW2
=
301 ILL F10.2
FIGURE 11: SOFTWARE ID ENTRY AND READ
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
16
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Three-Byte Sequence
for Software ID Exit and Reset
ADDRESS A
14-0
5555
2AAA
5555
DQ
AA
55
F0
7-0
T
IDA
CE#
OE#
WE#
T
WP
T
BLC
SW0
SW1
SW2
301 ILL F11.0
FIGURE 12: SOFTWARE ID EXIT AND RESET
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
17
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
V
IHT
V
V
HT
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
V
ILT
301 ILL F12.1
AC test inputs are driven at VIHT (2.4V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for
inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE
TO TESTER
V
DD
R
L HIGH
TO DUT
C
R
L LOW
L
301 ILL F13.1
FIGURE 14: A TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
18
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Start
Software Data
Protect Write
Command
See Figure 17
Set Page
Address
Set Byte
Address = 0
Load Byte
Data
Increment
Byte Address
By 1
Byte
Address =
128?
No
Yes
Wait T
BLCO
Wait for end of
Write (T
,
WC
Data# Polling bit
or Toggle bit
operation)
Write
Completed
301 ILL F14.1
FIGURE 15: WRITE ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
19
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Page-Write
Initiated
Page-Write
Initiated
Page-Write
Initiated
Read DQ
(Data for last
byte loaded)
7
Read a byte
from page
Wait T
WC
Write
Completed
No
Read same
byte
Is DQ =
7
true data?
Yes
Write
Completed
No
Does DQ
match?
6
Yes
Write
Completed
301 ILL F15.1
FIGURE 16: WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
20
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Software Data Protect Enable
Command Sequence
Software Data Protect
Disable Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: A0H
Address: 5555H
Write data: 80H
Address: 5555H
Optional Page Load
Operation
Load 0 to
128 Bytes of
page data
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Wait T
BLCO
Write data: 20H
Address: 5555H
Wait T
WC
Wait T
BLCO
SDP Enabled
Wait T
WC
SDP Disabled
301 ILL F16.1
FIGURE 17: SOFTWARE DATA PROTECTION FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
21
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Write data: AAH
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 55H
Address: 2AAAH
Write data: 90H
Address: 5555H
Write data: F0H
Address: 5555H
Pause 10 µs
Pause 10 µs
Return to normal
operation
Read Software ID
301 ILL F17.1
FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
22
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
Software Chip-Erase
Command Sequence
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 80H
Address: 5555H
Write data: AAH
Address: 5555H
Write data: 55H
Address: 2AAAH
Write data: 10H
Address: 5555H
Wait T
SCE
Chip-Erase
to FFH
301 ILL F18.2
FIGURE 19: SOFTWARE CHIP-ERASE COMMAND CODES
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
23
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST29xE512
-
XXX
-
XX
-
XX
Package Modifier
H = 32 leads or pins
Package Type
E = TSOP (type 1, die up, 8mm x 20mm)
N = PLCC
P = PDIP
W = TSOP (type 1, die up, 8mm x 14mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
250 = 250 ns
200 = 200 ns
150 =150 ns
90 = 90 ns
70 = 70 ns
Function
E = Page-Write
Voltage
E = 4.5-5.5V
L = 3.0-3.6V
V = 2.7-3.6V
Valid combinations for SST29EE512
SST29EE512-70-4C-NH
SST29EE512-70-4I-NH
SST29EE512-70-4C-WH
SST29EE512-70-4I-WH
SST29EE512-70-4C-EH
SST29EE512-70-4I-EH
SST29EE512-70-4C-PH
Valid combinations for SST29LE512
SST29LE512-150-4C-NH SST29LE512-150-4C-WH SST29LE512-150-4C-EH
SST29LE512-150-4I-NH SST29LE512-150-4I-WH SST29LE512-150-4I-EH
Valid combinations for SST29VE512
SST29VE512-200-4C-NH SST29VE512-200-4C-WH SST29VE512-200-4C-EH
SST29VE512-200-4I-NH SST29VE512-200-4I-WH SST29VE512-200-4I-EH
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
Note: The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you
require this function for an industrial temperature part.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
24
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.495
.485
.112
.106
.453
.447
Optional
Pin #1
Identifier
.048
.042
.029
.023
.040
.030
.020 R.
MAX.
x 30˚
R.
2
1
32
.042
.048
.021
.013
.400
BSC
.530
.490
.595 .553
.585 .547
.032
.026
.050
BSC
.015 Min.
.095
.075
.050
BSC
.032
.026
.140
.125
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10
7.90
0.27
0.17
0.15
0.05
12.50
12.30
DETAIL
1.20
max.
0.70
0.50
14.20
13.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
32-tsop-WH-7
1mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM
SST PACKAGE CODE: WH
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
25
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10
7.90
0.27
0.17
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0˚- 5˚
0.70
0.50
Note: 1.Complies with JEDEC publication 95 MO-142 BD dimensions,
although some dimensions may be more stringent.
2.All linear dimensions are in millimeters (max/min).
3.Coplanarity: 0.1 mm
1mm
32-tsop-EH-7
4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM
SST PACKAGE CODE: EH
32
C
L
1
Pin #1 Identifier
.625
.600
.550
.530
1.655
1.645
.075
.065
7˚
4 PLCS.
Base
Plane
.200
.170
Seating
Plane
.050
.015
0˚
15˚
.012
.008
.150
.120
.100 BSC
.022
.016
.080
.070
.600 BSC
.065
.045
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32-pdip-PH-3
32-PIN PLASTIC DUAL IN-LINE PINS (PDIP)
SST PACKAGE CODE: PH
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02 301
26
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