SST29VF040-70-4C-NHE [SILICON]
Flash, 512KX8, 70ns, PQCC32, ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32;
| 型号： | SST29VF040-70-4C-NHE |
| 厂家： | 
SILICON |
| 描述： | Flash, 512KX8, 70ns, PQCC32, ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32 |
| 文件： | 总26页 (文件大小：745K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
SST29SF/VF512 / 010 / 020 / 040512Kb / 1Mb / 2Mb / 4Mb (x8)
Preliminary Specifications
Byte-Program, Small Erase Sector flash memories
FEATURES:
•
•
Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8
Single Voltage Read and Write Operations
– 4.5-5.5V-only for SST29SF512/010/020/040
– 2.7-3.6V for SST29VF512/010/020/040
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
•
•
1 second (typical) for SST29SF/VF512
2 seconds (typical) for SST29SF/VF010
4 seconds (typical) for SST29SF/VF020
8 seconds (typical) for SST29SF/VF040
Low Power Consumption:
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
TTL I/O Compatibility for SST29SFxxx
CMOS I/O Compatibility for SST29VFxxx
JEDEC Standard
– Flash EEPROM Pinouts and command sets
Packages Available
– Active Current: 10 mA (typical)
– Standby Current:
30 µA (typical) for SST29SF512/010/020/040
1 µA (typical) for SST29VF512/010/020/040
•
•
Sector-Erase Capability
– Uniform 128 Byte sectors
Fast Read Access Time:
– 55 ns
– 70 ns
•
•
•
•
Latched Address and Data
•
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP
PRODUCT DESCRIPTION
The SST29SF512/010/020/040 and SST29VF512/010/
020/040 are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS
Small-Sector Flash (SSF) manufactured with SST’s propri-
etary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST29SFxxx devices write
(Program or Erase) with a 4.5-5.5V power supply. The
SST29VFxxx devices write (Program or Erase) with a 2.7-
3.6V power supply. These devices conform to JEDEC stan-
dard pinouts for x8 memories.
and reliability, while lowering power consumption. They
inherently use less energy during Erase and Program than
alternative flash technologies. The total energy consumed
is a function of the applied voltage, current, and time of
application. Since for any given voltage range, the Super-
Flash technology uses less current to program and has a
shorter erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
technologies. They also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
Featuring high performance Byte-Program, the
SST29SFxxx and SST29VFxxx devices provide a maxi-
mum Byte-Program time of 20 µsec. To protect against
inadvertent write, they have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of at least
10,000 cycles. Data retention is rated at greater than 100
years.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST29SFxxx and SST29VFxxx devices are offered in 32-
lead PLCC and 32-lead TSOP packages. A 600 mil, 32-pin
PDIP is also offered for SST29SFxxx devices. See Figures
1, 2, and 3 for pinouts.
The SST29SFxxx and SST29VFxxx devices are suited for
applications that require convenient and economical updat-
ing of program, configuration, or data memory. For all sys-
tem applications, they significantly improve performance
©2002 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Small-Sector Flash and SSF are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71160-05-000 2/02
1
505
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
pulse, while the command (20H) is latched on the rising
edge of the sixth WE# pulse. The internal Erase operation
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
begins after the sixth WE# pulse. The End-of-Erase opera-
tion can be determined using either Data# Polling or Toggle
Bit methods. See Figure 9 for timing waveforms. Any com-
mands issued during the Sector-Erase operation are
ignored.
Chip-Erase Operation
The SST29SFxxx and SST29VFxxx devices provide a
Chip-Erase operation, which allows the user to erase the
entire memory array to the “1s” state. This is useful when
the entire device must be quickly erased.
Read
The Read operation of the SST29SFxxx and SST29VFxxx
devices are controlled by CE# and OE#, both have to be
low for the system to obtain data from the outputs. CE# is
used for device selection. When CE# is high, the chip is
deselected and only standby power is consumed. OE# is
the output control and is used to gate data from the output
pins. The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing dia-
gram for further details (Figure 4).
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or CE#, whichever occurs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 10 for timing diagram, and Figure 19 for
the flowchart. Any commands written during the Chip-
Erase operation will be ignored.
Byte-Program Operation
The SST29SFxxx and SST29VFxxx devices are pro-
grammed on a byte-by-byte basis. Before programming,
the sector where the byte exists must be fully erased. The
Program operation is accomplished in three steps. The first
step is the three-byte load sequence for Software Data Pro-
tection. The second step is to load byte address and byte
data. During the Byte-Program operation, the addresses
are latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the rising
edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operation which is initi-
ated after the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once initiated, will
be completed, within 20 µs. See Figures 5 and 6 for WE#
and CE# controlled Program operation timing diagrams
and Figure 16 for flowcharts. During the Program opera-
tion, the only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.
Write Operation Status Detection
The SST29SFxxx and SST29VFxxx devices provide two
software means to detect the completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system
Write cycle time. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6).
The End-of-Write detection mode is enabled after the ris-
ing edge of WE# which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The SST29SFxxx and
SST29VFxxx offer Sector-Erase mode. The sector archi-
tecture is based on uniform sector size of 128 Bytes. The
Sector-Erase operation is initiated by executing a six-byte-
command sequence with Sector-Erase command (20H)
and sector address (SA) in the last bus cycle. The sector
address is latched on the falling edge of the sixth WE#
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
2
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Data# Polling (DQ7)
Hardware Data Protection
When the SST29SFxxx and SST29VFxxx devices are in
the internal Program operation, any attempt to read DQ7
will produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subse-
quent successive Read cycles after an interval of 1 µs.
During internal Erase operation, any attempt to read DQ7
will produce a ‘0’. Once the internal Erase operation is
completed, DQ7 will produce a ‘1’. The Data# Polling is
valid after the rising edge of fourth WE# (or CE#) pulse
for Program operation. For Sector- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE#
(or CE#) pulse. See Figure 7 for Data# Polling timing dia-
gram and Figure 17 for a flowchart.
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 2.5V for SST29SFxxx. The
Write operation is inhibited when VDD is less than 1.5V. for
SST29VFxxx.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST29SFxxx and SST29VFxxx provide the JEDEC
approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Pro-
gram operation requires the inclusion of a series of three-
byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection
from inadvertent Write operations, e.g., during the system
power-up or power-down. Any Erase operation requires the
inclusion of a six-byte load sequence. These devices are
shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode, within TRC.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating ‘0’s
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia-
gram and Figure 17 for a flowchart.
Data Protection
The SST29SFxxx and SST29VFxxx devices provide both
hardware and software features to protect nonvolatile data
from inadvertent writes.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
3
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Product Identification
Product Identification Mode Exit/Reset
The Product Identification mode identifies the devices as
SST29SF512, SST29SF010, SST29SF020, SST29SF040
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the Software ID Exit command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form, and Figure 18 for a flowchart.
and
SST29VF512,
SST29VF010,
SST29VF020,
SST29VF040 and manufacturer as SST. This mode may
be accessed by software operations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple manufactur-
ers in the same socket. For details, see Table 4 for software
operation, Figure 11 for the Software ID Entry and Read
timing diagram and Figure 18 for the Software ID Entry
command sequence flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
0000H
BFH
SST29SF512
SST29VF512
SST29SF010
SST29VF010
SST29SF020
SST29VF020
SST29SF040
SST29VF040
0001H
0001H
0001H
0001H
0001H
0001H
0001H
0001H
20H
21H
22H
23H
24H
25H
13H
14H
T1.1 505
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X-Decoder
Memory
Address
Address Buffers & Latches
Control Logic
Y-Decoder
CE#
OE#
WE#
I/O Buffers and Data Latches
DQ - DQ
7
0
505 ILL B1.1
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
4
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512
SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040
4
3
2
1
32 31 30
29
5
A7
A6
A7
A6
A7
A6
A7
A6
A14
A13
A8
A14
A13
A8
A14
A13
A8
A14
A13
A8
6
28
27
26
25
24
23
22
21
7
A5
A5
A5
A5
8
A4
A4
A4
A4
A9
A9
A9
A9
32-lead PLCC
Top View
9
A3
A3
A3
A3
A11
OE#
A10
CE#
DQ7
A11
OE#
A10
CE#
DQ7
A11
OE#
A10
CE#
DQ7
A11
OE#
A10
CE#
DQ7
10
11
12
13
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
DQ0
DQ0
DQ0
DQ0
14 15 16 17 18 19 20
505 ILL F02a.4
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
5
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512
SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040
A11
A9
A8
A13
A14
A17
WE#
A11
A9
A8
A13
A14
A17
WE#
A11
A9
A8
A13
A14
NC
A11
A9
A8
A13
A14
NC
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
OE#
A10
OE#
A10
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Standard Pinout
Top View
WE#
WE#
V
V
V
V
DD
DD
DD
DD
A18
A16
A15
A12
A7
NC
A16
A15
A12
A7
NC
A16
A15
A12
A7
NC
NC
A15
A12
A7
9
V
V
V
V
SS
SS
SS
SS
Die Up
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
DQ2
DQ1
DQ0
A0
DQ2
DQ1
DQ0
A0
DQ2
DQ1
DQ0
A0
A6
A5
A4
A6
A5
A4
A6
A5
A4
A6
A5
A4
A1
A2
A3
A1
A2
A3
A1
A2
A3
A1
A2
A3
505 ILL F01.2
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)
SST29SF040 SST29SF020 SST29SF010 SST29SF512
SST29SF512 SST29SF010 SST29SF020 SST29SF040
A18
A16
A15
A12
A7
NC
A16
A15
A12
A7
NC
A16
A15
A12
A7
NC
NC
A15
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
V
V
DD
DD
DD
DD
2
WE#
NC
WE#
NC
WE#
A17
A14
A13
A8
WE#
A17
A14
A13
A8
3
4
A14
A13
A8
A14
A13
A8
5
32-pin
PDIP
A6
A6
A6
A6
6
A5
A5
A5
A5
7
A9
A9
A9
A9
A4
A4
A4
A4
8
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
A3
A3
A3
A3
9
A2
A2
A2
A2
10
11
12
13
14
15
16
A1
A1
A1
A1
A0
A0
A0
A0
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
V
V
V
V
SS
SS
SS
SS
505 ILL F02b.4
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
6
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses. During Sector-Erase AMS-A8 address lines will select the
sector.
DQ7-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
4.5-5.5V for SST29SF512/010/020/040
2.7-3.6V for SST29VF512/010/020/040
VSS
NC
Ground
No Connection
Pin not connected internally
T2.3 505
1. AMS = Most significant address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040
TABLE 3: OPERATION MODES SELECTION
Mode
Read
CE# OE# WE# DQ
Address
AIN
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
DOUT
DIN
X1
Program
Erase
AIN
Sector address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 4
T3.4 505
1. X can be VIL or VIH, but no other value.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
7
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data
Byte-Program
555H
555H
555H
555H
XXH
AAH
AAH
AAH
AAH
F0H
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
555H
A0H
80H
80H
90H
BA2
Data
AAH
AAH
3
Sector-Erase
555H
555H
2AAH
2AAH
55H
55H
SAX
555H
20H
10H
Chip-Erase
Software ID Entry4,5
Software ID Exit6
Software ID Exit6
555H
2AAH
55H
555H
F0H
T4.5 505
1. Address format A14-A0 (Hex),
Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF512.
Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF020 and SST29SF/VF040.
AMS = Most significant address
AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040 for SST29SF/VF010.
2. BA = Program Byte address
3. SAX for Sector-Erase; uses AMS-A7 address lines for SST29SF/VFxxx
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,
SST29SF512 Device ID = 20H, is read with A0 = 1
SST29SF512 Device ID = 21H, is read with A0 = 1
SST29SF010 Device ID = 22H, is read with A0 = 1
SST29VF010 Device ID = 23H, is read with A0 = 1
SST29SF020 Device ID = 24H, is read with A0 = 1
SST29SF020 Device ID = 25H, is read with A0 = 1
SST29SF040 Device ID = 13H, is read with A0 = 1
SST29VF040 Device ID = 14H, is read with A0 = 1
6. Both Software ID Exit operations are equivalent
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
8
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE FOR SST29SF512/010/020/040
OPERATING RANGE FOR SST29VF512/010/020/040
Range
Ambient Temp
0°C to +70°C
VDD
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
4.5-5.5V
4.5-5.5V
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
-40°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 55 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 70 ns
See Figures 13, 14, and 15
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V FOR SST29SFXXX
Limits
Symbol Parameter
Min
Max Units Test Conditions
IDD
Power Supply Current
Address input=VIL/VIH, at f=1/TRC Min
VDD=VDD Max
Read
20
20
3
mA
mA
mA
µA
µA
µA
V
CE#=OE#=VIL, WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
CE#=VIH, VDD=VDD Max
CE#=VIHC, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
Write
ISB1
ISB2
ILI
Standby VDD Current (TTL input)
Standby VDD Current (CMOS input)
Input Leakage Current
Output Leakage Current
Input Low Voltage
100
1
ILO
10
0.8
VIL
VIH
VIHC
VOL
VOH
Input High Voltage
2.0
V
VDD=VDD Max
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
VDD-0.3
V
VDD=VDD Max
0.4
V
IOL=2.1 µA, VDD=VDD Min
IOH=-400 µA, VDD=VDD Min
2.4
V
T5.3 505
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
9
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
TABLE 6: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V FOR SST29VFXXX
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input=VIL/VIH, at f=1/TRC Min
IDD
Power Supply Current
VDD=VDD Max
Read
20
20
15
1
mA
mA
µA
µA
µA
V
CE#=OE#=VIL, WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
CE#=VIHC, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
Write
ISB
Standby VDD Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
ILI
ILO
10
0.8
VIL
VIH
VIHC
VOL
VOH
0.7VDD
V
VDD=VDD Max
VDD-0.3
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
VDD-0.2
V
T6.5 505
TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
µs
µs
1
TPU-WRITE
100
T7.1 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
T8.1 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T9.2 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
10
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
AC CHARACTERISTICS
TABLE 10: READ CYCLE TIMING PARAMETERS
VDD = 4.5-5.5V FOR SST29SFXXX AND 2.7-3.6V FOR SST29VFXXX
SST29SF/VFxxx-55
SST29SF/VFxxx-70
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
55
70
TCE
Chip Enable Access Time
Address Access Time
55
55
30
70
70
35
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
20
20
25
25
ns
1
TOHZ
ns
1
TOH
0
0
ns
T10.6 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: PROGRAM/ERASE CYCLE TIMING PARAMETERS
VDD = 4.5-5.5V FOR SST29SFXXX AND 2.7-3.6V FOR SST29VFXXX
Symbol Parameter
Min
Max
Units
µs
TBP
Byte-Program Time
20
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
ns
TAH
30
0
ns
TCS
ns
TCH
TOES
TOEH
TCP
0
ns
0
ns
10
40
40
30
30
40
0
ns
ns
TWP
TWPH
WE# Pulse Width
ns
1
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
TSCE
Chip-Erase
100
T11.7 505
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
11
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
T
T
AA
RC
ADDRESS A
MS-0
CE#
OE#
WE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
7-0
DATA VALID
DATA VALID
505 ILL F03.1
Note: A
= Most Significant Address
MS
MS
A
= A for SST29SF/VF512, A for SST29SF/VF010, A for SST29SF/VF020 and A for SST29SF/VF040
15
16
17
18
FIGURE 4: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
555
2AA
555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
WP
WE#
T
T
AS
DS
T
WPH
OE#
CE#
T
CH
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
(ADDR/DATA)
505 ILL F04.1
Note: A
A
= Most Significant Address
MS
MS
= A for SST29SF/VF512, A for SST29SF/VF010, A for SST29SF/VF020 and A for SST29SF/VF040
15 16 17 18
FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
12
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS
T
BP
555
2AA
555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
(ADDR/DATA)
505 ILL F05.1
Note: A
A
= Most Significant Address
MS
MS
= A for SST29SF/VF512, A for SST29SF/VF010, A for SST29SF/VF020 and A for SST29SF/VF040
15 16 17 18
FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
OEH
T
OE
DQ
7
D
D#
D#
D
505 ILL F06.1
Note: A
A
= Most Significant Address
MS
MS
= A for SST29SF/VF512, A for SST29SF/VF010, A for SST29SF/VF020 and A for SST29SF/VF040
15 16 17 18
FIGURE 7: DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
13
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
T
OE
OEH
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
505 ILL F07.1
Note: A
A
= Most Significant Address
MS
MS
= A for SST29SF/VF512, A for SST29SF/VF010, A for SST29SF/VF020 and A for SST29SF/VF040
15 16 17 18
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
555 555 2AA
555
2AA
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
20
SW5
SW0
505 ILL F10.2
Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 11)
A
A
= Most significant address
MS
MS
= A for SST29SF/VF512, A for SST29SF/VF010, A for SST29SF/VF020 and A for SST29SF/VF040
15 16 17 18
FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
14
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
555
2AA
555
555
2AA
555
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
SW2
AA
55
10
SW0
SW3
SW4
SW5
505 ILL F17.2
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 11)
Note:
A
A
= Most Significant Address
MS
MS
= A for SST29SF/VF512, A for SST29SF/VF010, A for SST29SF/VF020 and A for SST29SF/VF040
15 16 17 18
FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-Byte Sequence for
Software ID Entry
ADDRESS A
555
2AA
555
0000
0001
14-0
T
CE#
IDA
OE#
WE#
T
WP
T
WPH
T
AA
DQ
7-0
AA
55
90
BF
Device ID
SW0
SW1
SW2
505 ILL F08.2
Note: Device ID = 20H for SST29SF512, 22H for SST29SF010, 24H for SST29SF020, 13H for SST29SF040
21H for SST29VF512, 23H for SST29VF010, 25H for SST29VF020, 14H for SST29VF040
FIGURE 11: SOFTWARE ID ENTRY AND READ
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
15
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
555
2AA
555
ADDRESS A
14-0
DQ
AA
55
F0
7-0
T
IDA
CE#
OE#
T
WP
WE#
T
WHP
SW0
SW1
SW2
505 ILL F21.0
FIGURE 12: SOFTWARE ID EXIT AND RESET
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
16
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
505 ILL F11.0
AC test inputs are driven at VIHT (3.0 V) for a logic “1” and VILT (0 V) for a logic “0”. Measurement reference points for
inputs and outputs are VIT (1.5 VDD) and VOT (1.5 VDD). Input rise and fall times (10% ↔ 90%) are <10 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SST29SFXXX
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
505 ILL F11.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SST29VFXXX
TEST LOAD EXAMPLE FOR SST29SF512/010/020/040
TEST LOAD EXAMPLE FOR SST29VF512/010/020/040
TO TESTER
V
DD
TO TESTER
R
L HIGH
TO DUT
C
L
TO DUT
505 ILL F12b.2
C
R
L LOW
L
505 ILL F12.2
FIGURE 15: TEST LOAD EXAMPLES
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
17
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Start
Load data: AAH
Address: 555H
Load data: 55H
Address: 2AAH
Load data: A0H
Address: 555H
Load Byte
Address/Byte
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
505 ILL F13.1
FIGURE 16: BYTE-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
18
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Toggle Bit
Data# Polling
Internal Timer
Byte-
Program/Erase
Initiated
Byte-
Program/Erase
Initiated
Byte-
Program/Erase
Initiated
Read DQ
7
Read byte
Wait T
SCE, or SE
,
T
BP
T
Read same
byte
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
505 ILL F14.0
FIGURE 17: WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
19
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Software ID Entry
Software ID Exit &
Command Sequence
Reset Command Sequence
Load data: AAH
Address: 555H
Load data: AAH
Address: 555H
Load data: F0H
Address: XXH
Load data: 55H
Address: 2AAH
Load data: 55H
Address: 2AAH
Wait T
IDA
Load data: 90H
Address: 555H
Load data: F0H
Address: 555H
Return to normal
operation
Wait T
Wait T
IDA
IDA
Return to normal
operation
Read Software ID
505 ILL F15.1
FIGURE 18: SOFTWARE ID COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
20
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Chip-Erase
Sector-Erase
Command Sequence
Command Sequence
Load data: AAH
Address: 555H
Load data: AAH
Address: 555H
Load data: 55H
Address: 2AAH
Load data: 55H
Address: 2AAH
Load data: 80H
Address: 555H
Load data: 80H
Address: 555H
Load data: AAH
Address: 555H
Load data: AAH
Address: 555H
Load data: 55H
Address: 2AAH
Load data: 55H
Address: 2AAH
Load data: 10H
Address: 555H
Load data: 20H
Address: SA
X
Wait T
Wait T
SE
SCE
Chip erased
to FFH
Sector erased
to FFH
505 ILL F19.2
FIGURE 19: ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
21
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST29xFxxx
-
XXX
-
XX
-
XX
Package Modifier
H = 32 pins or leads
Package Type
N = PLCC
W = TSOP (type 1, die up, 8mm x 14mm)
P = PDIP
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
Device Density
040 = 4 Mbit
020 = 2 Mbit
010 = 1 Mbit
512 = 512 Kbit
Function
F = Chip- or Sector-Erase
Byte-Program
Voltage
S = 4.5-5.5V
V = 2.7-3.6V
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
22
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Valid combinations for SST29SF512
SST29SF512-55-4C-NH
SST29SF512-70-4C-NH
SST29SF512-55-4C-WH
SST29SF512-70-4C-WH
SST29SF512-70-4C-PH
SST29SF010-70-4C-PH
SST29SF020-70-4C-PH
SST29SF040-70-4C-PH
SST29SF512-55-4I-NH
SST29SF512-70-4I-NH
SST29SF512-55-4I-WH
SST29SF512-70-4I-WH
Valid combinations for SST29VF512
SST29VF512-55-4C-NH
SST29VF512-70-4C-NH
SST29VF512-55-4C-WH
SST29VF512-70-4C-WH
SST29VF512-55-4I-NH
SST29VF512-70-4I-NH
SST29VF512-55-4I-WH
SST29VF512-70-4I-WH
Valid combinations for SST29SF010
SST29SF010-55-4C-NH
SST29SF010-70-4C-NH
SST29SF010-55-4C-WH
SST29SF010-70-4C-WH
SST29SF010-55-4I-NH
SST29SF010-70-4I-NH
SST29SF010-55-4I-WH
SST29SF010-70-4I-WH
Valid combinations for SST29VF010
SST29VF010-55-4C-NH
SST29VF010-70-4C-NH
SST29VF010-55-4C-WH
SST29VF010-70-4C-WH
SST29VF010-55-4I-NH
SST29VF010-70-4I-NH
SST29VF010-55-4I-WH
SST29VF010-70-4I-WH
Valid combinations for SST29SF020
SST29SF020-55-4C-NH
SST29SF020-70-4C-NH
SST29SF020-55-4C-WH
SST29SF020-70-4C-WH
SST29SF020-55-4I-NH
SST29SF020-70-4I-NH
SST29SF020-55-4I-WH
SST29SF020-70-4I-WH
Valid combinations for SST29VF020
SST29VF020-55-4C-NH
SST29VF020-70-4C-NH
SST29VF020-55-4C-WH
SST29VF020-70-4C-WH
SST29VF020-55-4I-NH
SST29VF020-70-4I-NH
SST29VF020-55-4I-WH
SST29VF020-70-4I-WH
Valid combinations for SST29SF040
SST29SF040-55-4C-NH
SST29SF040-70-4C-NH
SST29SF040-55-4C-WH
SST29SF040-70-4C-WH
SST29SF040-55-4I-NH
SST29SF040-70-4I-NH
SST29SF040-55-4I-WH
SST29SF040-70-4I-WH
Valid combinations for SST29VF040
SST29VF040-55-4C-NH
SST29VF040-70-4C-NH
SST29VF040-55-4C-WH
SST29VF040-70-4C-WH
SST29VF040-55-4I-NH
SST29VF040-70-4I-NH
SST29VF040-55-4I-WH
SST29VF040-70-4I-WH
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
23
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
PACKAGING DIAGRAMS
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.495
.485
.112
.106
.453
.447
Optional
Pin #1
Identifier
.048
.042
.029
.023
.040
.030
.020 R.
MAX.
x 30˚
R.
2
1
32
.042
.048
.021
.013
.400
BSC
.530
.490
.595 .553
.585 .547
.032
.026
.050
BSC
.015 Min.
.095
.075
.050
BSC
.032
.026
.140
.125
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
24
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10
7.90
0.27
0.17
0.15
0.05
12.50
12.30
DETAIL
1.20
max.
0.70
0.50
14.20
13.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
32-tsop-WH-7
1mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM
SST PACKAGE CODE: WH
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
25
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
32
C
L
1
Pin #1 Identifier
.625
.600
.550
.530
1.655
1.645
.075
.065
7˚
4 PLCS.
Base
Plane
.200
.170
Seating
Plane
.050
.015
0˚
15˚
.012
.008
.150
.120
.100 BSC
.022
.016
.080
.070
.600 BSC
.065
.045
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32-pdip-PH-3
32-PIN PLASTIC DUAL IN-LINE PINS (PDIP)
SST PACKAGE CODE: PH
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02 505
26
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