SST30VR023-500-E-WH [SILICON]
Memory Circuit, ROM+SRAM, 256KX8, CMOS, PDSO32, 8 X 14 MM, TSOP1-32;
| 型号： | SST30VR023-500-E-WH |
| 厂家： | 
SILICON |
| 描述： | Memory Circuit, ROM+SRAM, 256KX8, CMOS, PDSO32, 8 X 14 MM, TSOP1-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
SST30VR021/022/0232 Mb Mask ROM (x8) + 1 Mb / 2Mb / 256 Kb SRAM (x8) Combo
Data Sheet
FEATURES:
•
ROM + SRAM ROM/RAM Combo
•
•
Low Power Dissipation:
– SST30VR021: 256K x8 ROM + 128K x8 SRAM
– SST30VR022: 256K x8 ROM + 256K x8 SRAM
– SST30VR023: 256K x8 ROM + 32K x8 SRAM
– Standby: 3 µW (Typical)
– Operating: 10 mW (Typical)
Fully Static Operation
– No clock or refresh required
Three state Outputs
•
•
ROM/RAM combo on a monolithic chip
Equivalent ComboMemory (Flash + SRAM):
SST31LF021E for code development and
pre-production
•
•
Packages Available
– 32-pin TSOP (8mm x14mm)
•
•
Wide Operating Voltage Range: 2.7-3.3V
Chip Access Time
– SST30VR022
70 ns
– SST30VR021/023 500 ns
PRODUCT DESCRIPTION
The SST30VR021/022/023 are ROM/RAM combo chips
consisting of 2 Mbit Read Only Memory organized as 256
KBytes and Static Random Access Memory organized as
128, 256, and 32 KBytes.
The SST30VR021/022/023 has an output enable input for
precise control of the data outputs. It also has two (2) sepa-
rate chip enable inputs for selection of either RAM or ROM
and for minimizing current drain during power-down mode.
The device is fabricated using SST’s advanced CMOS low
power process technology.
The SST30VR021/022/023 is particularly well suited for
use in low voltage (2.7-3.3V) supplies such as pagers,
organizers and other handheld applications.
FUNCTIONAL BLOCK DIAGRAM
RAMCS#
RAMCS#
ROMCS#
OE#
OE#
WE#
WE#
RAM
DQ -DQ
7
0
ROMCS#
OE#
A
-A
0
MS
ROM
380 ILL B1.1
Note: A
MS
= Most Significant Address
©2001 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71135-02-000 4/01
1
380
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
2
A10
A8
3
ROMCS#
DQ7
A13
4
A14
5
DQ6
Standard Pinout
Top View
A17
6
DQ5
RAMCS#
7
DQ4
V
8
DQ3
DD
WE#
A16
A15
A12
A7
9
V
SS
Die Up
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
A6
A1
A5
A2
A4
A3
380 ILL F01.0
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP
TABLE 1: PIN DESCRIPTION
Symbol
Pin Name
AMS1-A0
Address Inputs, for ROM: AMS = A17, for RAM: AMS =A16 for SST30VR021
A17 for SST30VR022
A14 for SST30VR023
WE#
Write Enable Input
Output Enable
RAM Enable Input
ROM Enable Input
Data Input/Output
Power Supply
OE#
RAMCS#
ROMCS#
DQ7-DQ0
VDD
VSS
Ground
T1.2 380
1. AMS = Most significant address
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
2
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on Any Pin Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD + 0.5V
Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Soldering Temperature (10 Seconds Lead Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
OPERATING RANGE
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
2.7-3.3V
2.7-3.3V
-20°C to +85°C
AC CONDITIONS OF TEST
Input Pulse Level. . . . . . . . . . . . . . . . . . . . . . . .0-VDD
Input & Output Timing Reference Levels . . . . . . .VDD/2
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 500 ns
TABLE 2: RECOMMENDED DC OPERATING CONDITIONS
Symbol
VDD
Parameter
Supply Voltage
Ground
Min
2.7
0
Max
3.3
Units
V
V
V
V
VSS
0
VIH
Input High Voltage
Input Low Voltage
2.4
-0.3
VDD + 0.5
0.3
VIL
T2.0 380
TABLE 3: DC OPERATING CHARACTERISTICS
VDD = 3.0 ± 0.3V
Symbol Parameter
Min
Max
Units Test Conditions
IDD1
ROM Operating Supply Current
4.0+1.1(f)1
mA
ROMCS#=VIL, RAMCS#=VIH,
VIN=VIH or VIL, II/O=Opens
IDD2
ISB
RAM Operating Supply Current
Standby VDD Current
2.5+1(f)1
10
mA
µA
ROMCS#=VIH, RAMCS#=VIL, II/O=Opens
ROMCS#≥VDD-0.2V, RAMCS#≥VDD-0.2V
VIN≥VDD-0.2V or VIN ≤0.2V
ILI
Input Leakage Current
Output Leakage Current
-1
-1
1
1
µA
µA
VIN=VSS to VDD
ILO
ROMCS#=RAMCS#=VIH or OE#=VIH or
WE#=VIL, VI/O=VSS to VDD
VOL
VOH
Output Low Voltage
Output High Voltage
0.4
V
V
IOL = 1.0 mA
IOH = -0.5 mA
2.2
T3.3 380
1. f = Frequency of operation (MHz) = 1/cycle time
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
3
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
TABLE 4: CAPACITANCE (Ta = 25°C, f=1 Mhz)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
8 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
T4.1 380
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
380 ILL F08.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
380 ILL F09.0
FIGURE 3: A TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
4
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
AC CHARACTERISTICS
I. ROM Operation
TABLE 5: READ CYCLE TIMING PARAMETERS VDD = 3.0V±0.3
SST30VR022-70
SST30VR021/023-500
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
500
TAA
Address Access Time
70
70
35
500
500
250
ns
TCO
Chip Select to Output
ns
TOE
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
ns
TLZ
0
0
25
25
ns
TOLZ
THZ
ns
25
25
30
30
ns
TOHZ
TOH
ns
10
15
ns
T5.1 380
T
RC
Address
T
AA
T
OH
Data Out
Previous Data Valid
Data Valid
380 ILL F02.0
FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = OE# = VIL)
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
5
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
T
RC
Address
T
T
HZ(1,2)
AA
T
CO
ROMCS#
OE#
T
T
OHZ(1)
LZ(2)
T
OE
T
T
OLZ
OH
High-Z
Data Valid
Data Out
380 ILL F03.0
Notes: 1. T
and T
are defined as the time at which the outputs achieve the open circuit condition
OHZ
HZ
and are referenced to the V
or V
.
OH
OL
2. At any given temperature and voltage condition T (max) is less than T (min) both for a given
HZ LZ
device and from device to device.
FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# & OE# CONTROLLED)
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
6
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
II. SRAM Operation (ROMCS# = VIH)
TABLE 6: READ CYCLE TIMING PARAMETERS VDD = 3.0V±0.3
SST30VR022-70
SST30VR021/023-500
Symbol Parameter
Min
Max
Min
Max
Units
ns
TRC
TAA
Read Cycle Time
70
500
Address Access Time
70
70
35
500
500
250
ns
TCO
TOE
TLZ
Chip Select to Output
ns
Output Enable to Valid Output
Chip Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
ns
0
25
15
ns
THZ
TOHZ
TOH
25
25
30
30
ns
ns
10
ns
T6.2 380
TABLE 7: WRITE CYCLE TIMING PARAMETERS VDD = 3.0V±0.3
SST30VR022-70
SST30VR021/023-500
Symbol Parameter
Min
Max
Min
500
365
375
0
Max
Units
ns
TWC
TCW
TAW
TAS
Write Cycle Time
70
60
60
0
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
ns
TWP
TWR
TWHZ
TDW
TDH
TOW
Write Pulse Width
60
0
375
0
ns
Write Recovery Time
ns
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
30
80
ns
30
0
200
0
ns
ns
0
15
ns
T7.1 380
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
7
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
T
RC
Address
Data Out
T
AA
T
OH
Previous Data Valid
Data Valid
380 ILL F04.0
FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE# = RAMCS# = VIL, WE# = VIH)
T
RC
Address
T
AA
T
OHZ(1)
T
OE
OE#
(1,2)
T
HZ
T
CO
RAMCS#
T
LZ(2)
T
OH
High-Z
Data Valid
Data Out
380 ILL F05.0
Notes: 1. T
and T
are defined as the time at which the outputs achieve the open circuit condition
OHZ
HZ
and are referenced to the V
or V
.
OH
OL
2. At any given temperature and voltage condition T (max) is less than T (min) both for a given
HZ LZ
device and from device to device.
3. WE# is high for Read cycle.
4. Address valid prior to coincidence with RAMCS# transition low.
FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE# OR RAMCS# CONTROLLED)
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
8
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
T
WC
Address
T
AW
T
WR(4)
T
CW(2)
RAMCS#
T
T
T
AS(3)
WP(1)
OH
WE#
Data In
T
T
DH
DW
High-Z
Data Valid
T
T
OW
WHZ(5)
(7)
(8)
High-Z (6)
Data Out
380 ILL F07.0
Notes: 1. A write occurs during the overlap (T
) of a low RAMCS# and low WE#. A write begins at the latest transition among
WP
RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high,
T
2. T
3. T
4. T
is measured from the beginning of write to the end of write.
is measured from the later of RAMCS# going low to the end of write.
is measured from the address valid to the beginning of write.
is measured from the end of write to the address change.
WP
CW
AS
WR
5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state.
7. D
8. D
is the same phase of the latest written data in this write cycle.
is the read data of new address
OUT
OUT
9. ROMCS# = V
IH
FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM
TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE
Address Inputs
X
ROMCS#1
RAMCS#1
WE#
X2
X2
X2
H
OE#
X2
H
DQ0-DQ7
H
L
H
H
H
L
Z
Z
Standby
Output Floating
ROM Read
A17-A0
A17-A0
L
L
Dout
Z
Only AMS3-A0 are valid4
Only AMS3-A0 are valid4
Only AMS3-A0 are valid4
H
H
H
H
Output Floating
RAM Read
L
H
L
Dout
Din
L
L
H
RAM Write
T8.4 380
1. If is forbidden for ROMCS# pin and RAMCS# pin to be “0” at the same time
2. X means Don’t Care.
3. AMS = A16 for SST30VR021, A17 for SST30VR022, and A14 for SST30VR023
4. For SST30VR021: A17 must be fixed to “L” or “H”
For SST30VR023: A15, A16, and A17 must be fixed to “L” or “H”
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
9
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
Device
Speed
Suffix1
Suffix2
XX
SST30VR023
-
XXX
-
X
-
-
RXXXX
C-Spec Number
Package Modifier
H = 32 leads
Numeric = Die modifier
Package Type
W = TSOP (8mm x 14mm)
U = Die only
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Read Access Speed
70 = 70 ns
500 = 500 ns
Device Density
021 = 2 Mbit ROM + 1 Mbit SRAM
022 = 2 Mbit ROM + 2 Mbit SRAM
023 = 2 Mbit ROM + 256 Kbit SRAM
Voltage Range
V = 2.7-3.3V
Device Family
30 = ROM/RAM Combo
SST30VR021 Valid combinations
SST30VR021-500-C-WH
SST30VR021-500-C-U1
SST30VR021-500-E-WH
SST30VR022 Valid combinations
SST30VR022-70-C-WH
SST30VR022-70-C-U1
SST30VR022-70-E-WH
SST30VR023 Valid combinations
SST30VR023-500-C-WH
SST30VR023-500-C-U1
SST30VR023-500-E-WH
Example:
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
10
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
.50
BSC
.270
.170
8.10
7.90
0.15
0.05
12.50
12.30
0.70
0.50
14.20
13.80
32.TSOP-WH-ILL.4
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM
SST PACKAGE CODE: WH
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
11
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
Data Sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380
12
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