SST32HF162C-70-4C-LBKE [SILICON]
Memory Circuit, 1MX16, CMOS, PBGA48, 10 X 12 MM, 1.40 MM HEIGHT, MO-210, LBGA-48;
| 型号： | SST32HF162C-70-4C-LBKE |
| 厂家： | 
SILICON |
| 描述： | Memory Circuit, 1MX16, CMOS, PBGA48, 10 X 12 MM, 1.40 MM HEIGHT, MO-210, LBGA-48 内存集成电路 |
| 文件： | 总28页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
SST32HF324 / 32832Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM
Preliminary Specifications
(x16) MCP ComboMemories
FEATURES:
•
ComboMemories organized as:
•
•
Erase-Suspend/Erase-Resume Capabilities
Fast Read Access Times:
– Flash: 70 ns
– SRAM: 70 ns
– SST32HF162C: 1M x16 Flash + 128K x16 SRAM
– SST32HF164C: 1M x16 Flash + 256K x16 SRAM
– SST32HF324C: 2M x16 Flash + 256K x16 SRAM
•
•
Single 2.7-3.3V Read and Write Operations
Concurrent Operation
•
•
Latched Address and Data for Flash
Flash Fast Erase and Word-Program:
– Read from or Write to SRAM while
Erase/Program Flash
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current:
- SST32HFx1C: 12 µA (typical)
Flexible Erase Capability
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
Flash Automatic Erase and Program Timing
– Internal VPP Generation
•
•
•
•
Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Package Available
•
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
– 48-ball LBGA (10mm x 12mm x 1.4mm)
PRODUCT DESCRIPTION
The SST32HF16xC/324C ComboMemory devices inte-
grate a CMOS flash memory bank with a CMOS SRAM
memory bank in a Multi-Chip Package (MCP), manufac-
tured with SST’s proprietary, high performance Super-
Flash technology.
selects the SRAM bank. The flash memory bank enable
signal, BEF# selects the flash memory bank. The WE# sig-
nal has to be used with Software Data Protection (SDP)
command sequence when controlling the Erase and Pro-
gram operations in the flash memory bank. The SDP com-
mand sequence protects the data stored in the flash
memory bank from accidental alteration.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. To protect against inadvertent flash write, the
SST32HF16xC/324C devices contain on-chip hardware
and software data protection schemes. The
SST32HF16xC/324C devices offer a guaranteed endur-
ance of 10,000 cycles. Data retention is rated at greater
than 100 years.
The SST32HF16xC/324C provide the added functionality
of being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST32HF16xC/324C devices consist of two indepen-
dent memory banks with respective bank enable signals.
The Flash and SRAM memory banks are superimposed in
the same memory address space. Both memory banks
share common address lines, data lines, WE# and OE#.
The memory bank selection is done by memory bank
enable signals. The SRAM bank enable signal, BES#
©2004 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71267-00-000
1
7/04
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
The SST32HF16xC/324C devices are suited for applica-
tions that use both flash memory and SRAM memory to
store code or data. For systems requiring low power and
small form factor, the SST32HF16xC/324C devices sig-
nificantly improve performance and reliability while lower-
ing power consumption when compared with multiple
chip solutions. The SST32HF16xC/324C inherently use
less energy during Erase and Program operations than
alternative flash technologies. The total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since, for any given voltage range,
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alterna-
tive flash technologies.
Concurrent Read/Write Operation
The SST32HF16xC/324C provide the unique benefit of
being able to read from or write to SRAM, while simulta-
neously erasing or programming the flash. This allows data
alteration code to be executed from SRAM, while altering
the data in flash. See Figure 21 for a flowchart. The follow-
ing table lists all valid states.
CONCURRENT READ/WRITE STATE TABLE
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
SuperFlash technology provides fixed Erase and Program
times independent of the number of Erase/Program cycles
that have occurred. Therefore the system software or hard-
ware does not have to be modified or de-rated as is neces-
sary with alternative flash technologies, whose Erase and
Program times increase with accumulated Erase/Program
cycles.
Flash Read Operation
The Read operation of the SST32HF16xC/324C devices
is controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when OE# is high. Refer to Figure 5 for
further details.
Device Operation
The ComboMemory uses BES# and BEF# to control oper-
ation of either the SRAM or the flash memory bank. When
BES# is low, the SRAM Bank is activated for Read and
Write operation. When BEF# is low the flash bank is acti-
vated for Read, Program or Erase operation. BES# and
BEF# cannot be at low level at the same time. If BES# and
BEF# are both asserted to low level bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by SRAM
Bank and flash bank which minimizes power consumption
and loading. The device goes into standby when both bank
enables are high.
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
2
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
Flash Word-Program Operation
Erase-Suspend/Erase-Resume Commands
The flash memory bank of the SST32HF16xC/324C
devices is programmed on a word-by-word basis. Before
Program operations, the memory must be erased first. The
Program operation consists of three steps. The first step is
the three-byte load sequence for Software Data Protection.
The second step is to load word address and word data.
During the Word-Program operation, the addresses are
latched on the falling edge of either BEF# or WE#, which-
ever occurs last. The data is latched on the rising edge of
either BEF# or WE#, whichever occurs last. The third step
is the internal Program operation which is initiated after the
rising edge of the fourth WE# or BEF#, whichever occurs
first. The Program operation, once initiated, will be com-
pleted, within 10 µs. See Figures 6 and 7 for WE# and
BEF# controlled Program operation timing diagrams and
Figure 17 for flowcharts. During the Program operation, the
only valid flash Read operations are Data# Polling and Tog-
gle Bit. During the internal Program operation, the host is
free to perform additional tasks. Any SDP commands
loaded during the internal Program operation will be
ignored.
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Flash Chip-Erase Operation
The SST32HF16xC/324C provide a Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the “1” state. This is useful when the entire device
must be quickly erased.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF16xC/324C offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines AMS-A11 are used to determine the sector address.
The Block-Erase operation is initiated by executing a six-
byte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines AMS-A15 are used to determine the block
address. The sector or block address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth
WE# pulse. The End-of-Erase operation can be deter-
mined using either Data# Polling or Toggle Bit methods.
See Figures 11 and 12 for timing waveforms. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or BEF#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 5 for the command sequence, Figure 9 for tim-
ing diagram, and Figure 20 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored.
Write Operation Status Detection
The SST32HF16xC/324C provide two software means to
detect the completion of a write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
3
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
TABLE 1: WRITE OPERATION STATUS
Status
DQ7 DQ6
DQ2
Normal
Standard
DQ7# Toggle No Toggle
Operation Program
Standard
Erase
0
1
Toggle
1
Toggle
Toggle
Erase-
Read from
Suspend Erase-Suspended
Mode
Sector/Block
Read from
Data
Data
Data
Non- Erase-Suspended
Sector/Block
Program
DQ7# Toggle
N/A
Flash Data# Polling (DQ7)
T1.0 1267
Note: DQ7 and DQ2 require a valid address when reading
When the SST32HF16xC/324C flash memory banks are
in the internal Program operation, any attempt to read DQ7
will produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles after an interval of 1 µs. During
internal Erase operation, any attempt to read DQ7 will pro-
duce a ‘0’. Once the internal Erase operation is completed,
DQ7 will produce a ‘1’. The Data# Polling is valid after the
rising edge of the fourth WE# (or BEF#) pulse for Program
operation. For Sector- or Block-Erase, the Data# Polling is
valid after the rising edge of the sixth WE# (or BEF#) pulse.
See Figure 8 for Data# Polling timing diagram and Figure
18 for a flowchart.
status information.
Flash Memory Data Protection
The SST32HF16xC/324C flash memory bank provides
both hardware and software features to protect nonvolatile
data from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Toggle Bits (DQ6 and DQ2)
Flash Software Data Protection (SDP)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or BEF#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
The SST32HF16xC/324C provide the JEDEC approved
software data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF16xC/324C devices are shipped with the soft-
ware data protection permanently enabled. See Table 5 for
the specific software command codes. During SDP com-
mand sequence, invalid commands will abort the device to
Read mode, within TRC. The contents of DQ15-DQ8 can be
VIL or VIH, but no other value, during any SDP command
sequence.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or
BEF#) pulse of Write operation. See Figure 9 for Toggle Bit
timing diagram and Figure 18 for a flowchart.
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
4
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
TABLE 2: PRODUCT IDENTIFICATION
SRAM Read
Address
Data
The SRAM Read operation of the SST32HF16xC/324C is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high.
Refer to the Read cycle timing diagram, Figure 2, for further
details.
Manufacturer’s ID
Device ID
0000H
BFH
SST32HF162C
SST32HF164C
SST32HF324C
0001H
0001H
0001H
234BH
234BH
235BH
T2.0 1267
Product Identification Mode Exit/Reset
SRAM Write
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
internal Program or Erase operation. This command may
also be used to reset the device to Read mode after any
inadvertent transient condition that apparently causes the
device to behave abnormally, e.g. not read correctly. See
Table 5 for software command codes, Figure 14 for timing
waveform and Figure 19 for a flowchart.
The SRAM Write operation of the SST32HF16xC/324C is
controlled by WE# and BES#; both have to be low for the
system to write to the SRAM. During the Word-Write oper-
ation, the addresses and data are referenced to the rising
edge of either BES# or WE#, whichever occurs first. The
Write time is measured from the last falling edge of BES#
or WE# to the first rising edge of BES# or WE#. Refer to
the Write cycle timing diagrams, Figures 3 and 4, for further
details.
Product Identification
The Product Identification mode identifies the devices as
the SST32HF16xC/324C and manufacturer as SST. This
mode may be accessed by software operations only.
The hardware device ID Read operation, which is typi-
cally used by programmers, cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, applica-
tion of high voltage to pin A9 may damage this device.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Tables 4 and 5 for software operation, Figure 13 for the
software ID entry and read timing diagram and Figure 19
for the ID entry command sequence flowchart.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
5
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
SRAM
UBS#
LBS#
BES#
BEF#
OE#
Control Logic
A
(1)-A
MS
DQ - DQ
15
8
0
I/O Buffers
DQ - DQ
7
0
WE#
Address Buffers
& Latches
SuperFlash
Memory
1267 B1.0
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
6
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
TOP VIEW (balls facing down)
TOP VIEW (balls facing down)
SST32HF324C
SST32HF162C/SST32HF164C
6
5
4
3
2
1
6
5
4
3
2
1
BES#
V
DQ1 A1
A2
A3
A4
A7
A19
NC A14
A15
BES#
V
DQ1 A1
A2
A3
A4
A7
A19
A20 A14
A15
SS
A9
SS
A9
A10 DQ5 DQ2 A0
OE# DQ7 DQ4 DQ0
A10 DQ5 DQ2 A0
OE# DQ7 DQ4 DQ0
A6 A18
A6 A18
NC
NC
A11 A8
A5 DQ8 DQ3 DQ12 A12 LBS#
A11 A8
A5 DQ8 DQ3 DQ12 A12 LBS#
A13 A17 UBS# BEF# DQ10
V
DQ6 DQ15
A13 A17 UBS# BEF# DQ10
V
DQ6 DQ15
DDF
DDF
WE#
V
A16
V
DQ9 DQ11 DQ13 DQ14
WE#
V
A16
V
SS
DQ9 DQ11 DQ13 DQ14
DDS
SS
DDS
A B C D E F G H
A B C D E F G H
FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM)
TABLE 3: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide flash addresses: A19-A0 for 16M and A20-A0 for 32M
SRAM addresses: A16-A0 for 2M and A17-A0 for 4M
DQ15-DQ0 Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
BES#
BEF#
OE#
WE#
VDDF
VDDS
VSS
SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low.
Flash Memory Bank Enable
Output Enable
To activate the flash memory bank when BEF# is low.
To gate the data output buffers.
Write Enable
To control the Write operations.
Power Supply (Flash)
Power Supply (SRAM)
Ground
2.7-3.3V Power Supply to flash only.
2.7-3.3V Power Supply to SRAM only
UBS#
LBS#
NC
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
No Connection
To enable DQ15-DQ8
To enable DQ7-DQ0
Unconnected Pins
T3.0 1267
1. AMS=Most significant address
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
7
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
TABLE 4: OPERATION MODES SELECTION
Mode
BES#1 BEF#1 OE# WE# UBS# LBS# DQ15 to DQ8 DQ7 to DQ0
Address
Not Allowed
Flash
VIL
VIL
X2
X
X
X
X
X
X
Read
VIH
VIH
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
X
X
X
X
X
X
DOUT
DIN
X
DOUT
DIN
X
AIN
AIN
Program
Erase
Sector or Block address,
XXH for Chip-Erase
SRAM
Read
VIL
VIL
VIL
VIL
VIL
VIL
VIHC
X
VIH
VIH
VIH
VIH
VIH
VIH
VIHC
X
VIL
VIL
VIL
X
VIH
VIH
VIH
VIL
VIL
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
VIL
VIH
VIL
VIL
VIH
VIL
X
DOUT
DOUT
High Z
DIN
DOUT
High Z
DOUT
DIN
AIN
AIN
AIN
AIN
AIN
AIN
X
Write
X
DIN
High Z
DIN
X
High Z
High Z
Standby
X
High Z
Flash Write Inhibit
VIL
X
X
X
X
High Z / DOUT High Z / DOUT
High Z / DOUT High Z / DOUT
High Z / DOUT High Z / DOUT
X
X
X
VIH
X
X
X
X
X
VIH
VIL
VIH
VIH
X
X
X
X
Output Disable
VIH
VIL
VIL
VIH
X
VIH
X
X
X
High Z
High Z
High Z
High Z
High Z
High Z
X
VIH
X
VIH
X
X
VIH
VIH
X
Product Identification
Software Mode
VIH
VIL
VIL
VIH
X
X
Manufacturer’s ID (00BFH)
Device ID3
A19-A1=VIL, A0=VIH
(See Table 4)
T4.0 1267
1. Do not apply BES#=VIL and BEF#=VIL at the same time
2. X can be VIL or VIH, but no other value.
3. With AMS-A1 = 0;
SST Manufacturer’s ID = 00BFH, is read with A0=0,
SST32HF16xC Device ID = 234BH, is read with A0=1,
SST32HF324C Device ID = 235BH, is read with A0=1
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
8
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
TABLE 5: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
WA3
Data
Word-Program
Sector-Erase
5555H
5555H
5555H
5555H
AAH 2AAAH 55H 5555H A0H
4
4
AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
BAX
30H
50H
Block-Erase
Chip-Erase
AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Erase-Suspend
Erase-Resume
Software ID Entry5,6
XXXXH B0H
XXXXH 30H
5555H
5555H
AAH 2AAAH 55H 5555H 90H
Software ID Exit7
/Sec ID Exit
AAH 2AAAH 55H 5555H F0H
Software ID Exit7
/Sec ID Exit
XXH
F0H
T5.0 1267
1. Address format A14-A0 (Hex).
Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST32HF16xC,
Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST32HF324C.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
A
A
MS = Most significant address
MS = A19 for SST32HF16xC and A20 for SST32HF324C.
5. The device does not remain in Software Product ID Mode if powered down.
6. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST32HF16xC Device ID = 234BH, is read with A0 = 1,
SST32HF324C Device ID = 235BH, is read with A0 = 1,
A
A
MS = Most significant address
MS = A19 for SST32HF16xC and A20 for SST32HF324C.
7. Both Software ID Exit operations are equivalent
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
9
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
2.7-3.3V
2.7-3.3V
-20°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 15 and 16
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
10
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
TABLE 6: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input = VILT/VIHT, at f=5 MHz,
IDD
Active VDD Current
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
18
30
40
mA
mA
mA
BEF#=VIL, BES#=VIH
BEF#=VIH, BES#=VIL
BEF#=VIH, BES#=VIL
WE#=VIL
SRAM
Concurrent Operation
Write1
Flash
35
30
30
1
mA
mA
µA
µA
µA
V
BEF#=VIL, BES#=VIH, OE#=VIH
BEF#=VIH, BES#=VIL
VDD = VDD Max, BEF#=BES#=VIHC
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
SRAM
ISB
Standby VDD Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input Low Voltage (CMOS)
Input High Voltage
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
SRAM Output Low Voltage
SRAM Output High Voltage
ILI
ILO
10
0.8
0.3
VIL
VILC
VIH
V
VDD=VDD Max
0.7 VDD
VDD-0.3
V
VDD=VDD Max
VIHC
VOLF
VOHF
VOLS
VOHS
V
VDD=VDD Max
0.2
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
IOL =1 mA, VDD=VDD Min
IOH =-500 µA, VDD=VDD Min
VDD-0.2
2.2
V
V
V
T6.0 1267
1. IDD active while Erase or Program is in progress.
TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
µs
µs
1
TPU-WRITE
100
T7.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
12 pF
1
CIN
VIN = 0V
T8.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: FLASH RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T9.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
11
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
AC CHARACTERISTICS
TABLE 10: SRAM READ CYCLE TIMING PARAMETERS
Symbol
TRCS
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TAAS
Address Access Time
70
70
35
70
ns
TBES
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES# to Active Output
ns
TOES
ns
TBYES
ns
1
TBLZS
0
0
0
ns
1
TOLZS
Output Enable to Active Output
UBS#, LBS# to Active Output
BES# to High-Z Output
ns
1
TBYLZS
ns
1
TBHZS
25
25
35
ns
1
TOHZS
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
0
ns
1
TBYHZS
ns
TOHS
10
ns
T10.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: SRAM WRITE CYCLE TIMING PARAMETERS
Symbol
TWCS
TBWS
TAWS
Parameter
Min
70
60
60
0
Max
Units
ns
Write Cycle Time
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
TASTS
TWPS
TWRS
TBYWS
TODWS
TOEWS
TDSS
ns
Write Pulse Width
60
0
ns
Write Recovery Time
ns
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
60
ns
30
ns
0
30
0
ns
ns
TDHS
Data Hold from Write Time
ns
T11.0 1267
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
12
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
TABLE 12: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
Symbol
TRC
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TCE
Chip Enable Access Time
Address Access Time
70
70
35
ns
TAA
ns
TOE
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
ns
1
TOLZ
ns
1
TCHZ
20
20
ns
1
TOHZ
ns
1
TOH
0
ns
T12.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
Parameter
Min
Max
Units
µs
Word-Program Time
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
10
TAS
0
30
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
ns
1
TWPH
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
TBE
Block-Erase
25
TSCE
Chip-Erase
50
ms
T13.0 1267
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
13
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
T
RCS
ADDRESSES A
MSS-0
T
T
T
OHS
AAS
T
BES#
BES
T
BLZS
BHZS
T
OES
OE#
T
OLZS
T
OHZS
T
BYES
UBS#, LBS#
T
BYLZS
T
BYHZS
DQ
15-0
DATA VALID
1267 F02.0
Note: AMSS = Most Significant SRAM Address
MSS = A16 for SST32HF162C and A17 for SST32HF164C or SST32HF324C
A
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
T
WCS
ADDRESSES
3
A
MSS -0
T
T
T
WRS
ASTS
WPS
WE#
T
AWS
T
BWS
BES#
T
BYWS
UBS#, LBS#
T
OEWS
T
ODWS
T
T
DSS
DHS
NOTE 2
NOTE 2
VALID DATA IN
DQ
DQ
7-0
15-8,
1267 F03.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.
If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
A
MSS = A16 for SST32HF162C and A17 for SST32HF164C or SST32HF324C
FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
14
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
T
WCS
ADDRESSES
3
A
MSS -0
T
WRS
T
WPS
WE#
T
BWS
BES#
T
AWS
T
T
BYWS
ASTS
UBS#, LBS#
T
T
DHS
DSS
NOTE 2
VALID DATA IN
NOTE 2
DQ
DQ
7-0
15-8,
1267 F04.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
A
MSS = A16 for SST32HF162C and A17 for SST32HF164C or SST32HF324C
FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
T
T
AA
RC
ADDRESS A
MS-0
BEF#
OE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1267 F05.0
Note: AMSF = Most Significant Flash Address
MSF = A19 for SST32HF16xC and A20 for SST32HF324C
A
FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
15
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
WP
WE#
T
T
AS
DS
T
WPH
OE#
T
CH
BEF#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1267 F06.0
Note: AMSF = Most Significant Flash Address
MSF = A19 for SST32HF16xC and A20 for SST32HF324C
X can be VIL or VIH, but no other value
A
FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
BEF#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
1267 F07.0
(ADDR/DATA)
Note: AMSF = Most Significant Flash Address
MSF = A19 for SST32HF16xC and A20 for SST32HF324C
X can be VIL or VIH, but no other value
A
FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
16
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
ADDRESSES A
MSF-0
BEF#
OE#
T
CE
T
OES
T
OEH
T
OE
WE#
Data
Data#
Data#
Data
DQ
7
1267 F08.0
Note: AMSF = Most Significant Flash Address
MSF = A19 for SST32HF16xC and A20 for SST32HF324C
A
FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM
ADDRESSES A
MSF-0
T
CE
BEF#
T
T
OE
T
OEH
OES
OE#
WE#
DQ and DQ
6
2
TWO READ CYCLES
WITH SAME OUTPUTS
1267 F09.0
Note: AMSF = Most Significant Flash Address
MSF = A19 for SST32HF16xC and A20 for SST32HF324C
A
FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
17
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
MS-0
BEF#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
1267 F10.0
Note: This device also supports BEF# controlled Chip-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13)
A
A
MSF = Most Significant Flash Address
MSF = A19 for SST32HF16xC and A20 for SST32HF324C
X can be VIL or VIH, but no other value.
FIGURE 10: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
5555
2AAA
5555
5555
2AAA
BA
ADDRESS A
X
MS-0
BEF#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
1267 F11.0
Note: AMSF = Most Significant Flash Address
MSF = A19 for SST32HF16xC and A20 for SST32HF324C
This device also supports BEF# controlled Block-Erase operation.
A
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.)
BAX = Block Address
X can be VIL or VIH, but no other value.
FIGURE 11: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
18
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555
2AAA
5555
5555
2AAA
SA
ADDRESS A
X
MS-0
BEF#
OE#
T
WP
WE#
DQ
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
15-0
1267 F12.0
Note: AMSF = Most Significant Flash Address
MSF = A19 for SST32HF16xC and A20 for SST32HF324C
This device also supports BEF# controlled Sector-Erase operation.
A
The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.)
SAX = Sector Address
X can be VIL or VIH, but no other value.
FIGURE 12: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
19
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
THREE-WORD SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
14-0
5555
2AAA
5555
0000
0001
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
DEVICE ID
1267 F13.0
MFG ID
Note: X can be VIL or VIH, but no other value.
Device ID - See Table 2 on page 5
FIGURE 13: SOFTWARE ID ENTRY AND READ
THREE-WORD SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
DQ
14-0
XXAA
XX55
XXF0
15-0
T
IDA
BEF#
OE#
T
WP
WE#
T
WHP
1267 F14.0
SW0
SW1
SW2
Note: X can be VIL or VIH, but no other value.
FIGURE 14: SOFTWARE ID EXIT AND RESET
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
20
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
V
IHT
V
V
IT
INPUT
REFERENCE POINTS
OUTPUT
OT
V
ILT
1267 F15.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 15: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1267 F16.0
FIGURE 16: A TEST LOAD EXAMPLE
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
21
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
Start
Write data: XXAAH
Address: 5555H
Write data: XX55H
Address: 2AAAH
Write data: XXA0H
Address: 5555H
Write Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1267 F17.0
Note: X can be V or V , but no other value
IL
IH
FIGURE 17: WORD-PROGRAM ALGORITHM
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
22
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
SCE, or BE
,
BP
T
T
No
Read same
word
Is DQ =
7
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
1267 F18.0
FIGURE 18: WAIT OPTIONS
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
23
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
Software Product ID Entry
Command Sequence
Software Product ID Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait T
IDA
Load data: XXF0H
Address: 5555H
Return to normal
operation
Load data: XX90H
Address: 5555H
Wait T
IDA
Wait T
IDA
Return to normal
operation
Read Software ID
1267 F19.0
X can be V or V but no other value
IL
IH,
FIGURE 19: SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
24
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1267 F20.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 20: ERASE COMMAND SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
25
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
Concurrent
Operation
Load SDP
Command
Sequence
Flash
Program/Erase
Initiated
Wait for End of
Write Indication
Read or Write
SRAM
End
Wait
Flash Operation
Completed
End Concurrent
Operation
1267 F21.0
FIGURE 21: CONCURRENT OPERATION FLOWCHART
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
26
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST32HFxxxC - XXX
-
XX
-
XXXX
Package Attribute
E = non-Pb
Package Modifier
K = 48 leads or balls
Package Type
LB = LBGA (10mm x 12mm x 1.4mm)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Density
162 = 16 Mbit Flash + 2 Mbit SRAM
164 = 16 Mbit Flash + 4 Mbit SRAM
324 = 32 Mbit Flash + 4 Mbit SRAM
Voltage
H = 2.7-3.3V
Product Series
32 = MPF + SRAM ComboMemory
Valid combinations for SST32HF162C
SST32HF162C-70-4C-LBK
SST32HF162C-70-4C-LBKE
SST32HF162C-70-4E-LBK
SST32HF162C-70-4E-LBKE
Valid combinations for SST32HF164C
SST32HF164C-70-4C-LBK
SST32HF164C-70-4C-LBKE
SST32HF164C-70-4E-LBK
SST32HF164C-70-4E-LBKE
Valid combinations for SST32HF324C
SST32HF324C-70-4C-LBK
SST32HF324C-70-4C-LBKE
SST32HF324C-70-4E-LBK
SST32HF324C-70-4E-LBKE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
27
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF162C / SST32HF164C / SST32HF324C
Preliminary Specifications
PACKAGING DIAGRAMS
TOP VIEW
12.00 0.20
BOTTOM VIEW
7.0
1.0
6
5
4
3
2
1
6
5
5.0
4
10.00 0.20
3
2
1
1.0
0.50 0.05
(48X)
H
G
F
E
D
C
B
A
A
B
C
D
E
F
G
H
A1 CORNER
A1 CORNER
1.4 Max
SIDE VIEW
0.12
SEATING PLANE
1mm
0.40 0.05
Note:
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
48-lbga-LBK-10x12-500mic-2
4. Ball opening size is 0.4 mm ( 0.05 mm)
48-BALL LOW-PROFILE BALL GRID ARRAY (LBGA) 10MM X 12MM
SST PACKAGE CODE: LBK
TABLE 14: REVISION HISTORY
Number
Description
Date
00
Jul 2004
•
Initial Release
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2004 Silicon Storage Technology, Inc.
S71267-00-000
7/04
28
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