SST32HF324-70-4C-LS [SILICON]
Memory Circuit, 2MX16, CMOS, PBGA62, 8 X 10 MM, 1.40 MM HEIGHT, LFBGA-62;
| 型号： | SST32HF324-70-4C-LS |
| 厂家： | 
SILICON |
| 描述： | Memory Circuit, 2MX16, CMOS, PBGA62, 8 X 10 MM, 1.40 MM HEIGHT, LFBGA-62 静态存储器 内存集成电路 |
| 文件： | 总34页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
SST32HF324 / 32832Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM
Preliminary Specifications
(x16) MCP ComboMemories
FEATURES:
•
ComboMemories organized as:
•
Fast Read Access Times:
– SST32HF324x: 2M x16 Flash + 256K x16 SRAM
– SST32HF328x: 2M x16 Flash + 512K x16 SRAM
– Flash: 70 ns and 90 ns
– SRAM: 70 ns and 90 ns
•
•
Single 2.7-3.3V Read and Write Operations
Concurrent Operation
•
•
Latched Address and Data for Flash
Flash Fast Erase and Word-Program:
– Read from or Write to SRAM while
Erase/Program Flash
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
– Chip Rewrite Time:
SST32HF32x/32xC: 15 seconds (typical)
Flash Automatic Erase and Program Timing
– Internal VPP Generation
•
•
Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or SRAM Read
•
•
Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
– Standby Current:
- SST32HF32x: 80 µA (typical)
- SST32HF32xC: 25 µA (typical)
•
Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Package Available
– 63-ball TFBGA (8mm x 10mm x 1.2mm)
– 63-ball LFBGA (8mm x 10mm x 1.4mm)
– 62-ball LFBGA (8mm x 10mm x 1.4mm)
PRODUCT DESCRIPTION
The SST32HF32x/32xC ComboMemory devices integrate
a 2M x16 CMOS flash memory bank with a 256K x16 or
512K x16 CMOS SRAM memory bank in a Multi-Chip
Package (MCP), manufactured with SST’s proprietary, high
performance SuperFlash technology. The SST32HF32x
devices use a Pseudo-SRAM. The SST32HF32xC devices
use standard SRAM.
share common address lines, data lines, WE# and OE#.
The memory bank selection is done by memory bank
enable signals. The memory bank selection is done by two
bank enable signals. The SRAM bank enable signals,
BES1# and BES2, select the SRAM bank. The flash mem-
ory bank enable signal, BEF#, has to be used with Soft-
ware Data Protection (SDP) command sequence when
controlling the Erase and Program operations in the flash
memory bank.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. The entire flash memory bank can be erased and
programmed word-by-word in typically 15 seconds for the
SST32HF32x/32xC, when using interface features such as
Toggle Bit or Data# Polling to indicate the completion of
Program operation. To protect against inadvertent flash
write, the SST32HF32x/32xC devices contain on-chip
hardware and software data protection schemes. The
SST32HF32x/32xC devices offer a guaranteed endurance
of 10,000 cycles. Data retention is rated at greater than
100 years.
The SST32HF32x/32xC provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
The SST32HF32x/32xC devices consist of two indepen-
dent memory banks with respective bank enable signals.
The Flash and SRAM memory banks are superimposed in
the same memory address space. Both memory banks
©2003 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.
MPF (Multi-Purpose Flash) and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71230-00-000
1
7/03
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
The SST32HF32x/32xC devices are suited for applications
that use both flash memory and SRAM memory to store
code or data. For systems requiring low power and small
form factor, the SST32HF32x/32xC devices significantly
improve performance and reliability, while lowering power
consumption, when compared with multiple chip solutions.
The SST32HF32x/32xC inherently use less energy during
erase and program than alternative flash technologies. The
total energy consumed is a function of the applied voltage,
current, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash technologies.
Concurrent Read/Write Operation
The SST32HF32x/32xC provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in flash. See Figure 23 for a flowchart. The following
table lists all valid states.
CONCURRENT READ/WRITE STATES
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
Flash Read
The Read operation of the SST32HF32x/32xC devices is
controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when OE# is high. Refer to Figure 6 for
further details.
Device Operation
The SST32HF32x/32xC use BES1#, BES2 and BEF# to
control operation of either the flash or the SRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the SRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time. If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
SRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to VIHC (Logic High) or
when BEF# is high and BES2 is low.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
2
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Flash Word-Program Operation
Flash Chip-Erase Operation
The flash memory bank of the SST32HF32x/32xC devices
is programmed on a word-by-word basis. Before Program
operations, the memory must be erased first. The Program
operation consists of three steps. The first step is the three-
byte load sequence for Software Data Protection. The sec-
ond step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either BEF# or WE#, whichever occurs last.
The data is latched on the rising edge of either BEF# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or BEF#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed, within 10
µs. See Figures 7 and 8 for WE# and BEF# controlled Pro-
gram operation timing diagrams and Figure 19 for flow-
charts. During the Program operation, the only valid flash
Read operations are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform
additional tasks. Any SDP commands loaded during the
internal Program operation will be ignored.
The SST32HF32x/32xC provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 4 for the command sequence, Figure 9 for tim-
ing diagram, and Figure 22 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored.
Flash Write Operation Status Detection
The SST32HF32x/32xC provide one hardware and two
software means to detect the completion of a Write (Pro-
gram or Erase) cycle, in order to optimize the system
Write cycle time. The software detection includes two
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6).
The End-of-Write detection mode is enabled after the ris-
ing edge of WE#, which initiates the internal Program or
Erase operation.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF32x/32xC offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A20-A11 are used to determine the sector address.
The Block-Erase operation is initiated by executing a six-
byte command sequence with Block-Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A20-A15 are used to determine the block
address. The sector or block address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth
WE# pulse. The End-of-Erase operation can be deter-
mined using either Data# Polling or Toggle Bit methods.
See Figures 12 and 13 for timing waveforms. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling
(DQ7) or Toggle Bit (DQ6) Read may be simultaneous with
the completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
3
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Flash Data# Polling (DQ7)
Flash Software Data Protection (SDP)
When the SST32HF32x/32xC flash memory banks are in
the internal Program operation, any attempt to read DQ7
will produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles after an interval of 1 µs. During
internal Erase operation, any attempt to read DQ7 will pro-
duce a ‘0’. Once the internal Erase operation is completed,
DQ7 will produce a ‘1’. The Data# Polling is valid after the
rising edge of the fourth WE# (or BEF#) pulse for Program
operation. For Sector- or Block-Erase, the Data# Polling is
valid after the rising edge of the sixth WE# (or BEF#) pulse.
See Figure 9 for Data# Polling timing diagram and Figure
20 for a flowchart.
The SST32HF32x/32xC provide the JEDEC approved
software data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF32x/32xC devices are shipped with the software
data protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode, within TRC. The contents of DQ15-DQ8 can be VIL or
VIH, but no other value, during any SDP command
sequence.
Concurrent Read and Write Operations
Flash Toggle Bit (DQ6)
The SST32HF32x/32xC provide the unique benefit of being
able to read from or write to SRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from SRAM, while altering the
data in flash. The following table lists all valid states.
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BEF#) pulse for Program operation. For
Sector- or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 10 for
Toggle Bit timing diagram and Figure 20 for a flowchart.
CONCURRENT READ/WRITE STATES
Flash
Program/Erase
Program/Erase
SRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Memory Data Protection
The SST32HF32x/32xC flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the flash Write operation. This prevents
inadvertent writes during power-up or power-down.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
4
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Product Identification
SRAM Read
The Product Identification mode identifies the devices as
the SST32HFxxx and manufacturer as SST. This mode
may be accessed by software operations only. The
hardware device ID Read operation, which is typically
used by programmers, cannot be used on this device
because of the shared lines between flash and SRAM
in the multi-chip package. Therefore, application of
high voltage to pin A9 may damage this device. Users
may use the software Product Identification operation to
identify the part (i.e., using the device ID) when using multi-
ple manufacturers in the same socket. For details, see
Tables 3 and 4 for software operation, Figure 14 for the
software ID entry and read timing diagram and Figure 21
for the ID entry command sequence flowchart.
The SRAM Read operation of the SST32HF32x/32xC is
controlled by OE# and BES1#, both have to be low with
WE# and BES2 high for the system to obtain data from the
outputs. BES1# and BES2 are used for SRAM bank selec-
tion. OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when OE# is high. Refer to the Read cycle timing diagram,
Figure 3, for further details.
SRAM Write
The SRAM Write operation of the SST32HF32x/32xC is
controlled by WE# and BES1#, both have to be low, BES2
must be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagrams, Figures 4 and 5, for further details.
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
0000H
00BFH
SST32HF32x/32xC
0001H
2783H
T1.0 1230
Design Considerations
Product Identification Mode Exit/Reset
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
internal Program or Erase operation. This command may
also be used to reset the device to Read mode after any
inadvertent transient condition that apparently causes the
device to behave abnormally, e.g. not read correctly. See
Table 4 for software command codes, Figure 15 for timing
waveform, and Figure 21 for the Software ID Entry com-
mand sequence flowchart.
SRAM Operation
With BES1# low, BES2 and BEF# high, the
SST32HF32x/32xC operate as either 256K x16 or 512K
x16 CMOS SRAM, with fully static operation requiring no
external clocks or timing strobes. The SST32HF32x/32xC
SRAM is mapped into the first 512 KWord address
space. When BES1#, BEF# are high and BES2 is low, all
memory banks are deselected and the device enters
standby. Read and Write cycle times are equal. The con-
trol signals UBS# and LBS# provide access to the upper
data byte and lower data byte. See Table 3 for SRAM
Read and Write data byte control modes of operation.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
5
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
FUNCTIONAL BLOCK DIAGRAM
SRAM/
PSRAM
Address Buffers
UBS#
LBS#
BES1#
BES2
BEF#
Control Logic
DQ - DQ
A
-A
0
15
8
MS
I/O Buffers
DQ - DQ
7
0
OE#1
WE#1
Address Buffers
& Latches
SuperFlash
Memory
1230 B1.2
Notes: 1. For LS package only: WE# = WEF# and/or WES#
OE# = OEF# and/or OES#
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
6
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
TOP VIEW (balls facing down)
8
7
6
5
4
3
2
1
NC
A20 A11 A15 A14 A13 A12
V
NC
NC
SSF
A16
A8
A10
A9 DQ15 WES# DQ14 DQ7
DQ13 DQ6 DQ4 DQ5
WEF# NC
V
NC
NC
DQ12 BES2 V
V
DDS DDF
SSS
NC
A19 DQ11
DQ10 DQ2 DQ3
LBS# UBS# OES#
DQ9 DQ8 DQ0 DQ1
A18 A17
NC A5
A7
A4
A6
A3
A2
A1 BES1#
OEF# NC NC
NC
A0 BEF#
V
SSF
A B C D E F G H J K
FIGURE 1: PIN ASSIGNMENTS FOR 62-BALL TFBGA AND LFBGA (8MM X 10MM) INTEL COMPATIBLE PACKAGE
TOP VIEW (balls facing down)
8
NC
NC
A15
A11 A12 A13 A14
A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5
WE# BES2 A20
NC NC NC
NC
NC
A16
NC
V
NC
SS
7
6
5
4
3
2
1
NC DQ15 DQ7 DQ14 NC
DQ4
DQ3
V
V
NC
DDS
DQ11
DDF
LBS# UBS# A18 A17 DQ1 DQ9 DQ10 DQ2
A7
A6
A3
A5
A2
A4
A1
V
OE# DQ0 DQ8 NC
SS
NC
A0 BEF# BES1# NC
A B C D E F G H J K
FIGURE 2: PIN ASSIGNMENTS FOR 63-BALL TFBGA AND LFBGA (8MM X 10MM)
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
7
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1 to A0 Address Inputs
To provide flash address, AMSF-A0.
To provide SRAM address, AMSS-A0
DQ15-DQ0 Data Inputs/Outputs
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle. The outputs are in
tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.
BEF#
BES1#
BES2
OEF#2
OES#2
WEF#2
WES#2
OE#
Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low
SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low
SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high
Output Enable
Output Enable
Write Enable
Write Enable
Output Enable
Write Enable
To gate the data output buffers for Flash2 only
To gate the data output buffers for SRAM2 only
To control the Write operations for Flash2 only
To control the Write operations for SRAM2 only
To gate the data output buffers
WE#
To control the Write operations
UBS#
LBS#
Upper Byte Control (SRAM) To enable DQ15-DQ8
Lower Byte Control (SRAM) To enable DQ7-DQ0
2
VSSF
Ground
Flash2 only
SRAM2 only
2
VSSS
Ground
VSS
Ground
VDD
Power Supply (Flash)
Power Supply (SRAM)
No Connection
2.7-3.3V Power Supply to Flash only
2.7-3.3V Power Supply to SRAM only
Unconnected pins
F
VDDS
NC
T2.0 1230
1. AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
AMSS = Most Significant SRAM Address
MSS = A17 for SST32HF324x and A18 for SST32HF328x
A
A
2. LS package only
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
8
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
1
TABLE 3: OPERATIONAL MODES SELECTION
Mode
BEF#
BES1#
VIH
X
BES22
OE#3
X
WE#3
X
LBS#
X
UBS#
DQ0-7
DQ8-15
Full Standby
VIH
X
X
X
HIGH-Z
HIGH-Z
VIL
VIH
VIH
X
X
X
X
Output Disable
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIH
X
VIH
X
VIH
X
X
X
HIGH-Z
HIGH-Z
DOUT
DIN
HIGH-Z
HIGH-Z
DOUT
DIN
VIH
X
VIH
X
VIH
VIH
VIL
X
Flash Read
Flash Write
Flash Erase
SRAM Read
VIH
X
VIL
VIH
VIH
VIL
VIH
VIL
VIL
VIH
X
X
X
X
X
X
VIL
X
VIH
X
VIL
X
VIH
X
X
X
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
DOUT
HIGH-Z
DOUT
DIN
DOUT
DOUT
HIGH-Z
DIN
SRAM Write
VIH
VIL
VIH
X
VIL
HIGH-Z
DIN
DIN
HIGH-Z
Product
VIL
VIH
X
X
VIL
VIH
Manufacturer’s ID5
Identification4
Device ID5
VIL
T3.0 1230
1. X can be VIL or VIH, but no other value.
2. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time
3. OE# = OEF# and OES#
WE# = WEF# and WES# for LS package only
4. Software mode only
5. With AMS-A1 = 0;SST Manufacturer’s ID = 00BFH, is read with A0=0,
SST32HF32xx Device ID = 2783H, is read with A0=1.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
9
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
5555H AAH 2AAAH 55H 5555H A0H Data
WA3
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
BAX
30H
50H
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H
Software ID Exit
Software ID Exit
XXH
F0H
5555H AAH 2AAAH 55H 5555H F0H
T4.0 1230
1. Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence.
3. WA = Program word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX for Block-Erase; uses A20-A15 address lines
AMS = Most significant address
AMS = A20 for SST32HF32x/32xC
5. The device does not remain in Software Product ID mode if powered down.
6. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0=0,
SST32HF32x/32xC Device ID = 2783H, is read with A0=1.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
10
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
2.7-3.3V
2.7-3.3V
-20°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 17 and 18
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
11
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
TABLE 5: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits
Symbol Parameter
IDD Active VDD Current
Min
Max Units Test Conditions
Address input = VILT/VIHT, at f=1/TRC Min,
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
18
30
40
mA BEF#=VIL, BES1#=VIH, or BES2=VIL
mA BEF#=VIH, BES1#=VIL , BES2=VIH
mA BEF#=VIH, BES1#=VIL , BES2=VIH
WE#=VIL
SRAM
Concurrent Operation
Write1
Flash
35
30
mA BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH
mA BEF#=VIH, BES1#=VIL , BES2=VIH
SRAM
ISB
Standby VDD Current SST32HF32x
SST32HF32xC
110
45
µA
µA
VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VILC
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
10
VIL
0.8
0.3
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7 VDD
VDD-0.3
V
VDD=VDD Max
VIHC
VOLF
VOHF
VOLS
VOHS
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
SRAM Output Low Voltage
SRAM Output High Voltage
V
VDD=VDD Max
0.2
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
IOL =1 mA, VDD=VDD Min
VDD-0.2
2.2
V
V
V
IOH =-500 µA, VDD=VDD Min
T5.0 1230
1. IDD active while Erase or Program is in progress.
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T6.0 1230
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
12 pF
1
CIN
VIN = 0V
T7.0 1230
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: FLASH RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T8.0 1230
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
12
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
AC CHARACTERISTICS
TABLE 9: SRAM READ CYCLE TIMING PARAMETERS
SST32HFx1/x1C-70
SST32HFx1/x1C-90
Symbol Parameter
Min
Max
Min
Max
Units
ns
TRCS
TAAS
TBES
TOES
TBYES
Read Cycle Time
70
90
Address Access Time
70
70
35
70
90
90
45
90
ns
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES# to Active Output
ns
ns
ns
1
TBLZS
TOLZS
0
0
0
0
0
0
ns
1
Output Enable to Active Output
UBS#, LBS# to Active Output
BES# to High-Z Output
ns
1
TBYLZS
ns
1
TBHZS
25
25
35
35
35
45
ns
1
TOHZS
TBYHZS
TOHS
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
0
0
ns
1
ns
10
10
ns
T9.0 1230
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS
SST32HFx1/x1C-70
SST32HFx1/x1C-90
Symbol Parameter
Min
70
60
60
0
Max
Min
90
80
80
0
Max
Units
ns
TWCS
TBWS
TAWS
Write Cycle Time
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
TASTS
TWPS
TWRS
TBYWS
TODWS
TOEWS
TDSS
ns
Write Pulse Width
60
0
80
0
ns
Write Recovery Time
ns
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
60
80
ns
30
40
ns
0
30
0
0
40
0
ns
ns
TDHS
Data Hold from Write Time
ns
T10.0 1230
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
13
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
TABLE 11: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
SST32HFx1/x1C-70
SST32HFx1/x1C-90
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
90
TCE
Chip Enable Access Time
Address Access Time
70
70
35
90
90
45
ns
TAA
ns
TOE
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TBLZ
0
0
0
0
ns
1
TOLZ
ns
1
TBHZ
20
20
30
30
ns
1
TOHZ
ns
1
TOH
0
0
ns
T11.0 1230
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter
Min
Max
Units
µs
TBP
Word-Program Time
10
TAS
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
0
30
0
ns
TAH
ns
TBS
ns
TBH
TOES
TOEH
TBP
0
ns
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
TWPH
ns
1
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
ns
1
TBPH
TDS
ns
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
TBE
Block-Erase
25
TSCE
Chip-Erase
50
ms
T12.0 1230
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
14
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
T
RCS
ADDRESSES A
MSS-0
T
OHS
T
AAS
T
BES1#
BES2
BES
T
BES
T
BLZS
T
BHZS
T
OES
OE#
T
OLZS
T
OHZS
T
BYES
UBS#, LBS#
T
BYLZS
T
BYHZS
DQ
15-0
DATA VALID
1230 F03.1
Note: AMSS = Most Significant SRAM Address
MSS = A17 for SST32HF324x and A18 for SST32HF328x
A
FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
15
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
T
WCS
3
ADDRESSES A
MSS -0
T
ASTS
T
WPS
T
WRS
WE#
T
AWS
T
BWS
BES1#
BES2
T
BWS
T
BYWS
UBS#, LBS#
T
OEWS
T
ODWS
T
DHS
T
DSS
NOTE 2
NOTE 2
VALID DATA IN
DQ
DQ
7-0
15-8,
1230 F04.1
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.
If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
AMSS = A17 for SST32HF324xx and A18 for SST32HF328x
FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
16
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
T
WCS
3
ADDRESSES A
MSS -0
T
WPS
T
WRS
WE#
T
BWS
BES1#
BES2
T
BWS
T
AWS
T
T
ASTS
BYWS
UBS#, LBS#
T
DSS
T
DHS
VALID DATA IN
NOTE 2
NOTE 2
DQ
DQ
7-0
15-8,
1236 F05.1
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
AMSS = A17 for SST32HF324x and A18 for SST32HF328x
FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
17
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
T
T
AA
RC
ADDRESSES A
MSF-0
BEF#
OE#
T
BE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
BHZ
T
OH
T
HIGH-Z
BLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1230 F06.1
Note: AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
A
FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESSES A
MSF-0
T
AH
T
DH
T
WP
WE#
T
AS
T
DS
T
WPH
OE#
T
CH
BEF#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1230 F07.0
Note: AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
A
FIGURE 7: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
18
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESSES A
MSF-0
T
AH
T
DH
T
CP
BEF#
T
AS
T
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1230 F08.0
Note: AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
A
FIGURE 8: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
ADDRESSES A
MSF-0
T
BE
BEF#
OE#
T
OES
T
OEH
T
OE
WE#
Data
Data#
Data#
Data
DQ
7
1230 F09.1
Note: AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
A
FIGURE 9: FLASH DATA# POLLING TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
19
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
ADDRESSES A
MSF-0
T
BE
BEF#
OE#
T
OES
T
T
OE
OEH
WE#
DQ and DQ
6
2
TWO READ CYCLES
WITH SAME OUTPUTS
1230 F10.1
Note: AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
A
FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
MSF-0
BEF#
OE#
WE#
T
WP
D
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
1230 F11.0
Note: AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
This device also supports BEF# controlled Chip-Erase operation.
A
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 12.)
X can be VIL or VIH, but no other value.
FIGURE 11: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
20
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
T
SBE
SIX-WORD CODE FOR BLOCK-ERASE
5555 5555 2AAA
5555
2AAA
BA
X
ADDRESSES A
MSF-0
BEF#
OE#
WE#
T
WP
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
D
15-0
1230 F12.0
Note: AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
This device also supports BEF# controlled Block-Erase operation.
A
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 12.)
BAX = Block Address
X can be VIL or VIH, but no other value.
FIGURE 12: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM
T
SE
SIX-WORD CODE FOR SECTOR-ERASE
5555
2AAA
5555
5555
2AAA
SA
X
ADDRESSES A
MSF-0
BEF#
OE#
WE#
T
WP
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
DQ
15-0
1230 F13.0
Note: AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
This device also supports BEF# controlled Sector-Erase operation.
A
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 12.)
SAX = Sector Address
X can be VIL or VIH, but no other value.
FIGURE 13: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
21
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
THREE-WORD SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
14-0
5555
2AAA
5555
0000
0001
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
DEVICE ID
1230 F14.1
MFG ID
Note: X can be VIL or VIH, but no other value.
Device ID - See Table 1 on page 5
FIGURE 14: SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
XX55
SW1
T
AA
DQ
15-0
XXAA
SW0
XX90
SW2
00BF
Device ID
1230 F16.1
Note: X can be VIL or VIH, but no other value.
Device ID - See Table 1 on page 5
FIGURE 15: SOFTWARE ID
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
22
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
ADDRESS A
5555
2AAA
5555
MSF-0
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX88
SW2
1230 F17.1
Note: AMSF = Most Significant Flash Address
MSF = A20 for SST32HF32xx
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 16: FLASH SEC ID ENTRY
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
23
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1230 F20.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1230 F21.0
FIGURE 18: A TEST LOAD EXAMPLE
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
24
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Start
Write data: XXAAH
Address: 5555H
Write data: XX55H
Address: 2AAAH
Write data: XXA0H
Address: 5555H
Write Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1230 F22.0
Note: X can be V or V , but no other value
IL
IH
FIGURE 19: WORD-PROGRAM ALGORITHM
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
25
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
SCE, or BE
,
BP
T
T
No
Read same
word
Is DQ =
7
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
1230 F23.0
FIGURE 20: WAIT OPTIONS
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
26
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Software ID Entry
Command Sequence
Software ID Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait T
IDA
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait T
Wait T
IDA
IDA
Return to normal
operation
Read Software ID
1230 F24.1
X can be V or V , but no other value
IL IH
FIGURE 21: SOFTWARE ID COMMAND SEQUENCE
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
27
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1230 F25.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 22: ERASE COMMAND SEQUENCE
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
28
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Concurrent
Operation
Load SDP
Command
Sequence
Flash
Program/Erase
Initiated
Wait for End of
Write Indication
Read or Write
SRAM
End
Wait
Flash Operation
Completed
End Concurrent
Operation
1230 F26.0
FIGURE 23: CONCURRENT OPERATION FLOWCHART
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
29
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
XX
SST32HFxxxC - XXX
-
XX
-
Package Modifier
FS = 63 balls
S = 62 balls
Package Type
B = TFBGA (8mm x 10mm x 1.2mm, 0.40mm ball size)
L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Device
Blank = Pseudo-SRAM
C = Standard SRAM
SRAM Density1
4 = 4 Mbit
8 = 8 Mbit
Flash Density
32 = 32 Mbit
Voltage
H = 2.7-3.3V
Device Family
32 = Multi-Purpose Flash + SRAM ComboMemory
1. No SRAM and 2 Mbit SRAM options not currently planned.
However, if business conditions merit, these devices could
go into production. Contact your SST sales representative
for availability.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
30
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
Valid combinations for SST32HF324
SST32HF324-70-4C-BFS SST32HF324-70-4C-LS
SST32HF324-90-4C-BFS SST32HF324-90-4C-LS
SST32HF324-70-4C-LFS
SST32HF324-90-4C-LFS
SST32HF324-70-4E-BFS SST32HF324-70-4E-LS
SST32HF324-90-4E-BFS SST32HF324-90-4E-LS
SST32HF324-70-4E-LFS
SST32HF324-90-4E-LFS
Valid combinations for SST32HF324C
SST32HF324C-70-4C-BFS SST32HF324C-70-4C-LS
SST32HF324C-90-4C-BFS SST32HF324C-90-4C-LS
SST32HF324C-70-4C-LFS
SST32HF324C-90-4C-LFS
SST32HF324C-70-4E-BFS SST32HF324C-70-4E-LS
SST32HF324C-90-4E-BFS SST32HF324C-90-4E-LS
SST32HF324C-70-4E-LFS
SST32HF324C-90-4E-LFS
Valid combinations for SST32HF328
SST32HF328-70-4C-BFS SST32HF328-70-4C-LS
SST32HF328-90-4C-BFS SST32HF328-90-4C-LS
SST32HF328-70-4C-LFS
SST32HF328-90-4C-LFS
SST32HF328-70-4E-BFS SST32HF328-70-4E-LS
SST32HF328-90-4E-BFS SST32HF328-90-4E-LS
SST32HF328-70-4E-LFS
SST32HF328-90-4E-LFS
Valid combinations for SST32HF328C
SST32HF328C-70-4C-BFS SST32HF328C-70-4C-LS
SST32HF328C-90-4C-BFS SST32HF328C-90-4C-LS
SST32HF328C-70-4C-LFS
SST32HF328C-90-4C-LFS
SST32HF328C-70-4E-BFS SST32HF328C-70-4E-LS
SST32HF328C-90-4E-BFS SST32HF328C-90-4E-LS
SST32HF328C-70-4E-LFS
SST32HF328C-90-4E-LFS
Note: Valid combinations are those products in mass production or will be in mass production.
A BGA package with a height of 1.2mm is not currently planned. However, if business conditions merit, these devices
could go into production. Consult your SST sales representative to confirm availability of valid combinations and to
determine availability of new combinations.
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
31
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
PACKAGING DIAGRAMS
TOP VIEW
10.0 0.1
BOTTOM VIEW
7.20
0.80
8
7
6
5
4
3
2
1
8
7
6
5
8.0 0.1
4
5.60
3
2
1
0.40 0.05
(63X)
0.80
A
B
C
D
E
F
G
H
J
K
K J H G F E D C B A
A1 CORNER
A1 CORNER
1.2 max
SIDE VIEW
0.12
SEATING PLANE
63-tfbga-BFS-8x10-400mic-0
1mm
0.32 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
63-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM
SST PACKAGE CODE: BFS
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
32
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
BOTTOM VIEW
10.00 0.20
TOP VIEW
7.20
0.80
8
7
6
5
8
7
6
5
4
3
2
1
8.00 0.20
5.60
4
3
2
1
0.40 0.05
(62X)
0.80
A
B
C
D
E
F
G
H
J
K
K J H G F E D C B A
A1 CORNER
A1 CORNER
1.30 0.10
SIDE VIEW
0.12
SEATING PLANE
62-lfbga-LS-8x10-400mic-3
1mm
0.32 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
62-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM
SST PACKAGE CODE: LS
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
33
Multi-Purpose Flash + SRAM ComboMemory
SST32HF324 / SST32HF328
SST32HF324C / SST32HF328C
Preliminary Specifications
TOP VIEW
BOTTOM VIEW
7.20
0.80
10.0 0.1
8
7
6
5
4
3
2
1
8
7
6
5
8.0 0.1
4
5.60
3
2
1
0.40 0.05
(63X)
0.80
A
B
C
D
E
F
G
H
J
K
K J H G F E D C B A
A1 CORNER
A1 CORNER
1.3 0.1
SIDE VIEW
0.12
SEATING PLANE
63-lfbga-LFS-8x10-400mic-0
1mm
0.32 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,
this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size: 0.32 mm
63-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM
SST PACKAGE CODE: LFS
TABLE 13: REVISION HISTORY
Number
Description
Date
Jul 2003
00
•
Initial Release
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2003 Silicon Storage Technology, Inc.
S71230-00-000
7/03
34
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