SST32HF64B1-70-4E-L2SE [SILICON]
Memory Circuit, 4MX16, CMOS, PBGA64, 8 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LFBGA-64;
| 型号： | SST32HF64B1-70-4E-L2SE |
| 厂家： | 
SILICON |
| 描述： | Memory Circuit, 4MX16, CMOS, PBGA64, 8 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LFBGA-64 静态存储器 内存集成电路 |
| 文件： | 总38页 (文件大小：428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
SST32HF64A1 / 64B164Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM
Preliminary Specifications
(x16) MCP ComboMemories
FEATURES:
•
ComboMemories organized as:
•
Hardware Block-Protection/WP# Input Pin
– SST32HF64Ax: 4M x16 Flash + 1024K x16 PSRAM
– SST32HF64Bx: 4M x16 Flash + 2048K x16 PSRAM
– Bottom Block-Protection (bottom 32 KWord)
for SST32HF64x1
– Top Block-Protection (top 32 KWord)
for SST32HF64x2
Latched Address and Data for Flash
Flash Fast Erase and Word-Program:
•
•
Single 2.7-3.3V Read and Write Operations
Concurrent Operation
– Read from or Write to PSRAM while
Erase/Program Flash
•
•
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
Flash Automatic Erase and Program Timing
– Internal VPP Generation
•
•
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or PSRAM Read
•
•
Flash End-of-Write Detection
– Standby Current: 60 µA (typical)
– Toggle Bit
– Data# Polling
CMOS I/O Compatibility
JEDEC Standard Command Set
Package Available
•
Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
Erase-Suspend/Erase-Resume Capabilities
Security-ID Feature
•
•
•
•
•
– 64-ball LFBGA (8mm x 10mm x 1.4mm)
All non-Pb (lead-free) devices are RoHS compliant
– SST: 128 bits; User: 128 bits
Fast Read Access Times:
•
•
– Flash: 70 ns
– PSRAM: 70 ns
PRODUCT DESCRIPTION
The SST32HF64Ax/64Bx ComboMemory devices inte-
grate a CMOS flash memory bank with a CMOS Pseu-
doSRAM (PSRAM) memory bank in a Multi-Chip
Package (MCP), manufactured with SST’s proprietary,
high-performance SuperFlash technology.
selects the PSRAM bank. The flash memory bank enable
signal, BEF# selects the flash memory bank. The WE# sig-
nal has to be used with Software Data Protection (SDP)
command sequence when controlling the Erase and Pro-
gram operations in the flash memory bank. The SDP com-
mand sequence protects the data stored in the flash
memory bank from accidental alteration.
Featuring high-performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. To protect against inadvertent flash write, the
SST32HF64Ax/64Bx devices contain on-chip hardware
and software data protection schemes. The
SST32HF64Ax/64Bx devices offer a guaranteed endur-
ance of 10,000 cycles. Data retention is rated at greater
than 100 years.
The SST32HF64Ax/64Bx provide the added functionality
of being able to simultaneously read from or write to the
PSRAM bank while erasing or programming in the flash
memory bank. The PSRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the PSRAM
bank can be accessed for Read or Write.
The SST32HF64Ax/64Bx devices consist of two indepen-
dent memory banks with respective bank enable signals.
The flash and PSRAM memory banks are superimposed
in the same memory address space. Both memory banks
share common address lines, data lines, WE# and OE#.
The memory bank selection is done by memory bank
enable signals. The PSRAM bank enable signal, BES1#
©2006 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71299-01-000
1
4/06
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
The SST32HF64Ax/64Bx devices are suited for applica-
tions that use both flash memory and PSRAM memory to
store code or data. For systems requiring low power and
small form factor, the SST32HF64Ax/64Bx devices signifi-
cantly improve performance and reliability, while lowering
power consumption, when compared with multiple chip
solutions. The SST32HF64Ax/64Bx inherently use less
energy during erase and program than alternative flash
technologies. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies.
CONCURRENT READ/WRITE STATE TABLE
Flash
PSRAM
Program/Erase
Program/Erase
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Read Operation
The Read operation of the SST32HF64Ax/64Bx devices is
controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when OE# is high. Refer to Figure 5 for
further details.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
Device Operation
Flash Word-Program Operation
The SST32HF64Ax/64Bx use BES1#, BES2 and BEF# to
control operation of either the flash or the PSRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the PSRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time. If all
bank enable signals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
PSRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to VIHC (Logic High) or
when BEF# is high and BES2 is low.
The flash memory bank of the SST32HF64Ax/64Bx
devices is programmed on a word-by-word basis. Before
Program operations, the memory must be erased first. The
Program operation consists of three steps. The first step is
the three-byte load sequence for Software Data Protection.
The second step is to load word address and word data.
During the Word-Program operation, the addresses are
latched on the falling edge of either BEF# or WE#, which-
ever occurs last. The data is latched on the rising edge of
either BEF# or WE#, whichever occurs first. The third step
is the internal Program operation which is initiated after the
rising edge of the fourth WE# or BEF#, whichever occurs
first. The Program operation, once initiated, will be com-
pleted, within 10 µs. See Figures 6 and 7 for WE# and
BEF# controlled Program operation timing diagrams and
Figure 21 for flowcharts. During the Program operation, the
only valid flash Read operations are Data# Polling and Tog-
gle Bit. During the internal Program operation, the host is
free to perform additional tasks. During the command
sequence, WP# should be statically held high or low. Any
SDP commands loaded during the internal Program oper-
ation will be ignored.
Concurrent Read/Write Operation
The SST32HF64Ax/64Bx provide the unique benefit of
being able to read from or write to PSRAM, while simulta-
neously erasing or programming the flash. This allows data
alteration code to be executed from PSRAM, while altering
the data in flash. See Figure 26 for a flowchart. The follow-
ing table lists all valid states.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
2
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Flash Sector/Block-Erase Operation
Flash Chip-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST32HF64Ax/64Bx offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase operation is initiated by executing a six-byte
command sequence with Sector-Erase command (50H)
and sector address (SA) in the last bus cycle. The address
lines AMS-A11 are used to determine the sector address.
The Block-Erase operation is initiated by executing a six-
byte command sequence with Block-Erase command
(30H) and block address (BA) in the last bus cycle. The
address lines AMS-A15 are used to determine the block
address. The sector or block address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth
WE# pulse. The End-of-Erase operation can be deter-
mined using either Data# Polling or Toggle Bit methods.
See Figures 11 and 12 for timing waveforms. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored, WP# should be statically held high or low.
The SST32HF64Ax/64Bx provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or BEF#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 9 for tim-
ing diagram, and Figure 25 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored.
Write Operation Status Detection
The SST32HF64Ax/64Bx provide two software means to
detect the completion of a write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
Erase-Suspend/Erase-Resume Commands
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase-Resume command (30H)
at any address in the last Byte sequence.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
3
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
TABLE 1: WRITE OPERATION STATUS
Flash Data# Polling (DQ7)
Status
DQ7 DQ6
DQ2
When the SST32HF64Ax/64Bx flash memory banks are in
the internal Program operation, any attempt to read DQ7
will produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. Note that even though DQ7 may have valid data
immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycles after an interval of 1 µs. During
internal Erase operation, any attempt to read DQ7 will pro-
duce a ‘0’. Once the internal Erase operation is completed,
DQ7 will produce a ‘1’. The Data# Polling is valid after the
rising edge of the fourth WE# (or BEF#) pulse for Program
operation. For Sector- or Block-Erase, the Data# Polling is
valid after the rising edge of the sixth WE# (or BEF#) pulse.
See Figure 8 for Data# Polling timing diagram and Figure
22 for a flowchart.
Normal
Operation Program
Standard
DQ7# Toggle No Toggle
Standard
Erase
0
1
Toggle
1
Toggle
Toggle
Erase-
Read from
Suspend Erase-Suspended
Mode
Sector/Block
Read from
Non- Erase-Suspended
Sector/Block
Data
Data
Data
Program
DQ7# Toggle
N/A
T1.0 1299
Note: DQ7 and DQ2 require a valid address when reading
status information.
Flash Memory Data Protection
The SST32HF64Ax/64Bx flash memory bank provides
both hardware and software features to protect nonvolatile
data from inadvertent writes.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or BEF#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the flash Write operation. This prevents
inadvertent writes during power-up or power-down.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or
BEF#) pulse of Write operation. See Figure 9 for Toggle Bit
timing diagram and Figure 22 for a flowchart.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
4
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Hardware Block Protection
PSRAM Deep Power-down Mode
The SST32HF64x1 support bottom hardware block pro-
tection, which protects the bottom 32 KWord block of the
device. The SST32HF64x2 support top hardware block
protection, which protects the top 32 KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 32 KWord when WP# is low. If WP# is left floating, it
is internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase oper-
ations on that block.
This mode can be used to lower the power consumption of
the PSRAM in the SST32HF64Ax and SST32HF64Bx
devices. Deep Power-down occurs 1 µs after being
enabled by driving BES2 low. Normal operation occurs 500
µs after BES2 is driven high. In Deep Power-down mode,
PSRAM data is lost. See Figure 20 for the state diagram.
PSRAM Read
The PSRAM Read operation of the SST32HF64Ax/64Bx is
controlled by OE# and BES1#, both have to be low with
WE# and BES2 high for the system to obtain data from the
outputs. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance
state when OE# is high. Refer to the Read cycle timing dia-
gram, Figure 2, for further details.
TABLE 2: BOOT BLOCK ADDRESS RANGES
Product
Address Range
000000H-007FFFH
3F8000H-3FFFFFH
Bottom Boot Block
SST32HF64x1
Top Boot Block
SST32HF64x2
PSRAM Write
The PSRAM Write operation of the SST32HF64Ax/64Bx is
controlled by WE# and BES1#, both have to be low, BES2
must be high for the system to write to the PSRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1# or WE#, which-
ever occurs first. The write time is measured from the last
falling edge of BES1# or WE# to the first rising edge of
BES1# or WE#. Refer to the Write cycle timing diagrams,
Figures 3 and 4, for further details.
T2.0 1299
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place (see Figure 16).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Flash Software Data Protection (SDP)
The SST32HF64Ax/64Bx provide the JEDEC approved
software data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF64Ax/64Bx devices are shipped with the soft-
ware data protection permanently enabled. See Table 6 for
the specific software command codes. During SDP com-
mand sequence, invalid commands will abort the device to
Read mode, within TRC. The contents of DQ15-DQ8 can be
VIL or VIH, but no other value, during any SDP command
sequence.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
5
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
Product Identification
The Product Identification mode identifies the devices as
the SST32HF64A1, SST32HF64A2, SST32HF64B1, or
SST32HF64B2 and manufacturer as SST. This mode
may be accessed by software operations only. The
hardware device ID Read operation, which is typically
used by programmers, cannot be used on this device
because of the shared lines between flash and PSRAM
in the multi-chip package. Therefore, application of
high voltage to pin A9 may damage this device. Users
may use the software Product Identification operation to
identify the part (i.e., using the device ID) when using multi-
ple manufacturers in the same socket. For details, see
Tables 5 and 6 for software operation, Figure 13 for the
software ID entry and read timing diagram and Figure 23
for the ID entry command sequence flowchart.
The Secure ID space can be queried by executing a three-
byte command sequence with Enter Sec ID command
(88H) at address 555H in the last byte sequence. To exit
this mode, the Exit Sec ID command should be executed.
Refer to Table 6 for more details.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
TABLE 3: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
0000H
BFH
SST32HF64x1
SST32HF64x2
0001H
0001H
236DH
236CH
T3.0 1299
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
internal Program or Erase operation. This command may
also be used to reset the device to Read mode after any
inadvertent transient condition that apparently causes the
device to behave abnormally, e.g. not read correctly. See
Table 6 for software command codes, Figure 14 for timing
waveform and Figure 23 for a flowchart.
Security ID
The SST32HF64Ax/64Bx devices offer a 256-bit Security
ID space. The Secure ID space is divided into two 128-bit
segments - one factory programmed segment and one
user programmed segment. The first segment is pro-
grammed and locked at SST with a random 128-bit num-
ber. The user segment is left un-programmed for the
customer to program as desired.
To program the user segment of the Security ID, the user
must use the Security ID Word-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
6
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
FUNCTIONAL BLOCK DIAGRAM
PSRAM
Address Buffers
UBS#
LBS#
BES1#
BES2
BEF#
OE#1
WE#1
WP#
Control Logic
DQ - DQ
A
-A
0
15
8
MS
I/O Buffers
DQ - DQ
7
0
RESET#
Address Buffers
& Latches
SuperFlash
Memory
1299 B1.0
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
7
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
PIN DESCRIPTION
TOP VIEW (balls facing down)
8
7
6
5
4
3
2
1
NC
A20 A11 A15 A14 A13 A12
V
NC
NC
SSF
A16
A8
A10
A21
A9 DQ15 WES# DQ14 DQ7
DQ13 DQ6 DQ4 DQ5
WEF# NC
V
RST# NC
DQ12 BES2 V
V
DDS DDF
SSS
WP# NC
LBS# UBS# OES#
A19 DQ11
DQ10 DQ2 DQ3
DQ9 DQ8 DQ0 DQ1
A18 A17
NC A5
A7
A4
A6
A3
A2
A1 BES1#
OEF# NC NC
NC
A0 BEF#
V
SSF
A B C D E F G H J K
FIGURE 1: PIN ASSIGNMENTS FOR 64-BALL LFBGA (8MM X 10MM)
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
8
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
TABLE 4: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1 to A0 Address Inputs
To provide flash address, AMS-A0.
To provide PSRAM address, AMS-A0
DQ15-DQ0 Data Inputs/Outputs
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle. The outputs are
in tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.
BEF#
BES1#
BES2
Flash Memory Bank Enable
To activate the Flash memory bank when BEF# is low
PSRAM Memory Bank Enable To activate the PSRAM memory bank when BES1# is low
PSRAM Deep
To activate the PSRAM memory deep power-down mode when BES2 is VIL
Power-down Enable
OEF#
OES#
WEF#
WES#
OE#
Output Enable
Output Enable
Write Enable
Write Enable
Output Enable
Write Enable
To gate the data output buffers for Flash only
To gate the data output buffers for PSRAM only
To control the Write operations for Flash only
To control the Write operations for PSRAM only
To gate the data output buffers
WE#
UBS#
LBS#
WP#
RST#
VSSF
To control the Write operations
Upper Byte Control (PSRAM) To enable DQ15-DQ8
Lower Byte Control (PSRAM) To enable DQ7-DQ0
Write Protect
Reset
To protect and unprotect sectors from Erase or Program operation
To Reset and return the device to Read mode
Ground
Flash only
VSSS
VSS
Ground
PSRAM only
Ground
VDDF
Power Supply (Flash)
Power Supply (PSRAM)
No Connection
2.7-3.3V Power Supply to Flash only
2.7-3.3V Power Supply to PSRAM only
Unconnected pins
VDD
S
NC
T4.0 1299
1. AMS = Most Significant Address
AMS = A21 for SST32HF64xx
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
9
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
1
TABLE 5: OPERATIONAL MODES SELECTION
Mode
BEF#,2
BES1#,2
BES2
VIH
OE#3
WE#3
LBS#
UBS#
DQ7-0
HIGH-Z
HIGH-Z
DQ15-8
HIGH-Z
HIGH-Z
Full Standby
VIH
VIH
X
X
X
X
X
X
X
X
PSRAM Deep
Power-down4
VIH
VIL
VIL
Output Disable
VIH
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIH
VIH
VIH
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIH
VIH
VIL
VIH
VIH
VIH
VIL
VIL
VIH
X
X
X
X
HIGH-Z
HIGH-Z
DOUT
DIN
HIGH-Z
HIGH-Z
DOUT
DIN
Flash Read
Flash Write
Flash Erase
PSRAM Read
X
X
X
X
X
X
X
X
VIL
VIH
VIL
VIL
VIH
VIL
X
VIL
VIL
VIH
VIL
VIL
VIH
X
DOUT
HIGH-Z
DOUT
DIN
DOUT
DOUT
HIGH-Z
DIN
PSRAM Write
VIH
VIL
VIH
X
VIL
HIGH-Z
DIN
DIN
HIGH-Z
Product
VIL
VIH
VIH
VIL
VIH
Manufacturer’s ID6
Identification5
Device ID6
T5.0 1299
1. X can be VIL or VIH, but no other value.
2. For SST32HF64Ax/64Bx, to avoid bus contention do not apply BEF# = VIL and BES1# = VIL at the same time
3. OE# = OEF# and OES#
WE# = WEF# and WES#
4. In PSRAM Deep power-down, PSRAM data is lost.
5. Software mode only
6. With A21-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0=0,
SST32HF64x1 Device ID = 236DH, is read with A0=1,
SST32HF64x2 Device ID = 236CH, is read with A0=1.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
10
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
TABLE 6: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
WA3
555H
555H
555H
Data
AAH
AAH
AAH
Word-Program
Sector-Erase
Block-Erase
555H
555H
555H
555H
AAH
AAH
AAH
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
555H
A0H
80H
80H
80H
4
4
2AAH
2AAH
2AAH
55H
55H
55H
SAX
BAX
50H
30H
10H
Chip-Erase
555H
Erase-Suspend
Erase-Resume
Query Sec ID5
XXXXH B0H
XXXXH 30H
555H
555H
AAH
AAH
2AAH
2AAH
55H
55H
555H
555H
88H
A5H
WA6
Data
User Security ID
Word-Program
XXH6 0000H
User Security ID
Program Lock-Out
555H
AAH
2AAH
55H
555H
85H
Software ID Entry7,8
555H
555H
AAH
AAH
2AAH
2AAH
55H
55H
555H
555H
90H
F0H
Software ID Exit9,10
/Sec ID Exit
Software ID Exit9,10
/Sec ID Exit
XXH
F0H
T6.0 1299
1. Address format A11-A0 (Hex).
Addresses A12-A21 can be VIL or VIH, but no other value, for Command sequence for SST32HF64xx.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
A
A
MS = Most significant address
MS = A21 for SST32HF64xx.
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000010H to 000017H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST32HF64x1 Device ID = 236DH, is read with A0=1,
SST32HF64x2 Device ID = 236CH, is read with A0=1.
A
A
MS = Most significant address
MS = A21 for SST32HF64xx.
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and
000010H-000017H.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
11
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Ambient Temp
VDD
Extended
-20°C to +85°C
2.7-3.3V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 18 and 19
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
12
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
TABLE 7: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input = VILT/VIHT, at f=5 MHz,
IDD
Active VDD Current
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
18
30
40
mA
mA
mA
BEF#=VIL, BES1#=VIH, or BES2=VIL
BEF#=VIH, BES1#=VIL , BES2=VIH
BEF#=VIH, BES1#=VIL , BES2=VIH
WE#=VIL
PSRAM
Concurrent Operation
Write1
Flash
35
30
135
10
30
1
mA
mA
µA
µA
µA
µA
µA
V
BEF#=VIL, BES1#=VIH, or BES2=VIL, OE#=VIH
BEF#=VIH, BES1#=VIL , BES2=VIH
VDD = VDD Max, BEF#=BES1#=VIHC, BES2=VIHC
BES2=VILC, BEF#=VIHC
PSRAM
ISB
Standby VDD Current
Deep Power Down: PSRAM
Reset VDD Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
ISBP
IRT
Reset=VSS 0.3V
ILI
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
10
0.8
0.2
VIL
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7 VDD
VDD-0.3
V
VDD=VDD Max
VIHC
VOLF
VOHF
VOLS
VOHS
Input High Voltage (CMOS)
Flash Output Low Voltage
Flash Output High Voltage
PSRAM Output Low Voltage
PSRAM Output High Voltage
V
VDD=VDD Max
0.2
0.4
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
IOL =1 mA, VDD=VDD Min
VDD-0.2
2.2
V
V
V
IOL =-500 µA, VDD=VDD Min
T7.0 1299
1. IDD active while Erase or Program is in progress.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
13
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
TABLE 8: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T8.0 1299
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
12 pF
1
CIN
VIN = 0V
T9.0 1299
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: FLASH RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T10.0 1299
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
14
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
AC CHARACTERISTICS
TABLE 11: PSRAM READ CYCLE TIMING PARAMETERS
Symbol
TRCS
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TAAS
Address Access Time
70
70
35
70
ns
TBES
Bank Enable Access Time
Output Enable Access Time
UBS#, LBS# Access Time
BES1# to Active Output
Output Enable to Active Output
UBS#, LBS# to Active Output
BES1# to High-Z Output
Output Disable to High-Z Output
UBS#, LBS# to High-Z Output
Output Hold from Address Change
ns
TOES
ns
TBYES
ns
1
TBLZS
0
0
0
ns
1
TOLZS
ns
1
TBYLZS
ns
1
TBHZS
25
25
35
ns
1
TOHZS
0
ns
1
TBYHZS
ns
TOHS
10
ns
T11.0 1299
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: PSRAM WRITE CYCLE TIMING PARAMETERS
Symbol
TWCS
TBWS
TAWS
Parameter
Min
70
60
60
0
Max
Units
ns
Write Cycle Time
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
TASTS
TWPS
TWRS
TBYWS
TODWS
TOEWS
TDSS
ns
Write Pulse Width
60
0
ns
Write Recovery Time
ns
UBS#, LBS# to End-of-Write
Output Disable from WE# Low
Output Enable from WE# High
Data Set-up Time
60
ns
30
ns
0
30
0
ns
ns
TDHS
Data Hold from Write Time
ns
T12.0 1299
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
15
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
TABLE 13: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
Symbol
TRC
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TCE
Chip Enable Access Time
Address Access Time
70
70
35
ns
TAA
ns
TOE
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
TCLZ
0
0
ns
1
TOLZ
ns
1
TCHZ
20
20
ns
1
TOHZ
ns
1
TOH
0
ns
1
TRP
500
50
ns
1
TRHR
RST# High before Read
RST# Pin Low to Read Mode
ns
1,2
TRY
20
µs
T13.0 1299
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations.
This parameter does not apply to Chip-Erase operations.
TABLE 14: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
Parameter
Min
Max
Units
µs
Word-Program Time
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
10
TAS
0
30
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
ns
1
TWPH
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
TBE
Block-Erase
25
TSCE
Chip-Erase
50
ms
T14.0 1299
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
16
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
T
RCS
ADDRESSES A
MSS-0
T
T
T
OHS
AAS
T
BES
BES1#
OE#
T
BLZS
BHZS
T
OES
T
OLZS
T
OHZS
T
BYES
UBS#, LBS#
T
BYLZS
T
BYHZS
DQ
15-0
DATA VALID
1299 F03b.0
Note: AMSS = Most Significant PSRAM Address
MSS = A19 for SST32HF64Ax and A20 for SST32HF64Bx
A
FIGURE 2: PSRAM READ CYCLE TIMING DIAGRAM FOR SST32HF64AX/64BX
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
17
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
T
WCS
3
ADDRESSES A
MSS -0
T
ASTS
T
WPS
T
WRS
WE#
T
AWS
T
BWS
BES1#
T
BYWS
UBS#, LBS#
T
OEWS
T
ODWS
T
DHS
T
DSS
NOTE 2
VALID DATA IN
NOTE 2
DQ
15-8,
DQ
7-0
1299 F04b.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES1# goes Low coincident with or after WE# goes Low, the output will remain at high impedance.
If BES1# goes High coincident with or before WE# goes High, the output will remain at high impedance.
Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant PSRAM Address
A
MSS = A19 for SST32HF64Ax and A20 for SST32HF64Bx
FIGURE 3: PSRAM WRITE CYCLE TIMING DIAGRAM FOR SST32HF64AX/65BX (WE# CONTROLLED)1
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
18
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
T
WCS
3
ADDRESSES A
MSS -0
T
T
WRS
WPS
WE#
T
BWS
BES1#
BES2
T
BWS
T
AWS
T
T
BYWS
ASTS
UBS#, LBS#
T
T
DHS
DSS
DQ
DQ
7-0
15-8,
NOTE 2
NOTE 2
VALID DATA IN
1299 F05.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant PSRAM Address
A
MSS = A19 for SST32HF64Ax and A20 for SST32HF64Bx
FIGURE 4: PSRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
19
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
T
T
AA
RC
ADDRESS A
MS-0
BEF#
OE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1299 F06.0
Note: AMSF = Most Significant Flash Address
MSF = A21 for SST32HF64xx
A
FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
555
2AA
555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
WP
WE#
T
T
AS
DS
T
WPH
OE#
T
CH
BEF#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1299 F07.0
Note: AMSF = Most Significant Flash Address
MSF = A21 for SST32HF64xx
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
20
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS
T
BP
555
2AA
555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
BEF#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
1299 F08.0
Note: AMSF = Most Significant Flash Address
MSF = A21 for SST32HF64xx
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
ADDRESSES A
MSF-0
BEF#
OE#
T
CE
T
OES
T
OEH
T
OE
WE#
Data
Data#
Data#
Data
DQ
7
1299 F09.0
Note: AMSF = Most Significant Flash Address
AMSF = A21 for SST32HF64xx
FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
21
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
ADDRESSES A
MSF-0
T
CE
BEF#
T
OES
T
T
OE
OEH
OE#
WE#
DQ and DQ
6
2
TWO READ CYCLES
WITH SAME OUTPUTS
1299 F10.0
Note: AMSF = Most Significant Flash Address
MSF = A21 for SST32HF64xx
A
FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
555
2AA
555
ADDRESS A
MS-0
BEF#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
1299 F11.0
Note: AMSF = Most Significant Flash Address
MSF = A21 for SST32HF64xx
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
This device also supports BEF# controlled Chip-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 14)
X can be VIL or VIH, but no other value.
FIGURE 10: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
22
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
555
2AA
555
555
2AA
BA
ADDRESS A
X
MS-0
BEF#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
1299 F12.0
Note: AMSF = Most Significant Flash Address
MSF = A21 for SST32HF64xx
This device also supports BEF# controlled Block-Erase operation.
A
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 14.)
BAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value.
FIGURE 11: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
23
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
555 555 2AA
555
2AA
SA
ADDRESS A
MS-0
X
BEF#
OE#
T
WP
WE#
DQ
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
15-0
1299 F13.0
Note: AMSF = Most Significant Flash Address
MSF = A21 for SST32HF64xx
This device also supports BEF# controlled Sector-Erase operation.
A
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 14.)
SAX = Sector Address
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value.
FIGURE 12: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
24
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
THREE-WORD SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
14-0
555
2AA
555
0000
0001
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
DEVICE ID
1299 F14.0
MFG ID
Note: X can be VIL or VIH, but no other value.
Device ID - See Table 3 on page 6
FIGURE 13: SOFTWARE ID ENTRY AND READ
THREE-WORD SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
555
2AA
555
ADDRESS A
DQ
14-0
XXAA
XX55
XXF0
15-0
T
IDA
BEF#
OE#
T
WP
WE#
T
WHP
1299 F15.0
SW0
SW1
SW2
Note: X can be VIL or VIH, but no other value.
FIGURE 14: SOFTWARE ID EXIT AND RESET
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
25
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
THREE-BYTE SEQUENCE FOR
SEC ID ENTRY
ADDRESS A
555
2AA
555
MSF-0
BEF#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX88
SW2
1299 F16.0
Note: AMSF = Most Significant Flash Address
MSF = A21 for SST32HF64xx
A
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 15: FLASH SEC ID ENTRY
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
26
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
T
RP
RST#
BEF#/OE#
T
RHR
1299 F17.0
FIGURE 16: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)
T
RP
RST#
T
RY
BEF#/OE#
End-of-Write Detection
(Toggle-Bit)
1299 F18.0
FIGURE 17: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
27
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1299 F19.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 18: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1299 F20.0
FIGURE 19: A TEST LOAD EXAMPLE
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
28
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Power on
BES1# = VIH or
VIL, BES2 = VIH
Power-up
Sequence
Initial State
(Wait 200 µs)
Active
Deep
Power-down
Exit
BES1# = VIL,
BES2 = VIH,
UBS# & LBS# and/or LBS# = VIL
BES1# = VIH or
VIL, BES2 = VIH
Sequence
BES2 = VIH,
LBS# = VIH,
BES1# = VIH or UBS#
Deep
Power-down
Mode
Standby
Mode
BES2 = VIL
1299 DPDFlwCht.0
FIGURE 20: DEEP POWER-DOWN STATE DIAGRAM
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
29
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Start
Write data: XXAAH
Address: 555H
Write data: XX55H
Address: 2AAH
Write data: XXA0H
Address: 555H
Write Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1299 F21.0
Note: X can be V or V , but no other value
IL
IH
FIGURE 21: WORD-PROGRAM ALGORITHM
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
30
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
SCE, or BE
,
BP
T
T
No
Read same
word
Is DQ =
7
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
1299 F22.0
FIGURE 22: WAIT OPTIONS
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
31
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX88H
Address: 555H
Load data: XX90H
Address: 555H
Wait T
Wait T
IDA
IDA
Read Sec ID
Read Software ID
1299 F23.0
X can be V or V but no other value
IL
IH,
FIGURE 23: SEC ID/SOFTWARE ID COMMAND FLOWCHARTS
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
32
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Software ID Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XXF0H
Address: 555H
Return to normal
operation
Wait T
IDA
Return to normal
operation
X can be V or V but no other value
IL
IH,
1299 F24.0
FIGURE 24: SOFTWARE ID/SEC ID COMMAND FLOWCHARTS
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
33
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX50H
Load data: XX30H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1299 F25.0
Note: X can be VIL or VIH, but no other value.
FIGURE 25: ERASE COMMAND SEQUENCE
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
34
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Concurrent
Operation
Load SDP
Command
Sequence
Flash
Program/Erase
Initiated
Wait for End of
Write Indication
Read or Write
SRAM
End
Wait
Flash Operation
Completed
End Concurrent
Operation
1299 F26.0
FIGURE 26: CONCURRENT OPERATION FLOWCHART
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
35
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST32HFxxxx - XXX
-
XX
-
XXX X
Environmental Attribute
E1 = non-Pb
Package Modifier
2S = 64 ball positions
Package Type
L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)
Temperature Range
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Hardware Block Protection
1 = Bottom Boot Block
2 = Top Boot Block
PSRAM Density
A = 16 Mbit
B = 32 Mbit
Flash Density
64 = 64 Mbit
Voltage
H = 2.7-3.3V
Product Series
32 = MPF+ + PSRAM ComboMemory
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
36
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
Valid combinations for SST32HF64A1
SST32HF64A1-70-4E-L2SE
Valid combinations for SST32HF64A2
SST32HF64A2-70-4E-L2SE
Valid combinations for SST32HF64B1
SST32HF64B1-70-4E-L2SE
Valid combinations for SST32HF64B2
SST32HF64B2-70-4E-L2SE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
37
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A1 / SST32HF64B1
SST32HF64A2 / SST32HF64B2
Preliminary Specifications
PACKAGING DIAGRAMS
TOP VIEW
10.00 0.10
BOTTOM VIEW
7.20
0.40 0.05
0.80
(64X)
8
7
6
5
4
3
2
1
8
7
6
5
8.00 0.10
4
5.60
3
2
1
0.80
A
B
C
D
E
F
G
H
J
K
K
J
H
G
F
E
D
C
B
A
A1 CORNER
A1 CORNER
1.30 0.10
SIDE VIEW
1mm
0.12
SEATING PLANE
0.32 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.32 mm ( 0.05 mm)
64-lfbga-L2S-8x10-400mic-2.0
64-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM
SST PACKAGE CODE: L2S
TABLE 15: REVISION HISTORY
Number
Description
Date
00
Dec 2005
•
•
Initial Release of S71299
Includes 64 MB devices and extended temperature MPNs previously released in
data sheets S71260 and S71261
•
•
Removed 63-Ball Low-Profile, Fine-Ptich Ball Grid Array (LFBGA) 8mm x 10mm
Changed ISP max limits to 135 µA in DC Operating Characteristics Table 7 page 13
01
Apr 2006
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2006 Silicon Storage Technology, Inc.
S71299-01-000
4/06
38
相关型号：
SST32HF64B2-70-4E-L2SE
SPECIALTY MEMORY CIRCUIT, PBGA64, 8 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LFBGA-64
MICROCHIP
SST32HF64B2-90-4E-LFS
Memory Circuit, 4MX16, CMOS, PBGA63, 8 X 10 MM, 1.40 MM HEIGHT, MO-210, LFBGA-63
SILICON
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