SST34HF1682D-70-4E-LS中文资料_数据手册_规格书

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

SST34HF16x2x16Mb CSF + 2/4/8 Mb SRAM (x16) MCP ComboMemory

Advance Information

FEATURES:

•

Flash Organization: 1M x16 or 2M x8

•

Block-Erase Capability

– Uniform 32 KWord blocks

Read Access Time

Dual-Bank Architecture for Concurrent

Read/Write Operation

– 16 Mbit: 4 Mbit + 12 Mbit

– Flash: 70 ns

•

(P)SRAM Organization:

– (P)SRAM: 70 ns

– 2 Mbit: 128K x16 or 256K x8

– 4 Mbit: 256K x16 or 512K x8

– 8 Mbit: 512K x16 or 1024K x8

•

Erase-Suspend / Erase-Resume Capabilities

Security ID Feature

– SST: 128 bits

– User: 128 bits

•

Single 2.7-3.3V Read and Write Operations

Superior Reliability

•

Latched Address and Data

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

Fast Erase and Word-/Byte-Program (typical):

– Sector-Erase Time: 18 ms

– Block-Erase Time: 18 ms

– Chip-Erase Time: 35 ms

– Word-Program Time: 7 µs

•

Low Power Consumption:

– Active Current: 25 mA (typical)

– Standby Current: 20 µA (typical)

Hardware Sector Protection (WP#)

•

Automatic Write Timing

– Internal V_PPGeneration

End-of-Write Detection

– Protects 4 outer most sectors (4 KWord) in the

larger bank by holding WP# low and unprotects

by holding WP# high

– Toggle Bit

– Data# Polling

•

Hardware Reset Pin (RST#)

– Resets the internal state machine to reading

data array

– Ready/Busy# pin

•

CMOS I/O Compatibility

JEDEC Standard Command Set

Packages Available

•

Byte Selection for Flash (CIOF pin)

– Selects 8-bit or 16-bit mode

Sector-Erase Capability

– 56-ball LFBGA (8mm x 10mm)

– 62-ball LFBGA (8mm x 10mm)

– Uniform 2 KWord sectors

PRODUCT DESCRIPTION

The SST34HF16x2C/D/S ComboMemory devices inte-

grate either a 1M x16 or 2M x8 CMOS flash memory bank

with either a 128K x16/256K x8, 256K x16/512 x8, or 512K

x16/1024K x8 CMOS SRAM or pseudo SRAM (PSRAM)

memory bank in a multi-chip package (MCP). These

devices are fabricated using SST’s proprietary, high-perfor-

mance CMOS SuperFlash technology incorporating the

split-gate cell design and thick-oxide tunneling injector to

attain better reliability and manufacturability compared with

alternate approaches. The SST34HF16x2C/D/S devices

are ideal for applications such as cellular phones, GPS

devices, PDAs, and other portable electronic devices in a

low power and small form factor system.

memory banks are partitioned into 4 Mbit and 12 Mbit with

top sector protection options for storing boot code, program

code, configuration/parameter data and user data.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore, the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles. The SST34HF16x2C/D/S devices offer a

guaranteed endurance of 10,000 cycles. Data retention is

rated at greater than 100 years. With high performance

Word-Program, the flash memory banks provide a typical

Word-Program time of 7 µsec. The entire flash memory

bank can be erased and programmed word-by-word in typ-

ically 4 seconds for the SST34HF16x2C/D/S, when using

interface features such as Toggle Bit, Data# Polling, or RY/

BY# to indicate the completion of Program operation. To

The SST34HF16x2C/D/S feature dual flash memory bank

architecture allowing for concurrent operations between the

two flash memory banks and the (P)SRAM. The devices

can read data from either bank while an Erase or Program

operation is in progress in the opposite bank. The two flash

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.

CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.

S71256-00-000

1

3/04

These specifications are subject to change without notice.

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

protect against inadvertent

SST34HF16x2C/D/S devices contain on-chip hardware

and software data protection schemes.

flash

write,

the

Concurrent Read/Write Operation

Dual bank architecture of SST34HF16x2C/D/S devices

allows the Concurrent Read/Write operation whereby the

user can read from one bank while programming or eras-

ing in the other bank. This operation can be used when the

user needs to read system code in one bank while updat-

ing data in the other bank. See Figures 1 and 2 for dual-

bank memory organization.

The flash and (P)SRAM operate as two independent mem-

ory banks with respective bank enable signals. The mem-

ory bank selection is done by two bank enable signals. The

(P)SRAM bank enable signals, BES1# and BES2, select

the (P)SRAM bank (BES1# and BES2 are NC for

SST34HF1602C). The flash memory bank enable signal,

BEF#, has to be used with Software Data Protection (SDP)

command sequence when controlling the Erase and Pro-

gram operations in the flash memory bank. The memory

banks are superimposed in the same memory address

space where they share common address lines, data lines,

WE# and OE# which minimize power consumption and

area.

CONCURRENT READ/WRITE STATES

Flash

Bank 1

Read

Bank 2

Write

(P)SRAM

No Operation

Read

Write

Read

Write

No Operation

Write

No Operation

Write

Read

Designed, manufactured, and tested for applications requir-

ing low power and small form factor, the SST34HF16x2C/

D/S are offered in both commercial and extended tempera-

tures and a small footprint package to meet board space

constraint requirements. See Figures 3 and 4 for pin

assignments.

No Operation

Write

No Operation

Write

Note: For the purposes of this table, write means to Block-, Sector,

or Chip-Erase, or Word-/Byte-Program as applicable to the

appropriate bank.

Flash Read Operation

Device Operation

The Read operation of the SST34HF16x2C/D/S is con-

trolled by BEF# and OE#, both have to be low for the sys-

tem to obtain data from the outputs. BEF# is used for

device selection. When BEF# is high, the chip is dese-

lected and only standby power is consumed. OE# is the

output control and is used to gate data from the output pins.

The data bus is in high impedance state when either BEF#

or OE# is high. Refer to the Read cycle timing diagram for

further details (Figure 8).

The SST34HF16x2C/D/S uses BES1#, BES2 and BEF#

to control operation of either the flash or the (P)SRAM

memory bank. When BEF# is low, the flash bank is acti-

vated for Read, Program or Erase operation. When BES1#

is low, and BES2 is high the (P)SRAM is activated for Read

and Write operation. BEF# and BES1# cannot be at low

level, and BES2 cannot be at high level at the same time. If

all bank enable signals are asserted, bus contention

will result and the device may suffer permanent dam-

age. All address, data, and control lines are shared by flash

and (P)SRAM memory banks which minimizes power con-

sumption and loading. The device goes into standby when

BEF# and BES1# bank enables are raised to V_IHC(Logic

High) or when BEF# is high and BES2 is low.

S71256-00-000

3/04

2

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Flash Word-/Byte-Program Operation

Flash Chip-Erase Operation

These devices are programmed on a word-by-word or

byte-by-byte basis depending on the state of the CIOF pin.

Before programming, one must ensure that the sector

which is being programmed is fully erased.

The SST34HF16x2C/D/S provide a Chip-Erase operation,

which allows the user to erase all sectors/blocks to the “1”

state. This is useful when the device must be quickly

erased.

The Program operation is accomplished in three steps:

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

BEF#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bits or Data# Polling. See

Table 7 for the command sequence, Figure 13 for timing

diagram, and Figure 26 for the flowchart. Any commands

issued during the Chip-Erase operation are ignored. When

WP# is low, any attempt to Chip-Erase will be ignored.

1. Software Data Protection is initiated using the

three-byte load sequence.

2. Word address and word data are loaded.

During the Word-Program operation, the

addresses are latched on the falling edge of either

BEF# or WE#, whichever occurs last. The data is

latched on the rising edge of either BEF# or WE#,

whichever occurs first.

3. The internal Program operation is initiated after

the rising edge of the fourth WE# or BEF#, which-

ever occurs first. The Program operation, once ini-

tiated, will be completed typically within 7 µs.

Flash Erase-Suspend/-Resume Operations

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memory location, or program data into any

sector/block that is not suspended for an Erase operation.

The operation is executed by issuing a one-byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode within 20 µs after

the Erase-Suspend command had been issued. Valid data

can be read from any sector or block that is not suspended

from an Erase operation. Reading at address location

within erase-suspended sectors/blocks will output DQ₂tog-

gling and DQ₆at “1”. While in Erase-Suspend mode, a

Word-/Byte-Program operation is allowed except for the

sector or block selected for Erase-Suspend. To resume

Sector-Erase or Block-Erase operation which has been

suspended, the system must issue an Erase-Resume

command. The operation is executed by issuing a one-byte

command sequence with Erase Resume command (30H)

at any address in the one-byte sequence.

See Figures 9 and 10 for WE# and BEF# controlled Pro-

gram operation timing diagrams and Figure 22 for flow-

charts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Pro-

gram operation, the host is free to perform additional tasks.

Any commands issued during an internal Program opera-

tion are ignored.

Flash Sector- (Block-) Erase Operation

These devices offer both Sector-Erase and Block-Erase

operations. These operations allow the system to erase the

devices on a sector-by-sector (or block-by-block) basis.

The sector architecture is based on a uniform sector size of

2 KWord. The Block-Erase mode is based on a uniform

block size of 32 KWord. The Sector-Erase operation is initi-

ated by executing a six-byte command sequence with a

Sector-Erase command (30H) and sector address (SA) in

the last bus cycle. The Block-Erase operation is initiated by

executing a six-byte command sequence with Block-Erase

command (50H) and block address (BA) in the last bus

cycle. The sector or block address is latched on the falling

edge of the sixth WE# pulse, while the command (30H or

50H) is latched on the rising edge of the sixth WE# pulse.

The internal Erase operation begins after the sixth WE#

pulse. Any commands issued during the Block- or Sector-

Erase operation are ignored except Erase-Suspend and

Erase-Resume. See Figures 14 and 15 for timing wave-

forms.

S71256-00-000

3/04

3

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Flash Write Operation Status Detection

Flash Data# Polling (DQ₇)

The SST34HF16x2C/D/S provide one hardware and two

software means to detect the completion of a Write (Pro-

gram or Erase) cycle, in order to optimize the system

Write cycle time. The hardware detection uses the

Ready/Busy# (RY/BY#) pin. The software detection

includes two status bits: Data# Polling (DQ₇) and Toggle

Bit (DQ₆). The End-of-Write detection mode is enabled

after the rising edge of WE#, which initiates the internal

Program or Erase operation.

When the devices are in an internal Program operation, any

attempt to read DQ₇will produce the complement of the

true data. Once the Program operation is completed, DQ₇

will produce true data. During internal Erase operation, any

attempt to read DQ₇will produce a ‘0’. Once the internal

Erase operation is completed, DQ₇will produce a ‘1’. The

Data# Polling is valid after the rising edge of fourth WE# (or

BEF#) pulse for Program operation. For Sector-, Block-, or

Chip-Erase, the Data# Polling is valid after the rising edge

of sixth WE# (or BEF#) pulse. See Figure 11 for Data# Poll-

ing (DQ₇) timing diagram and Figure 23 for a flowchart.

The actual completion of the nonvolatile write is asynchro-

nous with the system; therefore, either a Ready/Busy# (RY/

BY#), Data# Polling (DQ₇) or Toggle Bit (DQ₆) read may be

simultaneous with the completion of the Write cycle. If this

occurs, the system may possibly get an erroneous result,

i.e., valid data may appear to conflict with either DQ₇or

DQ₆. In order to prevent spurious rejection, if an erroneous

result occurs, the software routine should include a loop to

read the accessed location an additional two (2) times. If

both reads are valid, then the device has completed the

Write cycle, otherwise the rejection is valid.

Toggle Bits (DQ₆and DQ₂)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ₆will produce alternating “1”s

and “0”s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ₆bit will

stop toggling. The device is then ready for the next opera-

tion. The toggle bit is valid after the rising edge of the fourth

WE# (or BEF#) pulse for Program operations. For Sector-,

Block-, or Chip-Erase, the toggle bit (DQ₆) is valid after the

rising edge of sixth WE# (or BEF#) pulse. DQ₆will be set to

“1” if a Read operation is attempted on an Erase-sus-

pended Sector/Block. If Program operation is initiated in a

sector/block not selected in Erase-Suspend mode, DQ₆will

toggle.

Ready/Busy# (RY/BY#)

The SST34HF16x2C/D/S include a Ready/Busy# (RY/

BY#) output signal. RY/BY# is an open drain output pin that

indicates whether an Erase or Program operation is in

progress. Since RY/BY# is an open drain output, it allows

several devices to be tied in parallel to V_DDvia an external

pull-up resistor. After the rising edge of the final WE# pulse

in the command sequence, the RY/BY# status is valid.

An additional Toggle Bit is available on DQ₂, which can be

used in conjunction with DQ₆to check whether a particular

sector is being actively erased or erase-suspended. Table 1

shows detailed status bit information. The Toggle Bit (DQ₂)

is valid after the rising edge of the last WE# (or BEF#)

pulse of a Write operation. See Figure 12 for Toggle Bit tim-

ing diagram and Figure 23 for a flowchart.

When RY/BY# is actively pulled low, it indicates that an

Erase or Program operation is in progress. When RY/BY#

is high (Ready), the devices may be read or left in standby

mode.

TABLE 1: WRITE OPERATION STATUS

Byte/Word (CIOF)

Status

DQ₇

DQ₆

DQ₂

RY/BY#

The device includes a CIOF pin to control whether the

device data I/O pins operate x8 or x16. If the CIOF pin is at

logic “1” (V_IH) the device is in x16 data configuration: all

data I/0 pins DQ₀-DQ₁₅are active and controlled by BEF#

and OE#.

Normal

Operation Program

Standard

DQ7# Toggle No Toggle

0

Standard

Erase

0

1

Toggle

1

Toggle

0

1

Erase-

Suspend Erase

Mode Suspended

Read From

If the CIOF pin is at logic “0”, the device is in x8 data config-

uration: only data I/O pins DQ₀-DQ₇are active and con-

trolled by BEF# and OE#. The remaining data pins DQ₈-

DQ₁₄are at Hi-Z, while pin DQ₁₅is used as the address

input A_-1for the Least Significant Bit of the address bus.

Sector/Block

Read From

Non-Erase

Suspended

Sector/Block

Data

N/A

1

Program

DQ7# Toggle

0

T1.0 1256

Note: DQ_7,DQ_6,and DQ₂require a valid address when reading

status information.

S71256-00-000

3/04

4

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Data Protection

Software Data Protection (SDP)

The SST34HF16x2C/D/S provide both hardware and soft-

ware features to protect nonvolatile data from inadvertent

writes.

The SST34HF16x2C/D/S provide the JEDEC standard

Software Data Protection scheme for all data alteration

operations, i.e., Program and Erase. Any Program opera-

tion requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six-byte sequence. The SST34HF16x2C/D/S are shipped

with the Software Data Protection permanently enabled.

See Table 7 for the specific software command codes. Dur-

ing SDP command sequence, invalid commands will abort

the device to Read mode within T_RC.The contents of DQ₁₅-

DQ₈are “Don’t Care” during any SDP command

sequence.

Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

V_DDPower Up/Down Detection: The Write operation is

inhibited when V_DDis less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Hardware Block Protection

Security ID

The SST34HF16x2C/D/S provide a hardware block protec-

tion which protects the outermost 8 KWord in Bank 1. The

block is protected when WP# is held low. See Figures 1

and 2 for Block-Protection location.

The SST34HF16x2C/D/S devices offer a 256-bit Security

ID space. The Secure ID space is divided into two 128-bit

segments—one factory programmed segment and one

user programmed segment. The first segment is pro-

grammed and locked at SST with a unique, 128-bit num-

ber. The user segment is left un-programmed for the

customer to program as desired. To program the user seg-

ment of the Security ID, the user must use the Security ID

Word-Program command. End-of-Write status is checked

by reading the toggle bits. Data# Polling is not used for

Security ID End-of-Write detection. Once programming is

complete, the Sec ID should be locked using the User-Sec-

ID-Program-Lock-Out. This disables any future corruption

of this space. Note that regardless of whether or not the

Sec ID is locked, neither Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-

byte command sequence with Query-Sec-ID command

(88H) at address 5555H in the last byte sequence. To exit

this mode, the Exit-Sec-ID command should be executed.

Refer to Table 7 for more details.

A user can disable block protection by driving WP# high

thus allowing erase or program of data into the protected

sectors. WP# must be held high prior to issuing the write

command and remain stable until after the entire Write

operation has completed.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least T_RP,any in-progress operation will terminate and

return to Read mode (see Figure 19). When no internal

Program/Erase operation is in progress, a minimum period

of T_RHRis required after RST# is driven high before a valid

Read can take place (see Figure 18).

The Erase operation that has been interrupted needs to be

reinitiated after the device resumes normal operation mode

to ensure data integrity. See Figures 18 and 19 for timing

diagrams.

S71256-00-000

3/04

5

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Product Identification

(P)SRAM Operation

The Product Identification mode identifies the device as the

SST34HF16x2C/D/S and manufacturer as SST. This

mode may be accessed by software operations only. The

hardware device ID Read operation, which is typically used

by programmers cannot be used on this device because of

the shared lines between flash and (P)SRAM in the multi-

chip package. Therefore, application of high voltage to pin

A₉may damage this device. Users may use the software

Product Identification operation to identify the part (i.e.,

using the device ID) when using multiple manufacturers in

the same socket. For details, see Tables 4 and 7 for soft-

ware operation, Figure 16 for the Software ID Entry and

Read timing diagram and Figure 24 for the ID Entry com-

mand sequence flowchart.

With BES1# low, BES2 and BEF# high, the

SST34HF16x2C/D/S operate as either 128K x16, 256K

x16, or 512K x16 CMOS (P)SRAM, with fully static opera-

tion requiring no external clocks or timing strobes. The

SST34HF16x2C/D/S (P)SRAM is mapped into the first 512

KWord address space. When BES1#, BEF# are high and

BES2 is low, all memory banks are deselected and the

device enters standby. Read and Write cycle times are

equal. The control signals UBS# and LBS# provide access

to the upper data byte and lower data byte (UBS# and

LBS# signals are NC for SST3416x2S parts). See Table 4

for x16 (P)SRAM Read and Write data byte control modes

of operation. See Table 5 for x8 SRAM Read and Write

data byte control modes of operation.

TABLE 2: PRODUCT IDENTIFICATION

ADDRESS DATA

(P)SRAM Read

The (P)SRAM Read operation of the SST34HF16x2C/D/S

is controlled by OE# and BES1#, both have to be low with

WE# and BES2 high for the system to obtain data from the

outputs. BES1# and BES2 are used for (P)SRAM bank

selection. OE# is the output control and is used to gate

data from the output pins. The data bus is in high imped-

ance state when OE# is high. Refer to the Read cycle tim-

ing diagram, Figure 5, for further details.

Manufacturer’s ID

Device ID

BK0000H

00BFH

SST34HF16x2C/D/S

BK0001H

734AH

T2.0 1256

Note: BK = Bank Address (A₁₉-A₁₈

)

Product Identification Mode Exit

(P)SRAM Write

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit

command is ignored during an internal Program or Erase

operation. See Table 7 for software command codes, Fig-

ure 17 for timing waveform and Figure 24 for a flowchart.

The (P)SRAM Write operation of the SST34HF16x2C/D/S

is controlled by WE# and BES1#, both have to be low,

BES2 must be high for the system to write to the (P)SRAM.

During the Word-Write operation, the addresses and data

are referenced to the rising edge of either BES1#, WE#, or

the falling edge of BES2 whichever occurs first. The write

time is measured from the last falling edge of BES#1 or

WE# or the rising edge of BES2 to the first rising edge of

BES1#, or WE# or the falling edge of BES2. Refer to the

Write cycle timing diagrams, Figures 6 and 7, for further

details.

S71256-00-000

3/04

6

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

FUNCTIONAL BLOCK DIAGRAM

Address

Buffers

A

¹- A

SA

MS

0

5

SuperFlash Memory

(Bank 1)

RST#

BEF#

SuperFlash Memory

(Bank 2)

WP#

LBS#³

UBS#³

WE#²

Control

Logic

I/O Buffers

DQ /A- - DQ

OE#²

15

1

0

BES1#⁴

BES2⁴

RY/BY#

2 / 4 / 8 Mbit

SRAM or PSRAM

Address

Buffers

1256 B1.0

Notes: 1. A

= Most significant address

MS

2. For LS package only: WE# = WEF# and/or WES#

OE# = OEF# and/or OES#

3. For SST34FH16x2S, LBS# and UBS# are No Connect.

4. For SST34HF1602C, BES1#, BES2, SA, LBS#, and UBS# are No Connect

5. Additional Address for x8 SRAM

S71256-00-000

3/04

7

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Top Block Protection; 32 KWord Blocks; 2 KWord Sectors

8 KWord Block Protection

(4 - 2 KWord Sectors)

FFFFFH

FE000H

FDFFFH

F8000H

F7FFFH

F0000H

Block 31

Block 30

EFFFFH

E8000H

E7FFFH

E0000H

DFFFFH

D8000H

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

D7FFFH

D0000H

CFFFFH

C8000H

C7FFFH

C0000H

BFFFFH

B8000H

B7FFFH

B0000H

AFFFFH

A8000H

A7FFFH

A0000H

9FFFFH

98000H

97FFFH

90000H

8FFFFH

88000H

87FFFH

80000H

7FFFFH

78000H

77FFFH

70000H

6FFFFH

68000H

67FFFH

60000H

5FFFFH

58000H

57FFFH

50000H

4FFFFH

48000H

47FFFH

40000H

3FFFFH

38000H

37FFFH

30000H

2FFFFH

28000H

27FFFH

20000H

1FFFFH

18000H

17FFFH

10000H

0FFFFH

08000H

07FFFH

00000H

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

1256 F01.0

Note: The address input range in x16 mode (BYTE#=V_IH) is A₁₉-A₀

FIGURE 1: SST34HF16X2C/D, CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

S71256-00-000

3/04

8

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Top Block Protection; 64 KByte Blocks; 4 KByte Sectors

16 KByte Block Protection

1FFFFFH

(4 - 4 KByte Sectors)

1FC000H

1FBFFFH

1F0000H

1EFFFFH

1E0000H

1DFFFFH

1D0000H

1CFFFFH

1C0000H

1BFFFFH

1B0000H

1AFFFFH

1A0000H

19FFFFH

190000H

Block 31

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

18FFFFH

180000H

17FFFFH

170000H

16FFFFH

160000H

15FFFFH

150000H

14FFFFH

140000H

13FFFFH

130000H

12FFFFH

120000H

11FFFFH

110000H

10FFFFH

100000H

0FFFFFH

0F0000H

0EFFFFH

0E0000H

0DFFFFH

0D0000H

0CFFFFH

0C0000H

0BFFFFH

0B0000H

0AFFFFH

0A0000H

09FFFFH

090000H

08FFFFH

080000H

07FFFFH

070000H

06FFFFH

060000H

05FFFFH

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

00FFFFH

000000H

Block 0

1256 F01b.0

Note: The address input range in x8 mode (BYTE#=V_IL) is A₁₉-A_-1

FIGURE 2: SST34HF16X2S, 2M X8 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

S71256-00-000

3/04

9

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

TOP VIEW (balls facing down)

8

7

6

5

4

3

2

1

A15 NC

NC

A16 CIOF

V

SS

A15 NC

NC

A16 CIOF

V

SS

7

A11 A12 A13 A14

NC

DQ7 DQ14

DQ12 DQ5

NOTE*

DQ13

DQ4

DQ3

DQ9

OE#

A11 A12 A13 A14

SA

A10 DQ6

DQ7 DQ14

DQ12 DQ5

NOTE*

DQ13

DQ4

DQ3

DQ9

OE#

6

5

4

3

2

1

A8 A19 A9

WE# BES2 NC

WP# RST# RY/BY#

A10 DQ6

A8 A19 A9

WE# BES2 NC

WP# RST# RY/BY#

V

NC

DDS

V

NC

DDS

DQ11

DDF

DQ11

DDF

LBS# UBS# A18 A17 DQ1

DQ10 DQ2

DQ0 DQ8

BES1#

NC NC A18 A17 DQ1

DQ10 DQ2

DQ0 DQ8

BES1#

A7

A6

A5

A4

V

SS

A7

A6

A5

A4

V

SS

A3

A2

A1

A0

BEF#

A3

A2

A1

A0

BEF#

A

B

C

D

E

F

G

H

A

B

C

D

E

F

G

H

Note* = DQ /A

15 -1

Note* = DQ /A

15 -1

SST34HF1622S / SST34HF1642S

SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D

Note: 1. For SST34HF1602C, V_DDS,SA, BES2, and BES1# are No Connect.

FIGURE 3: PIN ASSIGNMENTS FOR 56-BALL LFBGA (8MM X 10MM)

TOP VIEW (balls facing down)

8

NC

A11

A8

A15

A10

A14

A13

A12

V

NC

SSF

7

6

5

4

3

2

1

A16

A9 DQ15 WES# DQ14 DQ7

DQ13 DQ6 DQ4 DQ5

WEF# RY/BY#

V

SSS

RST#

NC

DQ12 BES2

V

DDS DDF

WP#

A19 DQ11

DQ10 DQ2 DQ3

LBS# UBS# OES#

DQ9 DQ8 DQ0 DQ1

A18

A17

A7

A6

A3

A2

A1 BES1#

OEF# NC

NC

A5

A4

A0

BEF#

V

SSF

NC

A

B

C

D

E

F

G

H

J

K

SST34HF16x2C/D

Note: 1. For SST34HF1602C, V_SSS, V_DDS, WES#, BES2, OES#, UBS#, LBS#, and BES1# are No Connect.

FIGURE 4: PIN ASSIGNMENTS FOR 62-BALL LFBGA (8MM X 10MM)

S71256-00-000

3/04

10

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

TABLE 3: PIN DESCRIPTION

Symbol

Pin Name

Functions

A_MS¹to A₀Address Inputs

To provide flash address, A₁₉-A₀.

To provide (P)SRAM address, A_MS-A₀

SA

SRAM x8 Address

To provide additional address for x8 SRAM

DQ₁₄-DQ₀Data Inputs/Outputs

To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle. The outputs are in

tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.

DQ₁₅/A_-1

Data Input/Output

and LBS Address

DQ₁₅is used as data I/O pin when in x16 mode (CIOF = “1”)

A_-1is used as the LBS address pin when in x8 mode (CIOF = “0”)

BEF#

BES1#

BES2

OEF#²

OES#²

WEF#²

WES#²

OE#

Flash Memory Bank Enable

To activate the Flash memory bank when BEF# is low

(P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES1# is low

(P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES2 is high

Output Enable

Write Enable

To gate the data output buffers for Flash²only

To gate the data output buffers for SRAM²only

To control the Write operations for Flash²only

To control the Write operations for SRAM²only

To gate the data output buffers

Write Enable

Output Enable

Write Enable

WE#

To control the Write operations

CIOF

Byte Selection for Flash

When low, select Byte mode. When high, select Word mode.

UBS#

LBS#

WP#

Upper Byte Control ((P)SRAM) To enable DQ₁₅-DQ₈

Lower Byte Control ((P)SRAM) To enable DQ₇-DQ₀

Write Protect

To protect and unprotect the top 8 KWord (4 sectors) from Erase or Program

operation

RST#

Reset

To Reset and return the device to Read mode

RY/BY#

Ready/Busy#

To output the status of a Program or Erase Operation

RY/BY# is a open drain output, so a 10KΩ- 100KΩpull-up resistor is required to

allow RY/BY# to transition high indicating the device is ready to read.

2

V_SSF

Ground

Flash²only

SRAM²only

2

V_SSS

Ground

V_SS

Ground

V_DDF

V_DDS

NC

Power Supply (Flash)

Power Supply ((P)SRAM)

No Connection

2.7-3.3V Power Supply to Flash only

2.7-3.3V Power Supply to (P)SRAM only

Unconnected pins

T3.0 1256

1. A_MS= Most Significant Address

_MS= A₁₆for SST34HF1622C/S, A₁₇for SST34HF1642C/D/S, and A₁₈for SST34HF1682D

A

2. LS package only

S71256-00-000

3/04

11

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

TABLE 4: OPERATIONAL MODES SELECTION FOR X16 (P)SRAM

DQ_15-8

CIOF = V_IL

Mode

BEF#¹BES1#^1,2

BES2^1,2

X

OE#^2,3

X

WE#^2,3LBS#²UBS#²

DQ_7-0

CIOF = V_IH

Full Standby

V_IH

V_IL

V_IH

X

HIGH-Z

V_IL

V_IH

X

Output Disable

V_IL

V_IH

X

V_IH

X

V_IH

X

HIGH-Z

D_OUT

D_IN

HIGH-Z

D_OUT

D_IN

V_IH

X

V_IH

X

V_IH

V_IL

X

Flash Read

Flash Write

V_IH

X

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

X

DQ_14-8= HIGH-Z

DQ₁₅= A_-1

V_IL

X

V_IH

X

DQ_14-8= HIGH-Z

DQ₁₅= A_-1

V_IL

X

Flash Erase

(P)SRAM Read

V_IH

X

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

X

V_IL

V_IH

V_IL

V_IH

X

D_OUT

HIGH-Z

D_OUT

D_IN

D_OUT

HIGH-Z

D_IN

D_OUT

HIGH-Z

D_IN

(P)SRAM Write

V_IH

V_IL

V_IH

X

V_IL

HIGH-Z

D_IN

Manufacturer’s ID⁵

Device ID⁵

D_IN

HIGH-Z

Product

V_IL

V_IH

V_IL

V_IH

Identification⁴

T4.0 1256

1. Do not apply BEF# = V_IL, BES1# = V_ILand BES2 = V_IHat the same time

2. X can be V_ILor V_IH,but no other value.

3. OE# = OEF# and OES#

WE# = WEF# and WES# for LS package only

4. Software mode only

5. With A₁₉-A₁₈= V_IL;SST Manufacturer’s ID = BFH, is read with A₀=0,

SST34HF16x2C/D/S Device ID = 734AH, is read with A₀=1

S71256-00-000

3/04

12

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

TABLE 5: OPERATIONAL MODES SELECTION FOR X8 SRAM

,

DQ_15-8

Mode

BEF#¹BES1#^{1 2}

BES2^1,2OE#²WE#²SA²

DQ_7-0

CIOF = V_IH

CIOF = V_IL

HIGH-Z

Full Standby

V_IH

V_IL

V_IH

X

HIGH-Z

V_IL

V_IH

X

Output Disable

V_IL

V_IH

X

V_IH

X

V_IH

X

HIGH-Z

D_OUT

D_IN

HIGH-Z

D_OUT

D_IN

HIGH-Z

V_IH

X

V_IH

V_IL

X

Flash Read

Flash Write

Flash Erase

V_IH

X

V_IL

V_IH

V_IL

X

DQ_14-8= HIGH-Z

DQ₁₅= A_-1

V_IL

X

V_IH

X

DQ_14-8= HIGH-Z

DQ₁₅= A_-1

V_IL

X

V_IH

X

V_IL

V_IH

V_IL

SRAM Read

SRAM Write

V_IH

V_IL

V_IH

V_IL

X

V_IH

V_IL

V_IH

SA

X

D_OUT

D_IN

Manufacturer’s ID⁴

Device ID⁴

HIGH-Z

Product

V_IL

Manufacturer’s ID⁴

Device ID⁴

Identification³

T5.0 1256

1. Do not apply BEF# = V_IL, BES1# = V_ILand BES2 = V_IHat the same time

2. X can be V_ILor V_IH, but no other value.

3. Software mode only

4. With A₁₉-A₁₈= V_IL;SST Manufacturer’s ID = BFH, is read with A₀=0,

SST34HF16x2C/D/S Device ID = 734AH, is read with A₀=1, for x8 A_-1will not be part of the Device ID

TABLE 6: OPERATIONAL MODES SELECTION FOR 0 MBIT SRAM: SST34HF1602C

DQ_15-8

,

Mode

BEF#

OE#^{1 2}

WE#^{1 2}

DQ_7-0

CIOF = V_IH

CIOF = V_IL

Full Standby

V_IH

X

HIGH-Z

Output Disable

V_IH

X

V_IH

X

HIGH-Z

V_IL

V_IH

V_IL

V_IH

HIGH-Z

D_OUT

HIGH-Z

D_OUT

Flash Read

Flash Write

Flash Erase

DQ_14-8= HIGH-Z

DQ₁₅= A_-1

V_IL

V_IH

V_IL

D_IN

X

D_IN

X

DQ_14-8= HIGH-Z

DQ₁₅= A_-1

V_IL

V_IH

V_IL

V_IH

X

Product

Identification³

Manufacturer’s ID⁴

Device ID⁴

T6.0 1256

1. X can be V_ILor V_IH, but no other value.

2. OE# = OEF#, WE# = WEF#

3. Software mode only

4. With A₁₉-A₁₈= V_IL;SST Manufacturer’s ID = BFH, is read with A₀=0,

SST34HF1602C Device ID = 734AH, is read with A₀=1, for x8 A_-1will not be part of the Device ID

S71256-00-000

3/04

13

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

TABLE 7: SOFTWARE COMMAND SEQUENCE

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²

5555H

XXXXH

5555H

AAH

B0H

30H

2AAAH

55H

5555H

A0H

80H

WA³

Data

AAH

Word-/Byte-Program

Sector-Erase

4

5555H

2AAAH

55H

SA_X

BA_X

30H

50H

10H

Block-Erase

5555H

Chip-Erase

Erase-Suspend

Erase-Resume

Query Sec ID⁵

AAH

2AAAH

55H

5555H

88H

A5H

SIWA⁶

XXH

Data

User Security ID

Word-/Byte-Program

5555H

AAH

2AAAH

55H

5555H

85H

0000H

User Security ID

Program Lock-out⁷

9

Software ID Entry⁸

5555H

AAH

2AAAH

55H

BK_X

90H

F0H

5555H

Software ID Exit/

Sec ID Exit^10,11

XXH

F0H

Software ID Exit/

Sec ID Exit^10,11

T7.0 1256

1. Address format A₁₄-A₀(Hex), Addresses A₁₉-A₁₅can be V_ILor V_IH, but no other value, for the command sequence when in x16 mode.

When in x8 mode, Addresses A₁₉-A_15,Address A_-1and DQ₁₄-DQ₈can be V_ILor V_IH, but no other value, for the command sequence.

2. DQ₁₅-DQ₈can be V_ILor V_IH, but no other value, for the command sequence

3. WA = Program word/byte address

4. SA_Xfor Sector-Erase; uses A₁₉-A₁₀address lines

BA_Xfor Block-Erase; uses A₁₉-A₁₅address lines

5. For SST34HF16x2C/D/S,

SST ID is read with A₃= 0 (Address range = 00000H to 00007H),

User ID is read with A₃= 1 (Address range = 00010H to 00017H).

Lock Status is read with A₇-A₀= 000FFH. Unlocked: DQ₃= 1 / Locked: DQ₃= 0.

6. SIWA = User Security ID Program word/byte address

For SST34HF16x2C/D/S, valid Word-Addresses for User Sec ID are from C0010H-C0017H.

All 4 cycles of User Security ID Word-Program and Program Lock-out must be completed before going back to Read-Array mode.

7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=V_IH).

8. The device does not remain in Software Product Identification mode if powered down.

9. A₁₉and A₁₈= V_IL

10. Both Software ID Exit operations are equivalent

11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the

User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).

For SST34HF16x2C/D/S, valid Word-Addresses for User Sec ID are from C0010H-C0017H.

S71256-00-000

3/04

14

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V_DD¹+0.3V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to V_DD¹+1.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Output Short Circuit Current². . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. V_DD= V_DDFand V_DDS

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range

Ambient Temp

0°C to +70°C

V_DD

Commercial

Extended

2.7-3.3V

-20°C to +85°C

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . C_L= 30 pF

See Figures 20 and 21

S71256-00-000

3/04

15

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

TABLE 8: DC OPERATING CHARACTERISTICS (V_DD= V_DDFAND V_DDS= 2.7-3.3V)

Limits

Symbol Parameter

Min

Max Units Test Conditions

Address input = V_ILT/V_IHT,at f=1/T_RCMin,

1

I_DD

Active V_DDCurrent

V_DD=V_DDMax, all DQs open

Read

Flash

OE#=V_IL, WE#=V_IH

35

30

60

mA

BEF#=V_IL, BES1#=V_IH, or BES2=V_IL

BEF#=V_IH, BES1#=V_{IL ,}BES2=V_IH

WE#=V_IL

(P)SRAM

Concurrent Operation

Write²

Flash

40

30

mA

BEF#=V_IL, BES1#=V_IH, or BES2=V_IL, OE#=V_IH

BEF#=V_IH, BES1#=V_{IL ,}BES2=V_IH

V_DD= V_DDMax, BEF#=BES1#=V_IHC, BES2=V_ILC

(P)SRAM

I_SB

Standby V_DDCurrent SRAM

PSRAM

30

85

µA

I_RT

I_LI

Reset V_DDCurrent

30

1

µA

RST#=GND

Input Leakage Current

V_IN=GND to V_DD, V_DD=V_DDMax

I_LIW

Input Leakage Current

on WP# pin and RST# pin

10

WP#=GND to V_DD, V_DD=V_DDMax

RST#=GND to V_DD, V_DD=V_DDMax

I_LO

Output Leakage Current

Input Low Voltage

10

0.8

0.3

µA

V

V_OUT=GND to V_DD, V_DD=V_DDMax

V_DD=V_DDMin

V_IL

V_ILC

V_IH

Input Low Voltage (CMOS)

Input High Voltage

V_DD=V_DDMax

0.7 V_DD

V_DD-0.3

V_DD=V_DDMax

V_IHC

V_OLF

V_OHF

V_OLS

V_OHS

Input High Voltage (CMOS)

Flash Output Low Voltage

Flash Output High Voltage

(P)SRAM Output Low Voltage

(P)SRAM Output High Voltage

V_DD=V_DDMax

0.2

0.4

I_OL=100 µA, V_DD=V_DDMin

I_OH=-100 µA, V_DD=V_DDMin

IOL =1 mA, V_DD=V_DDMin

V_DD-0.2

2.2

IOH =-500 µA, V_DD=V_DDMin

T8.0 1256

1. Address input = V_ILT/V_IHT,V_DD=V_DDMax (See Figure 20)

2. I_DDactive while Erase or Program is in progress.

S71256-00-000

3/04

16

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol

Parameter

Minimum

100

Units

1

T_PU-READ

Power-up to Read Operation

Power-up to Write Operation

µs

1

T_PU-WRITE

100

µs

T9.0 1256

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

V_I/O= 0V

Maximum

20 pF

1

C_I/O

I/O Pin Capacitance

Input Capacitance

1

C_IN

V_IN= 0V

16 pF

T10.0 1256

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 11: FLASH RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Data Retention

Latch Up

Minimum Specification

Units

Test Method

1

N_END

10,000

100

Cycles JEDEC Standard A117

1

T_DR

Years

mA

JEDEC Standard A103

JEDEC Standard 78

1

I_LTH

100 + I_DD

T11.0 1256

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

S71256-00-000

3/04

17

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

AC CHARACTERISTICS

TABLE 12: (P)SRAM READ CYCLE TIMING PARAMETERS

Min

Max

Units

ns

T_RCS

T_AAS

T_BES

T_OES

T_BYES

Read Cycle Time

70

Address Access Time

70

35

70

ns

Bank Enable Access Time

Output Enable Access Time

UBS#, LBS# Access Time

BES# to Active Output

ns

1

T_BLZS

T_OLZS

0

ns

1

Output Enable to Active Output

UBS#, LBS# to Active Output

BES# to High-Z Output

ns

1

T_BYLZS

ns

1

T_BHZS

25

35

ns

T_OHZS

T_BYHZS

T_OHS

Output Disable to High-Z Output

UBS#, LBS# to High-Z Output

Output Hold from Address Change

ns

1

ns

10

ns

T12.0 1256

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 13: (P)SRAM WRITE CYCLE TIMING PARAMETERS

Symbol Parameter

Min

70

60

0

Max

Units

ns

T_WCS

T_BWS

T_AWS

Write Cycle Time

Bank Enable to End-of-Write

Address Valid to End-of-Write

Address Set-up Time

ns

T_ASTS

T_WPS

T_WRS

T_BYWS

T_ODWS

T_OEWS

T_DSS

ns

Write Pulse Width

60

0

ns

Write Recovery Time

ns

UBS#, LBS# to End-of-Write

Output Disable from WE# Low

Output Enable from WE# High

Data Set-up Time

60

ns

30

ns

0

30

0

ns

T_DHS

Data Hold from Write Time

ns

T13.0 1256

S71256-00-000

3/04

18

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

TABLE 14: FLASH READ CYCLE TIMING PARAMETERS V_DD= 2.7-3.3V

Symbol Parameter

Min

Max

Units

ns

T_RC

T_CE

T_AA

Read Cycle Time

70

Chip Enable Access Time

Address Access Time

70

35

ns

T_OE

T_CLZ

T_OLZ

Output Enable Access Time

BEF# Low to Active Output

OE# Low to Active Output

BEF# High to High-Z Output

OE# High to High-Z Output

Output Hold from Address Change

RST# Pulse Width

ns

1

0

ns

1

T_CHZ

T_OHZ

20

ns

1

ns

1

T_OH

0

ns

1

T_RP

500

50

ns

1

T_RHR

RST# High Before Read

RST# Pin Low to Read

ns

1,2

T_RY

20

µs

T14.0 1256

1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.

TABLE 15: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter

Min

Max

Units

µs

ns

µs

ns

µs

ms

T_BP

Word-Program Time

10

T_AS

Address Setup Time

Address Hold Time

WE# and BEF# Setup Time

WE# and BEF# Hold Time

OE# High Setup Time

OE# High Hold Time

BEF# Pulse Width

0

40

0

T_AH

T_CS

T_CH

T_OES

T_OEH

T_CP

0

10

40

30

0

T_WP

T_WPH

WE# Pulse Width

1

WE# Pulse Width High

BEF# Pulse Width High

Data Setup Time

1

T_CPH

T_DS

1

T_DH

Data Hold Time

1

T_IDA

Software ID Access and Exit Time

Erase-Suspend Latency

RY/BY# Delay Time

Bus# Recovery Time

Sector-Erase

150

20

T_ES

1,2

T_BY

T_BR

T_SE

T_BE

90

1

25

50

Block-Erase

T_SCE

Chip-Erase

ms

T15.0 1256

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

S71256-00-000

3/04

19

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

T

RCS

ADDRESSES A

MSS-0

T

OHS

AAS

T

BES1#

BES2

BES

T

BES

T

BLZS

BHZS

T

OES

OE#

T

OLZS

T

OHZS

T

BYES

UBS#, LBS#

T

BYLZS

T

BYHZS

DQ

15-0

DATA VALID

1256 F04.0

Note: A_MSS= Most Significant Address

_MSS= A₁₆for SST34HF1622C/S, A₁₇for SST34HF1622C/D/S, and A₁₈for SST34HF1682D

For SST34HF16x2S, LBS# and UBS# are No Connect and in x8 mode, the additional SRAM address is SA.

A

FIGURE 5: (P)SRAM READ CYCLE TIMING DIAGRAM

T

WCS

3

ADDRESSES A

MSS -0

T

ASTS

T

WPS

WRS

WE#

BES1#

BES2

T

AWS

T

BWS

T

BWS

BYWS

UBS#, LBS#

T

OEWS

T

DHS

T

ODWS

T

DSS

VALID DATA IN

NOTE 2

DQ

7-0

15-8,

1256 F05.0

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.

If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.

Because D_INsignals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. A_MSS= Most Significant SRAM Address

A

_MSS= A₁₆for SST34HF1622C/S, A₁₇for SST34HF1622C/D/S, and A₁₈for SST34HF1682D

For SST34HF16x2S, LBS# and UBS# are No Connect and in x8 mode, the additional SRAM address is SA.

FIGURE 6: (P)SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)¹

S71256-00-000

3/04

20

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

T

WCS

3

ADDRESSES A

MSS -0

T

WRS

WPS

WE#

T

BWS

BES1#

BES2

T

BWS

T

AWS

T

ASTS

T

BYWS

UBS#, LBS#

T

DHS

DSS

DQ

7-0

15-8,

NOTE 2

VALID DATA IN

1256 F06.0

Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.

2. Because D_INsignals may be in the output state at this time, input signals of reverse polarity must not be applied.

3. A_MSS= Most Significant SRAM Address

A_MSS= A₁₆for SST34HF1622C, A₁₇for SST34HF1622C/D, and A₁₈for SST34HF1682D

FIGURE 7: (P)SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)¹X16 (P)SRAM ONLY

S71256-00-000

3/04

21

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

T

AA

RC

ADDRESS A

19-0

T

CE

BEF#

OE#

T

OE

T

OHZ

T

OLZ

V

IH

WE#

T

CHZ

T

OH

T

CLZ

HIGH-Z

DQ

15-0

DATA VALID

1256 F07.0

FIGURE 8: FLASH READ CYCLE TIMING DIAGRAM FOR WORD MODE

(FOR BYTE MODE A_-1= ADDRESS INPUT)

T

BP

5555

2AAA

5555

ADDR

ADDRESS A

19-0

T

AH

T

WP

WE#

T

WPH

T

AS

OE#

BEF#

T

CH

T

CS

T

BY

T

BR

RY/BY#

T

DS

T

DH

DQ

15-0

XXAA

XX55

XXA0

DATA

VALID

WORD

(ADDR/DATA)

1256 F08.0

Note: X can be V or V , but no other value.

IL

IH

FIGURE 9: FLASH WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM FOR WORD MODE

(FOR BYTE MODE A_-1= ADDRESS INPUT)

S71256-00-000

3/04

22

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

T

BP

5555

2AAA

5555

ADDR

ADDRESS A

19-0

T

AH

T

CP

BEF#

OE#

T

CPH

T

AS

T

CH

WE#

T

CS

T

BY

BR

RY/BY#

T

DS

T

DH

DQ

15-0

XXAA

XX55

XXA0

DATA

WORD

VALID

(ADDR/DATA)

1256 F09.0

Note: X can be V or V , but no other value.

IL

IH

FIGURE 10: FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM FOR WORD MODE

(FOR BYTE MODE A_-1= ADDRESS INPUT)

ADDRESS A

19-0

T

CE

BEF#

OE#

T

OES

T

OEH

T

OE

WE#

T

BY

RY/BY#

DQ

7

DATA

DATA#

DATA

1256 F10.0

FIGURE 11: FLASH DATA# POLLING TIMING DIAGRAM FOR WORD MODE

(FOR BYTE MODE A_-1= ADDRESS INPUT)

S71256-00-000

3/04

23

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

ADDRESS A

19-0

T

CE

BEF#

OE#

T

OEH

T

OE

WE#

T

BR

VALID DATA

DQ

6

TWO READ CYCLES

WITH SAME OUTPUTS

1256 F11.0

FIGURE 12: FLASH TOGGLE BIT TIMING DIAGRAM FOR WORD MODE

(FOR BYTE MODE A_-1= DON’T CARE)

T

SCE

SIX-BYTE CODE FOR CHIP-ERASE

5555

2AAA

5555

2AAA

5555

ADDRESS A

19-0

BEF#

OE#

T

WP

WE#

T

BR

T

BY

RY/BY#

DQ

15-0

XXAA

XX55

XX80

XXAA

XX55

XX10

VALID

1256 F12.0

Note: This device also supports BEF# controlled Chip-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)

X can be V_ILor V_IH,but no other value.

FIGURE 13: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM FOR WORD MODE

(FOR BYTE MODE A_-1= DON’T CARE)

S71256-00-000

3/04

24

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

T

BE

SIX-BYTE CODE FOR BLOCK-ERASE

5555 5555 2AAA

ADDRESS A

19-0

5555

2AAA

BA

X

BEF#

OE#

T

WP

WE#

T

BR

T

BY

RY/BY#

DQ

15-0

XXAA

XX55

XX80

XXAA

XX55

XX50

VALID

1256 F13.0

Note: This device also supports BEF# controlled Block-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)

BA_X= Block Address

X can be V_ILor V_IH,but no other value.

FIGURE 14: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM FOR WORD MODE

(FOR BYTE MODE A_-1= DON’T CARE)

SIX-BYTE CODE FOR SECTOR-ERASE

2AAA 5555 5555 2AAA

T

SE

5555

SA

X

ADDRESS A

19-0

BEF#

OE#

T

WP

WE#

T

BR

T

BY

RY/BY#

DQ

15-0

XXAA

XX55

XX80

XXAA

XX55

XX30

VALID

1256 F14.0

Note: This device also supports BEF# controlled Sector-Erase operation.

The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)

SA_X= Sector Address

X can be V_ILor V_IH,but no other value.

FIGURE 15: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM FOR WORD MODE

(FOR BYTE MODE A_-1= DON’T CARE)

S71256-00-000

3/04

25

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Three-Byte Sequence For Software ID Entry

ADDRESS A

5555

2AAA

5555

0000

0001

14-0

BEF#

OE#

T

IDA

T

WP

WE#

T

WPH

T

AA

DQ

15-0

Device ID

XXAA

XX55

XX90

00BF

1256 F15.0

Note: X can be V_ILor V_IH,but no other value.

Device ID - 734AH for SST34HF16x2C/DS

FIGURE 16: FLASH SOFTWARE ID ENTRY AND READ FOR WORD MODE

(FOR BYTE MODE A_-1= 0)

Three-Byte Sequence for Software ID Exit and Reset

5555

2AAA

5555

ADDRESS A

DQ

14-0

15-0

XXAA

XX55

XXF0

T

IDA

BEF#

OE#

T

WP

WE#

T

WHP

1256 F16.0

Note: X can be V or V , but no other value

IL

IH

FIGURE 17: FLASH SOFTWARE ID EXIT FOR WORD MODE

(FOR BYTE MODE A_-1= 0)

S71256-00-000

3/04

26

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

RY/BY#

0V

T

RP

RST#

BEF#/OE#

T

RHR

1256 F17.0

FIGURE 18: RST# TIMING (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

T

RY

RY/BY#

RST#

BEF#

OE#

T

RP

T

BR

1256 F18.0

FIGURE 19: RST# TIMING (DURING SECTOR- OR BLOCK-ERASE OPERATION)

S71256-00-000

3/04

27

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

V

IHT

V

OT

V

IT

INPUT

REFERENCE POINTS

OUTPUT

ILT

1256 F19.0

AC test inputs are driven at V_IHT(0.9 V_DD) for a logic “1” and V_ILT(0.1 V_DD) for a logic “0”. Measurement reference points

for inputs and outputs are V_IT(0.5 V_DD) and V_OT(0.5 V_DD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: V_IT- V_INPUTTest

V_OT- V_OUTPUTTest

V

_IHT- V_INPUTHIGH Test

V_ILT- V_INPUTLOW Test

FIGURE 20: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO TESTER

TO DUT

C

L

1256 F20.0

FIGURE 21: A TEST LOAD EXAMPLE

S71256-00-000

3/04

28

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Load Word

Address/Word

Data

Wait for end of

Program (T

Data# Polling

,

BP

bit, or Toggle bit

operation)

Program

Completed

1256 F21.0

Note: X can be V_ILor V but no other value.

IH,

FIGURE 22: WORD-PROGRAM ALGORITHM

S71256-00-000

3/04

29

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Toggle Bit

Data# Polling

Internal Timer

Program/Erase

Initiated

Program/Erase

Initiated

Program/Erase

Initiated

Read DQ

7

Read word

Wait T

,

BP

T

SCE, SE

or T

BE

Read same

word

Is DQ =

7

No

true data?

Program/Erase

Completed

Yes

No

Does DQ

match?

Program/Erase

Completed

6

Yes

Program/Erase

Completed

1256 F22.0

FIGURE 23: WAIT OPTIONS

S71256-00-000

3/04

30

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Software Product ID Entry

Command Sequence

Software ID Exit

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

Load data: XXF0H

Address: 5555H

Wait T

IDA

Return to normal

operation

Read Software ID

1256 F23.0

Note: X can be V or V but no other value.

IL

IH,

FIGURE 24: SOFTWARE PRODUCT ID COMMAND FLOWCHARTS

S71256-00-000

3/04

31

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Sec ID Query Entry

Command Sequence

Sec ID Exit

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXF0H

Address: XXH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Wait T

IDA

Load data: XXF0H

Address: 5555H

Load data: XX88H

Address: 5555H

Return to normal

operation

1256 F24.0

Wait T

IDA

Wait T

IDA

Return to normal

operation

Read Sec ID

X can be V or V but no other value

IL

IH,

FIGURE 25: SOFTWARE SEC ID COMMAND FLOWCHARTS

S71256-00-000

3/04

32

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Chip-Erase

Sector-Erase

Block-Erase

Command Sequence

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX80H

Address: 5555H

Load data: XX80H

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XX30H

Load data: XX50H

Address: SA

Address: BA

X

Wait T

BE

SCE

SE

Chip erased

to FFFFH

Sector erased

to FFFFH

Block erased

to FFFFH

1256 F25.0

Note: X can be V or V but no other value.

IL

IH,

FIGURE 26: ERASE COMMAND SEQUENCE

S71256-00-000

3/04

33

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

PRODUCT ORDERING INFORMATION

Device

Speed

Suffix1

Suffix2

SST34HF16x2X- XXX

-

XX

-

XXXX

Package Attribute

E = non-Pb

Package Modifier

P = 56 balls

S = 62 balls

Package Type

L1 = LFBGA (8mm x 10mm x 1.4mm, 0.45mm ball size)

L = LFBGA (8mm x 10mm x 1.4mm, 0.40mm ball size)

B1 = TFBGA (8mm x 10mm x 1.2mm, 0.45mm ball size)

Temperature Range

C = Commercial = 0°C to +70°C

E = Extended = -20°C to +85°C

Minimum Endurance

4 =10,000 cycles

Read Access Speed

70 = 70 ns

Version

C = x16 Mbit SRAM

D = x16 Mbit PSRAM

S = x8 Mbit SRAM

Bank Split

2 = 4 Mbit + 12 Mbit

SRAM Density

0 = No SRAM

2 = 2 Mbit

4 = 4 Mbit

8 = 8 Mbit

Flash Density

16 = 16 Mbit

Voltage

H = 2.7-3.3V

Product Series

34 = Concurrent SuperFlash + SRAM ComboMemory

S71256-00-000

3/04

34

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

Valid combinations for SST34HF1602C

SST34HF1602C-70-4C-L1P

SST34HF1602C-70-4C-L1PE

SST34HF1602C-70-4C-LS

SST34HF1602C-70-4C-LSE

SST34HF1602C-70-4C-B1P

SST34HF1602C-70-4C-B1PE

SST34HF1602C-70-4E-L1P

SST34HF1602C-70-4E-L1PE

SST34HF1602C-70-4E-LS

SST34HF1602C-70-4E-LSE

SST34HF1602C-70-4E-B1P

SST34HF1602C-70-4E-B1PE

Valid combinations for SST34HF1622C

SST34HF1622C-70-4C-L1P

SST34HF1622C-70-4C-L1PE

SST34HF1622C-70-4C-LS

SST34HF1622C-70-4C-LSE

SST34HF1622C-70-4E-L1P

SST34HF1622C-70-4E-L1PE

SST34HF1622C-70-4E-LS

SST34HF1622C-70-4E-LSE

Valid combinations for SST34HF1622S

SST34HF1622S-70-4C-L1P

SST34HF1622S-70-4C-L1PE

SST34HF1622S-70-4E-L1P

SST34HF1622S-70-4E-L1PE

Valid combinations for SST34HF1642C

SST34HF1642C-70-4C-L1P

SST34HF1642C-70-4C-L1PE

SST34HF1642C-70-4C-LS

SST34HF1642C-70-4C-LSE

SST34HF1642C-70-4E-L1P

SST34HF1642C-70-4E-L1PE

SST34HF1642C-70-4E-LS

SST34HF1642C-70-4E-LSE

Valid combinations for SST34HF1642D

SST34HF1642D-70-4C-L1P

SST34HF1642D-70-4C-L1PE

SST34HF1642D-70-4C-LS

SST34HF1642D-70-4C-LSE

SST34HF1642D-70-4E-L1P

SST34HF1642D-70-4E-L1PE

SST34HF1642D-70-4E-LS

SST34HF1642D-70-4E-LSE

Valid combinations for SST34HF1642S

SST34HF1642S-70-4C-L1P

SST34HF1642S-70-4C-L1PE

SST34HF1642S-70-4E-L1P

SST34HF1642S-70-4E-L1PE

Valid combinations for SST34HF1682D

SST34HF1682D-70-4C-L1P

SST34HF1682D-70-4C-L1PE

SST34HF1682D-70-4C-LS

SST34HF1682D-70-4C-LSE

SST34HF1682D-70-4E-L1P

SST34HF1682D-70-4E-L1PE

SST34HF1682D-70-4E-LS

SST34HF1682D-70-4E-LSE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

S71256-00-000

3/04

35

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

PACKAGING DIAGRAMS

BOTTOM VIEW

10.00 ± 0.20

5.60

TOP VIEW

0.80

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

5.60

8.00 ± 0.20

0.80

0.45 ± 0.05

(56X)

H

G F E D C B A

A

B C D E F G H

A1 CORNER

1.30 ± 0.10

SIDE VIEW

0.12

56-lfbga-L1P-8x10-450mic-3

1mm

SEATING PLANE

0.35 ± 0.05

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

56-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE CODE: L1P

S71256-00-000

3/04

36

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

BOTTOM VIEW

10.00 ± 0.20

TOP VIEW

7.20

0.80

8

7

6

5

8

7

6

5

4

3

2

8.00 ± 0.20

4

5.60

3

2

1

0.40 ± 0.05

(62X)

0.80

A

B

C

D

E

F

G

H

J

K

J

H

G

F

E

D

C

B

A

A1 CORNER

1.30 ± 0.10

SIDE VIEW

0.12

SEATING PLANE

62-lfbga-LS-8x10-400mic-3

1mm

0.32 ± 0.05

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210,

this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. The actual shape of the corners may be slightly different than as portrayed in the drawing.

62-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 8MM X 10MM

SST PACKAGE CODE: LS

S71256-00-000

3/04

37

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

SST34HF1602C / SST34HF1622C / SST34HF1642C

SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S

Advance Information

TOP VIEW

BOTTOM VIEW

5.60

10.00 0.20

0.80

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

5.60

0.80

8.00 0.20

0.45 0.05

(56X)

H

G F E D C B A

A

B C D E F G H

A1 CORNER

1.2 max

SIDE VIEW

1mm

0.12

SEATING PLANE

0.35 0.05

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm ( 0.05 mm)

56-tfbga-B1P-8x10-450mic-1

56-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM

SST PACKAGE CODE: B1P

TABLE 16: REVISION HISTORY

Number

Description

Date

00

Mar 2004

•

Initial Release

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

S71256-00-000

3/04

38

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LFBGA,	针数：	62
Reach Compliance Code：	unknown	HTS代码：	8542.32.00.71
风险等级：	5.67	其他特性：	SRAM IS ORGANIZED AS 512K X 16 / 1024K X 8; FLASH CAN ALSO BE ORGANIZED AS 2M X 8
JESD-30 代码：	R-PBGA-B62	长度：	10 mm
内存密度：	16777216 bit	内存集成电路类型：	MEMORY CIRCUIT
内存宽度：	16	功能数量：	1
端子数量：	62	字数：	1048576 words
字数代码：	1000000	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-20 °C
组织：	1MX16	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
宽度：	8 mm	Base Number Matches：	1

型号	制造商	描述	价格	文档
SST34HF1682D-70-4E-LSE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格
SST34HF1682S-70-4C-B1PE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格
SST34HF1682S-70-4C-B1SE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格
SST34HF1682S-70-4C-L1PE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格
SST34HF1682S-70-4C-L1SE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格
SST34HF1682S-70-4C-LPE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格
SST34HF1682S-70-4C-LSE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格
SST34HF1682S-70-4E-B1PE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格
SST34HF1682S-70-4E-B1SE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格
SST34HF1682S-70-4E-L1PE	SST	16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory	获取价格

SST34HF1682D-70-4E-LS

SST34HF1682D-70-4E-LS 概述

SST34HF1682D-70-4E-LS 规格参数

SST34HF1682D-70-4E-LS 数据手册

SST34HF1682D-70-4E-LS 相关器件

SST34HF1682D-70-4E-LS 相关文章

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