SST39LF016-55-4C-EIE [SILICON]
Flash, 2MX8, 55ns, PDSO40;型号: | SST39LF016-55-4C-EIE |
厂家: | SILICON |
描述: | Flash, 2MX8, 55ns, PDSO40 光电二极管 |
文件: | 总26页 (文件大小:860K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
8 Mbit / 16 Mbit (x8) Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
SST39LF/VF080 / 0163.0 & 2.7V 8Mb / 16Mb (x8) MPF memories
Data Sheet
FEATURES:
•
•
Organized as 1M x8 / 2M x8
Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF080/016
– 2.7-3.6V for SST39VF080/016
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption:
– Active Current: 15 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
Sector-Erase Capability
– Uniform 4 KByte sectors
Block-Erase Capability
– Uniform 64 KByte blocks
Fast Read Access Time:
•
Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
•
•
15 seconds (typical) for SST39LF/VF080
30 seconds (typical) for SST39LF/VF016
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
•
•
•
•
•
CMOS I/O Compatibility
JEDEC Standard
– Flash EEPROM Pinouts and command sets
Packages Available
– 40-lead TSOP (10mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
•
– 55 ns for SST39LF080/016
– 70 and 90 ns for SST39VF080/016
•
Latched Address and Data
PRODUCT DESCRIPTION
The SST39LF/VF080/016 devices are 1M x8 / 2M x8
CMOS Multi-Purpose Flash (MPF) manufactured with
SST’s proprietary, high performance CMOS SuperFlash
technology. The split-gate cell design and thick oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39LF080/
016 write (Program or Erase) with a 3.0-3.6V power supply.
The SST39VF080/016 write (Program or Erase) with a 2.7-
3.6V power supply. They conform to JEDEC standard
pinouts for x8 memories.
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. They also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
Featuring high performance Byte-Program, the SST39LF/
VF080/016 devices provide a typical Byte-Program time of
14 µsec. The devices use Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect
against inadvertent write, they have on-chip hardware and
Software Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
To meet high density, surface mount requirements, the
SST39LF/VF080/016 are offered in 40-lead TSOP and 48-
ball TFBGA packaging. See Figures 1 and 2 for pinouts.
The SST39LF/VF080/016 devices are suited for applica-
tions that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than alter-
©2002 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Multi-Purpose Flash and MPF are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71146-03-000 2/02
1
396
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
operation, the host is free to perform additional tasks. Any
commands issued during the internal Program operation
are ignored.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39LF/VF080/016 offer both Sector-
Erase and Block-Erase mode. The sector architecture is
based on uniform sector size of 4 KByte. The Block-Erase
mode is based on uniform block size of 64 KByte. The Sec-
tor-Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms. Any commands issued during the Sector-
or Block-Erase operation are ignored.
The SST39LF/VF080/016 also have the Auto Low Power
mode which puts the device in a near standby mode after
data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 15 mA to
typically 4 µA. The Auto Low Power mode reduces the typi-
cal IDD active read current to the range of 1 mA/MHz of
Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto Low
Power mode after power-up with CE# held steadily low until
the first address transition or CE# is driven high.
Read
The Read operation of the SST39LF/VF080/016 is con-
trolled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
(Figure 3).
Chip-Erase Operation
The SST39LF/VF080/016 provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 8 for timing diagram,
and Figure 19 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Byte-Program Operation
The SST39LF/VF080/016 are programmed on a byte-by-
byte basis. Before programming, the sector where the byte
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load byte address and byte data. During the Byte-
Program operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Pro-
gram operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Program
operation, once initiated, will be completed within 20 µs.
See Figures 4 and 5 for WE# and CE# controlled Program
operation timing diagrams and Figure 16 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
Write Operation Status Detection
The SST39LF/VF080/016 provide two software means to
detect the completion of a write (Program or Erase) cycle, in
order to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and
Toggle Bit (DQ6). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
2
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
The actual completion of the nonvolatile write is asynchro-
Hardware Data Protection
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39LF/VF080/016 provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST39LF/VF080/016 devices are
shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to Read mode within TRC.
Data# Polling (DQ7)
When the SST39LF/VF080/016 are in the internal Program
operation, any attempt to read DQ7 will produce the com-
plement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase opera-
tion, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 17 for a flowchart.
Common Flash Memory Interface (CFI)
The SST39LF/VF080/016 also contain the CFI information
to describe the characteristics of the device. In order to
enter the CFI Query mode, the system must load the three-
byte sequence, similar to the Software ID Entry command.
The last byte cycle of this command loads 98H (CFI Query
command) to address 5555H. Once the device enters the
CFI Query mode, the system can read CFI data at the
addresses given in Tables 5 through 8. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diagram and Figure 17 for a flowchart.
Data Protection
The SST39LF/VF080/016 provide both hardware and
software features to protect nonvolatile data from inad-
vertent writes.
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
3
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
Product Identification
The Product Identification mode identifies the device as the
Product Identification Mode Exit/
CFI Mode Exit
SST39LF080,
SST39VF080,
SST39LF016,
and
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 13 for timing waveform and Figure 18 for a
flowchart.
SST39VF016 and manufacturer as SST. This mode may
be accessed by software operations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple manufactur-
ers in the same socket. For details, see Table 4 for software
operation, Figure 11 for the Software ID Entry and Read
timing diagram and Figure 18 for the Software ID Entry
command sequence flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
0000H
BFH
SST39LF/VF080
SST39LF/VF016
0001H
0001H
D8H
D9H
T1.2 396
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X-Decoder
Memory
Address
Address Buffer & Latches
Control Logic
Y-Decoder
CE#
I/O Buffers and Data Latches
OE#
WE#
DQ - DQ
7
0
396 ILL B1.2
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
4
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
SST39LF/VF160 SST39LF/VF080
SST39LF/VF080 SST39LF/VF016
A16
A15
A14
A13
A12
A11
A9
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
A17
V
NC
V
SS
SS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
A19
A10
DQ7
DQ6
DQ5
DQ4
A8
A8
Standard Pinout
Top View
WE#
NC
NC
NC
A18
A7
A6
A5
A4
A3
WE#
NC
NC
NC
A18
A7
A6
A5
A4
A3
9
10
11
12
13
14
15
16
17
18
19
20
V
V
NC
V
V
NC
DD
DD
DD
DD
Die Up
DQ3
DQ2
DQ1
DQ0
OE#
DQ3
DQ2
DQ1
DQ0
OE#
V
CE#
V
CE#
SS
SS
A2
A1
A2
A1
A0
A0
396 ILL F01.2
FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP
TOP VIEW (balls facing down)
SST39LF/VF080
TOP VIEW (balls facing down)
SST39LF/VF016
6
6
5
4
3
2
1
A14 A13 A15 A16 A17 NC
NC
V
A14 A13 A15 A16 A17 NC A20
V
SS
SS
5
4
3
2
1
A9 A8 A11 A12 A19 A10 DQ6 DQ7
A9 A8 A11 A12 A19 A10 DQ6 DQ7
WE# NC
NC NC
NC
NC
NC DQ5 NC
NC DQ2 DQ3
A5 DQ0 NC
V
DQ4
NC
WE# NC
NC NC
NC
NC
NC DQ5 NC
NC DQ2 DQ3
A5 DQ0 NC
V
V
DQ4
NC
DD
DD
DD
DD
V
A7 A18 A6
NC DQ1
A7 A18 A6
NC DQ1
A3
A4
A2
A1
A0 CE# OE#
V
A3
A4
A2
A1
A0 CE# OE# V
SS
SS
A
B
C
D
E
F
G
H
A
B
C
D
E F G H
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
5
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the
sector. During Block-Erase AMS-A16 address lines will select the block.
DQ7-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
3.0-3.6V for SST39LF080/016
2.7-3.6V for SST39VF080/016
VSS
NC
Ground
No Connection
Unconnected pins.
T2.3 396
1. AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016
TABLE 3: OPERATION MODES SELECTION
Mode
Read
CE#
VIL
OE#
VIL
WE#
VIH
VIL
DQ
DOUT
DIN
X1
Address
AIN
Program
Erase
VIL
VIH
VIH
AIN
VIL
VIL
Sector or Block address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 4
T3.4 396
1. X can be VIL or VIH, but no other value.
©2002 Silicon Storage Technology, Inc.
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6
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data
5555H AAH 2AAAH 55H 5555H A0H Data
WA2
Byte-Program
Sector-Erase
3
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
BAX
30H
50H
3
Block-Erase
Chip-Erase
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
5555H AAH 2AAAH 55H 5555H 90H
Software ID Entry4,5
CFI Query Entry4
5555H AAH 2AAAH 55H 5555H 98H
Software ID Exit6/
CFI Exit
XXH
F0H
Software ID Exit6/
CFI Exit
5555H AAH 2AAAH 55H 5555H F0H
T4.3 396
1. Address format A14-A0 (Hex),
Addresses A19-A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF080.
Addresses A20-A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF016.
2. WA = Program Byte address
3. SAX for Sector-Erase; uses AMS-A12 address lines
BAX for Block-Erase; uses AMS-A16 address lines
AMS = Most significant address
AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0
SST39LF/VF080 Device ID = D8H, is read with A0 = 1
SST39LF/VF016 Device ID = D9H, is read with A0 = 1
6. Both Software ID Exit operations are equivalent
1
TABLE 5: CFI QUERY IDENTIFICATION STRING FOR SST39LF/VF080/016
Address
10H
11H
12H
13H
14H
15H
16H
17H
Data
51H
52H
59H
01H
07H
00H
00H
00H
00H
00H
00H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
18H
19H
1AH
T5.3 396
1. Refer to CFI publication 100 for more details.
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
7
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39LF/VF080/016
Address
Data
27H1
30H1
36H
Data
1BH
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
00H
00H
04H
00H
04H
06H
01H
00H
01H
01H
VPP min (00H = no VPP pin)
VPP max (00H = no VPP pin)
Typical time out for Byte-Program 2N µs (24 = 16 µs)
Typical time out for min size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T6.1 396
1. 0030H for SST39LF080/016 and 0027H for SST39VF080/016
TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF080
Address
27H
28H
Data
14H
00H
00H
00H
00H
02H
FFH
00H
10H
00H
0FH
00H
00H
01H
Data
Device size = 2N Bytes (14H = 20; 220 = 1 MByte)
Flash Device Interface description; 0000H = x8-only asynchronous interface
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 255 + 1 = 256 sectors (00FFH = 255)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 15 + 1 = 16 blocks (000FH = 15)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.0 396
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
8
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
TABLE 8: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF016
Address
27H
28H
Data
15H
00H
00H
00H
00H
02H
FFH
01H
10H
00H
1FH
00H
00H
01H
Data
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 0000H = x8-only asynchronous interface
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 511 + 1 = 512 sectors (01FFH = 511)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001FH = 31)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T8.2 396
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
9
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE FOR SST39LF080/016
Range
Ambient Temp
VDD
Commercial
0°C to +70°C
3.0-3.6V
OPERATING RANGE FOR SST39VF080/016
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF080/016
Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF080/016
See Figures 14 and 15
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
10
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
TABLE 9: DC OPERATING CHARACTERISTICS
VDD = 3.0-3.6V FOR SST39LF080/016 AND 2.7-3.6V FOR SST39VF080/016
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input=VIL/VIH, at f=1/TRC Min
VDD=VDD Max
IDD
Power Supply Current
Read
15
20
20
20
mA
mA
µA
CE#=OE#=VIL, WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
Program and Erase
Standby VDD Current
Auto Low Power
ISB
CE#=VIHC, VDD=VDD Max
IALP
µA
CE#=VILC, VDD=VDD Max
All inputs=VIHC or VILC WE#=VIHC
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
10
0.8
0.3
VIL
VILC
VIH
VIHC
VOL
VOH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7VDD
V
VDD=VDD Max
Input High Voltage (CMOS)
Output Low Voltage
VDD-0.3
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
Output High Voltage
VDD-0.2
V
T9.2 396
TABLE 10: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
µs
µs
1
TPU-WRITE
100
T10.1 396
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T11.0 396
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T12.1 396
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
11
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
AC CHARACTERISTICS
TABLE 13: READ CYCLE TIMING PARAMETERS
VDD = 3.0-3.6V FOR SST39LF080/016 AND 2.7-3.6V FOR SST39VF080/016
SST39LF080/016-55 SST39VF080/016-70 SST39VF080/016-90
Symbol Parameter
Min
Max
Min
Max
Min
Max
Units
ns
TRC
TCE
TAA
Read Cycle Time
55
70
90
Chip Enable Access Time
Address Access Time
55
55
30
70
70
35
90
90
45
ns
ns
TOE
TCLZ
TOLZ
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
1
0
0
0
0
0
0
ns
ns
1
TCHZ
TOHZ
15
15
20
20
30
30
ns
1
ns
1
TOH
0
0
0
ns
T13.3 396
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter
Min
Max
Units
TBP
Byte-Program Time
20
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
30
0
TAH
TCS
TCH
TOES
TOEH
TCP
0
0
10
40
40
30
30
30
0
TWP
WE# Pulse Width
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
1
TCPH
TDS
1
TDH
Data Hold Time
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
TSE
TBE
Block-Erase
25
TSCE
Chip-Erase
100
T14.0 396
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
12
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
CE#
OE#
WE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
7-0
DATA VALID
DATA VALID
Note:
A
A
= Most significant address
396 ILL F02.1
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 3: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
WE#
T
AH
T
DH
T
WP
T
T
AS
DS
T
WPH
OE#
CE#
T
CH
T
CS
DQ
7-0
AA
55
A0
DATA
SW0
SW1
SW2
BYTE
(ADDR/DATA)
396 ILL F03.1
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
13
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
7-0
AA
55
A0
DATA
SW0
SW1
SW2
BYTE
(ADDR/DATA)
396 ILL F04.1
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
OEH
T
OE
DQ
7
DATA
DATA#
DATA#
DATA
396 ILL F05.1
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 6: DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
14
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
T
OE
OEH
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
396 ILL F06.1
Note:
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
80
AA
55
10
SW0
SW1
SW2
SW3
SW4
SW5
396 ILL F08.2
Note: The device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 14)
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
15
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
5555 5555 2AAA
5555
2AAA
BA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
AA
55
SW4
50
SW0
SW2
SW3
SW5
396 ILL F09.2
Note: The device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 14)
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555
2AAA
5555
5555
2AAA
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
80
AA
55
30
SW0
SW1
SW2
SW3
SW4
SW5
396 ILL F10.2
Note: The device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 14)
A
A
= Most significant address
MS
MS
= A for SST39LF/VF080 and A for SST39LF/VF016.
19 20
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
16
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
IDA
T
WP
AA
T
WPH
55
SW1
T
AA
DQ
7-0
90
BF
Device ID
SW0
SW2
Note: Device ID = D9H for SST39LF/VF016
D8H for SST39LF/VF080
396 ILL F11.3
FIGURE 11: SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
5555
2AAA
5555
14-0
CE#
OE#
WE#
T
IDA
T
WP
AA
T
WPH
55
SW1
T
AA
DQ
7-0
98
SW0
SW2
396 ILL F12.0
FIGURE 12: CFI QUERY ENTRY AND READ
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
17
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
14-0
DQ
AA
55
F0
7-0
T
IDA
CE#
OE#
T
WP
WE#
T
WHP
SW0
SW1
SW2
396 ILL F13.0
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
18
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
396 ILL F14.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
396 ILL F15.1
FIGURE 15: A TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
19
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
Start
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: A0H
Address: 5555H
Load Byte
Address/Byte
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
396 ILL F16.1
FIGURE 16: BYTE-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
20
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read byte
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
byte
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
396 ILL F17.0
FIGURE 17: WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
21
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
CFI Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: F0H
Address: XXH
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Wait T
IDA
Load data: 98H
Address: 5555H
Load data: 90H
Address: 5555H
Load data: F0H
Address: 5555H
Return to normal
operation
Wait T
Wait T
Wait T
IDA
IDA
IDA
Return to normal
operation
Read CFI data
Read Software ID
396 ILL F18.1
FIGURE 18: SOFTWARE ID/CFI COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
22
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 80H
Address: 5555H
Load data: 80H
Address: 5555H
Load data: 80H
Address: 5555H
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 10H
Address: 5555H
Load data: 30H
Load data: 50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFH
Sector erased
to FFH
Block erased
to FFH
396 ILL F19.1
FIGURE 19: ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
23
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST39VFxxx
-
XX
-
XX
-
XX
Package Modifier
I = 40 leads
K = 48 balls
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
E = TSOP (type 1, die up, 10mm x 20mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Device Density
016 = 16 Mbit
080 = 8 Mbit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Valid combinations for SST39LF080
SST39LF080-55-4C-EI SST39LF080-55-4C-B3K
Valid combinations for SST39VF080
SST39VF080-70-4C-EI
SST39VF080-90-4C-EI
SST39VF080-70-4C-B3K
SST39VF080-90-4C-B3K
SST39VF080-70-4I-EI
SST39VF080-90-4I-EI
SST39VF080-70-4I-B3K
SST39VF080-90-4I-B3K
Valid combinations for SST39LF016
SST39LF016-55-4C-EI
SST39LF016-55-4C-B3K
Valid combinations for SST39VF016
SST39VF016-70-4C-EI
SST39VF016-90-4C-EI
SST39VF016-70-4C-B3K
SST39VF016-90-4C-B3K
SST39VF016-70-4I-EI
SST39VF016-90-4I-EI
SST39VF016-70-4I-B3K
SST39VF016-90-4I-B3K
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
24
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
10.10
9.90
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
40-tsop-EI-7
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 20MM
SST PACKAGE CODE: EI
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
25
8 Mbit / 16 Mbit Multi-Purpose Flash
SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016
Data Sheet
BOTTOM VIEW
8.00 0.20
5.60
TOP VIEW
0.45 0.05
0.80
(48X)
6
5
6
5
4
3
2
1
4.00
4
3
6.00 0.20
2
1
0.80
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
48-tfbga-B3K-6x8-450mic-2
1mm
SEATING PLANE
0.35 0.05
Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1',
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2002 Silicon Storage Technology, Inc.
S71146-03-000 2/02 396
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