SST39VF160-70-4C-EKE [SILICON]
Flash, 1MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, MO-142DD, TSOP1-48;型号: | SST39VF160-70-4C-EKE |
厂家: | SILICON |
描述: | Flash, 1MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, MO-142DD, TSOP1-48 光电二极管 内存集成电路 闪存 |
文件: | 总24页 (文件大小:728K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16 Mbit (x16) Multi-Purpose Flash
SST39LF160 / SST39VF160
SST39LF/VF1603.0 & 2.7V 16Mb (x16) MPF memories
Data Sheet
FEATURES:
•
•
Organized as 1M x16
Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF160
– 2.7-3.6V for SST39VF160
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption
– Active Current: 15 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
Sector-Erase Capability
– Uniform 2 KWord sectors
Fast Read Access Time
•
Fast Erase and Word-Program
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 15 seconds (typical) for
SST39LF/VF160
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
•
•
•
•
– Toggle Bit
– Data# Polling
•
•
•
•
CMOS I/O Compatibility
JEDEC Standard
– Flash EEPROM Pinouts and command sets
Packages Available
– 55 ns for SST39LF160
– 70 and 90 ns for SST39VF160
•
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
•
Latched Address and Data
PRODUCT DESCRIPTION
The SST39LF/VF160 devices are 1M x16 CMOS Multi-
Purpose Flash (MPF) manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39LF160 write (Program or
Erase) with a 3.0-3.6V power supply. The SST39VF160
write (Program or Erase) with a 2.7-3.6V power supply.
These devices conform to JEDEC standard pinouts for x16
memories.
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
Featuring high performance Word-Program, the
SST39LF/VF160 devices provide a typical Word-Pro-
gram time of 14 µsec. These devices use Toggle Bit or
Data# Polling to indicate the completion of Program
operation. To protect against inadvertent write, they
have on-chip hardware and Software Data Protection
schemes. Designed, manufactured, and tested for a
wide spectrum of applications, these devices are
offered with a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
To meet high density, surface mount requirements, the
SST39LF/VF160 are offered in 48-lead TSOP and 48-ball
TFBGA packages. See Figure 1 for pinouts.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39LF/VF160 devices are suited for applications
that require convenient and economical updating of pro-
gram, configuration, or data memory. For all system appli-
cations, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than alter-
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
©2002 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Multi-Purpose Flash and MPF are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71145-02-000 2/02
1
399
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
The SST39LF/VF160 also have the Auto Low Power
mode which puts the device in a near standby mode after
data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 15 mA to
typically 4 µA. The Auto Low Power mode reduces the typi-
cal IDD active read current to the range of 1 mA/MHz of
read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto Low
Power mode after power-up with CE# held steadily low until
the first address transition or CE# is driven high.
is based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 8 and 9 for tim-
ing waveforms. Any commands issued during the Sector-
or Block-Erase operation are ignored.
Read
The Read operation of the SST39LF/VF160 is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 2).
Chip-Erase Operation
The SST39LF/VF160 provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 7 for timing diagram,
and Figure 18 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Word-Program Operation
The SST39LF/VF160 are programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within 20
µs. See Figures 3 and 4 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 15 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during the internal Program opera-
tion are ignored.
Write Operation Status Detection
The SST39LF/VF160 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Sector-/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39LF/VF160 offer both Sector-Erase
and Block-Erase modes. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
2
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Data# Polling (DQ7)
Hardware Data Protection
When the SST39LF/VF160 are in the internal Program
operation, any attempt to read DQ7 will produce the com-
plement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase opera-
tion, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of sixth WE# (or CE#) pulse. See Figure 5 for
Data# Polling timing diagram and Figure 16 for a flowchart.
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39LF/VF160 provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
4 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to Read mode within TRC. The contents of DQ15-
DQ8 can be VIL or VIH, but no other value, during any SDP
command sequence.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The Toggle Bit is valid after the rising edge of
fourth WE# (or CE#) pulse for Program operation. For Sec-
tor-, Block- or Chip-Erase, the Toggle Bit is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Toggle Bit timing diagram and Figure 16 for a flowchart.
Data Protection
The SST39LF/VF160 provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
3
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Common Flash Memory Interface (CFI)
TABLE 1: PRODUCT IDENTIFICATION
Address
The SST39LF/VF160 also contain the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must load the three-byte
sequence, similar to the Software ID Entry command. The
last byte cycle of this command loads 98H (CFI Query
command) to address 5555H. Once the device enters the
CFI Query mode, the system can read CFI data at the
addresses given in Tables 5 through 7. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
Data
Manufacturer’s ID
Device ID
0000H
00BFH
SST39LF/VF160
0001H
2782H
T1.2 399
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 12 for timing waveform, and Figure 17 for a
flowchart.
Product Identification
The Product Identification mode identifies the devices as
the SST39LF/VF160 and manufacturer as SST. This mode
may be accessed by software operations. Users may use
the Software Product Identification operation to identify the
part (i.e., using the device ID) when using multiple manu-
facturers in the same socket. For details, see Table 4 for
software operation, Figure 10 for the Software ID Entry and
Read timing diagram, and Figure 17 for the Software ID
Entry command sequence flowchart.
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X-Decoder
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
I/O Buffers and Data Latches
Control Logic
OE#
WE#
DQ - DQ
15
0
399 ILL B1.1
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
4
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
V
SS
DQ15
DQ7
TOP VIEW (balls facing down)
SST39LF/VF160
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
6
5
4
3
2
1
A8
A13 A12 A14 A15 A16 NC DQ15 V
SS
Standard Pinout
Top View
A19
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A9
WE# NC
NC NC A18 NC DQ2 DQ10 DQ11 DQ3
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
NC A19 DQ5 DQ12 DQ4
V
DD
V
Die Up
DD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
A3
A4
A2
A1
A0 CE# OE# V
SS
A
B
C
D
E F G H
V
CE#
SS
A0
SST39LF160/SST39VF160
399 ILL F01.2
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP AND 48-BALL TFBGA
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
A19-A0
Address Inputs
To provide memory addresses. During Sector-Erase A19-A11 address lines will select the
sector. During Block-Erase, A19-A15 address line will select the block.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low
To gate the data output buffers
To control the Write operations
To provide power supply voltage:
3.0-3.6V for SST39LF160
2.7-3.6V for SST39VF160
VSS
NC
Ground
No Connection
Unconnected pins
T2.3 399
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
5
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TABLE 3: OPERATION MODES SELECTION
Mode
Read
CE#
VIL
OE#
VIL
WE#
VIH
VIL
DQ
DOUT
DIN
X1
Address
AIN
Program
Erase
VIL
VIH
VIH
AIN
VIL
VIL
Sector or Block address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 4
T3.4 399
1. X can be VIL or VIH, but no other value
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
5555H AAH 2AAAH 55H 5555H A0H Data
WA3
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SAX
BAX
30H
50H
4
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H
CFI Query Entry5
Software ID Exit7/
CFI Exit
5555H AAH 2AAAH 55H 5555H 98H
XXH F0H
Software ID Exit7/
CFI Exit
5555H AAH 2AAAH 55H 5555H F0H
T4.5 399
1. Address format A14-A0 (Hex), Addresses A19-A15 can be VIL or VIH, but no other value, for Command sequence for SST39LF/VF160
2. DQ15 - DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program word address
4. SAX for Sector-Erase; uses A19-A11 address lines
BAX, for Block-Erase; uses A19-A15 address lines
5. The device does not remain in Software Product ID mode if powered down.
6. With A19-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
SST39LF/VF160 Device ID = 2782H, is read with A0 = 1
7. Both Software ID Exit operations are equivalent
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
6
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
1
TABLE 5: CFI QUERY IDENTIFICATION STRING FOR SST39LF/VF160
Address
10H
11H
12H
13H
14H
15H
16H
17H
Data
Data
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
18H
19H
1AH
T5.0 399
1. Refer to CFI publication 100 for more details.
TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39LF/VF160
Address
Data
Data
1BH
0027H1
0030H1
0036H
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
0000H
0000H
0004H
0000H
0004H
0006H
0001H
0000H
0001H
0001H
VPP min (00H = no VPP pin)
VPP max (00H = no VPP pin)
Typical time out for Word-Program 2N µs (24 = 16 µs)
Typical time out for min size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T6.2 399
1. 0030H for SST39LF160 and 0027H for SST39VF160
TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF160
Address
27H
28H
Data
Data
0015H
0001H
0000H
0000H
0000H
0002H
00FFH
0001H
0010H
0000H
003FH
0000H
0000H
0001H
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 155 + 1 = 512 sectors (01FFH = 511)
z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001FH = 31)
z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T7.3 399
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
7
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE: SST39LF160
Range
Ambient Temp
VDD
Commercial
0°C to +70°C
3.0-3.6V
OPERATING RANGE: SST39VF160
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF160
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF160
See Figures 13 and 14
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
8
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TABLE 8: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF160 AND 2.7-3.6V FOR SST39VF160
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
IDD
Power Supply Current
VDD=VDD Max
Read
20
25
20
20
mA
mA
µA
CE#=OE#=VIL,WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
CE#=VIHC, VDD=VDD Max
Program and Erase
Standby VDD Current
Auto Low Power Current
ISB
IALP
µA
CE#=VIHC, VDD=VDD Max,
all inputs = VIHC or VILC, WE#=VIHC
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
10
0.8
0.3
VIL
VILC
VIH
VIHC
VOL
VOH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7 VDD
VDD-0.3
V
VDD=VDD Max
Input High Voltage (CMOS)
Output Low Voltage
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH = -100 µA, VDD=VDD Min
Output High Voltage
VDD-0.2
V
T8.3 399
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
µs
µs
1
TPU-WRITE
100
T9.0 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T10.0 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T11.1 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
9
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
AC CHARACTERISTICS
TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF160 AND 2.7-3.6V FOR SST39VF160
SST39LF160-55 SST39VF160-70 SST39VF160-90
Symbol Parameter
Min
Max
Min
Max
Min
Max
Units
ns
TRC
TCE
TAA
Read Cycle Time
55
70
90
Chip Enable Access Time
Address Access Time
55
55
30
70
70
35
90
90
45
ns
ns
TOE
TCLZ
TOLZ
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
1
0
0
0
0
0
0
ns
ns
1
TCHZ
TOHZ
15
15
20
20
30
30
ns
1
ns
1
TOH
0
0
0
ns
T12.2 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter
Min
Max
Units
µs
TBP
Word-Program Time
20
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
30
0
ns
TAH
ns
TCS
ns
TCH
TOES
TOEH
TCP
0
ns
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
TDS
ns
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
TBE
Block-Erase
25
TSCE
Chip-Erase
100
ms
T13.0 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
10
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
T
T
AA
RC
ADDRESS A
19-0
CE#
OE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
399 ILL F03.2
FIGURE 2: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
19-0
T
AH
T
DH
T
WP
WE#
OE#
CE#
T
T
AS
DS
T
WPH
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
399 ILL F04.3
Note: X can be V or V , but no other value
IL
IH
FIGURE 3: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
11
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
19-0
T
AH
T
DH
T
CP
CE#
T
T
AS
DS
T
CPH
OE#
T
CH
WE#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
399 ILL F05.3
Note: X can be V or V , but no other value
IL
IH
FIGURE 4: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
19-0
T
CE
CE#
OE#
T
OES
T
OEH
T
OE
WE#
DQ
7
DATA
DATA#
DATA#
DATA
399 ILL F06.2
FIGURE 5: DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
12
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
ADDRESS A
19-0
T
CE
CE#
OE#
T
OES
T
T
OE
OEH
WE#
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
399 ILL F07.2
FIGURE 6: TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
19-0
CE#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
399 ILL F08.3
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 13)
X can be V or V , but no other value
IL
IH
FIGURE 7: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
13
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
5555 5555 2AAA
5555
2AAA
BA
ADDRESS A
X
19-0
CE#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
399 ILL F17.3
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 13)
BA = Block Address
X
X can be V or V , but no other value
IL
IH
FIGURE 8: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555
2AAA
5555
5555
2AAA
SA
ADDRESS A
X
19-0
CE#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
399 ILL F18.3
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 13)
SA = Sector Address
X
X can be V or V , but no other value
IL
IH
FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
14
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BF
Device ID
399 ILL F09.4
Device ID = 2782H for SST39LF/VF160
Note: X can be V or V , but no other value
IL
IH
FIGURE 10: SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
5555
2AAA
5555
14-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX98
SW2
399 ILL F20.1
Note: X can be V or V , but no other value
IL
IH
FIGURE 11: CFI QUERY AND READ
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
15
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
DQ
14-0
XXAA
XX55
XXF0
15-0
T
IDA
CE#
OE#
T
WP
WE#
T
WHP
SW0
SW1
SW2
399 ILL F10.1
Note: X can be V or V , but no other value
IL
IH
FIGURE 12: SOFTWARE ID EXIT/CFI EXIT
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
16
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
399 ILL F11.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
399 ILL F12.1
FIGURE 14: A TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
17
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
399 ILL F13.3
Note: X can be V or V , but no other value
IL
IH
FIGURE 15: WORD-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
18
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
word
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
399 ILL F14.0
FIGURE 16: WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
19
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
CFI Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait T
IDA
Load data: XX98H
Address: 5555H
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait T
Wait T
Wait T
IDA
IDA
IDA
Return to normal
operation
Read CFI data
Read Software ID
399 ILL F15.2
Note: X can be V or V , but no other value
IL
IH
FIGURE 17: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
20
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
399 ILL F16.2
Note: X can be V or V , but no other value
IL
IH
FIGURE 18: ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
21
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST39xFxxx
-
XXX
-
XX
-
XX
Package Modifier
K = 48 leads or balls
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
E = TSOP (type 1, die up, 12mm x 20mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Device Density
160 = 16 Mbit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Valid combinations for SST39LF160
SST39LF160-55-4C-EK SST39LF160-55-4C-B3K
Valid combinations for SST39VF160
SST39VF160-70-4C-EK
SST39VF160-90-4C-EK
SST39VF160-70-4C-B3K
SST39VF160-90-4C-B3K
SST39VF160-70-4I-EK
SST39VF160-90-4I-EK
SST39VF160-70-4I-B3K
SST39VF160-90-4I-B3K
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
22
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM
SST PACKAGE CODE: EK
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
23
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
BOTTOM VIEW
8.00 0.20
5.60
0.80
TOP VIEW
0.45 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.80
6.00 0.20
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
48-tfbga-B3K-6x8-450mic-2
1mm
SEATING PLANE
0.35 0.05
Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1',
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2002 Silicon Storage Technology, Inc.
S71145-02-000 2/02 399
24
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