SST39VF1602C-70-4I-EKE [SILICON]
Flash, 1MX16, 70ns, PDSO48, TSOP-48;
| 型号： | SST39VF1602C-70-4I-EKE |
| 厂家： | 
SILICON |
| 描述： | Flash, 1MX16, 70ns, PDSO48, TSOP-48 光电二极管 |
| 文件： | 总33页 (文件大小：901K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Mbit (x16) Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories
Data Sheet
FEATURES:
•
•
Organized as 1M x16: SST39VF1601C/1602C
Single Voltage Read and Write Operations
– 2.7-3.6V
•
•
•
Security-ID Feature
– SST: 128 bits; User: 128 words
Fast Read Access Time:
– 70 ns
•
•
Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 8 KWord)
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
•
– Bottom Block-Protection (bottom 8 KWord)
– Toggle Bits
•
•
Sector-Erase Capability
– Uniform 2 KWord sectors
Block-Erase Capability
– Flexible block architecture; one 8-, two 4-, one
16-, and thirty one 32-KWord blocks
– Data# Polling
– Ready/Busy# Pin
•
•
CMOS I/O Compatibility
JEDEC Standard
– Flash EEPROM Pinouts and command sets
•
•
•
•
Chip-Erase Capability
•
Packages Available
Erase-Suspend/Erase-Resume Capabilities
Hardware Reset Pin (RST#)
Latched Address and Data
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
•
All devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39VF1601C and SST39VF1602C devices are
1M x16 CMOS Multi-Purpose Flash Plus (MPF+) manu-
factured with SST proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST39VF160xC writes (Program or Erase) with a
2.7-3.6V power supply. These devices conform to JEDEC
standard pinouts for x16 memories.
reliability, while lowering power consumption. They inher-
ently use less energy during Erase and Program than alter-
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
Featuring high performance Word-Program, the
SST39VF1601C/1602C devices provide a typical Word-
Program time of 7 µsec. These devices use Toggle Bit,
Data# Polling, or the RY/BY# pin to indicate the completion
of Program operation. To protect against inadvertent write,
they have on-chip hardware and Software Data Protection
schemes. Designed, manufactured, and tested for a wide
spectrum of applications, these devices are offered with a
guaranteed typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
To meet high density, surface mount requirements, the
SST39VF1601C/1602C are offered in 48-lead TSOP, 48-
ball TFBGA, and 48-ball WFBGA packages. See Figures
2, 3, and 4 for pin assignments.
The SST39VF1601C/1602C devices are suited for applica-
tions that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
©2010 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
S71380-04-000
1
05/10
These specifications are subject to change without notice.
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Any commands issued during the internal Program opera-
tion are ignored. During the command sequence, WP#
should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF1601C/1602C offer both Sec-
tor-Erase and Block-Erase mode.
The SST39VF1601C/1602C also have the Auto Low
Power mode which puts the device in a near standby mode
after data has been accessed with a valid Read operation.
This reduces the IDD active read current from typically 9 mA
to typically 3 µA. The Auto Low Power mode reduces the
typical IDD active read current to the range of 2 mA/MHz of
Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
The sector architecture is based on a uniform sector size of
2 KWord. The Block-Erase mode is based on non-uniform
block sizes—thirty-one 32 KWord, one 16 KWord, two 4
KWord, and one 8 KWord blocks. See Figure 5 for top and
bottom boot device block addresses. The Sector-Erase
operation is initiated by executing a six-byte command
sequence with Sector-Erase command (50H) and sector
address (SA) in the last bus cycle. The Block-Erase opera-
tion is initiated by executing a six-byte command sequence
with Block-Erase command (30H) and block address (BA)
in the last bus cycle. The sector or block address is latched
on the falling edge of the sixth WE# pulse, while the com-
mand (30H or 50H) is latched on the rising edge of the
sixth WE# pulse. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase operation can be
determined using either Data# Polling or Toggle Bit meth-
ods. See Figures 12 and 13 for timing waveforms and Fig-
ure 26 for the flowchart. Any commands issued during the
Sector- or Block-Erase operation are ignored. When WP#
is low, any attempt to Sector- (Block-) Erase the protected
block will be ignored. During the command sequence,
WP# should be statically held high or low.
Read
The Read operation of the SST39VF1601C/1602C is
controlled by CE# and OE#, both have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 6).
Word-Program Operation
Erase-Suspend/Erase-Resume Commands
The SST39VF1601C/1602C are programmed on a word-
by-word basis. Before programming, the sector where the
word exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within 10
µs. See Figures 7 and 8 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 22 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
2
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output sig-
nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to VDD via an external pull-up
resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.
Chip-Erase Operation
The SST39VF1601C/1602C provide a Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the ‘1’ state. This is useful when the entire device
must be quickly erased.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 7 for the command sequence, Figure 11 for tim-
ing diagram, and Figure 26 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
Data# Polling (DQ7)
When the SST39VF1601C/1602C are in the internal Pro-
gram operation, any attempt to read DQ7 will produce the
complement of the true data. Once the Program operation
is completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 9 for
Data# Polling timing diagram and Figure 23 for a flowchart.
Write Operation Status Detection
The SST39VF1601C/1602C provide two software means
to detect the completion of a Write (Program or Erase)
cycle, in order to optimize the system write cycle time. The
software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
3
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating ‘1’s
and ‘0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to ‘1’ if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
Hardware Block Protection
The SST39VF1602C supports top hardware block protec-
tion, which protects the top 8 KWord block of the device.
The SST39VF1601C supports bottom hardware block pro-
tection, which protects the bottom 8KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 8 KWord when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or CE#)
pulse of Write operation. See Figure 10 for Toggle Bit tim-
ing diagram and Figure 23 for a flowchart.
TABLE 2: Boot Block Address Ranges
Product
Address Range
00000H - 01FFFH
FE000H - FFFFFH
Bottom Boot Block
SST39VF1601C
Top Boot Block
SST39VF1602C
TABLE 1: Write Operation Status
Status
DQ7
DQ6
DQ2
No
Toggle
RY/BY#
Normal
Standard
DQ7# Toggle
0
T2.0 1380
Operation Program
Standard
Erase
0
1
Toggle Toggle
0
1
Hardware Reset (RST#)
Erase-
Suspend Erase-
Mode Suspended
Read from
1
Toggle
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place (see Figure 18).
Sector/
Block
Read from
Non-Erase-
Suspended
Sector/Block
Program
Data
Data
Data
N/A
1
The Erase or Program operation that has been interrupted
needs to be re-initiated after the device resumes normal
operation mode to ensure data integrity.
DQ7# Toggle
0
T1.0 1380
Note: DQ7 and DQ2 require a valid address when reading
status information.
Software Data Protection (SDP)
Data Protection
The SST39VF1601C/1602C provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
7 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
The SST39VF1601C/1602C provide both hardware and
software features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
4
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
device to read mode within TRC. The contents of DQ15-DQ8
can be VIL or VIH, but no other value, during any SDP com-
mand sequence.
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 7 for software command
codes, Figure 16 for timing waveform, and Figure 25 for
flowcharts.
Common Flash Memory Interface (CFI)
The SST39VF1601C/1602C also contain the CFI informa-
tion to describe the characteristics of the device. In order
to enter the CFI Query mode, the system writes a three-
byte sequence, same as product ID entry command with
98H (CFI Query command) to address 555H in the last
byte sequence. Additionally, the system can use the one-
byte sequence with 55H on the Address and 89H on the
Data Bus to enter the CFI Query mode. Once the device
enters the CFI Query mode, the system can read CFI data
at the addresses given in Tables 8 through 10. The system
must write the CFI Exit command to return to Read mode
from the CFI Query mode.
Security ID
The SST39VF1601C/1602C devices offer a 136 Word
Security ID space. The Secure ID space is divided into two
segments—one factory programmed segment and one
user programmed segment. The first segment is pro-
grammed and locked at SST with a random 128-bit num-
ber. The user segment, with a 128 word space, is left un-
programmed for the customer to program as desired.
Product Identification
The Product Identification mode identifies the devices as
the SST39VF1601C, SST39VF1602C, and manufacturer
as SST. This mode may be accessed software opera-
tions. Users may use the Software Product Identification
operation to identify the part (i.e., using the device ID)
when using multiple manufacturers in the same socket.
For details, see Table 7 for software operation, Figure 14
for the Software ID Entry and Read timing diagram and
Figure 24 for the Software ID Entry command sequence
flowchart.
To program the user segment of the Security ID, the user
must use the Security ID Word-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
TABLE 3: Product Identification
Address
Data
The Secure ID space can be queried by executing a three-
byte command sequence with Enter Sec ID command
(88H) at address 555H in the last byte sequence. To exit
this mode, the Exit Sec ID command should be executed.
Refer to Table 7 for more details.
Manufacturer’s ID
Device ID
0000H
BFH
SST39VF1601C
SST39VF1602C
0001H
0001H
234FH
234EH
T3.2 1380
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
5
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
SuperFlash
Memory
X-Decoder
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
WP#
I/O Buffers and Data Latches
DQ - DQ
Control Logic
RESET#
RY/BY#
15
0
1380 B1.0
FIGURE 1: Functional Block Diagram
A16
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Standard Pinout
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Top View
Die Up
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
V
DD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
A6
A5
A4
A3
A2
A1
V
SS
CE#
A0
1380 48-tsop P01.0
FIGURE 2: Pin Assignments for 48-Lead TSOP
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
6
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TOP VIEW (balls facing down)
SST39VF1601C/1602C
6
5
4
3
2
1
A13 A12 A14 A15 A16 NC DQ15 V
SS
A9
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
WE# RST# NC A19 DQ5 DQ12
V
DQ4
DD
RY/BY#WP# A18 NC DQ2 DQ10 DQ11 DQ3
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# V
SS
A
B
C
D
E F G H
1380 48-tfbga B3K P02.0
FIGURE 3: Pin Assignments for 48-Ball TFBGA
TOP VIEW (balls facing down)
SST39WF160xC
6
5
4
3
2
1
A2
A1
A0
A4
A3
A6 A17 NC NC WE# RST# A9 A11
A7 WP# RY/BY# A10 A13 A14
A5 A18
A8 A12 A15
DQ4 DQ11 A16
CE# DQ8 DQ10
V
OE# DQ9 A19
NC DQ5 DQ6 DQ7
SS
DQ0 DQ1 DQ2 DQ3
V
DQ12 DQ13 DQ14 DQ15 V
DD SS
A B C D E F G H J K L
1380 48-wfbga MAQ P03.0
FIGURE 4: Pin Assignments for 48-Ball WFBGA
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
7
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TABLE 4: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
RST#
CE#
OE#
WE#
VDD
Write Protect
Reset
To protect the top/bottom boot block from Erase/Program operation when grounded.
To reset and return the device to Read mode.
To activate the device when CE# is low.
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
VSS
NC
No Connection
Ready/Busy#
Unconnected pins.
RY/BY#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
T4.2 1380
1. AMS = Most significant address
MS = A19
A
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
8
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TABLE 5: Top / Bottom Boot Block Address
Top Boot Block Address SST39VF1602C
Bottom Boot Block Address SST39VF1601C
#
Size (KWord)
Address Range
FE000H-FFFFFH
FD000H-FDFFFH
FC000H-FCFFFH
F8000H-FBFFFH
F0000H-F7FFFH
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
00000H-07FFFH
#
Size (KWord)
Address Range
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
4
F8000H-FFFFFH
F0000H-F7FFFH
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
04000H-07FFFH
03000H-03FFFH
02000H-02FFFH
00000H-01FFFH
4
4
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
4
0
0
8
T5.1380
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
9
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TABLE 6: Operation Modes Selection
Mode
Read
Program
Erase
Standby
Write Inhibit
CE#
VIL
VIL
VIL
VIH
X
OE#
VIL
VIH
VIH
X
WE#
VIH
VIL
VIL
X
DQ
DOUT
DIN
X1
High Z
High Z/ DOUT
High Z/ DOUT
Address
AIN
AIN
Sector or block address, XXH for Chip-Erase
X
X
X
VIL
X
X
VIH
X
Product Identification
Software Mode
VIL
VIL
VIH
See Table 7
T6.0 1380
1. X can be VIL or VIH, but no other value.
TABLE 7: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
555H
555H
555H
555H
XXXH
XXXH
555H
555H
Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
WA3
555H
555H
555H
Data
AAH
AAH
AAH
Word-Program
Sector-Erase
Block-Erase
AAH
AAH
AAH
AAH
B0H
30H
AAH
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
555H
A0H
80H
80H
80H
4
4
2AAH
2AAH
2AAH
55H
55H
55H
SAX
BAX
50H
30H
10H
Chip-Erase
555H
Erase-Suspend
Erase-Resume
Query Sec ID5
2AAH
2AAH
55H
55H
555H
555H
88H
A5H
WA6
Data
User Security ID
Word-Program
XXH6 0000H
User Security ID
Program Lock-Out
555H
AAH
2AAH
55H
555H
85H
Software ID Entry7,8
CFI Query Entry
CFI Query Entry
555H
555H
55H
AAH
AAH
98H
AAH
2AAH
2AAH
55H
55H
555H
555H
90H
98H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
555H
2AAH
55H
555H
F0H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
XXH
F0H
T7.6 1380
1. Address format A10-A0 (Hex). Addresses A11-A19 can be VIL or VIH, but no other value, for Command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
A
MS = Most significant address; AMS = A19
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000008H to 000087H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF1601C Device ID = 234FH, is read with A0 = 1, SST39VF1602C Device ID = 234EH, is read with A0 = 1,
AMS = Most significant address; AMS = A19
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed ‘0’ bits cannot be reversed to ‘1’). Valid Word-Addresses for Sec ID are from 000000H-000007H and
000008H-000087H.
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
10
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TABLE 8: CFI Query Identification String1
Address
10H
11H
12H
13H
14H
15H
16H
17H
Data
Data
0051H
0052H
0059H
0002H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
18H
19H
1AH
T8.1 1380
1. Refer to CFI publication 100 for more details.
TABLE 9: System Interface Information
Address
Data
Data
1BH
0027H
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
0000H
0000H
0003H
0000H
0004H
0005H
0001H
0000H
0001H
0001H
V
PP min. (00H = no VPP pin)
PP max. (00H = no VPP pin)
V
Typical time out for Word-Program 2N µs (23 = 8 µs)
Typical time out for min. size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (25 = 32 ms)
Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T9.3 1380
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
11
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TABLE 10: Device Geometry Information
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
Data
Data
0015H
0001H
0000H
0000H
0000H
0005H
0000H
0000H
0040H
0000H
0001H
0000H
0020H
0000H
0000H
0000H
0080H
0000H
001EH
0000H
0000H
0001H
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Erase Block Region 1 Information (Refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
T10.0 1380
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
12
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range
Range
Ambient Temp
VDD
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
2.7-3.6V
2.7-3.6V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 20 and 21
Power Up Specifications
All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V
in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The recom-
mended VDD power-up to RESET# high time should be greater than 100 µs to ensure a proper reset.
> 100 µs
T
PU-READ
V
min
V
DD
DD
0V
V
IH
RESET#
CE#
T
> 50ns
RHR
1380 F24.0
FIGURE 5: Power-Up Diagram
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
13
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TABLE 11: DC Operating Characteristics VDD = 2.7-3.6V1
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
IDD
Power Supply Current
Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
Read3
18
35
20
20
mA
mA
µA
CE#=VIL, OE#=WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
Program and Erase
Standby VDD Current
Auto Low Power
ISB
CE#=VIHC, VDD=VDD Max
IALP
µA
CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI
Input Leakage Current
1
µA
µA
VIN=GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST#
10
WP#=GND to VDD or RST#=GND to VDD
ILO
Output Leakage Current
Input Low Voltage
10
0.8
0.3
µA
V
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7VDD
V
VDD=VDD Max
VIHC
VOL
VOH
Input High Voltage (CMOS)
Output Low Voltage
VDD-0.3
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
Output High Voltage
VDD-0.2
V
IOH=-100 µA, VDD=VDD Min
T11.8 1380
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 20
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
TABLE 12: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T12.0 1380
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T13.0 1380
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 14: Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Cycles
Years
mA
Test Method
1,2
NEND
10,000
100
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
1
ILTH
100 + IDD
T14.2 1380
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher
minimum specification.
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
14
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
AC CHARACTERISTICS
TABLE 15: Read Cycle Timing Parameters VDD = 2.7-3.6V
Symbol Parameter
Min
Max
Units
ns
TRC
TCE
TAA
Read Cycle Time
70
Chip Enable Access Time
Address Access Time
70
70
35
ns
ns
TOE
TCLZ
TOLZ
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
1
0
0
ns
ns
1
TCHZ
20
20
ns
1
TOHZ
ns
1
TOH
0
ns
1
TRP
500
50
ns
1
TRHR
RST# High before Read
RST# Pin Low to Read Mode
ns
1,2
TRY
20
µs
T15.3 1380
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations.
This parameter does not apply to Chip-Erase operations.
TABLE 16: Program/Erase Cycle Timing Parameters
Symbol Parameter
Min
Max
Units
µs
TBP
Word-Program Time
10
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
30
0
ns
TAH
ns
TCS
ns
TCH
TOES
TOEH
TCP
0
ns
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
TDS
ns
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
ns
TSE
ms
ms
ms
ns
TBE
Block-Erase
25
TSCE
Chip-Erase
50
1,2
TBY
TBR
RY/BY# Delay Time
Bus Recovery Time
90
1
0
µs
T16.1 1380
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
15
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
CE#
OE#
T
CE
T
OE
T
T
OHZ
OLZ
V
IH
WE#
T
CHZ
T
T
OH
CLZ
HIGH-Z
HIGH-Z
DQ
DATA VALID
DATA VALID
15-0
Note:
A
A
= Most significant address
MS
= A
MS
19
1380 F03.0
FIGURE 6: Read Cycle Timing Diagram
T
BP
555
2AA
555
ADDR
ADDRESSES
WE#
T
AH
T
WP
T
T
WPH
AS
OE#
CE#
T
CH
T
CS
T
T
BR
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
1380 F25.0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 7: WE# Controlled Program Cycle Timing Diagram
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
16
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
T
BP
555
2AA
555
ADDR
ADDRESSES
WE#
T
AH
T
CP
T
CPH
T
AS
OE#
CE#
T
CH
T
CS
T
T
BR
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
1380 F26.0
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 8: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
19-0
T
CE
CE#
T
T
OES
OEH
OE#
T
OE
WE#
T
BY
RY/BY#
DQ
7
DATA
DATA#
DATA#
DATA
1380 F27.0
FIGURE 9: Data# Polling Timing Diagram
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
17
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
T
OEH
T
OES
T
OE
OE#
WE#
DQ and DQ
6
2
TWO READ CYCLES
WITH SAME OUTPUTS
Note:
A
A
= Most significant address
MS
= A
MS
19
1380 F07.0
FIGURE 10: Toggle Bits Timing Diagram
T
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
SCE
555
2AA
555
ADDRESSES
CE#
OE#
WE#
T
OEH
T
T
BR
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX10
XX80
VALID
1380 F31.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchange-
able as long as minimum timings are met. (See Table 16).
WP# must be held in proper logic state (VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 11: WE# Controlled Chip-Erase Timing Diagram
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
18
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
T
SIX-BYTE CODE FOR BLOCK-ERASE
555 555 2AA
BE
555
2AA
BA
X
ADDRESSES
CE#
OE#
WE#
T
WP
T
BR
T
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX30
XX80
VALID
1380 F32.0
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchange-
able as long as minimum timings are met. (See Table 16).
BAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 12: WE# Controlled Block-Erase Timing Diagram
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
19
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
T
SIX-BYTE CODE FOR SECTOR-ERASE
555 555 2AA
SE
555
2AA
SA
X
ADDRESSES
CE#
OE#
WE#
T
WP
T
BR
T
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX50
XX80
VALID
1380 F28.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchange-
able as long as minimum timings are met. (See Table 16).
SAX = Block Address
WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 13: WE# Controlled Sector-Erase Timing Diagram
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
20
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
Three-Byte Sequence for Software ID Entry
ADDRESS
CE#
555
2AA
555
0000
0001
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
XXAA
SW0
XX55
SW1
XX90
SW2
Device ID
DQ
00BF
15-0
Note: Device ID = 234BH for 39VF1601C and 234AH for 39VF1602C
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence
IL
IH
X can be V or V but no other value
IH,
IL
1380 F11.0
FIGURE 14: Software ID Entry and Read
Three-Byte Sequence for CFI Query Entry
ADDRESS
CE#
555
2AA
555
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
DQ
XXAA
SW0
XX55
SW1
XX98
SW2
15-0
Note:
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence
IL IH
X can be V or V but no other value
IL
IH,
1380 F12.0
FIGURE 15: CFI Query Entry and Read
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
21
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
555
2AA
555
ADDRESS
XXAA
XX55
XXF0
DQ
15-0
T
IDA
CE#
OE#
WE#
T
WP
T
WHP
SW0
SW1
SW2
Note:
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence
IL
IH
X can be V or V but no other value
IH,
IL
1380 F13.0
FIGURE 16: Software ID Exit/CFI Exit
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
555
2AA
555
MS-0
CE#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
XXAA
SW0
XX55
SW1
XX88
SW2
DQ
15-0
Note:
A
A
= Most significant address
MS
= A
MS
19
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence
IL
IH
X can be V or V but no other value.
IH,
IL
1380 F20.0
FIGURE 17: Sec ID Entry
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
22
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
RY/BY#
0V
T
RP
RST#
T
RHR
CE#/OE#
1380 F29.0
FIGURE 18: RST# Timing Diagram (When no internal operation is in progress)
T
RY
RY/BY#
RST#
T
RP
CE#
OE#
T
BR
1380 F30.0
FIGURE 19: RST# Timing Diagram (During Program or Erase operation)
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1380F14.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic ‘1’ and VILT (0.1 VDD) for a logic ‘0’. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 20: AC Input/Output Reference Waveforms
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
23
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TO TESTER
TO DUT
CL
1380 F15.0
FIGURE 21: A Test Load Example
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
24
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
X can be V or V , but no other value
IL IH
1380 F16.0
FIGURE 22: Word-Program Algorithm
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
25
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
Toggle Bit
Data# Polling
RY/BY#
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
Read RY/BY#
BP
T
T
SCE, SE
or T
BE
Read same
word
Is DQ =
7
No
Is
No
true data?
Program/Erase
Completed
RY/BY# = 1?
Yes
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Program/Erase
Completed
Yes
Program/Erase
Completed
1380 F17.1
FIGURE 23: Wait Options
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
26
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XX98H
Address: 55H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XX98H
Address: 55H
Load data: XX88H
Address: 555H
Load data: XX90H
Address: 555H
Read CFI data
Wait T
Wait T
Wait T
IDA
IDA
IDA
Read CFI data
Read Sec ID
Read Software ID
X can be V or V , but no other value
IL IH
1380 F21.0
FIGURE 24: Software ID/CFI Entry Command Flowcharts
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
27
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XXF0H
Address: 555H
Return to normal
operation
Wait T
IDA
Return to normal
operation
X can be V or V , but no other value
IL IH
1380 F18.0
FIGURE 25: Software ID/CFI Exit Command Flowcharts
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
28
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX50H
Load data: XX30H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
X can be V or V , but no other value
IL IH
1380 F19.0
FIGURE 26: Erase Command Sequence
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
29
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
PRODUCT ORDERING INFORMATION
SST 39 VF 1602 C
-
70
-
4C
-
EK
E
XX XX XXXXX
-
XX
-
XX - XXX
X
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Q = 48 balls (66 possible positions)
Package Type
E = TSOP (type1, die up, 12mm x 20mm)
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)
MA = WFBGA (4mm x 6mm, 0.5mm pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
160 = 16 Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid Combinations for SST39VF1601C
SST39VF1601C-70-4C-EKE
SST39VF1601C-70-4I-EKE
SST39VF1601C-70-4C-B3KE
SST39VF1601C-70-4I-B3KE
SST39VF1601C-70-4C-MAQE
SST39VF1601C-70-4I-MAQE
Valid Combinations for SST39VF1602C
SST39VF1602C-70-4C-EKE
SST39VF1602C-70-4I-EKE
SST39VF1602C-70-4C-B3KE
SST39VF1602C-70-4I-B3KE
SST39VF1602C-70-4C-MAQE
SST39VF1602C-70-4I-MAQE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
30
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0°- 5°
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
FIGURE 27: 48-lead Thin Small Outline Package (TSOP) 12mm x 20mm
SST Package Code: EK
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
31
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60
0.45 0.05
0.80
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.80
6.00 0.20
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
FIGURE 28: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
TOP VIEW
BOTTOM VIEW
5.00
0.50
6.00
0.08
0.32 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.08
2.50
0.50
A B C D E F G H J K L
L K J H G F E D C B A
A1 CORNER
A1 INDICATOR
0.73 max.
0.636 nom.
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.20 0.06
1mm
Note:
1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger
and bottom side A1 indicator is triangle at corner.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.29 mm ( 0.05 mm)
48-wfbga-MAQ-4x6-32mic-2.0
FIGURE 29: 48-ball Very, Very Thin-profile, Fine-pitch Ball Grid Array (WFBGA) 6mm x 8mm
SST Package Code: MAQ
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
32
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
Data Sheet
TABLE 17: Revision History
Number
Description
Date
00
01
Apr 2008
Sep 2008
•
•
•
•
•
•
Initial release
Corrected typo in Hardware Block Protection on page 4.
Corrected typo in table title, Table 5 page 8
02
03
Jan 2009
Aug 2009
Changed 1V per 100 µs to 1V per 100 ms in Power Up Specifications on page 12
Changed from Preliminary Specification to Data Sheet
Clarified RY/BY# pin timing by updating Features, Figures 7, 8, 9, 11, 12, 13, 18,
19, and 23, and Tables 1 and 16.
04
May 2010
•
•
Added information for MAQE package
Updated SST address information on page 33.
Silicon Storage Technology, Inc.
www.SuperFlash.com or www.sst.com
©2010 Silicon Storage Technology, Inc.
S71380-04-000
05/10
33
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