SST45LF010-10-4C-SAE-DD014 [SILICON]
Flash, 1MX1, PDSO8, 4.90 X 6 MM, MS-012AA, LEAD FREE, SOIC-8;
| 型号： | SST45LF010-10-4C-SAE-DD014 |
| 厂家： | 
SILICON |
| 描述： | Flash, 1MX1, PDSO8, 4.90 X 6 MM, MS-012AA, LEAD FREE, SOIC-8 时钟 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 Mbit Serial Flash
SST45LF010
SST45LF0101Mb 4-wire Serial Interface flash memory
Data Sheet
FEATURES:
•
•
•
•
Single 3.0-3.6V Read and Write Operations
•
•
Automatic Write Timing
Serial Interface Architecture
Byte Serial Read with Single Command
Superior Reliability
– Internal VPP Generation
End-of-Write Detection
– Software Status
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
10 MHz Max Clock Frequency
Hardware Reset Pin (RST#)
– Resets the device to Standby Mode
CMOS I/O Compatibility
•
Low Power Consumption
– Active Current: 10 mA (typical)
– Standby Current: 10 µA (typical)
•
•
Hardware Data Protection (WP#)
•
•
Sector or Chip-Erase Capability
– Uniform 4 KByte sectors
– Protects and unprotects the device from Write
operation
Fast Erase and Byte-Program
•
Packages Available
– Chip-Erase Time: 70 ms (typical)
– Sector-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
– 8-lead SOIC (4.9mm x 6mm)
– 8-contact WSON
PRODUCT DESCRIPTION
The SST45LF010 is a 1 Mbit serial flash memory manufac-
tured with SST’s proprietary, high performance CMOS
SuperFlash technology. The 1 Mbit of memory is organized
as 32 sectors of 4096 Bytes. The flash memory uses a 4-
wire serial interface and a chip enable to select and
sequentially access its data. The serial interface consists
of; serial data input (SI), serial data output (SO), serial clock
(SCK), and chip enable (CE#). A write protect (WP#) inhib-
its the entire memory from Write operation and a hardware
reset pin (RST#) resets the device to standby mode.
Read
The Read operation outputs the data in order from the ini-
tial accessed address. While SCK is input, the address will
be incremented automatically until end (top) of the address
space (1FFFFH), then the internal address pointer auto-
matically increments to beginning (bottom) of the address
space (00000H), and data out stream will continue. The
read data stream is continuous through all addresses until
terminated by a low to high transition on CE#.
The SST45LF010 device is offered in both 8-lead SOIC
and 8-contact WSON packages. See Figure 2 for the pin
assignments.
Sector/Chip-Erase Operation
The Sector-Erase operation clears all bits in the selected
sector to FFH. The Chip-Erase instruction clears all bits in
the device to FFH.
Device Operation
The SST45LF010 uses bus cycles of 8 bits each for com-
mands, data, and addresses to execute operations. The
operation instructions are listed in Table 3.
Byte-Program Operation
The Byte-Program operation programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. The data is input from bit 7 to bit 0 in order.
All instructions are synchronized off a high to low transition
of CE#. The first low to high transition on SCK will initiate
the instruction sequence. Inputs will be accepted on the ris-
ing edge of SCK starting with the most significant bit. Any
low to high transition on CE# before the input instruction
completes will terminate any instruction in progress and
return the device to the standby mode.
Software Status Operation
The Status operation determines if an Erase or Program
operation is in progress. If bit 0 is at a “0” an Erase or Pro-
gram operation is in progress, the device is busy. If bit 0 is
at a “1” the device is ready for any valid operation. The sta-
tus read is continuous with ongoing clock cycles until termi-
nated by a low to high transition on CE#.
©2003 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71128-04-000 3/03
1
372
1 Mbit Serial Flash
SST45LF010
Data Sheet
Reset
Reduced-Function Option
(SST45LF010-10-4C-SA-DD014)
Reset will terminate any operation, e.g., Read, Erase and
Program, in progress. It is activated by a high to low tran-
sition on the RST# pin. The device will remain in reset
condition as long as RST# is low. Minimum reset time is
10 µs. See Figure 15 for reset timing diagram. RST# is
internally pulled-up and could remain unconnected dur-
ing normal operation. After reset, the device is in standby
mode, a high to low transition on CE# is required to start
the next operation.
The SST45LF010-10-4C-SA-DD014 is a reduced-function
option of the SST45LF010-10-4C-xA.
For these devices, SST only tests and guarantees func-
tionality when separate serial input and serial output data
lines are used. Valid connections must be as illustrated in
Figure 1.
The RESET# pin is not tested during production; it must be
left unconnected or tied to VDD.
An internal power-on reset circuit protects against acci-
dental data writes. Applying a logic level low to RST# dur-
ing the power-on process then changing to a logic level
high when VDD has reached the correct voltage level will
provide additional protection against accidental writes
during power on.
Host Controller
SST45LF010-10-4C-SA-DD014
Read SST ID/Read Device ID
SCK
SO
SCK
SI
The Read SST ID and Read Device ID operations read the
JEDEC assigned manufacturer’s identification and the manu-
facturer assigned device IDs. These IDs may be used to
determine the actual device resident in the system.
SI
SO
TABLE 1: PRODUCT IDENTIFICATION
372 ILL F21.0
Byte
Data
BFH
42H
Manufacturer’s ID
Device ID
0000H
0001H
FIGURE 1: VALID CONNECTIONS FOR
SST45LF010-10-4C-SA-DD014
T1.2 372
Write Protect
The WP# pin provides inadvertent write protection. The
WP# pin must be held high for any Erase or Program oper-
ation. The WP# pin can be VIL or VIH, but no other value, for
all other operations. In typical use, the WP# pin is con-
nected to VSS with a standard pull-down resistor. WP# is
then driven high whenever an Erase or Program operation
is required. If the WP# pin is tied to VDD with a pull-up resis-
tor, then all operations may occur and the write protection
feature is disabled. The WP# pin has an internal pull-up
and could remain unconnected when not used.
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Control Logic
Data Latches
Serial Interface
372 ILL B1.4
CE# SCK SI SO WP# RST#
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
1
2
3
4
8
7
6
5
WP#
RST#
1
2
3
4
8
7
6
5
WP#
RST#
V
V
V
V
DD
SS
DD
SS
Top View
Top View
CE#
SCK
SO
SI
CE#
SCK
SO
SI
372 ILL F01a.2
372 ILL F01.6
8-LEAD SOIC
8-CONTACT WSON
FIGURE 2: PIN ASSIGNMENTS
TABLE 2: PIN DESCRIPTION
Symbol Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface. Commands, addresses, or input data are latched
on the rising edge of the clock input, while output data is shifted out on the falling edge of the
clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device. Inputs are latched on the
rising edge of the serial clock.
SO
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE#
Chip Enable
Write Protect
The device is enabled by a high to low transition on CE#.
WP#
To protect the device from unintentional Write (Erase or Program) operations. When WP# is
low, all Erase and Program commands are ignored. When WP# is high, the device may be
erased or programmed. This pin has an internal pull-up and could remain unconnected when
not used.
RST#
Reset
A high to low transition on RST# will terminate any operation in progress and reset the internal
logic to the standby mode. The device will remain in the reset condition as long as the RST# is
low. Operations may only occur when RST# is high. This pin has an internal pull-up and could
remain unconnected when not used.
VDD
VSS
Power Supply
Ground
To provide power supply (3.0-3.6V).
T2.5 372
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
1
TABLE 3: DEVICE OPERATION INSTRUCTIONS
Bus Cycle2
1
2
3
4
5
6
7
Cycle Type/
Operation3,4
SIN SOUT
SIN
SOUT
SIN
SOUT
SIN
SOUT SIN
Hi-Z
SOUT SIN SOUT SIN SOUT
Read
FFH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
X
X
Hi-Z
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
X
X
X
X
X
DOUT
Hi-Z
Hi-Z
Hi-Z
Sector-Erase5 20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
Hi-Z D0H Hi-Z
Hi-Z D0H Hi-Z
Chip-Erase 60H Hi-Z Hi-Z Hi-Z
X
X
X
Byte-Program 10H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
Note6
A7-A0
X
Hi-Z
DIN
X
Hi-Z
6
6
6
6
Status Reg.
Read-ID
9FH
X
X
DOUT
Hi-Z
X
Note
Note
Note
Note
Note
7
8
8
90H Hi-Z
00H
00H
Hi-Z ID Addr7 Hi-Z
X
DOUT
Note
T3.10 372
1. For SST45LF010, A23-A17 can be VIL or VIH, but no other value.
2. One bus cycle is eight clock periods
3. Operation: SIN=Serial In, SOUT=Serial Out
4. X = Dummy cycles (can be VIL or VIH, but no other value.)
5. A16-A12 are used to determine sector address, A11-A8 can be VIL or VIH, but no other value.
6. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
7. Manufacturer’s ID = BFH, is read with A0 = 0 and Device ID = 42H, is read with A0 = 1; All other address bits are 0
8. The data output is arbitrary.
TABLE 4: DEVICE OPERATION TABLE
Operation
SI
X
SO
DOUT
X
CE#1
Low
Low
Low
Low
Low
X
WP#
X
RST#
High
High
High
High
High
Low
Read
Sector-Erase
Chip-Erase
Byte-Program
Software-Status
Reset2
X
High
High
High
X
X
X
DIN
X
X
DOUT
X
X
X
Read SST ID
Read Device ID
X
DOUT
DOUT
Low
Low
X
High
High
X
X
T4.6 372
1. A high to low transition on CE# will be required to start any device operation except for Reset.
2. The RST# low will return the device to standby and terminate any Erase or Program operation in progress.
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 3 and 4
Range
Ambient Temp
VDD
Commercial
0°C to +70°C
3.0-3.6V
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V
Limits
Symbol
Parameter
Min
Max
Units Test Conditions
SCK input=VILT/VIHT at f=10 MHz Max
IDD
Active VDD Current
Read
20
30
15
1
mA
mA
µA
µA
µA
µA
V
CE#=VIL, VDD=VDD Max
CE#=VIL, VDD=VDD Max
CE#=VIHC, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
WP#, RST#=GND
Program and Erase
Standby VDD Current
Input Leakage Current
Output Leakage Current
Input Low Current1
Input Low Voltage
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
ISB
ILI
ILO
IIL
1
360
0.8
VIL
VIH
VIHC
VOL
VOH
VDD=VDD Min
0.7 VDD
VDD-0.3
V
VDD=VDD Max
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
VDD-0.2
V
T5.4 372
1. This parameter only applies to WP# and RST# pins.
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
TABLE 6: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VOUT = 0V
Maximum
1
COUT
Output Pin Capacitance
Input Capacitance
12 pF
1
CIN
VIN = 0V
6 pF
T6.1 372
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T7.1 372
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: AC OPERATING CHARACTERISTICS, VDD = 3.0-3.6V
Limits
Symbol
FCLK
TSCKH
TSCKL
TCES
TCEH
TCPH
TCHZ
TCLZ
TRLZ
TDS
Parameter
Min
Max
Units
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
CE# Setup Time
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
µs
µs
µs
µs
45
45
250
250
250
CE# Hold Time
CE# High Time
CE# High to High-Z Output
SCK Low to Low-Z Output
RST# Low to High-Z Output
Data In Setup Time
Data In Hold Time
25
25
0
20
20
0
TDH
TOH
Output Hold from SCK Change
Output Valid from SCK
Write Protect Setup Time
Write Protect Hold Time
Sector-Erase
TV
35
TWPS
TWPH
TSE
10
10
25
100
20
TSCE
TBP
Chip-Erase
Byte-Program
TRST
TREC
TPURST
Reset Pulse Width
10
10
Reset Recovery Time
Reset Time After Power-Up
1
T8.2 372
©2003 Silicon Storage Technology, Inc.
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7
1 Mbit Serial Flash
SST45LF010
Data Sheet
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
372 ILL F02.2
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 3: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
372 ILL F03.2
FIGURE 4: A TEST LOAD EXAMPLE
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
WP#
CE#
SCK
T
CPH
T
T
SCKL
T
T
SCKH
CES
CEH
T
T
DS
DH
DATA VALID
HIGH-Z
SI
HIGH-Z
SO
372 ILL F04.6
FIGURE 5: SERIAL INPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW)
WP#
CE#
T
T
SCKH SCKL
T
CEH
SCK
T
T
CHZ
OH
T
CLZ
DATA VALID
SO
SI
T
V
372 ILL F05.6
FIGURE 6: SERIAL OUTPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW)
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
T
T
WPS
WPH
WP#
CE#
SCK
T
SE
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39
47
40
SELF-TIMED SECTOR-
ERASE CYCLE
20H
ADD.
ADD.
D0H
X
X
SI
HIGH IMPEDANCE
SO
372 ILL F06.7
FIGURE 7: SECTOR-ERASE TIMING DIAGRAM
T
WPS
T
WPH
WP#
CE#
SCK
T
SCE
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47
SELF-TIMED CHIP-
ERASE CYCLE
60H
X
X
X
D0H
X
SI
HIGH IMPEDANCE
SO
372 ILL F07.10
FIGURE 8: CHIP-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
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10
1 Mbit Serial Flash
SST45LF010
Data Sheet
T
WPS
T
WPH
WP#
CE#
SCK
T
BP
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47
SELF-TIMED BYTE-
PROGRAM CYCLE
10H
ADD.
ADD.
Din
X
ADD.
SI
MSB
LSB
HIGH IMPEDANCE
SO
372 ILL F08.8
FIGURE 9: BYTE-PROGRAM TIMING DIAGRAM
WP#
CE#
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
71
47 48
55 56
63 64
SCK
FFH
ADD.
ADD.
X
X
ADD.
SI
N
Dout
MSB
N+1
N+2
HIGH IMPEDANCE
SO
Dout
Dout
MSB
MSB
372 ILL F10.6
FIGURE 10: READ TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
WP#
CE#
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
71
47 48
55 56
63 64
SCK
1
ADD
90H
00H
00H
SI
HIGH IMPEDANCE
1
SO
Dout
MSB
LSB
372 ILL F19.4
Note: 1. SST Manufacturer's ID = BFH is read with A =0
0
SST45LF010 Device ID = 42H is read with A =1
0
FIGURE 11: READ-ID TIMING DIAGRAM
WP#
CE#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
23 24
31
SCK
9FH
SI
HIGH IMPEDANCE
SO
DATA
DATA
MSB
DATA
MSB
MSB
372 ILL F11.5
FIGURE 12: SOFTWARE-STATUS TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
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12
1 Mbit Serial Flash
SST45LF010
Data Sheet
CE#
T
T
CES
REC
...
SCK
T
RST
RESET#
T
RLZ
HIGH IMPEDANCE
HIGH IMPEDANCE
...
...
SO
SI
372 ILL F20.4
FIGURE 13: RESET TIMING DIAGRAM (INACTIVE CLOCK POLARITY LOW)
V
DD
T
PURST
RESET#
CE#
T
REC
372 ILL F13.3
FIGURE 14: POWER-ON RESET TIMING DIAGRAM
T
WPS
T
WPH
WP#
CE#
SCK
T
CPH
T
T
CES
CEH
372 ILL F14.1
FIGURE 15: WRITE PROTECT TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed Suffix1 Suffix2
XX
Suffix 3
SST45LFxxx - XXX - XX
-
-
XXXXX
Custom Specification Number
DD014 = Reduced-Function Option1
Package Modifier
A = 8 leads or contacts
Package Type
S = SOIC
Q = WSON
Temperature Range
C = Commercial = 0°C to +70°C
Minimum Endurance
4 = 10,000 cycles
Operating Frequency
10 = 10 MHz
Device Density
010 = 1 Mbit
Voltage
L = 3.0-3.6V
1. For details, see “Reduced-Function Option
(SST45LF010-10-4C-SA-DD014)” on page 2.
Valid combinations for SST45LF010
SST45LF010-10-4C-SA
SST45LF010-10-4C-QA
SST45LF010-10-4C-SA-DD014
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
Non-Pb:Several devices in this data sheet are also offered in non-Pb (no lead added) packages.
The non-Pb part number is simply the standard part number with the letter “E” added to the end of the package code.
The non-Pb package codes corresponding to the packages listed above are SAE and QAE.
©2003 Silicon Storage Technology, Inc.
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1 Mbit Serial Flash
SST45LF010
Data Sheet
PACKAGING DIAGRAMS
Pin #1
Identifier
Side View
7˚
Top View
4 places
0.51
0.33
5.0
4.8
1.27 BSC
End View
45˚
7˚
4 places
4.00
3.80
0.25
0.10
6.20
5.80
1.75
1.35
0.25
0.19
0˚
8˚
1.27
0.40
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
08-soic-5x6-SA-7
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC)
SST PACKAGE CODE: SA
©2003 Silicon Storage Technology, Inc.
S71128-04-000 3/03 372
15
1 Mbit Serial Flash
SST45LF010
Data Sheet
Side View
Bottom View
Top View
0.25
0.19
Pin #1
Pin #1
Corner
1.27 BSC
4.00
5.00
BSC
0.076
3.40
0.48
0.35
0.05 Max
6.00
BSC
0.75
0.50
0.8
0.7
Cross Section
0.8
0.7
Note: 1. All linear dimensions are in millimeters (max/min).
8-wson-5x6-QA-5
8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON)
SST PACKAGE CODE: QA
TABLE 9: REVISION HISTORY
Number
03
Description
Date
May 2002
Mar 2003
•
•
•
•
2002 Data Book
04
Added section for Custom Specification number DD014 on page 2
Part number changes - see page 14 for additional information
Clarified the Test Conditions for Active VDD Current parameter in Table 5 on page 6
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2003 Silicon Storage Technology, Inc.
S71128-04-000 3/03 372
16
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