SST58LD024-80-I-P1H_技术文档

SST ATA-Disk Chip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

PreliminarySpecifications

FEATURES:

1

•

ZeroPowerDataRetention

– Batteries not required for data storage

•

ATA/IDEstandardinterface

– 512 Bytes per sector

– ATA command set compatible

– Support Data Transfer Speed up to PIO Mode-3

Start Up Time

2

– Sleep to read: 200 ns (typical)

– Sleep to write: 200 ns (typical)

– Power-on to Ready: 200 ms (typical),

500 ms (maximum)

•

8, 16, 24, 32, 48 and 64 MByte capacities

Standard 600mil 32pin DIP package

Single Voltage Read and Write Operation

– 5.0 Volt-only for SST58SDxxx

– 3.3 Volt-only for SST58LDxxx

3

•

Support for Both Commercial and Industrial

TemperatureRange

– 0°C to 70°C for Operating Commercial

– -40 °C to +85 °C for Operating Industrial

– -50 °C to +100 °C for non-Operating (storage)

4

•

Supports 5.0-Volt or 3.3-Volt Read and Write

– 5V + 10% or 3.3V + 5% for Commercial

– 5V + 5% or 3.3V + 5% for Industrial

5

Extremely Rugged and Reliable

– Built-in ECC support corrects 3 Bytes

of error per 512 Byte sector

– Endurance: 1,000,000 cycles (typical)

– Greaterthan1,000,000hoursMTBF

LowPowerConsumption:

– Active mode: 30mA/50mA (3.3V/5.0V) (typical)

– Sleepmode: 200µA/600µA(3.3V/5.0V)(maximum)

6

DataTransferRateto/fromHost

– 20 MB/s burst at 5.0 V

– 6.6 MB/s burst at 3.3 V

•

IntelligentATA/IDEController

– Built-inmicrocontrollerwithintelligentfirmware

– Built-in Flash File System

7

•

SustainedWritePerformance

– Up to 1.4MB/sec (host to flash)

PowerManagementUnit

– Immediate disabling of unused circuitry

8

ControllerOverheadCommandtoDRQ

– Less than 0.5 ms

9

ProductDescription

10

11

12

13

14

15

16

SST’s ATA-Disk Chip (ADC) is a low cost, high perfor-

mance, embedded flash memory data storage system.

This product is well suited for solid state mass storage

applications offering new and expanded functionality

while enabling cost effective designs.

The ADC is a solid state disk drive that is designed to

replace conventional IDE hard disk drive and uses

standard ATA/IDE protocol. It has built in

microcontroller and file management firmware that

communicateswithATAstandardinterfaces;therefore,

the ADC does not require additional or proprietary

software such as Flash File System (FFS) and Memory

Technology Driver (MTD) software.

ATA-based solid state mass storage technology is

widely used in such products as portable and desktop

computers, digital cameras, music players, handheld

datacollectionscanners,cellularphones,PCSphones,

PDAs, handy terminals, personal communicators, ad-

vanced two-way pagers, audio recorders, monitoring

devices, and set-top boxes.

The ADC is designed to work at either 5V±10% or 3.3V

±5%. Thepinassignmentisdesignedtomatchexisting

IDE signaltraces on the motherboard. It uses standard

ATA driver that is part of all major OS such as Windows

95/98/2000/NT/CE, MAC, UNIX, etc.

ADC provides complete IDE Hard Disk Drive function-

ality and compatibility. ADC is a perfect solution to

consumer electronic products requiring smaller, but

more reliable and cost effective data storage. The ADC

is read and written using a single power supply of 5.0-

Voltsor3.3-Voltsandisavailablein8,16,24,32,48and

64 MByte capacities.

The ADC is packaged in the standard 600 mil. 32-pin

DIPpackageforeasyandcosteffectivemountingtothe

system motherboard.

391-2 8/00

TheSSTlogoandSuperFlashareregisteredtrademarksofSiliconStorageTechnology,Inc.ATA-DiskChipis

atrademarkofSiliconStorageTechnology,Inc.Thesespecificationsaresubjecttochangewithoutnotice.

1

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

Table of Contents

Product Description .................................................................................................................1

1.0 General Description...........................................................................................................5

1.1 Optimized for performance ATA Controller ................................................................................................... 5

1.1.1 Microcontroller Unit (MCU).................................................................................................................... 5

1.1.2 Internal Direct Memory Access (DMA) .................................................................................................. 5

1.1.3 Power Management Unit (PMU)............................................................................................................. 5

1.1.4 SRAM Buffer........................................................................................................................................... 5

1.1.5 Firmware Storage .................................................................................................................................. 5

1.2 SST’s ADC Product Offering............................................................................................................................ 6

2.0 Electrical Interface ..............................................................................................................6

2.0.1 Pin Assignment and Pin Type ................................................................................................................ 6

2.1 Electrical Description....................................................................................................................................... 6

2.2 Absolute Maximum Stress Ratings ................................................................................................................ 9

2.3 Electrical Specification .................................................................................................................................. 10

2.3.1 Absolute Maximum Conditions .......................................................................................................... 10

2.3.2 Input Leakage Current .......................................................................................................................... 11

2.3.3 Input Characteristics............................................................................................................................. 11

2.3.4 Output Drive Type ................................................................................................................................. 11

2.3.5 Output Drive Characteristics ................................................................................................................ 11

2.3.6 I/O Input (Read) Timing Specification.................................................................................................. 12

2.3.7 I/O Output (Write) Timing Specification............................................................................................... 13

2.4 I/O Transfer Function ..................................................................................................................................... 14

2.4.1 I/O Function .......................................................................................................................................... 14

3.0 Software Interface.............................................................................................................15

3.1 ADC Drive Register Set Definitions and Protocol......................................................................................... 15

3.1.1 ADC Addressing.................................................................................................................................... 15

3.1.2 ADC Registers ....................................................................................................................................... 15

3.1.2.1 Data Register ...................................................................................................................................... 15

3.1.2.2 Error Register (Read Only) ................................................................................................................ 16

3.1.2.3 Feature Register (Write Only) ............................................................................................................ 16

3.1.2.4 Sector Count Register ....................................................................................................................... 16

3.1.2.5 Sector Number (LBA 7-0) Register .................................................................................................... 16

3.1.2.6 Cylinder Low (LBA 15-8) Register ..................................................................................................... 16

3.1.2.7 Cylinder High (LBA 23-16) Register................................................................................................... 16

3.1.2.8 Drive/Head (LBA 27-24) Register ....................................................................................................... 16

3.1.2.9 Status & Alternate Status Registers (Read Only).............................................................................. 18

3.1.2.10 Device Control Register (Write Only) .............................................................................................. 18

3.1.2.11 Drive Address Register (Read Only)................................................................................................ 19

3.1.2.12 Command Register (Write Only)...................................................................................................... 19

391-2 8/00

2

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2 ADC Command Description........................................................................................................................... 20

3.2.1 ADC Command Set ............................................................................................................................... 20

3.2.1.1 Check Power Mode - 98h or E5h ....................................................................................................... 21

3.2.1.2 Execute Drive Diagnostic - 90h ......................................................................................................... 22

3.2.1.3 Format Track - 50h ............................................................................................................................. 23

3.2.1.4 Identify Drive - ECh ............................................................................................................................ 23

3.2.1.4.1 General Configuration .................................................................................................................... 25

3.2.1.4.2 Default Number of Cylinders .......................................................................................................... 25

3.2.1.4.3 Default Number of Heads ................................................................................................................ 25

3.2.1.4.4 Number of Unformatted Bytes per Track ........................................................................................ 25

3.2.1.4.5 Number of Unformatted Bytes per Sector ...................................................................................... 25

3.2.1.4.6 Default Number of Sectors per Track ............................................................................................. 25

3.2.1.4.7 Number of Sectors .......................................................................................................................... 25

3.2.1.4.8 Memory Serial Number................................................................................................................... 25

3.2.1.4.9 Buffer Type ...................................................................................................................................... 25

3.2.1.4.10 Buffer Size ..................................................................................................................................... 25

3.2.1.4.11 ECC Count ..................................................................................................................................... 25

3.2.1.4.12 Firmware Revision ........................................................................................................................ 26

3.2.1.4.13 Model Number ............................................................................................................................... 26

3.2.1.4.14 Read/Write Multiple Sector Count ................................................................................................ 26

3.2.1.4.15 Double Word Support ................................................................................................................... 26

3.2.1.4.16 Capabilities.................................................................................................................................... 26

3.2.1.4.17 PIO Data Transfer Cycle Timing Mode ......................................................................................... 26

3.2.1.4.18 DMA Data Transfer Cycle Timing Mode ........................................................................................ 26

3.2.1.4.19 Translation Parameters Valid ........................................................................................................ 26

3.2.1.4.20 Current Number of Cylinders, Heads, Sectors/Track ................................................................... 26

3.2.1.4.21 Current Capacity............................................................................................................................ 26

3.2.1.4.22 Multiple Sector Setting ................................................................................................................. 27

3.2.1.4.23 Total Sectors Addressable in LBA Mode ..................................................................................... 27

3.2.1.4.24Advanced PIO Data Transfer Mode ............................................................................................... 27

3.2.1.4.25 Minimum PIO Transfer Cycle Time Without Flow Control .......................................................... 27

3.2.1.4.26 Minimum PIO Transfer Cycle Time With IORDY .......................................................................... 27

3.2.1.5 Idle - 97h or E3h................................................................................................................................. 27

3.2.1.6 Idle Immediate - 95h or E1h .............................................................................................................. 27

3.2.1.7 Initialize Drive Parameters - 91h ....................................................................................................... 28

3.2.1.8 Read Buffer - E4h ............................................................................................................................... 28

3.2.1.9 Read Multiple - C4h............................................................................................................................ 29

3.2.1.10 Read Long Sector - 22h or 23h........................................................................................................ 30

3.2.1.11 Read Sector(s) - 20h or 21h ............................................................................................................. 30

3.2.1.12 Read Verify Sector(s) - 40h or 41h ................................................................................................... 31

3.2.1.13 Recalibrate - 1Xh .............................................................................................................................. 31

3.2.1.14 Seek - 7Xh ........................................................................................................................................ 32

3.2.1.15 Set Features - EFh............................................................................................................................ 32

3.2.1.16 Set Multiple Mode - C6h .................................................................................................................. 34

3.2.1.17 Set Sleep Mode- 99h or E6h ............................................................................................................ 34

3.2.1.18 Standby - 96h or E2h ....................................................................................................................... 35

3.2.1.19 Standby Immediate - 94h or E0h ..................................................................................................... 35

3.2.1.20 Write Buffer - E8h ............................................................................................................................. 35

3.2.1.21 Write Long Sector - 32h or 33h ........................................................................................................ 36

3.2.1.22 Write Multiple Command - C5h ....................................................................................................... 36

3.2.1.24 Write Verify - 3Ch .............................................................................................................................. 38

3.2.1.23 Write Sector(s) - 30h or 31h ............................................................................................................. 38

3.2.2 Error Posting......................................................................................................................................... 39

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

391-2 8/00

3

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

4.0 Appendix ...........................................................................................................................40

4.1 Differences between ADC andATA/ATAPI-5 Specifications ......................................................................... 40

4.1.1 Electrical Differences ............................................................................................................................ 40

4.1.1.1 TTL Compatibility .............................................................................................................................. 40

4.1.1.2 Pull Up Resistor Input Leakage Current ........................................................................................... 40

4.1.2 Functional Differences.......................................................................................................................... 40

4.1.2.1 Set Features Codes not Supported in ATA/ATAPI-5 Specifications................................................. 40

4.1.2.2 Additional Set Features Codes in ADC ............................................................................................. 40

4.1.2.3 Idle Timer ........................................................................................................................................... 40

4.1.2.4 Recovery from Sleep Mode ............................................................................................................... 40

5.0 Physical Dimensions........................................................................................................41

Ordering Information ........................................................................................................................................... 42

Valid combinations .............................................................................................................................................. 43

Limited Warranty .................................................................................................................................................. 44

Life Support Policy .............................................................................................................................................. 44

Patent Protection ................................................................................................................................................. 44

391-2 8/00

4

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

1.1.2 Internal Direct Memory Access (DMA)

TheATAcontrollerinsideADCusesDMAallowinginstant

datatransferfrombuffertomemory.Thisimplementation

eliminatesmicrocontrolleroverheadassociatedwithtra-

ditional,firmwarebased,memorycontrol,increasingdata

transferrate.

1.0 General Description

The SST’s ATA-Disk Chip (ADC) contains a controller,

embedded firmware and flash media in a 32-pin DIP

package. Refer to Figure 1-1 for SST’s ADC block

diagram. The controller interfaces with the host system

allowing data to be written to and read from the flash

media.

1

2

1.1.3 Power Management Unit (PMU)

PowerManagementUnitcontrolsthepowerconsumption

of the ADC. The PMU dramatically extends product

battery life by putting the part of the circuitry that is not

in operation into sleep mode.

3

1.1 Optimized for performance ATA Controller

The heart of the ADC is the ATA controller which trans-

lates standard ATA signals into Flash media data and

controls. SST’sADCcontainsaproprietaryATAcontrol-

ler that was specifically designed to attain high data

throughputfromhosttoFlash.Thefollowingcomponents

contribute to the ATA controller’s performance.

4

1.1.4 SRAM Buffer

A key contributor to the ATA controller performance is a

SRAM buffer. The buffer optimizes the data writes to

Flash.

5

1.1.1 Microcontroller Unit (MCU)

TheMCUtranslatesATAcommandsintodataandcontrol

signals required for flash memory operation.

6

1.1.5 Firmware Storage

FirmwareStorageisembeddedwithintheATAcontroller

for optimum data transfer performance.

7

8

ATA Controller

9

Firmware

Storage

MCU

10

11

12

13

14

15

16

SRAM Buffer

Internal

DMA

HOST

Flash

Media

PMU

391 ILL1-1.2

FIGURE 1-1:SSTADCBLOCK DIAGRAM

391-2 8/00

5

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

1.2 SST’s ADC Product Offering

The SST58SDxxx ADC product family is available in 8 to 64 MByte densities. The following table shows the specific

capacity, default number of cylinder heads, sectors and cylinders for each product line.

ModelNumber

SST58SD008

SST58SD016

SST58SD024

SST58SD032

SST58SD048

SST58SD064

Density

8 MB

TotalBytes

8,028,160

Cylinders

245

Heads

Sectors

32

2

4

16 MB

24 MB

32 MB

48 MB

64 MB

16,023,552

24,051,712

32,047,104

48,037,888

64,028,672

489

32

367

32

489

32

733

32

977

32

2.0ElectricalInterface

2.0.1 Pin Assignment and Pin Type

Table 2-2 describes the I/O signals. Signals whose

source is the host are designated as inputs while signals

that the ADC sources are outputs. All outputs from the

ADCaretotempoleexceptthedatabussignalswhichare

in the bi-directional tri-state. Refer to Section 2.3.2 for

definitions of Input and Output types.

The signal/pin assignments are listed in Table 2-1. Low

active signals have a “#” suffix. Pin types are Input,

Output or Input/Output. Section 2.3 defines the DC

characteristics for all input and output type structures.

2.1ElectricalDescription

The ADC functions in ATA Mode, which is compatible

with IDE hard disk drives.

RESET#

D7

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V

CC

D8

2

D6

3

D9

D5

4

D10

D4

5

D11

32-Pin

PDIP

D3

6

D12

D2

7

D13

D1

8

D14

Top View

D0

9

D15

Reserved

IORD#

INTRQ

A1

10

11

12

13

14

15

16

IOWR#

CSEL

IOCS16#

PDIAG#

A2

A0

CS1FX#

GND

CS3FX#

DASP#

391 ILL F01.2

F^IGURE1-2:PIN ASSIGNMENTS FOR 32-PIN PDIP

391-2 8/00

6

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

TABLE 2-1:PIN ASSIGNMENT

1

Pin NO. Signal

Name

Type

I/O

Type*

1

2

3

4

5

6

7

8

RESET#

D7

I

I2U

I1D, O2

-

2

I/O

-

I

O

I

-

I/O

I

I/O

O

I

D6

D5

D4

D3

D2

D1

D0

3

4

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Reserved

IORD#

INTRQ

A1

5

I3U

O1

I1D

6

A0

CS1FX#

GND

DASP#

CS3FX#

A2

PDIAG#

IOCS16#

CSEL

IOWR#

D15

I3U

Ground

I1U, O1

I3U

I1D

I1U, O1

O2

7

8

9

I2U

I3U

I

I/O

-

I1D, O2

Power

10

11

12

13

14

15

16

D14

D13

D12

D11

D10

D9

D8

V_CC

* Please refer to Sections 2.3.1 to 2.3.4 for detail.

391-2 8/00

7

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

TABLE 2-2:SIGNAL DESCRIPTION

Symbol

Type*

NameandFunctions

A2 - A0

I

13,14,19

A[2:0] are used to select the one of eight registers in

the Task File.

D15 - D0

I/O

9,8,7,6,5,4,3,

2,31,30,29,28,

27,26,25,24

Data bus

CS1FX#,CS3FX#

CSEL

I

15,18

CS1FX# is the chip select for the task file registers

while CS3FX# is used to select the Alternate Status

Register and the Device Control Register.

22

This internally pulled up signal is used to configure this

device as a Master or a Slave. When this pin is grounded,

this device is configured as a Master. When the pin is

open, this device is configured as a Slave.

IORD#

I

11

23

21

This is an I/O Read strobe generated by the host. This

signal gates I/O data onto the bus from the chip.

IOWR#

IOCS16#

The I/O Write strobe pules is used to clock I/O data into

the chip.

O

This output signal is asserted low when this device is

expecting a word data transfer cycle.

Reserved

INTRQ

-

10

12

20

Reserved for future use.

O

Signal is the active high Interrupt Request to the host.

PDIAG#

I/O

This input/output is the Pass Diagnostic signal in the

Master/Slavehandshakeprotocol.

DASP#

I/O

17

This input/output is the Disk Active/Slave present signal in

the Master/Slave handshake protocol.

RESET#

GND

I

1

This input pin is the active low hardware reset from the host.

-

16

32

Ground

Power

Vcc

391-2 8/00

8

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

2.2 Absolute Maximum Stress Ratings

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress

Ratings”maycausepermanentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedevice

at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.

Exposure to absolute maximum stress rating conditions may affect device reliability.)

1

2

TemperatureUnderBias ................................................................................................................... -55°Cto+125°C

StorageTemperature ........................................................................................................................ -50°Cto+100°C

D. C. Voltage on Any Pin to Ground Potential .............................................................................. -0.5V to V_DD+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential.......................................................... -1.0V to V_DD+ 1.0V

Package Power Dissipation Capability (Ta = 25°C) ............................................................................................ 1.0W

ThroughHoleLeadSolderingTemperature(10Seconds) .................................................................................. 300°C

SurfaceMountLeadSolderingTemperature(3Seconds) .................................................................................. 240°C

Output Short Circuit Current¹.................................................................................................................................................................... 50 mA

Note: 1. Outputs shorted for no more than one second. No more than one output shorted at a time.

3

4

5

SST58SDXXX OPERATING RANGE

ACCONDITIONS OF TEST

6

Range

AmbientTemp

0 °C to +70 °C

-40 °C to +85 °C

V_DD

Input Rise/Fall Time ......... 10 ns

OutputLoad ..................... C_L= 100 pF

See Figures 12 and 13

Commercial

Industrial

5V ± 10%

5V ± 5%

7

SST58LDXXX OPERATING RANGE

Range

AmbientTemp

0 °C to +70 °C

-40 °C to +85 °C

V_DD

8

Commercial

Industrial

3.3V ± 5%

9

TABLE 2-3:RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol

Parameter

Maximum

Units

10

11

12

13

14

15

16

1

T_PU-READY

Power-uptoReadyOperation

Power-uptoWriteOperation

500

ms

1

T_PU-WRITE

391PGMT10.0

TABLE 2-4: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open)

Parameter

Description

TestCondition

V_I/O= 0V

Maximum

15 pF

1

C_I/O

I/O Pin Capacitance

InputCapacitance

1

C_IN

V_IN= 0V

9 pF

391PGMT11.0

Note: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE2-5:RELIABILITY CHARACTERISTICS

Symbol

Parameter

Minimum Specification

Units

TestMethod

1

V_{ZAP_HBM}

ESD Susceptibility

HumanBodyModel

2000

Volts

JEDECStandardA114

1

V_{ZAP_MM}

ESD Susceptibility

MachineModel

200

Volts

mA

JEDECStandardA115

JEDEC Standard 78

1

I_LTH

Latch Up

100 + I_DD

391PGMT12.0

Note: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

391-2 8/00

9

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

2.3ElectricalSpecification

The following tables define all D.C. Characteristics for the SST ADC product family

2.3.1 Absolute Maximum Conditions

Unless otherwise stated, conditions are for Commercial Temperature:

V_CC= 5.0V ± 10%

V_CC= 3.3V ± 5%

T_A= 0°C to 70°C

Nonoperating(storage)temperaturerange-50°Cto+100°C

ABSOLUTE MAXIMUMCONDITIONS

Parameter

Symbol

V_CC

Conditions

InputPower

-0.3V min. to 6.5V max.

-0.5V min. to V_CC+ 0.5V max.

Voltage on any pin except Vcc with respect to GND.

V

I^NPUTPOWER

Voltage

3.3V ± 5%

5.0V ± 10%

MaximumAverageRMSCurrent

MeasurementMethod

3.3V at 25°C ¹

75 mA

100 mA

5.0V at 25°C ¹

Note 1: Current measurement is accomplished by connecting an amp meter (set to the 2 amp scale range) in series with the Vcc supply

to the ADC. Current measurements are to be taken while looping on a data transfer command with a sector count of 128. Current

consumption values for both read and write commands are not to exceed the Maximum Average RMS Current

specified in the above table.

Unless otherwise stated, conditions are for Industrial Temperature:

V_CC= 5.0V ± 5%

V_CC= 3.3V ± 5%

T_A= -40°C to 85°C

Nonoperating(storage)temperaturerange-50°Cto+100°C

ABSOLUTE MAXIMUMCONDITIONS

Parameter

Symbol

V_CC

Conditions

InputPower

-0.3V min. to 6.5V max.

-0.5V min. to V_CC+ 0.5V max.

Voltage on any pin except Vcc with respect to GND.

V

INPUT POWER

Voltage

3.3V ± 5%

5.0V ± 10%

MaximumAverageRMSCurrent

MeasurementMethod

3.3V at 25°C ¹

75 mA

100 mA

5.0V at 25°C ¹

Note 1: Current measurement is accomplished by connecting an amp meter (set to the 2 amp scale range) in series with the Vcc supply

to the ADC. Current measurements are to be taken while looping on a data transfer command with a sector count of 128. Current

consumption values for both read and write commands are not to exceed the Maximum Average RMS Current

specified in the above table.

391-2 8/00

10

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

ADC products shall operate correctly in both voltage ranges as shown in the tables above. To comply with this

specification, current requirements must not exceed the maximum limit.

1

2.3.2InputLeakageCurrent

Note: In the table below, x refers to the characteristics described in section 2.3.2. For example, I1U indicates a pull up resistor with a

2

type 1 input characteristic.

Type

IxZ

Parameter

Symbol

IL

Conditions

Vih = Vcc / Vil = Gnd

Vcc = 5.0V

MIN

-1

TYP

MAX

1

Units

µA

3

InputLeakageCurrent

Pull Up Resistor

Pull Down Resistor

IxU

RPU1

RPD1

50k

500k

Ohm

4

IxD

Vcc = 5.0V

5

2.3.3INPUTCHARACTERISTICS

Type

Parameter

Symbol

MIN

TYP

MAX

MIN

TYP

MAX

Units

V_CC= 3.3V

V_CC= 5.0V

6

1

2

3

InputVoltage

CMOS

Vih

Vil

2.4

2.0

4.0 ¹

2.0

Volts

0.6

0.8

7

InputVoltage

TTL(compatible)

Vih

Vil

InputVoltage

CMOS

Vth

Vtl

2.15

1.05

3.0

2.0

8

Schmitt Trigger

Note 1: The host must provide a logic output high voltage for a CMOS load of .9 x V_CC. For a 5 volt product, this translates to .9 x 4.5 =

9

4.05 volts minimum Voh.

10

11

12

13

14

15

16

2.3.4 Output Drive Type

All output drive type are CMOS level.

2.3.5OUTPUT DRIVE CHARACTERISTICS

Type

Parameter

Symbol

Conditions

MIN

TYP

MAX

Units

O1

OutputVoltage

Voh

Ioh = -4 mA

Vcc

-0.8V

Volts

Vol

Iol = 4 mA

Gnd

+0.4V

O2

OutputVoltage

Voh

Vol

Ioh = -8 mA

Iol = 8 mA

Vcc

-0.8V

Volts

Gnd

+0.4V

391-2 8/00

11

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

2.3.6 I/O Input (Read) Timing Specification

TABLE 2-6:I/OREAD TIMING

Item

Symbol

IEEE Symbol

tDVIRH

Min ns

20

Max ns

DataSetupbeforeIORD#

DataHoldfollowingIORD#

IORD# Width Time

tsu(IORD)

–

th(IORD)

tlGHQX

tlGLIGH

tAVIGL

5

tw(IORD)

80

–

Address Setup before IORD #

AddressHoldfollowingIORD#

IOIS16# Delay Falling from Address

IOIS16# Delay Rising from Address

tsuA(IORD)

thA(IORD)

30

–

tlGHAX

20

–

tdfIOIS16(ADR)

tdrIOIS16(ADR)

tAVISL

–

35

–

tAVISH

12

Note: The maximum load on IOIS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds.

A2-A0

tsuA(IORD)

tw(IORD)

thA(IORD)

IORD#

tdrIOIS16(ADR)

tsu (IORD)

IOIS16#

tdfIOIS16(ADR)

th(IORD)

D15-D0

Dout

391 ILL2-7.0

F^IGURE2-1:I/OREAD TIMING DIAGRAM

391-2 8/00

12

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

2.3.7 I/O Output (Write) Timing Specification

T^ABLE2-7:I/OWRITE TIMING

1

Item

Symbol

IEEE Symbol

tDVIWH

tlWHDX

Min ns

30

Max ns

DataSetupbeforeIOWR#

DataHoldfollowingIOWR#

IOWR# Width Time

tsu(IOWR)

th(IOWR)

–

2

10

tw(IOWR)

tlWLIWH

tAVIWL

80

–

Address Setup before IOWR#

AddressHoldfollowingIOWR#

IOIS16# Delay Falling from Address

IOIS16# Delay Rising from Address

tsuA(IOWR)

thA(IOWR)

tdfIOIS16(ADR)

tdrIOIS16(ADR)

30

–

3

tlWHAX

20

–

tAVISL

–

35

–

4

tAVISH

12

Notes: The maximum load on IOIS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds.

5

6

A2-A0

7

tsuA(IOWR)

tw(IOWR)

thA(IOWR)

IOWR#

tdrIOIS16(ADR)

8

IOIS16#

9

tdfIOIS16(ADR)

tsu(IOWR)

th(IOWR)

D15-D0

Din Valid

10

11

12

13

14

15

16

391 ILL2-8.1

FIGURE 2-2:I/OWRITE TIMING DIAGRAM

V

IHT

V

HT

INPUT

REFERENCE POINTS

OUTPUT

V

LT

V

ILT

391 ILL F11.0

AC test inputs are driven at V_IHT(2.4 V) for a logic “1” and V_ILT(0.4 V) for a logic “0”. Measurement reference points

for inputs and outputs are V_HT(2.0 V) and V_LT(0.8 V). Inputs rise and fall times (10% « 90%) are <10 ns.

Note: V_HT–V_HIGHTest

V_LT–V_LOWTest

V_IHT–V_INPUTHIGH Test

V_ILT–V_INPUTLOW Test

FIGURE 2-3:ACINPUT/OUTPUT REFERENCE WAVEFORMS

391-2 8/00

13

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

2.4 I/O Transfer Function

2.4.1 I/O Function

ADC permits 8-bit data access if the user issues a Set Feature Command to enable 8-bit Mode.

The following table defines the function of various operations.

TABLE 2-8:I/OFUNCTION

FunctionCode

InvalidMode

CS3FX# CS1FX# A0-A2 IORD#

IOWR#

D15-D8

Undefined

High Z

D7-D0

Undefined

High Z

Data In

Data Out

In

L

H

L

H

L

X

H

L

X

L

StandbyMode

Task File Write

Task File Read

DataRegisterWrite

DataRegisterRead

1-7h

0

Don’tCare

High Z

L

H

L

H

L

In*

L

0

H

L

Out*

Out

ControlRegister

Write

H

6h

H

Don’tCare

ControlIn

Alt Status Read

L

H

6h

7h

L

H

High Z

Status Out

Data Out

DriveAddress

* If 8-bit data transfer mode is enabled.

In 8-bit data transfer mode, High Byte is undefined for Data Out, Don't Care for Data In.

391-2 8/00

14

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.0SoftwareInterface

3.1 ADC Drive Register Set Definitions and Protocol

1

3.1.1ADCAddressing

The I/O decoding for an ADC is as follows:

2

T^ABLE3-1:TASK REGISTERS

3

CS3FX# CS1FX#

A2

0

A1

0

A0

0

IORD# = 0

IOWR# = 0

WRData

1

0

1

RDData

0

1

ErrorRegister

SectorCount

Sector No.

Features

4

0

1

0

SectorCount

Sector No.

0

1

5

1

0

CylinderLow

CylinderHigh

SelectCard/Head

Status

CylinderLow

CylinderHigh

SelectCard/Head

Command

1

0

1

6

1

0

1

0

Alt Status

DeviceControl

Reserved

7

1

DriveAddress

8

3.1.2ADCRegisters

ThefollowingsectiondescribesthehardwareregistersusedbythehostsoftwaretoissuecommandstotheADC.These

registers are often collectively referred to as the “Task File Registers.”

9

10

11

12

13

14

15

16

3.1.2.1DataRegister

This 16-bit register is used to transfer data blocks between the device data buffer and the host. It is also the register

through which sector information is transferred on a Format Track command. Data transfer can be performed in PIO

mode.

391-2 8/00

15

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.1.2.2 Error Register (Read Only)

Thisregistercontainsadditionalinformationaboutthesourceofanerrorwhenanerrorisindicatedinbit0oftheStatus

register. The bits are defined as follows:

D7

D6

D5

D4

D3

D2

D1

D0

BBK

UNC

0

IDNF

0

ABRT

0

AMNF

Bit7(BBK)

Bit6(UNC)

Bit 5

This bit is set when a Bad Block is detected.

This bit is set when an Uncorrectable Error is encountered.

This bit is 0.

Bit 4 (IDNF)

Bit 3

The requested sector ID is in error or cannot be found.

This bit is 0.

Bit2(Abort)

This bit is set if the command has been aborted because of an ADC status condition:

(Not Ready, Write Fault, etc.) or when an invalid command has been issued.

Bit 1

This bit is 0.

Bit0(AMNF) This bit is set in case of a general error.

3.1.2.3FeatureRegister(WriteOnly)

This register provides information regarding features of the ADC that the host can utilize.

3.1.2.4SectorCountRegister

ThisregistercontainsthenumbersofsectorsofdatarequestedtobetransferredonaReadorWriteoperationbetween

the host and the ADC. If the value in this register is zero, a count of 256 sectors is specified. If the command was

successful,thisregisteriszeroatcommandcompletion.Ifnotsuccessfullycompleted,theregistercontainsthenumber

of sectors that need to be transferred in order to complete the request.

3.1.2.5SectorNumber(LBA7-0)Register

Thisregistercontainsthestartingsectornumberorbits7-0oftheLogicalBlockAddress(LBA)foranyADCdataaccess

for the subsequent command.

3.1.2.6CylinderLow(LBA15-8)Register

This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of then Logical Block Address.

3.1.2.7CylinderHigh(LBA23-16)Register

This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address.

391-2 8/00

16

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.1.2.8Drive/Head(LBA27-24)Register

TheDrive/Headregisterisusedtoselectthedriveandhead.ItisalsousedtoselectLBAaddressinginsteadofcylinder/

head/sector addressing. The bits are defined as follows:

1

D7

D6

D5

D4

D3

D2

D1

D0

1

LBA

1

DRV

HS3

HS2

HS1

HS0

2

Bit 7

Bit 6

This bit is set to 1.

LBAisaflagtoselecteitherCylinder/Head/Sector(CHS)orLogicalBlockAddressMode(LBA).When

LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is selected. In

Logical Block Mode, the Logical Block Address is interpreted as follows:

3

4

LBA7-LBA0:SectorNumberRegisterD7-D0.

LBA15-LBA8:CylinderLowRegisterD7-D0.

LBA23-LBA16:CylinderHighRegisterD7-D0.

LBA27-LBA24:Drive/HeadRegisterbitsHS3-HS0.

This bit is set to 1.

5

6

Bit 5

Bit 4 (DRV)

Bit 3 (HS3)

Bit 2 (HS2)

Bit 1 (HS1)

Bit 0 (HS0)

DRV is the drive number. When DRV=0 (Master), Master is selected. When DRV=1(Slave), Slave is

selected.

7

When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in

the Logical Block Address mode.

8

When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the

Logical Block Address mode.

When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the

Logical Block Address mode.

9

When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the

Logical Block Address mode.

10

11

12

13

14

15

16

391-2 8/00

17

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.1.2.9Status&AlternateStatusRegisters(ReadOnly)

TheseregistersreturntheADCstatuswhenreadbythehost.ReadingtheStatusregisterdoesclearapendinginterrupt

while reading the Auxiliary Status register does not. The meaning of the status bits are described as follows:

D7

D6

D5

D4

D3

D2

D1

D0

BUSY

RDY

DWF

DSC

DRQ

CORR

0

ERR

Bit 7 (BUSY) The busy bit is set when the ADC has access to the command buffer and registers and

the host is locked out from accessing the command register and buffer. No other bits in this register

are valid when this bit is set to a 1.

Bit 6 (RDY)

RDY indicates whether the device is capable of performing ADC operations. This bit

is cleared at power up and remains cleared until the ADC is ready to accept a command.

Bit 5 (DWF)

Bit 4 (DSC)

Bit3(DRQ)

This bit, if set, indicates a write fault has occurred.

This bit is set when the ADC is ready.

The Data Request is set when the ADC requires that information be transferred either

to or from the host through the Data register.

Bit2(CORR) This bit is set when a Correctable data error has been encountered and the data has been corrected.

This condition does not terminate a multi-sector Read operation.

Bit 1 (IDX)

Bit 0 (ERR)

This bit is always set to 0.

Thisbitissetwhenthepreviouscommandhasendedinsometypeoferror.ThebitsintheErrorregister

contain additional information describing the error. It is recommended that media access commands

(such as Read Sectors and Write Sectors) that end with an error condition should have the address

of the first sector in error in the command block registers.

3.1.2.10DeviceControlRegister(WriteOnly)

This register is used to control the ADC interrupt request and to issue a software Reset. This register can be written to

even if the device is BUSY. The bits are defined as follows:

D7

D6

D5

D4

D3

D2

D1

D0

X

1

SW Rst

-IEn

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

This bit is an X (don’t care).

This bit is ignored by the ADC.

Bit 2 (SW Rst) This bit is set to 1 in order to force the ADC to perform a software Reset operation. The chip

remains in Reset until this bit is reset to ‘0.’

391-2 8/00

18

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

Bit 1 (-IEn)

The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the

ADC are disabled. This bit is Reset to 0 at power on and Reset.

Bit 0

This bit is ignored by the ADC.

1

3.1.2.11DriveAddressRegister(ReadOnly)

This register contains the inverted drive select and head select addresses of the currently selected drive. The bits in

this register are as follows:

2

3

D7

D6

D5

D4

D3

D2

D1

D0

HiZ

-WTG

-HS3

-HS2

-HS1

-HS0

-DS1

-DS0

4

Bit 7

This bit is HiZ.

5

Bit6(-WTG)

Bit 5 (-HS3)

Bit 4 (-HS2)

Bit 3 (-HS1)

Bit 2 (-HS0)

Bit 1 (-DS1)

Bit 0 (-DS0)

This bit is 0 when a Write operation is in progress, otherwise, it is 1.

This bit is the negation of bit 3 in the Drive/Head register.

This bit is the negation of bit 2 in the Drive/Head register.

This bit is the negation of bit 1 in the Drive/Head register.

This bit is the negation of bit 0 in the Drive/Head register.

This bit is 0 when drive 1 is active and selected.

6

7

8

This bit is 0 when the drive 0 is active and selected.

9

3.1.2.12CommandRegister(WriteOnly)

This register contains the command code being sent to the drive. Command execution begins immediately after this

registeriswritten.Theexecutablecommands,thecommandcodes,andthenecessaryparametersforeachcommand

are listed in Table 3-2.

10

11

12

13

14

15

16

391-2 8/00

19

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2ADCCommandDescription

ThissectiondefinesthesoftwarerequirementsandtheformatofthecommandsthehostsendstotheADC.Commands

are issued to the ADC by loading the required registers in the command block with the supplied parameters, and then

writing the command code to the Command Register. The manner in which a command is accepted varies. There are

threeclasses(seeTable3-2)ofcommandacceptance,alldependentonthehostnotissuingcommandsunlesstheADC

is not busy (BSY=0).

3.2.1 ADC Command Set

Table 3-2 summarizes the ADC command set with the paragraphs that follow describing the individual commands and

the task file for each.

TABLE 3-2:ADCCOMMAND SET

Class

1

COMMAND

Code

FR

-

SC

-

SN

-

CY

-

DH

D

Y

D

Y

D

Y

D

Y

D

Y

LBA

-

CheckPowerMode

Execute Drive Diagnostic

Format Track

E5h or 98h

90h

1

-

2

50h

-

Y

-

Y

-

Y

-

1

Identify Drive

ECh

-

1

Idle

E3h or 97h

E1h or 95h

91h

-

Y

-

1

Idle Immediate

Initialize Drive Parameters

ReadBuffer

-

1

-

Y

-

1

E4h

-

1

ReadLongSector

ReadMultiple

ReadSector(s)

Read Verify Sector(s)

Recalibrate

22h or 23h

C4h

-

Y

-

Y

-

Y

-

1

-

Y

-

1

20h or 21h

40h or 41h

1Xh

-

1

-

1

-

1

Seek

7Xh

-

Y

-

Y

-

Y

-

1

Set Features

EFh

Y

-

1

Set Multiple Mode

Set Sleep Mode

Stand By

C6h

Y

-

1

E6h or 99h

E2h or 96h

E0h or 94h

E8h

-

1

-

1

Stand By Immediate

Write Buffer

-

2

-

2

Write Long Sector

WriteMultiple

WriteSector(s)

Write Verify

32h or 33h

C5h

-

Y

3

-

Y

2

30h or 31h

3Ch

-

3

-

391-2 8/00

20

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

Definitions:

FR = Features Register, SC = Sector Count Register, SN = Sector Number Register, CY = Cylinder

Registers, DH = Drive/Head Register, LBA = Logical Block Address Mode Supported (see command

descriptions for use).

1

Y - The register contains a valid parameter for this command. For the Drive/Head Register Y means

both the ADC and Head parameters are used; D - only the ADC parameter is valid and not the Head

parameter.

2

3

3.2.1.1 Check Power Mode - 98h or E5h

4

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

98h or E5h

Drive

5

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

6

7

8

This command checks the power mode.

Because SST ADC can recover from sleep in 200ns, Idle Mode is never enabled.

ADC sets BSY, sets the Sector Count Register to 00h, clears BSY and generates an interrupt.

9

10

11

12

13

14

15

16

391-2 8/00

21

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.2 Execute Drive Diagnostic - 90h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

90h

X

Drive

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

This command performs the internal diagnostic tests implemented by the ADC.

If the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave with the Master

responding with status for both devices.

The Diagnostic codes shown in Table 3-3 are returned in the Error Register at the end of the command.

TABLE 3-3:DIAGNOSTIC CODES

Code

01h

02h

03h

04h

05h

8Xh

Error Type

NoErrorDetected

FormatterDeviceError

Sector Buffer Error

ECCCircuitryError

ControllingMicroprocessorError

SlaveError

391-2 8/00

22

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.3 Format Track - 50h

1

Bit ->

Command(7)

C/D/H(6)

7

1

6

5

1

4

3

2

1

0

50h

LBA

Drive

Head (LBA 27-24)

2

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

X (LBA 7-0)

3

Count (LBA mode only)

X

4

Thiscommandwritesthedesiredheadandcylinderoftheselecteddrivewithavendoruniquedatapattern(typicallyFFh

or 00h). To remain host backward compatible, the ADC expects a sector buffer of data from the host to follow the

command with the same protocol as the Write Sector(s) command although the information in the buffer is not used by

the ADC. If LBA=1 then the number of sectors to format is taken from the Sec Cnt register (0=256). The use of this

command is not recommended.

5

6

7

3.2.1.4 Identify Drive - ECh

8

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

ECh

9

X

Drive

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

10

11

12

13

14

15

16

The Identify Drive command enables the host to receive parameter information from the ADC. This command has the

sameprotocolastheReadSector(s)command.Theparameterwordsinthebufferhavethearrangementandmeanings

defined in Table 3-4. All reserved bits or words are zero. Table 3-4 is the definition for each field in the Identify Drive

Information.

391-2 8/00

23

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

TABLE 3-4:IDENTIFYDRIVE INFORMATION

Word

Address

Default

Value

Total

Bytes

Data Field Type Information

0

044Ah

XXXXh

0000h

00XXh

XXXXh

aaaa*

2

Generalconfigurationbit-significantinformation

Default number of cylinders

1

2

Reserved

3

2

Default number of heads

4

2

Number of unformatted bytes per track

Number of unformatted bytes per sector

Default number of sectors per track

Number of sectors per card (Word 7 = MSW, Word 8 = LSW)

VendorUnique

5

2

6

2

7-8

9

4

2

10-19

20

2

Serial number in ASCII (Right Justified) Big Endian Byte Order in Word

Buffer type

0002h

XXXXh

0004h

aaaa*

21

2

Buffer size in 512 Byte increments

# of ECC bytes passed on Read/Write Long Commands

Firmware revision in ASCII. Big Endian Byte Order in Word

Model number in ASCII (Left Justified) Big Endian Byte Order in Word

Maximum number of sectors on Read/Write Multiple command

DoubleWordnotsupported

22

2

23-26

27-46

47

8

aaaa*

40

2

000Xh

0000h

0200h

0000h

0X00h

0000h

000Xh

XXXXh

010Xh

XXXXh

0000h

00XX

48

2

49

2

Capabilities

50

2

Reserved

51

2

PIO data transfer cycle timing mode

DMA data transfer cycle timing mode

Translationparametersarevalid

Current numbers of cylinders

52

2

53

2

54

2

55

2

Currentnumbersofheads

56

2

Current sectors per track

57-58

59

4

Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW)

Multiple sector setting

2

60-61

62-63

64

4

Total number of sectors addressable in LBA Mode

Reserved for DMA Data Transfer

Advance PIO Transfer Mode Supported

Reserved

4

2

65-66

67

0000h

XXXXh

0000h

4

2

Minimum PIO transfer cycle time without flow control

Minimum PIO transfer cycle time with IORDY flow control

Reserved

68

2

69-127

128-159

160-255

138

64

192

Vendoruniquebytes

Reserved

*aaaa - any SST specific number

391-2 8/00

24

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.4.1GeneralConfiguration

This field informs the host that this is a non-magnetic, hard sectored, removable storage device with a transfer

rate greater than 10 MByte/sec and is not MFM encoded.

1

3.2.1.4.2 Default Number of Cylinders

Thisfieldcontainsthenumberoftranslatedcylindersinthedefaulttranslationmode.Thisvaluewillbethesame

as the number of cylinders.

2

3.2.1.4.3 Default Number of Heads

3

This field contains the number of translated heads in the default translation mode.

3.2.1.4.4NumberofUnformattedBytesperTrack

4

This field contains the number of unformatted bytes per translated track in the default translation mode.

3.2.1.4.5NumberofUnformattedBytesperSector

5

This field contains the number of unformatted bytes per sector in the default translation mode.

3.2.1.4.6 Default Number of Sectors per Track

This field contains the number of sectors per track in the default translation mode.

6

3.2.1.4.7 Number of Sectors

This field contains the number of sectors per ADC. This double word value is also the first invalid

address in LBA translation mode.

7

3.2.1.4.8 Memory Serial Number

8

The contents of this field are right justified and padded with spaces (20h).

3.2.1.4.9BufferType

9

This field defines the buffer capability:

0002h: a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the

ADC.

10

11

12

13

14

15

16

3.2.1.4.10 Buffer Size

This field defines the buffer capacity in 512 Byte increments. SST’s ADC has up to 2 sector data

buffer for host interface.

3.2.1.4.11ECCCount

This field defines the number of ECC bytes used on each sector in the Read and Write Long commands.

391-2 8/00

25

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.4.12FirmwareRevision

This field contains the revision of the firmware for this product.

3.2.1.4.13 Model Number

This field contains the model number for this product and is left justified and padded with spaces (20h).

3.2.1.4.14Read/WriteMultipleSectorCount

This field contains the maximum number of sectors that can be read or written per interrupt using the Read

Multiple or Write Multiple commands.

3.2.1.4.15 Double Word Support

This field indicates this product will not support double word transfers.

3.2.1.4.16Capabilities

Bit 13: Standby Timer

Set to 0, forces sleep mode when host is inactive.

Bit 11: IORDY Support

Set to 0, indicates that this device may support IORDY operation.

Bit 9: LBA support

Set to 1, SST’s ADCs support LBA mode addressing.

Bit 8: DMA Support

This bit is set to 0. DMA mode is not supported.

3.2.1.4.17 PIO Data Transfer Cycle Timing Mode

This field defines the mode for PIO data transfer.

3.2.1.4.18 DMA Data Transfer Cycle Timing Mode

This field defines the mode for DMA data transfer.

3.2.1.4.19TranslationParametersValid

Ifbit0is1,itindicatesthatwords54to58arevalidandreflectthecurrentnumberofcylinders,headsandsectors.

If bit 1 is 1, it indicates that words 64 to 70 are valid to support PIO mode 3.

3.2.1.4.20CurrentNumberofCylinders,Heads,Sectors/Track

These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the

currenttranslationmode.

3.2.1.4.21CurrentCapacity

This field contains the product of the current cylinders times heads times sectors.

391-2 8/00

26

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.4.22 Multiple Sector Setting

This field contains a validity flag in the Odd Byte and the current number of sectors that can be transferred per

interrupt for R/W Multiple in the Even Byte. The Odd Byte is always 01h which indicates that the Even Byte is

always valid.

1

The Even Byte value depends on the value set by the Set Multiple command. The Even Byte of this word by

default contains a 00h which indicates that R/W Multiple commands are not valid.

2

3.2.1.4.23 Total Sectors Addressable in LBA Mode

This field contains the number of sectors addressable for the ADC in LBA mode only.

3

3.2.1.4.24AdvancedPIODataTransferMode

ADC supports up to PIO Mode-3.

4

3.2.1.4.25 Minimum PIO Transfer Cycle Time Without Flow Control

The ADC’s minimum cycle time is 180 ns.

5

3.2.1.4.26 Minimum PIO Transfer Cycle Time With IORDY

The ADC’s minimum cycle time is 180 ns, e.g., PIO Mode-3.

6

3.2.1.5 Idle - 97h or E3h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

7

97h or E3h

Drive

X

8

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

9

Timer Count (5 msec increments)

X

10

11

12

13

14

15

16

ThiscommandcausestheADCtosetBSY,entertheIdleMode,clearBSYandgenerateaninterrupt.Ifthesectorcount

isnon-zero, itisinterpretedasatimercountwitheachcountbeing5millisecondsandtheautomaticpowerdownmode

is enabled. If the sector count is zero, the automatic power down mode is also enabled, the timer count is set to 3, with

each count being 5 ms. Note that this time base (5 msec) is different from the ATA specification.

3.2.1.6 Idle Immediate - 95h or E1h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

95h or E1h

Drive

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

This command causes the ADC to set BSY, enter the Idle Mode, clear BSY and generate an interrupt.

391-2 8/00

27

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.7 Initialize Drive Parameters - 91h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

91h

X

0

X

Drive

Max Head (no. of heads-1)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

Number of Sectors

X

This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the

Sector Count and the Drive/Head registers are used by this command.

3.2.1.8 Read Buffer - E4h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

E4h

X

Drive

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

TheReadBuffercommandenablesthehosttoreadthecurrentcontentsoftheADC’ssectorbuffer.Thiscommandhas

the same protocol as the Read Sector(s) command.

391-2 8/00

28

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.9 Read Multiple - C4h

Bit ->

Command(7)

C/D/H(6)

7

6

5

1

4

3

2

1

0

C4h

1

LBA

Drive

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

Sector Number (LBA 7-0)

SectorCount

2

3

X

The Read Multiple command is similar to the Read Sector(s) command. Interrupts are not generated on every sector,

but on the transfer of a block which contains the number of sectors defined by a Set Multiple command.

4

CommandexecutionisidenticaltotheReadSectorsoperationexceptthatthenumberofsectorsdefinedbyaSetMultiple

command are transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of

the data block, not on each sector.

5

The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode

command, which must be executed prior to the Read Multiple command. When the Read Multiple command is issued,

the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If

thenumberofrequestedsectorsisnotevenlydivisiblebytheblockcount,asmanyfullblocksaspossiblearetransferred,

followed by a final, partial block transfer. The partial block transfer is for n sectors, where

6

7

n = (sector count) - modulo (block count).

8

If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read

Multiple commands are disabled, the Read Multiple operation is rejected with an Aborted Command error. Disk errors

encounteredduringReadMultiplecommandsarepostedatthebeginningoftheblockorpartialblocktransfer,butDRQ

is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any.

9

InterruptsaregeneratedwhenDRQissetatthebeginningofeachblockorpartialblock.Theerrorreportingisthesame

as that on a Read Sector(s) Command. This command reads from 1 to 256 sectors as specified in the Sector Count

register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number

Register.

10

11

12

13

14

15

16

Atcommandcompletion,theCommandBlockRegisterscontainthecylinder,headandsectornumberofthelastsector

read.

If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain

the cylinder, head and sector number of the sector where the error occurred. The flawed data is pending in the sector

buffer.

Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause

the command to stop after transfer of the block which contained the error.

391-2 8/00

29

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.10 Read Long Sector - 22h or 23h

Bit ->

Command(7)

C/D/H(6)

7

6

5

1

4

3

2

1

0

22h or 23h

Drive

1

LBA

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

Sector Number (LBA 7-0)

X

The Read Long command performs similarly to the Read Sector(s) command except that it returns 516 Bytes of data

instead of 512 Bytes. During a Read Long command, the ADC does not check the ECC bytes to determine if there has

been a data error. Only single sector read long operations are supported. The transfer consists of 512 Bytes of data

transferred in Word-Mode followed by 4 Bytes of ECC data transferred in Byte-Mode. This command has the same

protocol as the Read Sector(s) command. Use of this command is not recommended.

3.2.1.11 Read Sector(s) - 20h or 21h

Bit ->

Command(7)

C/D/H(6)

7

6

5

1

4

3

2

1

0

20h or 21h

Drive

1

LBA

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

Sector Number (LBA 7-0)

SectorCount

X

This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256

sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued and

after each sector of data (except the last one) has been read by the host, the ADC sets BSY, puts the sector of data

inthebuffer,setsDRQ,clearsBSY,andgeneratesaninterrupt.Thehostthenreadsthe512Bytesofdatafromthebuffer.

Atcommandcompletion,theCommandBlockRegisterscontainthecylinder,headandsectornumberofthelastsector

read.Ifanerroroccurs,thereadterminatesatthesectorwheretheerroroccurred.TheCommandBlockRegisterscontain

the cylinder, head, and sector number of the sector where the error occurred. The flawed data is pending in the sector

buffer.

391-2 8/00

30

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.12 Read Verify Sector(s) - 40h or 41h

Bit ->

Command(7)

C/D/H(6)

7

6

5

1

4

3

2

1

0

40h or 41h

Drive

1

LBA

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

Sector Number (LBA 7-0)

SectorCount

2

3

X

This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to

the host. When the command is accepted, the ADC sets BSY.

4

When the requested sectors have been verified, the ADC clears BSY and generates an interrupt. Upon command

completion, the Command Block Registers contain the cylinder, head, and sector number of the last sector verified.

5

Ifanerroroccurs, theverifyterminatesatthesectorwheretheerroroccurs. TheCommandBlockRegisterscontainthe

cylinder,headandsectornumberofthesectorwheretheerroroccurred.TheSectorCountRegistercontainsthenumber

of sectors not yet verified.

6

7

3.2.1.13 Recalibrate - 1Xh

8

Bit ->

Command(7)

C/D/H(6)

7

1

6

5

1

4

3

2

1

0

1Xh

LBA

Drive

X

9

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

10

11

12

13

14

15

16

This command is effectively a NOP command to the ADC and is provided for compatibility purposes.

391-2 8/00

31

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.14 Seek - 7Xh

Bit ->

7

1

6

5

1

4

3

2

1

0

Command(7)

C/D/H(6)

7Xh

LBA

Drive

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

X (LBA 7-0)

X

This command is effectively a NOP command to the ADC although it does perform a range check of cylinder and head

or LBA address and returns an error if the address is out of range.

3.2.1.15 Set Features - EFh

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

EFh

X

Drive

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

Config

Feature

Thiscommandisusedbythehosttoestablishorselectcertainfeatures.Table3-5definesallfeaturesthataresupported.

391-2 8/00

32

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

TABLE 3-5:FEATURES SUPPORTED

Feature

01h

Operation

1

Enable 8-bit data transfers.

55h

Disable Read Look Ahead.

66h

Disable Power on Reset (POR) establishment of defaults at software Reset.

NOP - Accepted for backward compatibility.

Disable 8-bit data transfer.

2

69h

81h

3

96h

NOP - Accepted for backward compatibility.

Accepted for backward compatibility. Use of this Feature is not recommended.

NOP- accepted for compatibility.

97h

4

9Ah

BBh

CCh

4 Bytes of data apply on Read/Write Long commands.

Enable Power on Reset (POR) establishment of defaults at software Reset.

5

Features 01h and 81h are used to enable and clear 8-bit data transfer mode. If the 01h feature command is issued all

data transfers will occur on the low order D7-D0 data bus and the IOIS16 signal will not be asserted for data register

accesses.

6

Features 55h and BBh are the default features for the ADC; thus, the host does not have to issue this command with

these features unless it is necessary for compatibility reasons.

7

Features66handCChcanbeusedtoenableanddisablewhetherthePowerOnReset(POR)Defaultswillbesetwhen

a software Reset occurs.

8

9

10

11

12

13

14

15

16

391-2 8/00

33

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.16 Set Multiple Mode - C6h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

C6h

X

Drive

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

SectorCount

X

ThiscommandenablestheADCtoperformReadandWriteMultipleoperationsandestablishestheblockcountforthese

commands. The Sector Count Register is loaded with the number of sectors per block. Upon receipt of the command,

the ADC sets BSY to 1 and checks the Sector Count Register.

IftheSectorCountRegistercontainsavalidvalueandtheblockcountissupported,thevalueisloadedforallsubsequent

Read Multiple and Write Multiple commands and execution of those commands is enabled. If a block count is not

supported, an Aborted Command error is posted, and Read Multiple and Write Multiple commands are disabled. If the

Sector Count Register contains 0 when the command is issued, Read and Write Multiple commands are disabled. At

power on, or after a hardware or (unless disabled by a Set Feature command) software reset, the default mode is Read

and Write Multiple disabled.

3.2.1.17 Set Sleep Mode- 99h or E6h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

99h or E6h

Drive

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

ThiscommandcausestheADCtosetBSY, entertheSleepmode, clearBSYandgenerateaninterrupt. Recoveryfrom

sleep mode is accomplished by simply issuing another command (a reset is permitted but not required). Sleep mode is

alsoenteredwheninternaltimersexpiresothehostdoesnotneedtoissuethiscommandexceptwhenitwishestoenter

Sleep mode immediately. The default value for the timer is 15 milliseconds.

391-2 8/00

34

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.18 Standby - 96h or E2h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

96h or E2h

Drive

1

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

2

3

4

ThiscommandcausestheADCtosetBSY,entertheSleepmode(whichcorrespondstotheATA“Standby”Mode),clear

BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another

command (a reset is not required).

5

6

3.2.1.19 Standby Immediate - 94h or E0h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

94h or E0h

Drive

7

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

8

9

10

11

12

13

14

15

16

This command causes the ADC to set BSY, enter the Sleep mode (which corresponds to the ATA “Standby” Mode),

clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply issuing another

command (a reset is not required).

3.2.1.20 Write Buffer - E8h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

E8h

X

Drive

X

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

X

The Write Buffer command enables the host to overwrite contents of the ADC’s sector buffer with any data pattern

desired. This command has the same protocol as the Write Sector(s) command and transfers 512 Bytes.

391-2 8/00

35

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.21 Write Long Sector - 32h or 33h

Bit ->

Command(7)

C/D/H(6)

7

6

5

1

4

3

2

1

0

32h or 33h

Drive

Cylinder High (LBA 23-16)

CylinderLow(LBA15-8)

1

LBA

Head(LBA27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

SectorNumber(LBA7-0)

X

ThiscommandissimilartotheWriteSector(s)commandexceptthatitwrites516Bytesinsteadof512Bytes.Onlysingle

sectorWriteLongoperationsaresupported.Thetransferconsistsof512BytesofdatatransferredinWord-Modefollowed

by 4 Bytes of ECC transferred in Byte-Mode. Because of the unique nature of the solid-state ADC, the 4 Bytes of ECC

transferred by the host may be used by the ADC. The ADC may discard these 4 Bytes and write the sector with valid

ECC data. This command has the same protocol as the Write Sector(s) command. Use of this command is not

recommended.

3.2.1.22 Write Multiple Command - C5h

Bit ->

Command(7)

C/D/H(6)

7

6

5

4

3

2

1

0

C5h

X

LBA

X

Drive

Head

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

Cylinder High

Cylinder Low

Sector Number

Sector Count

X

Note: The current revision of the SST ADC can support up to a block count of 2 as indicated in the Identify Drive Command information.

This command is similar to the Write Sectors command. The ADC sets BSY within 400 ns of accepting the command.

Interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined

bySetMultiple.CommandexecutionisidenticaltotheWriteSectorsoperationexceptthatthenumberofsectorsdefined

by the Set Multiple command is transferred without intervening interrupts.

DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of

sectorstobetransferredwithoutinterveninginterruptsisprogrammedbytheSetMultipleModecommand, whichmust

be executed prior to the Write Multiple command.

391-2 8/00

36

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

WhentheWriteMultiplecommandisissued,theSectorCountRegistercontainsthenumberofsectors(notthenumber

of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block,

as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is

for n sectors, where:

1

n = sector count (modulo sector/block).

2

If the Write Multiple command is attempted before the Set Multiple Mode command has been executed or when Write

Multiple commands are disabled, the Write Multiple operation will be rejected with an aborted command error.

Errors encountered during Write Multiple commands are posted after the attempted writes of the block or partial block

transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks

are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or

partial block.

3

4

TheCommandBlockRegisterscontainthecylinder,headandsectornumberofthesectorwheretheerroroccurredand

theSectorCountRegistercontainstheresidualnumberofsectorsthatneedtobetransferredforsuccessfulcompletion

of the command e.g. each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector.

The Sector Count Register contains 6 and the address is that of the third sector.

5

6

7

8

9

10

11

12

13

14

15

16

391-2 8/00

37

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.1.23 Write Sector(s) - 30h or 31h

Bit ->

Command(7)

C/D/H(6)

7

6

5

1

4

3

2

1

0

30h or 31h

Drive

1

LBA

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

Sector Number (LBA 7-0)

SectorCount

X

This command writes from 1 to 256 sectors as specified in the Sector Count Register. A sector count of zero requests

256sectors.ThetransferbeginsatthesectorspecifiedintheSectorNumberRegister.Whenthiscommandisaccepted,

the ADC sets BSY, then sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be

written. Nointerruptisgeneratedtostartthefirsthosttransferoperation. Nodatashouldbetransferredbythehostuntil

BSY has been cleared by the host.

For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next

buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is

transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time

BSY is cleared and an interrupt is generated.

If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The

CommandBlockRegisterscontainthecylinder,headandsectornumberofthesectorwheretheerroroccurred.Thehost

may then read the command block to determine what error has occurred, and on which sector.

3.2.1.24 Write Verify - 3Ch

Bit ->

Command(7)

C/D/H(6)

7

6

5

1

4

3

2

1

0

3Ch

1

LBA

Drive

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature(1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

Sector Number (LBA 7-0)

SectorCount

X

ThiscommandissimilartotheWriteSector(s)command,excepteachsectorisverifiedimmediatelyafterbeingwritten.

This command has the same protocol as the Write Sector(s) command.

391-2 8/00

38

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

3.2.2 Error Posting

The following table summarizes the valid status and error value for all the ADC Command set.

TABLE 3-6ERROR AND STATUS REGISTER

1

ErrorRegister

StatusRegister

Command

BBK UNC

IDNF ABRT AMNF DRDY DWF

DSC

V

CORR ERR

2

CheckPowerMode

Execute Drive Diagnostic ¹

Format Track

V

3

V

Identify Drive

Idle

4

Idle Immediate

Initialize Drive Parameters

ReadBuffer

5

V

ReadMultiple

V

6

ReadLongSector

ReadSector(s)

Read Verify Sectors

Recalibrate

V

7

Seek

V

8

Set Features

Set Multiple Mode

Set Sleep Mode

Standby

9

StandbyImmediate

Write Buffer

10

11

12

13

14

15

16

Write Long Sector

WriteMultiple

V

WriteSector(s)

Write Verify

InvalidCommandCode

V = valid on this command

1. See Table 3-3

391-2 8/00

39

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

4.0Appendix

4.1DifferencesbetweenADCandATA/ATAPI-5Specifications

This section details differences between ADC vs. ATA.

4.1.1ElectricalDifferences

4.1.1.1 TTL Compatibility

ADC is not TTL compatible, it is a purely CMOS interface. Refer to section 2.3.2 of this specification.

4.1.1.2 Pull Up Resistor Input Leakage Current

The minimum pull up resistor input leakage current is 50K ohms rather than the 10K ohms stated in the ATA

specification.

4.1.2FunctionalDifferences

4.1.2.1 Set Features Codes not Supported in ATA/ATAPI-5 Specifications

The following Set Features codes are specified in, but not implemented in ADC:

• 03h, Set Transfer Mode

• 44h, Vendor unique ECC length

• AAh, Enable Read Look Ahead

4.1.2.2 Additional Set Features Codes in ADC

The following Set Features codes are not in ATA specifications, but provide additional functionality in

ADC.

• 69h, Accepted for backward compatibility

• 96h, Accepted for backward compatibility

• 97h, Accepted for backward compatibility

• 9Ah, Set the host current source capability

4.1.2.3 Idle Timer

The Idle timer uses an incremental value of 5 ms, rather than the 5 sec minimum increment value specified

in ATA specifications.

4.1.2.4 Recovery from Sleep Mode

For ADC devices, recovery from sleep mode is accomplished by simply issuing another command

to the device. A hardware or software reset is not required.

391-2 8/00

40

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

5.0PhysicalDimensions

1

TOP VIEW

BOTTOM VIEW

2

19.30

19.50

15.24

3

2.54

42.50

42.70

4

38.00

38.20

SIDE VIEW

5

5.60

5.70

4.30

4.70

32.psdipP1H-ILL.5

6

0.50

Note: All linear dimensions are in millimeters (min/max).

7

32-PIN PLASTIC SQUARE DUAL-IN-LINE PACKAGE (PSDIP) - P1HPACKAGE

8

9

10

11

12

13

14

15

16

391-2 8/00

41

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

OrderingInformation

SST 58 SD

064

-

80 - C - P 1 H

X XX X X X X X

XX XX XXXX

X

Package Modifier

H = 32 Pins

Package Version

Package Type

P = PDIP

Operating Temperature

C = Commercial: 0° to 70°C

I = Industrial: -40° to +85°C

Endurance

Data Transfer Speed

80 = 80 ns, supports PIO Modes 0-3

Version

Device Density

008 =

8 MBytes

016 = 16 MBytes

024 = 24 MBytes

032 = 32 MBytes

048 = 48 MBytes

064 = 64 MBytes

Voltage

S = 5V

L = 3.3V

Device Family

391-2 8/00

42

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

Valid combinations

SST58SD008 - 80 - C - P1H

SST58SD016 - 80 - C - P1H

SST58SD024 - 80 - C - P1H

SST58SD032 - 80 - C - P1H

SST58SD048 - 80 - C - P1H

SST58SD064 - 80 - C - P1H

SST58SD008 - 80 - I - P1H

SST58SD016 - 80 - I - P1H

SST58SD024 - 80 - I - P1H

SST58SD032 - 80 - I - P1H

SST58SD048 - 80 - I - P1H

SST58SD064 - 80 - I - P1H

1

2

3

SST58LD008 - 80 - C - P1H

SST58LD016 - 80 - C - P1H

SST58LD024 - 80 - C - P1H

SST58LD032 - 80 - C - P1H

SST58LD048 - 80 - C - P1H

SST58LD064 - 80 - C - P1H

SST58LD008 - 80 - I - P1H

SST58LD016 - 80 - I - P1H

SST58LD024 - 80 - I - P1H

SST58LD032 - 80 - I - P1H

SST58LD048 - 80 - I - P1H

SST58LD064 - 80 - I - P1H

4

5

Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

6

representative to confirm availability of valid combinations and to determine availability of new combinations.

7

8

9

10

11

12

13

14

15

16

391-2 8/00

43

SSTATA-DiskChip

SST58SD008 / 016 / 024 / 032 / 048 / 064

SST58LD008 / 016 / 024 / 032 / 048 / 064

Preliminary Specifications

Limited Warranty

SST warrants all products against nonconformances in

materialsandworkmanshipforaperiodofoneyearfrom

the delivery date of subject products. SST’s liability is

limited to replacing or repairing the product if it has been

paidfor.SST’swarrantieswillnotbeaffectedbyrendering

of technical advice in connection with the order of prod-

ucts furnished hereunder. Except as expressly provided

above, SST makes no warranties, express or implied,

includingwithoutlimitationanywarrantyofmerchantabil-

ity or fitness for a particular purpose. In no event shall

SST be liable for any incidental or consequential dam-

ages with respect to the products purchased hereunder.

SST reserves the right to discontinue production or

change specifications or change prices at any time and

without notice.

The information in this publication is believed to be

accurate in all respects at the time of publication, but is

subject to change without notice. SST assumes no

responsibility for any errors or omissions, and disclaims

responsibility for any consequences resulting from the

useoftheinformationprovidedherein. SSTassumesno

responsibility for the use of any circuitry other than

circuitry embodied in an SST product; no other circuits,

patents, or licenses are implied. SST assumes no re-

sponsibility for the functioning of features or parameters

notdescribedherein.

Life Support Policy

SST’s products are not authorized for use as critical

component in life support devices or systems. Life

support devices or systems are devices or systems that,

(a) are intended for surgical implant into the body, or (b)

supportorsustainlifeandwhosefailuretoperform,when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury to the user.

A critical component is any component of a life support

device or system whose failure to perform can be ex-

pected to cause the failure of the life support device or

system, or the affect its safety or effectiveness.

Patent Protection

SST products are protected by assigned U.S. and

foreignpatents.

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873

391-2 8/00

44


型号：	SST58LD024-80-I-P1H
厂家：	SILICON
描述：	EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总44页 (文件大小：309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SST58LD024-80-I-P1H [SILICON]

相关型号：

SST58LD032

SST58LD032-70-C-P1H

SST58LD032-80-C-P1H

SST58LD032-80-I-P1H

SST58LD048

SST58LD048-70-C-P1H

SST58LD048-70-I-P1H

SST58LD048-80-C-P1H

SST58LD048-80-I-P1H

SST58LD064

SST58LD064-70-C-P1H

SST58LD064-70-I-P1H