SST58LD192-70-I-P1H [SILICON]
EEPROM;
| 型号： | SST58LD192-70-I-P1H |
| 厂家： | 
SILICON |
| 描述： | EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总40页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58SD/LDxxxATA-Disk Chip
8MB / 16MB / 24MB / 32MB / 48MB / 64MB / 96MB / 128MB / 192MB
Preliminary Specifications
FEATURES:
•
ATA/IDE standard interface
•
•
•
Controller Overhead Command to DRQ
– 512 Bytes per sector
– ATA command set compatible
– Support Data Transfer Speed up to PIO Mode-4
– Less than 0.5 ms
Zero Power Data Retention
– Batteries not required for data storage
Start Up Time
•
8, 16, 24, 32, 48, 64, 96, 128, and 192 MByte
capacities
– Sleep to read: 200 ns (typical)
– Sleep to write: 200 ns (typical)
– Power-on to Ready:200 ms (typical),
500 ms (maximum)
•
•
600 mil 32-pin DIP package
Single Voltage Read and Write Operation
– 5.0V-only for SST58SDxxx
– 3.3V-only for SST58LDxxx
•
•
Support for Both Commercial and Industrial
Temperature Range
•
•
•
•
Supports 5.0-Volt or 3.3-Volt Read and Write
– 5V ± 10% or 3.3V ± 5% for Commercial
– 5V ± 5% or 3.3V ± 5% for Industrial
–
0°C to +70°C for Operating Commercial
– -40°C to +85°C for Operating Industrial
– -50°C to +100°C for non-Operating (storage)
Low Power Consumption
Extremely Rugged and Reliable
– Active mode: 30mA/50mA (3.3V/5.0V)(typical)
– Sleep mode: 200µA/300µA (3.3V/5.0V)(maximum)
– Built-in ECC support corrects 3 Bytes of error
per 512 Byte sector
– Endurance: 1,000,000 cycles (typical)
– Greater than 1,000,000 hours MTBF
Extended Data Protection and Security
– WP# pin for Data Protection
– Factory-Programmed, 20-Byte Unique ID number
•
•
Intelligent ATA/IDE Controller
Sustained Write Performance
– Built-in microcontroller with intelligent firmware
– Built-in Embedded Flash File System
– Up to 1.4MB/sec (host to flash)
Power Management Unit
– Immediate disabling of unused circuitry
PRODUCT DESCRIPTION
SST’s ATA-Disk Chip (ADC) is a low cost, high perfor-
mance, embedded flash memory data storage system.
This product is well suited for solid state mass storage
applications offering new and expanded functionality while
enabling cost effective designs.
dard interfaces; therefore, the ADC does not require addi-
tional or proprietary software such as Flash File System
(FFS) and Memory Technology Driver (MTD) software.
The ADC is designed to work at either 5V ±10% or 3.3V
±5%. The pin assignment is designed to match existing
IDE signal traces on the motherboard. It uses standard ATA
driver that is part of all major OS such as Windows 95/98/
2000/NT/CE, MAC, UNIX, etc.
ATA-based solid state mass storage technology is widely
used in such products as portable and desktop computers,
digital cameras, music players, handheld data collection
scanners, cellular phones, PCS phones, PDAs, handy termi-
nals, personal communicators, advanced two-way pagers,
audio recorders, monitoring devices, and set-top boxes.
All signals, except WP#, are in compliance with the ATA
specifications. WP# is used to write protect the information
stored on the ADC. The WP# can be either connected to
motherboard write protect control logic or a jumper. When
WP# is low, the ADC is write protected to prohibit any inad-
vertent writes.
ADC provides complete IDE Hard Disk Drive functionality
and compatibility. ADC is a perfect solution to consumer
electronic products requiring smaller, but more reliable and
cost effective data storage. The ADC is read and written to
using a single power supply of 5.0-Volts or 3.3-Volts and is
available in 8 to 192 MByte capacities.
Every ADC comes with factory-programmed, 20-Byte long,
unique identification number for extended data protection.
This feature prevents unauthorized duplication by allowing
encryption of customer data.
The ADC is a solid state disk drive that is designed to
replace conventional IDE hard disk drive and uses stan-
dard ATA/IDE protocol. It has built in microcontroller and file
management firmware that communicates with ATA stan-
The ADC is packaged in the 600 mil 32-pin DIP package
for easy and cost effective mounting to the system mother-
board.
©2001 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ATA-Disk Chip is a trademark of Silicon Storage Technology, Inc.
S71167-04-000 6/01
1
391
These specifications are subject to change without notice.
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
TABLE OF CONTENTS
1.0 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Performance-optimized ATA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.1 Microcontroller Unit (MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.2 Internal Direct Memory Access (DMA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.3 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.4 SRAM Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.5 Embedded Flash File System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1.6 Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 SST’s ATA-Disk Chip Product Offering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.0 ELECTRICAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.0.1 Pin Assignment and Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Electrical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Absolute Maximum Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 Absolute Maximum Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2 Input Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.3 Input Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.4 Output Drive Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.5 Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.6 I/O Input (Read) Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.7 I/O Output (Write) Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 I/O Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.1 I/O Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.0 SOFTWARE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 ATA-Disk Chip Drive Register Set Definitions and Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 ATA-Disk Chip Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2 ATA-Disk Chip Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2.1 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2.2 Error Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2.3 Feature Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2.4 Sector Count Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2.5 Sector Number (LBA 7-0) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2.6 Cylinder Low (LBA 15-8) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2.7 Cylinder High (LBA 23-16) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2.8 Drive/Head (LBA 27-24) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2.9 Status & Alternate Status Registers (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2.10 Device Control Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2.11 Drive Address Register (Read Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.2.12 Command Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 ATA-Disk Chip Command Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 ATA-Disk Chip Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1.1 Check Power Mode - 98H or E5H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1.2 Execute Drive Diagnostic - 90H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1.3 Format Track - 50H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
2
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.4 Identify Drive - ECH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.1.4.1 General Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.2 Default Number of Cylinders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.3 Default Number of Heads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.4 Default Number of Sectors per Track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.5 Number of Sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.6 Memory Serial Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.7 Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.8 Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.9 ECC Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.10 Firmware Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.11 Model Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.12 Read/Write Multiple Sector Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.13 Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1.4.14 PIO Data Transfer Cycle Timing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1.4.15 Translation Parameters Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1.4.16 Current Number of Cylinders, Heads, Sectors/Track . . . . . . . . . . . . . . . . . . . 24
3.2.1.4.17 Current Capacity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1.4.18 Multiple Sector Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1.4.19 Total Sectors Addressable in LBA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1.4.20 Advanced PIO Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1.4.21 Minimum PIO Transfer Cycle Time Without Flow Control . . . . . . . . . . . . . . . 24
3.2.1.4.22 Minimum PIO Transfer Cycle Time With IORDY . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1.5 Idle - 97H or E3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1.6 Idle Immediate - 95H or E1H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1.7 Initialize Drive Parameters - 91H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1.8 Read Buffer - E4H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1.9 Read Multiple - C4H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.1.10 Read Long Sector - 22H or 23H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1.11 Read Sectors - 20H or 21H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1.12 Read Verify Sector(s) - 40H or 41H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1.13 Recalibrate - 1XH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1.14 Seek - 7XH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1.15 Set Features - EFH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.1.16 Set Multiple Mode - C6H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.1.17 Set Sleep Mode - 99H or E6H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.1.18 Standby - 96H or E2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.1.19 Standby Immediate - 94H or E0H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.1.20 Write Buffer - E8H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.1.21 Write Long Sector - 32H or 33H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.1.22 Write Multiple Command - C5H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.1.23 Write Sector(s) - 30H or 31H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.1.24 Write Verify - 3CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.2 Error Posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.0 APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1 Differences between ATA-Disk Chip and ATA/ATAPI-5 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.1 Electrical Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.1.1 TTL Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.1.2 Pull Up Resistor Input Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.2 Functional Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1.2.1 Idle Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
3
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
4.1.2.2 Recovery from Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.0 PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.0 LIMITED WARRANTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 Life Support Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 Patent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
4
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
1.0 GENERAL DESCRIPTION
The SST’s ATA-Disk Chip (ADC) contains a controller,
embedded firmware and Flash Media in a 32-pin DIP pack-
age. Refer to Figure 1-1 for SST’s ADC block diagram. The
controller interfaces with the host system allowing data to
be written to and read from the Flash Media.
1.1.3 Power Management Unit (PMU)
Power Management Unit controls the power consumption
of the ADC. The PMU dramatically extends product battery
life by putting the part of the circuitry that is not in operation
into sleep mode.
1.1 Performance-optimized ATA Controller
1.1.4 SRAM Buffer
The heart of the ADC is the ATA controller which translates
standard ATA signals into Flash Media data and controls.
SST’s ADC contains a proprietary ATA controller that was
specifically designed to attain high data throughput from
host to Flash. The following components contribute to the
ATA controller’s operation.
A key contributor to the ATA controller performance is an
SRAM buffer. The buffer optimizes host’s data writes to
Flash Media.
1.1.5 Embedded Flash File System
Embedded Flash File System is an integral part of the
SST’s ATM controller. It contains MCU Firmware that per-
forms the following tasks:
1.1.1 Microcontroller Unit (MCU)
The MCU translates ATA commands into data and control
signals required for flash memory operation.
1. Translates host side signals into Flash Media
Writes and Reads.
1.1.2 Internal Direct Memory Access (DMA)
2. Provides Flash Media wear leveling to spread the
Flash writes across all the memory address space
to increase the longevity of Flash Media.
The ATA controller inside ADC uses DMA allowing instant
data transfer from buffer to memory. This implementation
eliminates microcontroller overhead associated with tradi-
tional, firmware based, memory control, increasing data
transfer rate.
3. Keeps track of data file structures.
1.1.6 Error Correction Code (ECC)
The ATA Controller contains ECC algorithm that corrects
3 bytes of error per 512 Byte sector.
ATA Controller
Embedded
Flash
MCU
File System
SRAM Buffer
Flash
Media
HOST
ATA/IDE
BUS
ECC
Internal
DMA
PMU
391 ILL1-1.5
FIGURE
1-1: SST ATA-DISK CHIP BLOCK DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
5
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
1.2 SST’s ATA-Disk Chip Product Offering
The SST58SD/LDxxx ATA-Disk Chip product family is available in 8 to 192 MByte capacities. The following table
shows the specific capacity, default number of cylinder heads, sectors and cylinders for each product line.
Model Number
SST58SD/LD008
SST58SD/LD016
SST58SD/LD024
SST58SD/LD032
SST58SD/LD048
SST58SD/LD064
SST58SD/LD096
SST58SD/LD128
SST58SD/LD192
Density
8 MB
Total Bytes
8,028,160
Cylinders
245
Heads
Sectors
32
2
2
16 MB
24 MB
32 MB
48 MB
64 MB
96 MB
128 MB
192 MB
16,023,552
24,051,712
32,047,104
48,037,888
64,028,672
96,075,776
128,450,560
192,675,840
489
32
367
4
32
489
4
32
733
4
32
977
4
32
733
8
32
980
8
32
735
16
32
2.0 ELECTRICAL INTERFACE
2.0.1 Pin Assignment and Pin Type
The signal/pin assignments are listed in Table 2-1. Low active signals have a “#” suffix. Pin types are Input, Output or Input/
Output. Section 2.3 defines the DC characteristics for all input and output type structures.
2.1 Electrical Description
The ADC functions in ATA Mode, which is compatible with IDE hard disk drives.
Table 2-2 describes the I/O signals. Signals whose source is the host are designated as inputs while signals that the ADC
sources are outputs. All outputs from the ADC are totem pole except the data bus signals which are in the bi-directional tri-
state. Refer to Section 2.3.2 for definitions of Input and Output types.
RESET#
D7
1
32
31
30
29
28
27
V
CC
D8
2
D6
3
D9
D5
4
D10
D4
5
D11
32-pin
D3
6
D12
D2
7
PSDIP 26
D13
D1
8
25
D14
Top View
D0
9
24
23
22
21
20
19
18
17
D15
WP#
IORD#
INTRQ
A1
10
11
12
13
14
15
16
IOWR#
CSEL
IOCS16#
PDIAG#
A2
A0
CS1FX#
GND
CS3FX#
DASP#
391 ILL F01.5
FIGURE
2-1: PIN ASSIGNMENTS FOR 32-PIN PSDIP
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
6
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
TABLE
Pin No.
2-1: PIN ASSIGNMENTS
Signal Name
RESET#
D7
Pin Type
I/O Type1
I2U
1
I
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I2D, O2
I2D, O2
I2D, O2
I2D, O2
I2D, O2
I2D, O2
I2D, O2
I2D, O2
I2U
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
9
D0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
WP#
IORD#
INTRQ
A1
I
I3U
O
O1
I
I2D
A0
I
I2D
CS1FX#
GND
DASP#
CS3FX#
A2
I
I3U
-
Ground
I2U, O1
I3U
I/O
I
I
I2D
PDIAG#
IOCS16#
CSEL
IOWR#
D15
I/O
O
I2U, O1
O2
I
I2U
I
I3U
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I2D, O2
I2D, O2
I2D, O2
I2D, O2
I2D, O2
I2D, O2
I2D, O2
I2D, O2
D14
D13
D12
D11
D10
D9
D8
VCC
Power
T2-1.4 391
1. Please refer to Sections 2.3.1 to 2.3.4 for detail
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
7
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
TABLE
Symbol
A2 - A0
2-2: SIGNAL DESCRIPTION
Type1
Pin
13,14,19
Name and Functions
I
A[2:0] are used to select the one of eight registers in the Task File.
D15 - D0
I/O
9,8,7,6,5,4,3,2, Data bus
31,30,29,28,27,
26,25,24
CS1FX#, CS3FX#
CSEL
I
I
15,18
22
CS1FX# is the chip select for the task file registers while CS3FX# is used to
select the Alternate Status Register and the Device Control Register.
This internally pulled-up signal is used to configure this device as a Master
or a Slave. When this pin is grounded, this device is configured as a Master.
When the pin is open, this device is configured as a Slave.
IORD#
I
11
This is an I/O Read strobe generated by the host. This signal gates I/O data
onto the bus from the chip.
IOWR#
I
23
21
The I/O Write strobe pulse is used to clock I/O data into the chip.
IOCS16#
O
This output signal is asserted low when this device is expecting a word data
transfer cycle.
WP#
I
10
Write protect pin is used to disable Write operation. When this pin is low,
data on chip will be write protected.
INTRQ
O
12
20
Signal is the active high Interrupt Request to the host.
PDIAG#
I/O
This input/output is the Pass Diagnostic signal in the Master/Slave
handshake protocol.
DASP#
I/O
17
This input/output is the Disk Active/Slave present signal in the Master/Slave
handshake protocol.
RESET#
GND
I
-
-
1
This input pin is the active low hardware reset from the host.
Ground
16
32
VCC
Power
T2-2.2 391
1. Please refer to Sections 2.3.1 to 2.3.4 for detail
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
8
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
2.2 Absolute Maximum Stress Ratings
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50°C to +100°C
D.C. Voltage on any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VCC + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to VCC + 1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Lead Soldering Temperature (3 Seconds)
240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE: SST58SDXXX
OPERATING RANGE: SST58LDXXX
Range
Ambient Temp
0°C to +70°C
VCC
Range
Ambient Temp
0°C to +70°C
VCC
Commercial
Industrial
5V ± 10%
5V ± 5%
Commercial
Industrial
3.3V ± 5%
3.3V ± 5%
-40°C to +85°C
-40°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 100 pF
See Figures 2-3 and 2-4
Note: All AC specifications are guaranteed by design.
TABLE
2-3: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Maximum
500
Units
ms
1
TPU-READY
Power-up to Ready Operation
Power-up to Write Operation
1
TPU-WRITE
500
ms
T2-3.0 391
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE
2-4: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
15 pF
9 pF
1
CIN
VIN = 0V
T2-4.0 391
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE
2-5: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Test Method
JEDEC Standard 78
1
ILTH
Latch Up
100 + IDD
mA
T2-5.1 391
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
9
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
2.3 Electrical Specification
The following tables define all D.C. Characteristics for the SST ATA-Disk Chip product family.
2.3.1 Absolute Maximum Conditions
Unless otherwise stated, conditions are for Commercial Temperature:
Non-operating (storage) temperature range: -50°C to +100°C
VCC = 5V ± 10%
VCC = 3.3V ± 5%
Ta = 0°C to +70°C
ABSOLUTE MAXIMUM CONDITIONS
Parameter
Symbol
VCC
Conditions
Input Power
-0.3V min. to 6.5V max.
-0.5V min. to VCC + 0.5V max.
Voltage on any pin except VCC with respect to GND
V
INPUT POWER
Voltage
Maximum Average RMS Current
Measurement Method
3.3V at 25°C1
3.3V ± 5%
5.0V ± 10%
75 mA
100 mA
5.0V at 25°C1
1. Current measurement is accomplished by connecting an amp meter (set to the 2 amp scale range) in series with the VCC supply to
the ADC. Current measurements are to be taken while looping on a data transfer command with a sector count of 128.
Current consumption values for both Read and Write commands are not to exceed the Maximum Average RMS Current specified in
the above table.
Unless otherwise stated, conditions are for Industrial Temperature:
Non-operating (storage) temperature range: -50°C to +100°C
VCC = 5.0V ± 5%
VCC = 3.3V ± 5%
Ta = -40°C to +85°C
ABSOLUTE MAXIMUM CONDITIONS
Parameter
Symbol
VCC
Conditions
Input Power
-0.3V min. to 6.5V max.
-0.5V min. to VCC + 0.5V max.
Voltage on any pin except VCC with respect to GND
V
INPUT POWER
Voltage
3.3V ± 5%
5.0V ± 5%
Maximum Average RMS Current
Measurement Method
3.3V at 25°C1
75 mA
100 mA
5.0V at 25°C1
1. Current measurement is accomplished by connecting an amp meter (set to the 2 amp scale range) in series with the VCC supply to
the ADC. Current measurements are to be taken while looping on a data transfer command with a sector count of 128.
Current consumption values for both Read and Write commands are not to exceed the Maximum Average RMS Current specified in
the above table.
ADC products shall operate correctly in both voltage ranges as shown in the tables above. To comply with this
specification, current requirements must not exceed the maximum limit.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
10
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
2.3.2 Input Leakage Current
In the table below, x refers to the characteristics described in section 2.3.2. For example, I1U indicates a pull up
resistor with a type 1 input characteristic.
Type
IxZ
Parameter
Symbol
IL
Conditions
Min
-1
Typ
Max
1
Units
µA
Input Leakage Current
Pull Up Resistor
Pull Down Resistor
VIH = VCC / VIL = Gnd
IxU
RPU1
RPD1
V
CC = 5.0V
50k
50k
500k
500k
Ohm
Ohm
IxD
VCC = 5.0V
2.3.3 Input Characteristics
Min
2.4
2.0
Typ
Max
Min
3.0
2.4
Typ
Max
Type
Parameter
Input Voltage
CMOS
Symbol
VIH
VCC = 3.3V
VCC = 5.0V
Units
1
Volts
VIL
0.6
0.8
0.8
0.8
2
3
Input Voltage
CMOS
VIH
Volts
Volts
VIL
Input Voltage
CMOS
VTH
VTL
2.0
2.4
0.8
0.55
Schmitt Trigger
2.3.4 Output Drive Type
All output drive type are CMOS level.
2.3.5 Output Drive Characteristics
Type
Parameter
Symbol
Conditions
Min
Typ
Max
Units
O1
Output Voltage
VOH
IOH = -4 mA
VCC
Volts
-0.8V
VOL
VOH
VOL
IOL = 4 mA
IOH = -8 mA
IOL = 8 mA
Gnd
+0.4V
O2
Output Voltage
VCC
-0.8V
Volts
Gnd
+0.4V
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
11
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
2.3.6 I/O Input (Read) Timing Specification
TABLE
Item
2-6: I/O READ TIMING
Symbol
IEEE Symbol
tDVIRH
Min
20
5
Max
Data Setup before IORD#
tsu(IORD)
-
-
Data Hold following IORD#
IORD# Width Time
th(IORD)
tlGHQX
tlGLIGH
tAVIGL
tw(IORD)
70
25
10
-
-
Address Setup before IORD#
Address Hold following IORD#
IOIS16# Delay Falling from Address
IOIS16# Delay Rising from Address
tsuA(IORD)
thA(IORD)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
-
tlGHAX
tAVISL
-
20
tAVISH
-
20
T2-6.3 391
Note: All times are in nanoseconds. The maximum load on IOIS16# is 1 LSTTL with 50pF total load.
All AC specifications are guaranteed by design.
A2-A0
tsuA(IORD)
tw(IORD)
thA(IORD)
IORD#
tdrIOIS16(ADR)
tsu (IORD)
IOIS16#
tdfIOIS16(ADR)
th(IORD)
D15-D0
Dout
391 ILL2-7.0
FIGURE
2-2: I/O READ TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
12
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
2.3.7 I/O Output (Write) Timing Specification
TABLE
Item
2-7: I/O WRITE TIMING
Symbol
IEEE Symbol
tDVIWH
tlWHDX
tlWLIWH
tAVIWL
Min
20
10
70
25
10
-
Max
Data Setup before IOWR#
tsu(IOWR)
th(IOWR)
-
-
Data Hold following IOWR#
IOWR# Width Time
tw(IOWR)
-
Address Setup before IOWR#
Address Hold following IOWR#
IOIS16 Delay Falling from Address
IOIS16 Delay Rising from Address
tsuA(IOWR)
thA(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
-
tlWHAX
tAVISL
-
20
tAVISH
-
20
T2-7.3 391
Note: All times are in nanoseconds. The maximum load on -IOIS16 is 1 LSTTL with 50pF total load.
All AC specifications are guaranteed by design.
A2-A0
tsuA(IOWR)
tw(IOWR)
thA(IOWR)
IOWR#
tdrIOIS16(ADR)
th(IOWR)
IOIS16#
tdfIOIS16(ADR)
tsu(IOWR)
D15-D0
Din Valid
391 ILL2-8.1
FIGURE
2-3: I/O WRITE TIMING DIAGRAM
V
IHT
V
V
HT
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
V
ILT
391 ILL F11.0
AC test inputs are driven at VIHT (2.4V) for a logic “1” and VILT (0.4V) for a logic “0”. Measurement reference points for
inputs and outputs are VHT (2.0V) and VLT (0.8V). Input rise and fall times (10% ↔ 90%) are <10 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE
2-4: AC INPUT/OUTPUT REFERENCE WAVEFORMS
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
13
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
2.4 I/O Transfer Function
2.4.1 I/O Function
ADC permits 8-bit data access if the user issues a Set Feature Command to enable 8-bit Mode.
The following table defines the function of various operations.
TABLE
2-8: I/O FUNCTION
Function Code
Invalid Mode
CS3FX#
VIL
CS1FX#
VIL
A0-A2
X
IORD#
X
IOWR#
X
D15-D8
Undefined
High Z
D7-D0
Undefined
High Z
Standby Mode
VIH
VIH
X
X
X
Task File Write
VIH
VIL
1-7H
1-7H
0
VIH
VIL
VIH
VIL
VIH
VIL
VIL
VIL
VIH
VIL
VIH
VIL
VIH
VIH
Don’t Care
Data In
Data Out
In
Task File Read
VIH
VIL
High Z
In1
Out1
Data Register Write
Data Register Read
Control Register Write
Alt Status Read
Drive Address
VIH
VIL
VIH
VIL
0
Out
VIL
VIH
6H
6H
7H
Don’t Care
High Z
Control In
Status Out
Data Out
VIL
VIH
VIL
VIH
High Z
T2-8.0 391
1. If 8-bit data transfer mode is enabled.
In 8-bit data transfer mode, High Byte is undefined for Data Out, Don’t Care for Data In.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
14
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.0 SOFTWARE INTERFACE
3.1 ATA-Disk Chip Drive Register Set Definitions and Protocol
3.1.1 ATA-Disk Chip Addressing
The I/O decoding for an ADC is as follows:
TABLE
3-1: TASK REGISTERS
CS3FX#
CS1FX#
A2
0
A1
0
A0
0
IORD# = 0
IOWR# = 0
WR Data
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
RD Data
0
0
1
Error Register
Sector Count
Sector No.
Features
0
1
0
Sector Count
Sector No.
0
1
1
1
0
0
Cylinder Low
Cylinder High
Select Card/Head
Status
Cylinder Low
Cylinder High
Select Card/Head
Command
1
0
1
1
1
0
1
1
1
1
1
0
Alt Status
Device Control
Reserved
1
1
1
Drive Address
T3-1.0 391
3.1.2 ATA-Disk Chip Registers
The following section describes the hardware registers used by the host software to issue commands to the ADC.
These registers are often collectively referred to as the “Task File Registers.”
3.1.2.1 Data Register
This 16-bit register is used to transfer data blocks between the device data buffer and the host. It is also the register
through which sector information is transferred on a Format Track command. Data transfer can be performed in
PIO mode.
3.1.2.2 Error Register (Read Only)
This register contains additional information about the source of an error when an error is indicated in bit 0 of the
Status register. The bits are defined as follows:
D7
D6
D5
D4
D3
D2
D1
D0
BBK
UNC
0
IDNF
0
ABRT
0
AMNF
Bit 7 (BBK)
This bit is set when a Bad Block is detected.
Bit 6 (UNC) This bit is set when an Uncorrectable Error is encountered.
Bit 5 This bit is 0.
Bit 4 (IDNF) The requested sector ID is in error or cannot be found.
Bit 3 This bit is 0.
Bit 2 (Abort) This bit is set if the command has been aborted because of an ADC status condition:
(Not Ready, Write Fault, etc.) or when an invalid command has been issued.
Bit 1
This bit is 0.
Bit 0 (AMNF) This bit is set in case of a general error.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
15
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.1.2.3 Feature Register (Write Only)
This register provides information regarding features of the ADC that the host can utilize.
3.1.2.4 Sector Count Register
This register contains the numbers of sectors of data requested to be transferred on a Read or Write operation
between the host and the ADC. If the value in this register is zero, a count of 256 sectors is specified. If the com-
mand was successful, this register is zero at command completion. If not successfully completed, the register con-
tains the number of sectors that need to be transferred in order to complete the request.
3.1.2.5 Sector Number (LBA 7-0) Register
This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any ADC data
access for the subsequent command.
3.1.2.6 Cylinder Low (LBA 15-8) Register
This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of then Logical Block
Address.
3.1.2.7 Cylinder High (LBA 23-16) Register
This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address.
3.1.2.8 Drive/Head (LBA 27-24) Register
The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of
cylinder/head/sector addressing. The bits are defined as follows:
D7
D6
D5
D4
D3
D2
D1
D0
1
LBA
1
DRV
HS3
HS2
HS1
HS0
Bit 7
Bit 6
This bit is set to 1.
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA).
When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is
selected. In Logical Block Mode, the Logical Block Address is interpreted as follows:
LBA7-LBA0: Sector Number Register D7-D0.
LBA15-LBA8: Cylinder Low Register D7-D0.
LBA23-LBA16: Cylinder High Register D7-D0.
LBA27-LBA24: Drive/Head Register bits HS3-HS0.
This bit is set to 1.
Bit 5
Bit 4 (DRV) DRV is the drive number. When DRV=0 (Master), Master is selected.
When DRV=1(Slave), Slave is selected.
Bit 3 (HS3)
Bit 2 (HS2)
Bit 1 (HS1
Bit 0 (HS0)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number.
It is Bit 27 in the Logical Block Address mode.
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number.
It is Bit 26 in the Logical Block Address mode.
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number.
It is Bit 25 in the Logical Block Address mode.
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number.
It is Bit 24 in the Logical Block Address mode.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
16
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.1.2.9 Status & Alternate Status Registers (Read Only)
These registers return the ADC status when read by the host. Reading the Status register does clear a pending
interrupt while reading the Auxiliary Status register does not. The meaning of the status bits are described as follows:
D7
D6
D5
D4
D3
D2
D1
D0
BUSY
RDY
DWF
DSC
DRQ
CORR
0
ERR
Bit 7 (BUSY) The busy bit is set when the ADC has access to the command buffer and registers and
the host is locked out from accessing the command register and buffer. No other bits in
this register are valid when this bit is set to a 1.
Bit 6 (RDY)
RDY indicates whether the device is capable of performing ADC operations. This bit is
cleared at power up and remains cleared until the ADC is ready to accept a command.
Bit 5 (DWF) This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC) This bit is set when the ADC is ready.
Bit 3 (DRQ) The Data Request is set when the ADC requires that information be transferred either to
or from the host through the Data register.
Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector Read operation.
Bit 1 (IDX)
This bit is always set to 0.
Bit 0 (ERR) This bit is set when the previous command has ended in some type of error. The bits in
the Error register contain additional information describing the error. It is recommended
that media access commands (such as Read Sectors and Write Sectors) that end with
an error condition should have the address of the first sector in error in the command
block registers.
3.1.2.10 Device Control Register (Write Only)
This register is used to control the ADC interrupt request and to issue a software Reset. This register can be written
to even if the device is BUSY. The bits are defined as follows:
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
1
SW Rst
-IEn
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
This bit is an X (don’t care).
This bit is an X (don’t care).
This bit is an X (don’t care).
This bit is an X (don’t care).
This bit is ignored by the ADC.
Bit 2 (SW Rst)This bit is set to 1 in order to force the ADC to perform a software Reset operation. The
chip remains in Reset until this bit is reset to ‘0.’
Bit 1 (-IEn)
Bit 0
The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts
from the ADC are disabled. This bit is Reset to 0 at power on and Reset.
This bit is ignored by the ADC.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
17
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.1.2.11 Drive Address Register (Read Only)
This register contains the inverted drive select and head select addresses of the currently selected drive. The bits
in this register are as follows:
D7
D6
D5
D4
D3
D2
D1
D0
HiZ
-WTG
-HS3
-HS2
-HS1
-HS0
-DS1
-DS0
Bit 7
This bit is HiZ.
Bit 6 (-WTG) This bit is 0 when a Write operation is in progress, otherwise, it is 1.
Bit 5 (-HS3) This bit is the negation of bit 3 in the Drive/Head register.
Bit 4 (-HS2) This bit is the negation of bit 2 in the Drive/Head register.
Bit 3 (-HS1) This bit is the negation of bit 1 in the Drive/Head register.
Bit 2 (-HS0
This bit is the negation of bit 0 in the Drive/Head register.
Bit 1 (-DS1) This bit is 0 when drive 1 is active and selected.
Bit 0 (-DS0) This bit is 0 when drive 0 is active and selected.
3.1.2.12 Command Register (Write Only)
This register contains the command code being sent to the drive. Command execution begins immediately after
this register is written. The executable commands, the command codes, and the necessary parameters for each
command are listed in Table 3-2.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
18
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2 ATA-Disk Chip Command Description
This section defines the software requirements and the format of the commands the host sends to the ADC. Commands
are issued to the ADC by loading the required registers in the command block with the supplied parameters, and then
writing the command code to the Command Register. The manner in which a command is accepted varies. There are
three classes (see Table 3-2) of command acceptance, all dependent on the host not issuing commands unless the
ADC is not busy (BSY=0).
3.2.1 ATA-Disk Chip Command Set
Table 3-2 summarizes the ADC command set with the paragraphs that follow describing the individual commands
and the task file for each.
TABLE
3-2: ATA-DISK CHIP COMMAND SET
Class
1
Command
Code
E5H or 98H
90H
FR1
SC2
-
SN3
-
CY4
-
DH5
D8
D
Y8
D
D
D
Y
LBA6
Check Power Mode
Execute Drive Diagnostic
Format Track
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
1
-
Y7
-
-
2
50H
-
Y
-
Y
-
1
Identify Drive
ECH
-
-
1
Idle
E3H or 97H
E1H or 95H
91H
Y
-
-
-
-
1
Idle Immediate
Initialize Drive Parameters
Read Buffer
-
-
-
1
Y
-
-
-
-
1
E4H
-
-
D
Y
-
1
Read Long Sector
Read Multiple
Read Sector(s)
Read Verify Sector(s)
Recalibrate
22H or 23H
C4H
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
1
Y
Y
Y
-
Y
1
20H or 21H
40H or 41H
1XH
Y
1
Y
1
D
Y
1
Seek
7XH
-
Y
-
Y
-
Y
-
1
Set Features
EFH
-
D
D
D
D
D
D
Y
1
Set Multiple Mode
Set Sleep Mode
Stand By
C6H
Y
-
-
-
-
1
E6H or 99H
E2H or 96H
E0H or 94H
E8H
-
-
-
1
-
-
-
-
1
Stand By Immediate
Write Buffer
-
-
-
-
2
-
-
-
-
2
Write Long Sector
Write Multiple
Write Sector(s)
Write Verify
32H or 33H
C5H
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
3
Y
Y
Y
Y
2
30H or 31H
3CH
Y
3
Y
Y
T3-2.1 391
1. FR - Features Register
2. SC - Sector Count Register
3. SN - Sector Number Register
4. CY - Cylinder Registers
5. DH - Drive/Head Register
6. LBA - Logical Block Address Mode Supported (see command descriptions for use)
7. Y - The register contains a valid parameter for this command.
8. For the Drive/Head Register: Y means both the ADC and Head parameters are used;
D means only the ADC parameter is valid and not the Head parameter.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
19
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.1 Check Power Mode - 98H or E5H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
98H or E5H
Drive
X
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
This command checks the power mode.
Because SST ADC can recover from sleep in 200 ns, Idle Mode is never enabled.
ADC sets BSY, sets the Sector Count Register to 00H, clears BSY and generates an interrupt.
3.2.1.2 Execute Drive Diagnostic - 90H
Bit ->
7
6
5
4
3
2
1
0
90H
Command (7)
C/D/H (6)
X
Drive
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
This command performs the internal diagnostic tests implemented by the ADC.
If the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave
with the Master responding with status for both devices.
The Diagnostic codes shown in Table 3-3 are returned in the Error Register at the end of the command.
TABLE 3-3: DIAGNOSTIC CODES
Code
01H
02H
03H
04H
05H
8XH
Error Type
No Error Detected
Formatter Device Error
Sector Buffer Error
ECC Circuitry Error
Controlling Microprocessor Error
Slave Error
T3-3.1 391
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
20
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.3 Format Track - 50H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
50H
1
LBA
1
Drive
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
X (LBA 7-0)
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
Count (LBA mode only)
X
This command writes the desired head and cylinder of the selected drive with a vendor unique data
pattern (typically FFH or 00H). To remain host backward compatible, the ADC expects a sector buffer of
data from the host to follow the command with the same protocol as the Write Sector(s) command
although the information in the buffer is not used by the ADC. If LBA=1 then the number of sectors to
format is taken from the Sec Cnt register (0=256). The use of this command is not recommended.
3.2.1.4 Identify Drive - ECH
Bit ->
7
6
5
4
3
2
1
0
ECH
Command (7)
C/D/H (6)
X
X
X
Drive
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
The Identify Drive command enables the host to receive parameter information from the ADC. This
command has the same protocol as the Read Sector(s) command. The parameter words in the buffer
have the arrangement and meanings defined in Table 3-4. All reserved bits or words are zero. Table 3-4
gives the definition for each field in the Identify Drive Information.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
21
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
TABLE 3-4: IDENTIFY DRIVE INFORMATION
Word
Address
Default
Value
Total
Bytes
Data Field Type Information
General configuration bit-significant information
Default number of cylinders
0
1
044AH
XXXXH
0000H
00XXH
0000H
0000H
XXXXH
XXXXH
XXXXH
aaaa1
2
2
2
2
Reserved
3
2
Default number of heads
4
2
Reserved
5
2
Reserved
6
2
Default number of sectors per track
Number of sectors per card (Word 7 = MSW, Word 8 = LSW)
Vendor Unique
7-8
9
4
2
10-19
20
20
2
Serial number in ASCII. Big Endian Byte Order in Word
Buffer type
0002H
XXXXH
0004H
aaaa1
21
2
Buffer size in 512 Byte increments
# of ECC bytes passed on Read/Write Long Commands
Firmware revision in ASCII. Big Endian Byte Order in Word
Model number in ASCII. Big Endian Byte Order in Word
Maximum number of sectors on Read/Write Multiple command
Reserved
22
2
23-26
27-46
47
8
aaaa1
40
2
000XH
0000H
0200H
0000H
0X00H
0000H
000XH
XXXXH
XXXXH
XXXXH
XXXXH
010XH
XXXXH
0000H
00XXH
0000H
XXXXH
XXXXH
0000H
0000H
0000H
48
2
49
2
Capabilities
50
2
Reserved
51
2
PIO data transfer cycle timing mode
Reserved
52
2
53
2
Translation parameters are valid
Current numbers of cylinders
54
2
55
2
Current numbers of heads
56
2
Current sectors per track
57-58
59
4
Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW)
Multiple sector setting
2
60-61
62-63
64
4
Total number of sectors addressable in LBA Mode
Reserved (DMA data transfer is not supported in ADC)
Advanced PIO Transfer Mode Supported
Reserved
4
2
65-66
67
4
2
Minimum PIO transfer cycle time without flow control
Minimum PIO transfer cycle time with IORDY flow control
Reserved
68
2
69-127
128-159
160-255
138
64
192
Vendor unique bytes
Reserved
T3-4.3 391
1. aaaa - any SST specific number
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
22
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.4.1 General Configuration
This field informs the host that this is a non-magnetic, hard sectored, removable storage device with a
transfer rate greater than 10 MByte/sec and is not MFM encoded.
3.2.1.4.2 Default Number of Cylinders
This field contains the number of translated cylinders in the default translation mode. This value will be
the same as the number of cylinders.
3.2.1.4.3 Default Number of Heads
This field contains the number of translated heads in the default translation mode.
3.2.1.4.4 Default Number of Sectors per Track
This field contains the number of sectors per track in the default translation mode.
3.2.1.4.5 Number of Sectors
This field contains the number of sectors per ADC. This double word value is also the first invalid
address in LBA translation mode.
3.2.1.4.6 Memory Serial Number
The contents of this field are right justified and padded with spaces (20H).
3.2.1.4.7 Buffer Type
This field defines the buffer capability:
0002H: a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the ADC.
3.2.1.4.8 Buffer Size
This field defines the buffer capacity in 512 Byte increments. SST’s ADC has up to 2 sector data buffer
for host interface.
3.2.1.4.9 ECC Count
This field defines the number of ECC bytes used on each sector in the Read and Write Long commands.
3.2.1.4.10 Firmware Revision
This field contains the revision of the firmware for this product.
3.2.1.4.11 Model Number
This field contains the model number for this product and is left justified and padded with spaces (20H).
3.2.1.4.12 Read/Write Multiple Sector Count
This field contains the maximum number of sectors that can be read or written per interrupt using the
Read Multiple or Write Multiple commands.
3.2.1.4.13 Capabilities
Bit 13: Standby Timer
Bit 11: IORDY Support
Bit 9: LBA support
Set to 0, forces sleep mode when host is inactive.
Set to 0, indicates that this device may support IORDY operation.
Set to 1, SST’s ADCs support LBA mode addressing.
This bit is set to 0. DMA mode is not supported.
Bit 8: DMA Support
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
23
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.4.14 PIO Data Transfer Cycle Timing Mode
This field defines the mode for PIO data transfer. ADC supports up to PIO Mode-4.
3.2.1.4.15 Translation Parameters Valid
If bit 0 is 1, it indicates that words 54 to 58 are valid and reflect the current number of cylinders, heads
and sectors. If bit 1 is 1, it indicates that words 64 to 70 are valid to support PIO Mode-3 and 4.
3.2.1.4.16 Current Number of Cylinders, Heads, Sectors/Track
These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in
the current translation mode.
3.2.1.4.17 Current Capacity
This field contains the product of the current cylinders times heads times sectors.
3.2.1.4.18 Multiple Sector Setting
This field contains a validity flag in the Odd Byte and the current number of sectors that can be
transferred per interrupt for R/W Multiple in the Even Byte. The Odd Byte is always 01H which indicates
that the Even Byte is always valid.
The Even Byte value depends on the value set by the Set Multiple command. The Even Byte of this
word by default contains a 00H which indicates that R/W Multiple commands are not valid.
3.2.1.4.19 Total Sectors Addressable in LBA Mode
This field contains the number of sectors addressable for the ADC in LBA mode only.
3.2.1.4.20 Advanced PIO Data Transfer Mode
ADC supports up to PIO Mode-4.
3.2.1.4.21 Minimum PIO Transfer Cycle Time Without Flow Control
The ADC’s minimum cycle time is 120 ns.
3.2.1.4.22 Minimum PIO Transfer Cycle Time With IORDY
The ADC’s minimum cycle time is 120 ns, e.g., PIO Mode-4.
3.2.1.5 Idle - 97H or E3H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
97H or E3H
Drive
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
Timer Count (5 msec increments)
X
This command causes the ADC to set BSY, enter the Idle Mode, clear BSY and generate an interrupt. If
the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and
the automatic power down mode is enabled. If the sector count is zero, the automatic power down
mode is also enabled, the timer count is set to 3, with each count being 5 ms. Note that this time base
(5 msec) is different from the ATA specification.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
24
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.6 Idle Immediate - 95H or E1H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
95H or E1H
Drive
X
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
This command causes the ADC to set BSY, enter the Idle Mode, clear BSY and generate an interrupt.
3.2.1.7 Initialize Drive Parameters - 91H
Bit ->
7
6
5
4
3
2
1
0
91H
Command (7)
C/D/H (6)
X
0
X
Drive
Max Head (no. of heads-1)
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
Number of Sectors
X
This command enables the host to set the number of sectors per track and the number of heads per
cylinder. Only the Sector Count and the Drive/Head registers are used by this command.
3.2.1.8 Read Buffer - E4H
Bit ->
7
6
5
4
3
2
1
0
E4H
Command (7)
C/D/H (6)
X
Drive
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
The Read Buffer command enables the host to read the current contents of the ADC’s sector buffer.
This command has the same protocol as the Read Sector(s) command
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
25
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.9 Read Multiple - C4H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
C4H
1
LBA
1
Drive
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
X
The Read Multiple command is similar to the Read Sector(s) command. Interrupts are not generated on
every sector, but on the transfer of a block which contains the number of sectors defined by a Set
Multiple command.
Command execution is identical to the Read Sectors operation except that the number of sectors
defined by a Set Multiple command are transferred without intervening interrupts. DRQ qualification of
the transfer is required only at the start of the data block, not on each sector.
The block count of sectors to be transferred without intervening interrupts is programmed by the Set
Multiple Mode command, which must be executed prior to the Read Multiple command. When the Read
Multiple command is issued, the Sector Count Register contains the number of sectors (not the number
of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the
block count, as many full blocks as possible are transferred, followed by a final, partial block transfer.
The partial block transfer is for n sectors, where
n = remainder (sector count/block count).
If the Read Multiple command is attempted before the Set Multiple Mode command has been executed
or when Read Multiple commands are disabled, the Read Multiple operation is rejected with an Aborted
Command error. Disk errors encountered during Read Multiple commands are posted at the beginning
of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it
normally would, including transfer of corrupted data, if any.
Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error
reporting is the same as that on a Read Sector(s) Command. This command reads from 1 to 256
sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer
begins at the sector specified in the Sector Number Register.
At command completion, the Command Block Registers contain the cylinder, head and sector number
of the last sector read.
If an error occurs, the read terminates at the sector where the error occurred. The Command Block
Registers contain the cylinder, head and sector number of the sector where the error occurred. The
flawed data is pending in the sector buffer.
Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All
other errors cause the command to stop after transfer of the block which contained the error.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
26
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.10 Read Long Sector - 22H or 23H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
22H or 23H
Drive
1
LBA
1
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
X
X
The Read Long command performs similarly to the Read Sector(s) command except that it returns 516
Bytes of data instead of 512 Bytes. During a Read Long command, the ADC does not check the ECC
bytes to determine if there has been a data error. Only single sector read long operations are
supported. The transfer consists of 512 Bytes of data transferred in Word-Mode followed by 4 Bytes of
ECC data transferred in Byte-Mode. This command has the same protocol as the Read Sector(s)
command. Use of this command is not recommended.
3.2.1.11 Read Sectors - 20H or 21H
Bit ->
7
6
5
4
3
2
1
0
20H or 21H
Drive
Command (7)
C/D/H (6)
1
LBA
1
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
X
This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of
0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register.
When this command is issued and after each sector of data (except the last one) has been read by the
host, the ADC sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an
interrupt. The host then reads the 512 Bytes of data from the buffer.
At command completion, the Command Block Registers contain the cylinder, head and sector number
of the last sector read. If an error occurs, the read terminates at the sector where the error occurred.
The Command Block Registers contain the cylinder, head, and sector number of the sector where the
error occurred. The flawed data is pending in the sector buffer.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
27
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.12 Read Verify Sector(s) - 40H or 41H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
40H or 41H
Drive
1
LBA
1
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
X
This command is identical to the Read Sectors command, except that DRQ is never set and no data is
transferred to the host. When the command is accepted, the ADC sets BSY.
When the requested sectors have been verified, the ADC clears BSY and generates an interrupt. Upon
command completion, the Command Block Registers contain the cylinder, head, and sector number of
the last sector verified.
If an error occurs, the verify terminates at the sector where the error occurs. The Command Block
Registers contain the cylinder, head and sector number of the sector where the error occurred. The
Sector Count Register contains the number of sectors not yet verified.
3.2.1.13 Recalibrate - 1XH
Bit ->
7
6
5
4
3
2
1
0
1XH
Command (7)
C/D/H (6)
1
LBA
1
Drive
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
This command is effectively a NOP command to the ADC and is provided for compatibility purposes.
3.2.1.14 Seek - 7XH
Bit ->
7
6
5
4
3
2
1
0
7XH
Command (7)
C/D/H (6)
1
LBA
1
Drive
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
Cylinder Low (LBA 15-8)
X (LBA 7-0)
X
X
This command is effectively a NOP command to the ADC although it does perform a range check of
cylinder and head or LBA address and returns an error if the address is out of range.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
28
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.15 Set Features - EFH
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
EFH
X
Drive
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
X
Config
Feature
This command is used by the host to establish or select certain features. Table 3-5 defines all features
that are supported.
TABLE 3-5: FEATURES SUPPORTED
Feature
01H
Operation
Enable 8-bit data transfers.
55H
Disable Read Look Ahead.
66H
Disable Power on Reset (POR) establishment of defaults at software Reset.
NOP - Accepted for backward compatibility.
Disable 8-bit data transfer.
69H
81H
96H
NOP - Accepted for backward compatibility.
Accepted for backward compatibility. Use of this Feature is not recommended.
NOP - accepted for compatibility.
97H
9AH
BBH
CCH
4 Bytes of data apply on Read/Write Long commands.
Enable Power on Reset (POR) establishment of defaults at software Reset.
T3-5.0 391
Features 01H and 81H are used to enable and clear 8-bit data transfer mode. If the 01H feature command is issued
all data transfers will occur on the low order D7-D0 data bus and the IOIS16# signal will not be asserted for data
register accesses.
Features 55H and BBH are the default features for the ADC; thus, the host does not have to issue this command
with these features unless it is necessary for compatibility reasons.
Features 66H and CCH can be used to enable and disable whether the Power On Reset (POR) Defaults will be set
when a software Reset occurs.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
29
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.16 Set Multiple Mode - C6H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
C6H
X
Drive
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
Sector Count
X
This command enables the ADC to perform Read and Write Multiple operations and establishes the
block count for these commands. The Sector Count Register is loaded with the number of sectors per
block. Upon receipt of the command, the ADC sets BSY to 1 and checks the Sector Count Register.
If the Sector Count Register contains a valid value and the block count is supported, the value is loaded
for all subsequent Read Multiple and Write Multiple commands and execution of those commands is
enabled. If a block count is not supported, an Aborted Command error is posted, and Read Multiple and
Write Multiple commands are disabled. If the Sector Count Register contains 0 when the command is
issued, Read and Write Multiple commands are disabled. At power on, or after a hardware or (unless
disabled by a Set Feature command) software reset, the default mode is Read and Write Multiple
disabled.
3.2.1.17 Set Sleep Mode - 99H or E6H
Bit ->
7
6
5
4
3
2
1
0
99H or E6H
Drive
Command (7)
C/D/H (6)
X
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
This command causes the ADC to set BSY, enter the Sleep mode, clear BSY and generate an interrupt.
Recovery from sleep mode is accomplished by simply issuing another command (a reset is permitted
but not required). Sleep mode is also entered when internal timers expire so the host does not need to
issue this command except when it wishes to enter Sleep mode immediately. The default value for the
timer is 15 milliseconds.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
30
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.18 Standby - 96H or E2H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
96H or E2H
Drive
X
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
This command causes the ADC to set BSY, enter the Sleep mode (which corresponds to the ATA
“Standby” Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is
accomplished by simply issuing another command (a reset is not required).
3.2.1.19 Standby Immediate - 94H or E0H
Bit ->
7
6
5
4
3
2
1
0
94H or E0H
Drive
Command (7)
C/D/H (6)
X
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
This command causes the ADC to set BSY, enter the Sleep mode (which corresponds to the ATA
“Standby” Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is
accomplished by simply issuing another command (a reset is not required).
3.2.1.20 Write Buffer - E8H
Bit ->
7
6
5
4
3
2
1
0
E8H
Command (7)
C/D/H (6)
X
Drive
X
X
X
X
X
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
The Write Buffer command enables the host to overwrite contents of the ADC’s sector buffer with any
data pattern desired. This command has the same protocol as the Write Sector(s) command and
transfers 512 Bytes.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
31
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.1.21 Write Long Sector - 32H or 33H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
32H or 33H
Drive
1
LBA
1
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
X
X
This command is similar to the Write Sector(s) command except that it writes 516 Bytes instead of 512
Bytes. Only single sector Write Long operations are supported. The transfer consists of 512 Bytes of
data transferred in Word-Mode followed by 4 Bytes of ECC transferred in Byte-Mode. Because of the
unique nature of the solid-state ADC, the 4 Bytes of ECC transferred by the host may be used by the
ADC. The ADC may discard these 4 Bytes and write the sector with valid ECC data. This command has
the same protocol as the Write Sector(s) command. Use of this command is not recommended.
3.2.1.22 Write Multiple Command - C5H
Bit ->
7
6
5
4
3
2
1
0
C5H
Command (7)
C/D/H (6)
X
LBA
X
Drive
Head
Cylinder High
Cylinder Low
Sector Number
Sector Count
X
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
Note: The current revision of the SST ADC can support up to a block count of 1 as indicated in the Identify Drive Command information.
This command is similar to the Write Sectors command. The ADC sets BSY within 400 ns of accepting
the command. Interrupts are not presented on each sector but on the transfer of a block which contains
the number of sectors defined by Set Multiple. Command execution is identical to the Write Sectors
operation except that the number of sectors defined by the Set Multiple command is transferred without
intervening interrupts.
DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The
block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple
Mode command, which must be executed prior to the Write Multiple command.
When the Write Multiple command is issued, the Sector Count Register contains the number of sectors
(not the number of blocks or the block count) requested. If the number of requested sectors is not
evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final,
partial block transfer. The partial block transfer is for n sectors, where:
n = remainder (sector count/block).
If the Write Multiple command is attempted before the Set Multiple Mode command has been executed
or when Write Multiple commands are disabled, the Write Multiple operation will be rejected with an
aborted command error.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
32
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
Errors encountered during Write Multiple commands are posted after the attempted writes of the block
or partial block transferred. The Write command ends with the sector in error, even if it is in the middle
of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated
when DRQ is set at the beginning of each block or partial block.
The Command Block Registers contain the cylinder, head and sector number of the sector where the
error occurred and the Sector Count Register contains the residual number of sectors that need to be
transferred for successful completion of the command e.g. each block has 4 sectors, a request for 8
sectors is issued and an error occurs on the third sector. The Sector Count Register contains 6 and the
address is that of the third sector.
3.2.1.23 Write Sector(s) - 30H or 31H
Bit ->
Command (7)
C/D/H (6)
7
6
5
4
3
2
1
0
30H or 31H
Drive
1
LBA
1
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
X
This command writes from 1 to 256 sectors as specified in the Sector Count Register. A sector count of
zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register.
When this command is accepted, the ADC sets BSY, then sets DRQ and clears BSY, then waits for the
host to fill the sector buffer with the data to be written. No interrupt is generated to start the first host
transfer operation. No data should be transferred by the host until BSY has been cleared by the host.
For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be
cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated.
When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state
until the command is completed at which time BSY is cleared and an interrupt is generated.
If an error occurs during a write of more than one sector, writing terminates at the sector where the
error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector
where the error occurred. The host may then read the command block to determine what error has
occurred, and on which sector.
3.2.1.24 Write Verify - 3CH
Bit ->
7
6
5
4
3
2
1
0
3CH
Command (7)
C/D/H (6)
1
LBA
1
Drive
Head (LBA 27-24)
Cylinder High (LBA 23-16)
Cylinder Low (LBA 15-8)
Sector Number (LBA 7-0)
Sector Count
Cyl High (5)
Cyl Low (4)
Sec Num (3)
Sec Cnt (2)
Feature (1)
X
This command is similar to the Write Sector(s) command, except each sector is verified immediately
after being written. This command has the same protocol as the Write Sector(s) command.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
33
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
3.2.2 Error Posting
The following table summarizes the valid status and error value for all the ADC Command set.
TABLE
3-6: ERROR AND STATUS REGISTER
Error Register
Status Register
DWF CORR
Command
BBK
UNC
IDNF
ABRT AMNF DRDY
DSC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ERR
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Check Power Mode
Execute Drive Diagnostic1
Format Track
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Identify Drive
Idle
Idle Immediate
Initialize Drive Parameters
Read Buffer
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Read Multiple
Read Long Sector
Read Sector(s)
Read Verify Sectors
Recalibrate
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Seek
V
Set Features
Set Multiple Mode
Set Sleep Mode
Standby
Standby Immediate
Write Buffer
Write Long Sector
Write Multiple
Write Sector(s)
Write Verify
V
V
V
V
V
V
V
V
V
V
V
V
Invalid Command Code
V
T3-6.0 391
1. See Table 3-3
V = valid on this command
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
34
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
4.0 APPENDIX
4.1 Differences between ATA-Disk Chip and ATA/ATAPI-5 Specifications
This section details differences between ADC vs. ATA.
4.1.1 Electrical Differences
4.1.1.1 TTL Compatibility
ADC is not TTL compatible, it is a purely CMOS interface. Refer to section 2.3.2 of this specification.
4.1.1.2 Pull Up Resistor Input Leakage Current
The minimum pull up resistor input leakage current is 50K ohms rather than the 10K ohms stated in the
ATA specification.
4.1.2 Functional Differences
4.1.2.1 Idle Timer
The Idle timer uses an incremental value of 5 ms, rather than the 5 sec minimum increment value specified in ATA
specifications.
4.1.2.2 Recovery from Sleep Mode
For ADC devices, recovery from sleep mode is accomplished by simply issuing another command to the device.
A hardware or software reset is not required.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
35
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
5.0 PHYSICAL DIMENSIONS
TOP VIEW
BOTTOM VIEW
19.30
19.50
15.24
2.54
42.50
42.70
38.00
38.20
SIDE VIEW
5.60
5.80
3.60
4.00
32-psdip-P1H-ILL.8
0.50
Note: All linear dimensions are in millimeters (min/max).
32-PIN PLASTIC SUBASSEMBLY DUAL-IN-LINE PACKAGE (PSDIP)
SST PACKAGE CODE: P1H
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
36
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
6.0 PRODUCT ORDERING INFORMATION
SST 58 SD
192
-
70
- C
P1 H
XX XX XXXX X
XXX
X X
XX X
Package Modifier
H = 32 pins
Package Version
Package Type
P = PSDIP
Operation Temperature
C = Commercial: 0°C to +70°C
I = Industrial: -40°C to +85°C
Endurance
Data Transfer Speed
70 = 70 ns, supports up to PIO Mode 4
Version
Device Density
008 = 8 MBytes
016 = 16 MBytes
024 = 24 MBytes
032 = 32 MBytes
048 = 48 MBytes
064 = 64 MBytes
096 = 96 MBytes
128 = 128 MBytes
192 = 192 MBytes
Voltage
SD = 5.0V
LD = 3.3V
Device Family
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
37
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
6.1 Valid Combinations
SST58SD008 - 70 - C - P1H
SST58SD016 - 70 - C - P1H
SST58SD024 - 70 - C - P1H
SST58SD032 - 70 - C - P1H
SST58SD048 - 70 - C - P1H
SST58SD064 - 70 - C - P1H
SST58SD096 - 70 - C - P1H
SST58SD128 - 70 - C - P1H
SST58SD192 - 70 - C - P1H
SST58SD008 - 70 - I - P1H
SST58SD016 - 70 - I - P1H
SST58SD024 - 70 - I - P1H
SST58SD032 - 70 - I - P1H
SST58SD048 - 70 - I - P1H
SST58SD064 - 70 - I - P1H
SST58SD096 - 70 - I - P1H
SST58SD128 - 70 - I - P1H
SST58SD192 - 70 - I - P1H
SST58LD008 - 70 - C - P1H
SST58LD016 - 70 - C - P1H
SST58LD024 - 70 - C - P1H
SST58LD032 - 70 - C - P1H
SST58LD048 - 70 - C - P1H
SST58LD064 - 70 - C - P1H
SST58LD096 - 70 - C - P1H
SST58LD128 - 70 - C - P1H
SST58LD192 - 70 - C - P1H
SST58LD008 - 70 - I - P1H
SST58LD016 - 70 - I - P1H
SST58LD024 - 70 - I - P1H
SST58LD032 - 70 - I - P1H
SST58LD048 - 70 - I - P1H
SST58LD064 - 70 - I - P1H
SST58LD096 - 70 - I - P1H
SST58LD128 - 70 - I - P1H
SST58LD192 - 70 - I - P1H
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
38
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
7.0 LIMITED WARRANTY
SST warrants all products against non-conformances in
materials and workmanship for a period of one year from
the delivery date of subject products. SST’s liability is
limited to replacing or repairing the product if it has been
paid for. SST’s warranties will not be affected by rendering
of technical advice in connection with the order of products
furnished hereunder. Except as expressly provided above,
SST makes no warranties, express or implied, including
without limitation any warranty of merchantability or fitness
for a particular purpose. In no event shall SST be liable for
any incidental or consequential damages with respect to
the products purchased hereunder. SST reserves the right
to discontinue production or change specifications or
change prices at any time and without notice.
The information in this publication is believed to be
accurate in all respects at the time of publication, but is
subject to change without notice. SST assumes no
responsibility for any errors or omissions, and disclaims
responsibility for any consequences resulting from the use
of the information provided herein. SST assumes no
responsibility for the use of any circuitry other than circuitry
embodied in an SST product; no other circuits, patents, or
licenses are implied. SST assumes no responsibility for the
functioning of features or parameters not described herein.
7.1 Life Support Policy
SST’s products are not authorized for use as critical
component in life support devices or systems. Life support
devices or systems are devices or systems that, (a) are
intended for surgical implant into the body, or (b) support or
sustain life and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
A critical component is any component of a life support
device or system whose failure to perform can be expected
to cause the failure of the life support device or system, or
the affect its safety or effectiveness.
7.2 Patent Protection
SST products are protected by assigned U.S. and foreign
patents.
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
39
SST ATA-Disk Chip
SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192
Preliminary Specifications
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
S71167-04-000 6/01 391
40
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