Si4705-D60-GU2 [SILICON]
BROADCAST FM RADIO RECEIVER WITH RDS/RBDS;
| 型号： | Si4705-D60-GU2 |
| 厂家： | 
SILICON |
| 描述： | BROADCAST FM RADIO RECEIVER WITH RDS/RBDS |
| 文件： | 总39页 (文件大小：1700K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4704/05-D60
BROADCAST FM RADIO RECEIVER WITH RDS/RBDS
Features
Worldwide FM band support
(64–108 MHz)
Excellent real-world performance
Integrated VCO
Advanced FM seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Digital FM stereo decoder
Programmable de-emphasis
Advanced Audio Processing
FM digital tuning
EN55020 compliant
No manual alignment necessary
Programmable reference clock
Adjustable soft mute control
RDS/RBDS processor (Si4705-D60)
Digital audio out
2-wire and 3-wire control interface
Integrated LDO regulator
QFN and SSOP packages
RoHS compliant
Ordering Information:
See page 29.
Applications
Pin Assignments
Table and portable radios
Mini/micro systems
CD/DVD and Blu-ray players
Stereo boom boxes
Modules for consumer electronics
Clock radios
Mini HiFi and docking stations
Entertainment systems
Si4704/05-D60 (QFN)
Description
20 19 18 17
NC
FMI
1
16
2
15 DOUT
14 LOUT/[DFS]
13 ROUT/[DOUT]
12 GND
The Si4704/05-D60 digital CMOS FM radio receiver IC integrates the complete
tuner function from antenna input to digital audio output, enabling a cost efficient
digital audio platform for consumer electronic applications with high TDMA noise
immunity, superior radio performance, and high fidelity audio power amplification.
RFGND
LPI
3
4
5
GND
PAD
RST
6
11 VA
7
8
9
10
Si4704/05-D60 (SSOP)
Functional Block Diagram
DOUT
DFS
1
2
24
23
22
21
20
19
18
17
16
15
14
13
LOUT/[DFS]
FM Antenna
Si4704/05-D60
ROUT/[DOUT]
GPO3/[DCLK]
GPO2/[INT]
GPO1
NC
3
DBYP
VA
DOUT
RDS
(Si4705)
FMI
DIGITAL
AUDIO
4
DFS
LNA
AGC
RFGND
5
VD
GPO/DCLK
LOW-IF
DSP
RCLK
SDIO
SCLK
SEN
RST
GND
GND
6
NC
7
0/90
Mux
ADC
ADC
DAC
DAC
ROUT
LOUT
FMI
8
32.768 kHz
RFGND
NC
9
Mux
RCLK
AFC
LDO
10
11
12
2.7~5.5 V (QFN) / 2.0~5.5 V (SSOP)
LPI
VA
CONTROL
INTERFACE
VD
1.62 - 3.6 V
NC
+
GND
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both
foreign and domestic: 7,127,217;
7,272,373;
7,355,476;
7,272,375;
7,426,376;
7,321,324;
7,471,940;
7,339,503; 7,339,504.
Rev. 1.2 8/13
Copyright © 2013 by Silicon Laboratories
Si4704/05-D60
Si4704/05-D60
2
Rev. 1.2
Si4704/05-D60
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1. QFN Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. SSOP Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3. QFN/SSOP Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.4. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.6. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.7. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.8. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.9. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.10. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.11. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.12. RDS/RBDS Processor (Si4705-D60 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.13. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.14. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.18. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.19. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.20. 2 V Operation (SSOP Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.21. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.1. Si4704/05-D60-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.2. Si4704/05-D60-GU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7.1. Si4704/05-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7.2. Si4704/05-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.1. Si4704/05-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.2. Si4704/05-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
9. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9.1. Si4704/05-D60 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9.2. Top Marking Explanation (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9.3. Si4704/05-D60 Top Marking (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.2
3
Si4704/05-D60
9.4. Top Marking Explanation (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Document Change List: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4
Rev. 1.2
Si4704/05-D60
1. Electrical Specifications
Table 1. Recommended Operating Conditions1
Parameter
Analog Supply Voltage
Symbol Test Condition
Min
Typ
—
Max
5.5
3.6
—
Unit
V
2
V
2.7
A
Digital and I/O Supply Voltage
V
1.62
10
—
V
D
Power Supply Powerup Rise Time
Interface Power Supply Powerup Rise Time
V
—
µs
µs
C
DDRISE
V
10
—
—
IORISE
Ambient Temperature
T
–20
25
85
A
Notes:
1. All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
VA = 3.3 V and 25 C unless otherwise stated.
2. SSOP devices operate down to 2 V at 25 °C. See Section “4.20. 2 V Operation (SSOP Only)” for details.
Rev. 1.2
5
Si4704/05-D60
Table 2. DC Characteristics
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Mode
V
Supply Current
Supply Current
I
—
—
—
—
—
—
—
8.2
10.5
18.5
0.15
9.1
9.5
13.5
21.5
0.6
AQFN
FMVA
V
I
DQFN
FMVD
1
Digital Output Mode
V
Supply Current
Supply Current
I
ASSOP
FMVA
V
I
DSSOP
FMVD
mA
V
Supply Current
Supply Current
I
10.3
12.8
21.3
0.6
AQFN
FMVA
V
I
9.9
DQFN
FMVD
2
Analog Output Mode
V
Supply Current
Supply Current
I
19.1
0.1
ASSOP
FMVA
V
I
DSSOP
FMVD
Powerdown
Powerdown Current
V
—
—
4
9.5
3
15
15
10
10
AQFN
I
µA
µA
APD
V
Powerdown Current
Powerdown Current
ASSOP
V
V
SCLK, RCLK inactive
SCLK, RCLK inactive
—
DQFN
I
DPD
Powerdown Current
—
3
DSSOP
3
High Level Input Voltage
V
0.7 x V
–0.3
–10
–10
—
—
—
—
V + 0.3
V
V
IH
D
D
D
3
Low Level Input Voltage
V
0.3 x V
10
IL
D
3
High Level Input Current
I
V
= V = 3.6 V
µA
µA
IH
IN
D
3
Low Level Input Current
I
V
= 0 V,
IN
10
IL
V = 3.6 V
D
4
High Level Output Voltage
V
I
= 500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
OUT
4
Low Level Output Voltage
V
I
= –500 µA
0.2 x V
OL
D
Notes:
1. Guaranteed by characterization.
2. Backwards compatible mode to rev B and rev C. Additional features on this device may increase typical supply current.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
6
Rev. 1.2
Si4704/05-D60
Table 3. Reset Timing Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
t
SRST
t
—
—
ns
HRST
RST Pulse Release Time Before VDD/VIO Turn Off
t
30
—
—
ns
RRST
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the first start condition.
3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
5. RST must be held low for at least 100 µs after all voltage supplies have been ramped up.
6. RST needs to be asserted (pulled low) prior to any supply voltage is ramped down.
Figure 1. Reset Timing Parameters for Busmode Select
Rev. 1.2
7
Si4704/05-D60
Table 4. 2-Wire Control Interface Characteristics1,2,3
(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)
Parameter
SCLK Frequency
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
f
SCL
SCLK Low Time
SCLK High Time
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold
0.6
—
—
µs
HD:STA
(START)
SDIO Input to SCLK Setup
t
t
100
0
—
—
—
—
900
—
ns
ns
µs
SU:DAT
4,5
SDIO Input to SCLK Hold
HD:DAT
SU:STO
SCLK input to SDIO Setup
t
0.6
(STOP)
STOP to START Time
SDIO Output Fall Time
t
1.3
—
—
—
µs
ns
BUF
t
250
f:OUT
Cb
----------
1pF
20 + 0.1
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
r:IN
Cb
----------
1pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VD = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4704/05-D60 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
8
Rev. 1.2
Si4704/05-D60
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
SCLK
SDIO
70%
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
D7-D0
D7-D0
SDIO
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
Rev. 1.2
9
Si4704/05-D60
Table 5. 3-Wire Control Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
f
CLK
SCLK High Time
t
25
25
20
10
10
2
HIGH
SCLK Low Time
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
SEN Input to SCLKHold
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
—
ns
S
t
—
ns
HSDIO
t
—
ns
HSEN
t
Read
Read
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHSDIO
tHIGH
tLOW
tHSEN
tS
70%
30%
tS
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN
tS
tCDZ
70%
30%
tS
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
10
Rev. 1.2
Si4704/05-D60
Table 6. Digital Audio Interface Characteristics
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol Test Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK Pulse Width High
t
—
ns
DCLK Pulse Width Low
t
—
—
ns
DCL
DFS Set-up Time to DCLK Rising Edge
DFS Hold Time from DCLK Rising Edge
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
DOUT Propagation Delay from DCLK Falling
Edge
t
0
—
50
ns
PD:DOUT
tDCH
tDCL
DCLK
tDCT
DFS
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 6. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.2
11
Si4704/05-D60
Table 7. FM Receiver Characteristics1,2
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
76
—
Typ
—
Max
108
3.5
—
Unit
MHz
Input Frequency
f
RF
3,4,5,6
Sensitivity
(S+N)/N = 26 dB
2.2
10
µV EMF
µV EMF
6,7
RDS Sensitivity
f = 2 kHz,
—
RDS BLER < 5%
7,8
LNA Input Resistance
3
4
4
5
5
6
k
7,8
LNA Input Capacitance
pF
7,9
Input IP3
100
40
35
60
35
72
—
—
15
35
55
—
—
70
45
—
—
105
50
50
70
—
—
—
—
—
—
90
1
dBµV EMF
3,4,7,8
m = 0.3
±200 kHz
±400 kHz
In-band
dB
dB
dB
dB
AM Suppression
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
7
3,4,8
80
—
mV
Audio Output Voltage
RMS
3,8,10
7
dB
Hz
Audio Output L/R Imbalance
–3 dB
–3 dB
—
30
—
—
—
—
0.5
80
54
—
—
Audio Frequency Response Low
Audio Frequency Response High
7
—
kHz
dB
8,10
42
63
58
0.1
75
50
34
30
Audio Stereo Separation
3,4,5,8
dB
Audio Mono S/N
4,5,7,8
dB
Audio Stereo S/N
3,8,10
%
Audio THD
7
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
f = ±400 kHz
µs
µs
3,4,5,6,7,11, 12
Blocking Sensitivity
dBµV
dBµV
f = ±4 MHz
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Analog audio output mode.
7. Guaranteed by characterization.
8. V
= 1 mV.
EMF
9. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
10. f = 75 kHz.
11. Sensitivity measured at (S+N)/N = 26 dB.
12. Blocker Amplitude = 100 dBµV.
13. At temperature (25 °C).
14. At LOUT and ROUT pins.
12
Rev. 1.2
Si4704/05-D60
Table 7. FM Receiver Characteristics1,2 (Continued)
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
f = ±400 kHz, ±800 kHz
f = ±4 MHz, ±8 MHz
Single-ended
Min
—
Typ
40
35
—
Max
—
Unit
dBµV
dBµV
k
3,4,5,6,7,11,12
Intermod Sensitivity
—
—
7,14
R
10
—
—
Audio Output Load Resistance
L
7,14
C
Single-ended
—
50
60
pF
Audio Output Load Capacitance
L
7
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
—
ms/channel
7
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
13
RSSI Offset
Input levels of 8 and
60 dBµV at RF Input
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
4. f = 22.5 kHz.
5. B = 300 Hz to 15 kHz, A-weighted.
AF
6. Analog audio output mode.
7. Guaranteed by characterization.
8. V
= 1 mV.
EMF
9. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
10. f = 75 kHz.
11. Sensitivity measured at (S+N)/N = 26 dB.
12. Blocker Amplitude = 100 dBµV.
13. At temperature (25 °C).
14. At LOUT and ROUT pins.
Rev. 1.2
13
Si4704/05-D60
Table 8. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,3
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
64
—
3
Typ
—
Max
75.9
—
5
Unit
MHz
µV EMF
k
Input Frequency
f
RF
,
4,5,6 8
Sensitivity
LNA Input Resistance
(S+N)/N = 26 dB
3.5
4
3,7
3,7
LNA Input Capacitance
4
5
6
pF
9
Input IP3
—
—
—
—
72
—
—
15
—
—
70
45
10
—
—
105
50
50
70
80
—
—
—
—
—
90
1
dBµV EMF
dB
3,4,5,7
m = 0.3
±200 kHz
±400 kHz
AM Suppression
dB
Adjacent Channel Selectivity
Alternate Channel Selectivity
dB
4,5,7
mV
Audio Output Voltage
RMS
4,7,10
dB
Audio Output L/R Imbalance
3
–3 dB
–3 dB
—
30
—
—
—
80
54
—
50
60
Hz
Audio Frequency Response Low
3
—
kHz
Audio Frequency Response High
4,3,5,7
63
0.1
75
50
—
dB
Audio Mono S/N
4,7,10
%
Audio THD
3
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
µs
µs
k
3,11
R
Audio Output Load Resistance
L
L
3,11
C
Single-ended
—
pF
Audio Output Load Capacitance
3
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
ms/channel
3
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
12
RSSI Offset
Input levels of 8 and
60 dBµV EMF
–3
Notes:
1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”
Volume = maximum for all tests. Tested at RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. Guaranteed by characterization.
4. F
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
5. f = 22.5 kHz.
6. B = 300 Hz to 15 kHz, A-weighted.
AF
7. V
= 1 mV.
EMF
8. Analog output mode.
9. |f – f | > 2 MHz, f = 2 x f – f . AGC is disabled.
2
1
0
1
2
10. f = 75 kHz.
11. At LOUT and ROUT pins.
12. At temperature (25 °C).
14
Rev. 1.2
Si4704/05-D60
Table 9. Reference Clock and Crystal Characteristics
(V = 2.7 to 5.5 V, V = 1.62 to 3.6 V, TA = –20 to 85 °C)
A
D
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock
1
RCLK Supported Frequencies
31.130
–100
1
32.768
—
40,000
100
kHz
2
RCLK Frequency Tolerance
ppm
REFCLK_PRESCALE
REFCLK
—
4095
31.130
32.768
34.406
kHz
Crystal Oscillator
Crystal Oscillator Frequency
—
–100
—
32.768
—
—
100
3.5
50
kHz
ppm
pF
2
Crystal Frequency Tolerance
Board Capacitance
ESR
—
—
—
pF
3
CL
7
12
22
3
CL–single ended
14
24
44
pF
Notes:
1. The Si473x-D60 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx
Programming Guide”.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.
3. Guaranteed by characterization.
Table 10. Thermal Conditions
Parameter
Thermal Resistance*
Ambient Temperature
Junction Temperature
Symbol
Min
—
Typ
80
Max
—
Unit
°C/W
°C
JA
T
–20
—
25
85
A
T
—
92
°C
J
*Note: Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad.
Rev. 1.2
15
Si4704/05-D60
Table 11. Absolute Maximum Ratings1,2
Parameter
Analog Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
V
A
Digital and I/O Supply Voltage
V
V
D
3
Input Current
I
mA
V
IN
3
Input Voltage
V
T
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
–40 to 95
–55 to 150
0.4
C
C
OP
Storage Temperature
T
STG
4
RF Input Level
V
pk
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4704/05-D60 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2
kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK.
4. At RF input pin FMI and LPI.
16
Rev. 1.2
Si4704/05-D60
2. Typical Application Schematic
2.1. QFN Typical Application Schematic
Optional: Digital Audio Out
OPMODE: 0xB0, 0xB5
C9
GPO1
GPO2/INT
R3
R2
R1
GPO3/DCLK
DFS
DOUT
1
15
NC
DOUT
C2
2
3
4
5
14
FM Antenna
FMI
LOUT
LOUT
13
RFGND
ROUT
ROUT
12
Embedded Antenna
Si4704/05
LPI
GND
2.7 to 5.5 V
C1
D60
11
RSTB
VA
VA
1.62 to 3.6 V
C4
VD
RSTB
RCLK
SDIO
SCLK
SENB
GPO3
RCLK
X1
C6
C5
Optional: For Crystal OSC
Notes:
1. Place C1 close to VA pin and C4 close to VD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface.
6. Place Si4704/05-D60 as close as possible to antenna and keep the FMI traces as short as possible.
Rev. 1.2
17
Si4704/05-D60
2.2. SSOP Typical Application Schematic
Optional: Digital Audio Out
OPMODE: 0xB0, 0xB5
C9
R1
R2
R3
1
24
23
22
21
20
19
18
17
16
15
14
13
DOUT
LOUT
ROUT
DBYP
VA
DOUT
DFS
LOUT
ROUT
2
DFS
3
GPO3/DCLK
GPO2/INT
GPO3/DCLK
GPO2/INT
GPO1
C1
4
2.0 to 5.5 V
VA
1.62 to 3.6 V
C4
5
GPO1
NC
VD
VD
6
RCLK
SDIO
SCLK
SENB
RCLK
SDIO
SCLK
SENB
RSTB
7
NC
C2
8
FM Antenna
FMI
9
RFGND
NC
10
11
12
RSTB
GND
LPI
NC
Embedded Antenna
GND
GPO3
RCLK
X1
C6
C5
Optional: For Crystal OSC
Notes:
1. Place C1 close to VA and C4 close to VD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 6 and 7 are no connects, leave floating.
4. Pin 10 is unused. Tie this pin to GND.
5. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,
Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
6. Pin 8 connects to the FM antenna interface.
7. Place Si4704/05-D60 as close as possible to antenna and keep the FMI traces as short as possible.
18
Rev. 1.2
Si4704/05-D60
3. QFN/SSOP Bill of Materials
Table 12. Si4704/05-D60 QFN/SSOP Bill of Materials
Component(s)
Value/Description
Supplier
Murata
C1
C2
C4
U1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Coupling capacitor, 1 nF, ±20%, Z5U/X7R
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R
Si4704/05-D60 FM Radio Tuner
Murata
Murata
Silicon Laboratories
Optional Components
C5, C6
C9
Crystal load capacitors, 22 pF, ±5%, COG
(Optional for crystal oscillator)
Venkel
Murata
Venkel
Venkel
Venkel
Epson
Noise mitigating capacitor, 2~5 pF
(Optional for digital audio)
R1
Resistor, 600
(Optional for digital audio)
R2
Resistor, 2 k
(Optional for digital audio)
R3
Resistor, 2 k
(Optional for digital audio)
X1
32.768 kHz crystal
(Optional for crystal oscillator)
Rev. 1.2
19
Si4704/05-D60
4. Functional Description
4.1. Overview
FM Antenna
Si4704/05-D60
DOUT
RDS
(Si4705)
FMI
DIGITAL
AUDIO
DFS
LNA
AGC
RFGND
GPO/DCLK
LOW-IF
0/90
Mux
ADC
ADC
DAC
DAC
ROUT
LOUT
DSP
32.768 kHz
RCLK
Mux
AFC
LDO
2.7~5.5 V (QFN) / 2.0~5.5 V (SSOP)
+
VA
CONTROL
INTERFACE
VD
1.62 - 3.6 V
GND
Figure 7. Functional Block Diagram
The Si4704/05-D60 CMOS FM radio receiver IC The Si4704/05-D60 is a feature-rich solution that
integrates the complete tuner function from antenna includes advanced seek algorithms, soft mute, auto-
input to audio output. This feature enables a cost- calibrated digital tuning, FM stereo processing and
efficient digital audio platform for consumer electronics advanced audio processing.
applications with high TDMA noise immunity, superior
radio performance, and high fidelity audio power
digital audio outputs and a programmable reference
amplification. Offering unmatched integration and PCB
In addition, the Si4704/05-D60 provides analog and
2
clock. The device supports I C-compatible 2-wire
space savings, the Si4704/05-D60 requires only few
control interface, and
a
Si4700/01 backwards-
2
external components and less than 15 mm of board
compatible 3-wire control interface.
area, excluding the antenna inputs. The Si4704/05-D60
FM radio provides the space savings and low power
consumption necessary for portable devices while
delivering the high performance and design simplicity
desired for all FM solutions.
The Si4704/05-D60 utilizes digital signal processing to
achieve high fidelity, optimal performance, and design
flexibility. The chip provides excellent pilot rejection,
selectivity, and unmatched audio performance, and
offers both the manufacturer and the end-user
Leveraging Silicon Laboratories' proven and patented
Si4700/01 FM tuner's digital low intermediate frequency
(low-IF) receiver architecture, the Si4704/05-D60
delivers superior RF performance and interference
rejection in the FM bands. The high level of integration
and complete system production test simplifies design-
in, increases system quality, and improves reliability and
manufacturability.
extensive programmability and
experience.
a better listening
The Si4705-D60 incorporates a digital signal processor
for the European Radio Data System (RDS) and the
North American Radio Broadcast Data System (RBDS)
including all required symbol decoding, block
synchronization, error detection, and error correction
functions. Using this feature, the Si4705-D60 enables
broadcast data such as station identification and song
name to be displayed to the user.
20
Rev. 1.2
Si4704/05-D60
4.4.1. Audio Data Formats
4.2. Operating Modes
The digital audio interface operates in slave mode and
supports three different audio data formats:
The Si4704/05-D60 operates in FM receive mode. In
FM mode, radio signals are received on FMI and
processed by the FM front-end circuitry. In addition to
the receiver mode, there is a clocking mode to choose
to clock the Si4704/05-D60 from a reference clock or
crystal. On the Si4704/05-D60, there is an audio output
mode to choose between an analog and/or digital audio
output. In the analog audio output mode, ROUT and
LOUT are used for the audio output pins. In the digital
audio mode, DOUT, DFS, and DCLK pins are used.
Concurrent analog/digital audio output mode is also
available requiring all five pins.
2
I S
Left-Justified
DSP Mode
2
In I S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
In left-justified mode, by default the MSB is captured on
the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
4.3. FM Receiver
The Si4704/05-D60 FM receiver is based on the proven
Si4700/01 FM tuner. The receiver uses a digital low-IF
architecture allowing the elimination of external
components and factory adjustments. The Si4704/05-
D60 integrates a low noise amplifier (LNA) supporting
the worldwide FM broadcast band (64 to 108 MHz). An
AGC circuit controls the gain of the LNA to optimize
sensitivity and rejection of strong interferers. An image-
reject mixer downconverts the RF signal to low-IF. The
quadrature mixer output is amplified, filtered, and
digitized with high resolution analog-to-digital
converters (ADCs). This advanced architecture allows
the Si4704/05-D60 to perform channel selection, FM
demodulation, and stereo audio processing to achieve
superior performance compared to traditional analog
architectures.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
4.4. Digital Audio Interface
The digital audio interface operates in slave mode and
supports a variety of MSB-first audio data formats
2
4.4.2. Audio Sample Rates
including I S and left-justified modes. The interface has
three pins: digital data input (DIN), digital frame
The device supports a number of industry-standard
sampling rates including 32, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
synchronization input (DFS), and
a
digital bit
synchronization input clock (DCLK). The Si4704/05-D60
supports a number of industry-standard sampling rates
including 32, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
Rev. 1.2
21
Si4704/05-D60
INVERTED
(OFALL = 1)
DCLK
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
I2S
RIGHT CHANNEL
(OMODE = 0000)
1 DCLK
1 DCLK
n-2
DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 8. I2S Digital Audio Format
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(OMODE = 0110)
DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 9. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DOUT
1
2
3
2
n-1
n
(OMODE = 1100)
(OMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2nd rising edge)
MSB
LSB
MSB
LSB
Figure 10. DSP Digital Audio Format
22
Rev. 1.2
Si4704/05-D60
4.5. Stereo Audio Processing
4.6. Received Signal Qualifiers
The output of the FM demodulator is a stereo The quality of a tuned signal can vary depending on
multiplexed (MPX) signal. The MPX standard was many factors including environmental conditions, time of
developed in 1961, and is used worldwide. Today's day, and position of the antenna. To adequately manage
MPX signal format consists of left + right (L+R) audio, the audio output and avoid unpleasant audible effects to
left – right (L–R) audio, a 19 kHz pilot tone, and the end-user, the Si4704/05-D60 monitors and provides
RDS/RBDS data as shown in Figure 11 below.
indicators of the signal quality, allowing the host
processor to perform additional processing if required
by the customer. The Si4704/05-D60 monitors signal
quality metrics including RSSI, SNR, and multipath
interference on FM signals. These metrics are used to
optimize signal processing and are also reported to the
host processor. The signal processing algorithms can
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
use
either
Silicon
Labs'
optimized
settings
(recommended) or be customized to modify
performance.
0
15 19 23
38
53 57
Frequency (kHz)
4.7. Volume Control
Figure 11. MPX Signal Spectrum
The audio output may be muted. Volume is adjusted
digitally by the RX_VOLUME property.
4.5.1. Stereo Decoder
The Si4704/05-D60's integrated stereo decoder
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
4.8. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted.
4.9. Soft Mute
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The soft mute feature is triggered by the
SNR metric. The SNR threshold for activating soft mute
is programmable, as are soft mute attenuation levels
and attack and release rates.
4.5.2. Stereo-Mono Blending
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Three metrics, received signal
strength indicator (RSSI), signal-to-noise ratio (SNR),
4.10. FM Hi-Cut Control
Hi-cut control is employed on audio outputs with
degradation of the signal due to low SNR and/or
multipath interference. Two metrics, SNR and multipath
interference, are monitored concurrently in forcing hi-cut
of the audio outputs. Programmable minimum and
maximum thresholds are available for both metrics. The
transition frequency for hi-cut is also programmable with
up to seven hi-cut filter settings. A single set of attack
and release rates for hi-cut are programmable for both
metrics from a range of 2 ms to 64 s. The level of hi-cut
applied can be monitored with the FM_RSQ_STATUS
command. Hi-cut can be disabled by setting the hi-cut
filter to audio bandwidth of 15 kHz.
and
multipath
interference,
are
monitored
simultaneously in forcing a blend from stereo to mono.
The metric which reflects the minimum signal quality
takes precedence and the signal is blended
appropriately.
All three metrics have programmable stereo/mono
thresholds and attack/release rates. If a metric falls
below its mono threshold, the signal is blended from
stereo to full mono. If all metrics are above their
respective stereo thresholds, then no action is taken to
blend the signal. If a metric falls between its mono and
stereo thresholds, then the signal is blended to the level
proportional to the metric’s value between its mono and
stereo thresholds, with an associated attack and
release rate.
Rev. 1.2
23
Si4704/05-D60
The Si4704/05-D60 uses RSSI, SNR, and AFC to
qualify stations. Most of these variables have
programmable thresholds for modifying the seek
function according to customer needs.
4.11. De-emphasis
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
RSSI is employed first to screen all possible candidate
stations. SNR and AFC are subsequently used in
screening the RSSI qualified stations. The more
thresholds the system engages, the higher the
confidence that any found stations will indeed be valid
broadcast stations. The Si4704/05-D60 defaults set
RSSI to a mid-level threshold and add an SNR
threshold set to a level delivering acceptable audio
performance. This trade-off will eliminate very low RSSI
stations while keeping the seek time to acceptable
levels. Generally, the time to auto-scan and store valid
channels for an entire FM band with all thresholds
engaged is very short depending on the band content.
Seek is initiated using the FM_SEEK_START
command. The RSSI, SNR, and AFC threshold settings
are adjustable using properties.
transmitted,
a
pre-emphasis filter is applied to
accentuate the high audio frequencies. The Si4704/05-
D60 incorporates a de-emphasis filter which attenuates
high frequencies to restore a flat frequency response.
Two time constants are used in various regions. The de-
emphasis time constant is programmable to 50 or 75 µs
and is set by the FM_DEEMPHASIS property.
4.12. RDS/RBDS Processor (Si4705-D60
Only)
The Si4705-D60 implements an RDS/RBDS* processor
for symbol decoding, block synchronization, error
detection, and error correction.
The Si4705-D60 device is user configurable and
provides an optional interrupt when RDS is
synchronized, loses synchronization, and/or the user
configurable RDS FIFO threshold has been met.
4.15. Reference Clock
The Si4704/05-D60 reference clock is programmable,
supporting RCLK frequencies listed in Table 9,
“Reference Clock and Crystal Characteristics,” on
page 15. Refer to Table 2, “DC Characteristics,” on
page 6 for switching voltage levels and Table 9 for
frequency tolerance information.
The Si4705-D60 reports RDS decoder synchronization
status and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors or that the block checkword
contains errors. The pilot does not have to be present to
decode RDS/RBDS.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 17. This mode is enabled using the
POWER_UP command. Refer to “AN332: Si47xx
Programming Guide”.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
4.13. Tuning
The Si4704/05-D60 performance may be affected by
data activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4704/05-D60 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
The tuning frequency is directly programmed using the
FM_TUNE_FREQ command. The Si4704/05-D60
supports channel spacing steps of 10 kHz in FM mode.
4.14. Seek
The Si4704/05-D60 seek functionality is performed
completely on-chip and will search up or down the
selected frequency band for a valid channel. A valid
channel is qualified according to
a
series of
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4704/05-D60 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
programmable signal indicators and thresholds. The
seek function can be made to stop at the band edge and
provide an interrupt, or wrap the band and continue
seeking until arriving at the original departure frequency.
The device sets interrupts with found valid stations or, if
the seek results in zero found valid stations, the device
indicates failure and again sets an interrupt. Refer to
“AN332: Si47xx Programming Guide”.
24
Rev. 1.2
Si4704/05-D60
edges of SCLK. The Si4704/05-D60 acknowledges
each data byte by driving SDIO low for one cycle, on the
next falling edge of SCLK. The user may write up to 8
data bytes in a single 2-wire transaction. The first byte is
a command, and the next seven bytes are arguments.
4.16. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4704/05-
D60 and receive responses from the device. The serial
port can operate in two bus modes: 2-wire mode and 3-
wire mode. The Si4704/05-D60 selects the bus mode by
sampling the state of the GPO1 and GPO2 pins on the
rising edge of RST. The GPO1 pin includes an internal
pull-up resistor, which is connected while RST is low,
and the GPO2 pin includes an internal pull-down
resistor, which is connected while RST is low.
Therefore, it is only necessary for the user to actively
drive pins which differ from these states. See Table 13.
For read operations, after the Si4704/05-D60 has
acknowledged the control byte, it will drive an 8-bit data
byte on SDIO, changing the state of SDIO on the falling
edge of SCLK. The user acknowledges each data byte
by driving SDIO low for one cycle, on the next falling
edge of SCLK. If a data byte is not acknowledged, the
transaction will end. The user may read up to 16 data
bytes in a single 2-wire transaction. These bytes contain
the response data from the Si4704/05-D60.
Table 13. Bus Mode Select on Rising Edge of
RST
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
to Table 4, “2-Wire Control Interface Characteristics” on
page 8; Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 9, and Figure 3, “2-
Wire Control Interface Read and Write Timing Diagram,”
on page 9.
Bus Mode
2-Wire
3-Wire
GPO1
1
0 (must drive)
GPO2
0
0
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins, as
described in Section “4.17. GPO Outputs”. In any bus
mode, commands may only be sent after VD and VA
supplies are applied.
4.16.2. 3-Wire Control Interface Mode
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
The 3-wire bus mode uses the SCLK, SDIO, and SEN_
pins. A transaction begins when the user drives SEN
low. Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a 9-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a 5-bit register address (A4:A0).
4.16.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
The 2-wire bus mode uses only the SCLK and SDIO
pins for signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a 7-bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4704/05-D60 acknowledges the
control word by driving SDIO low on the next falling
edge of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4704/05-D60 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
Although the Si4704/05-D60 will respond to only a
single device address, this address can be changed
with the SEN pin (note that the SEN pin is not used for
signaling in 2-wire mode). Refer to “AN332: Si47xx
Programming Guide”
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
For details on timing specifications and diagrams, refer
to Table 5, “3-Wire Control Interface Characteristics,” on
page 10, Figure 4, and Figure 5.
For write operations, the user then sends an 8-bit data
byte on SDIO, which is captured by the device on rising
Rev. 1.2
25
Si4704/05-D60
4.17. GPO Outputs
4.21. Programming with Commands
The Si4704/05-D60 provides three general-purpose To ease development time and offer maximum
output pins. The GPO pins can be configured to output customization, the Si4704/05-D60 provides a simple yet
a constant low, constant high, or high-impedance. The powerful software interface to program the receiver. The
GPO pins can be reconfigured as specialized functions. device is programmed using commands, arguments,
properties, and responses.
4.18. Firmware Upgrades
To perform an action, the user writes a command byte
The Si4704/05-D60 contains on-chip program RAM to
and associated arguments, causing the chip to execute
accommodate minor changes to the firmware. This
the given command. Commands control an action such
allows Silicon Labs to provide future firmware updates
as powerup the device, shut down the device, or tune to
to optimize the characteristics of new radio designs and
a station. Arguments are specific to a given command
those already deployed in the field.
and are used to modify the command.
Properties are a special command argument used to
4.19. Reset, Powerup, and Powerdown
modify the default chip operation and are generally
Setting the RST pin low will disable analog and digital
configured immediately after powerup. Examples of
circuitry, reset the registers to their default settings, and
properties are de-emphasis level, RSSI seek threshold,
disable the bus. Setting the RST pin high will bring the
and soft mute attenuation threshold.
device out of reset.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. All commands provide a 1-byte status update,
indicating interrupt and clear-to-send status information.
The Si4704/05-D60 contains an on-board non-volatile
memory for storing its operational firmware. Proper
timing as specified in this data sheet, particularly with
respect to keeping RST pin low during any power
For a detailed description of the commands and
supply transitions, must be honored to avoid the risk of
properties for the Si4704/05-D60, see “AN332: Si47xx
corrupting the contents of this memory, which can
render the device permanently non-functional.
Programming Guide.”
A powerdown mode is available to reduce power
consumption when the part is idle. Putting the device in
powerdown mode will disable analog and digital circuitry
while keeping the bus active.
4.20. 2 V Operation (SSOP Only)
The Si4704/05-D60 is capable of operating down to 2 V
as the battery drains in an application. Any power-up or
reset is not guaranteed to work below the dc
characteristics defined in Table 2. This capability
enables a much longer run time in battery operated
devices.
26
Rev. 1.2
Si4704/05-D60
5. Pin Descriptions
5.1. Si4704/05-D60-GM
20 19 18 17
NC
FMI
1
16
2
15 DOUT
14 LOUT/[DFS]
13 ROUT/[DOUT]
12 GND
RFGND
LPI
3
4
5
GND
PAD
RST
6
11 VA
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 20
No connect. Leave floating.
2
FMI
FM RF inputs. FMI should be connected to the antenna trace.
RF ground. Connect to ground plane on PCB.
Embedded antenna input.
3
RFGND
LPI
4
5
Device reset input (active low).
RST
6
Serial enable input (active low).
SEN
7
SCLK
SDIO
RCLK
Serial clock input.
8
Serial data input/output.
9
External reference oscillator input.
Digital and I/O supply voltage.
10
V
D
11
V
Analog supply voltage. May be connected directly to battery.
Ground. Connect to ground plane on PCB.
A
12, GND PAD
GND
13
14
15
16
17
ROUT/[DOUT] Right audio line output for analog output mode.
LOUT/[DFS] Left audio line output for analog output mode.
DOUT
DFS
Digital output data for digital output mode.
Digital frame synchronization input for digital output mode.
GPO3/[DCLK] General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
18
19
General purpose output or interrupt pin.
General purpose output.
GPO2/[INT]
GPO1
Rev. 1.2
27
Si4704/05-D60
5.2. Si4704/05-D60-GU
DOUT
DFS
1
2
24
23
22
21
20
19
18
17
16
15
14
13
LOUT/[DFS]
ROUT/[DOUT]
GPO3/[DCLK]
GPO2/[INT]
GPO1
NC
3
DBYP
VA
4
5
VD
RCLK
SDIO
SCLK
SEN
RST
6
NC
7
FMI
8
RFGND
NC
9
10
11
12
LPI
GND
GND
NC
Pin Number(s)
Name
DOUT
DFS
Description
1
2
3
Digital output data for digital output mode.
Digital frame synchronization input for digital output mode.
GPO3/[DCLK] General purpose output, crystal oscillator, or digital bit synchronous clock input
in digital output mode.
4
5
GPO2/[INT]
GPO1
NC
General purpose output or interrupt pin.
General purpose output.
6,7
8
No connect. Leave floating.
FMI
FM RF inputs. FMI should be connected to the antenna trace.
RF ground. Connect to ground plane on PCB.
Unused. Tie these pins to GND.
9
RFGND
NC
10
11
LPI
Embedded antenna input.
12
13,14
NC
Unused. Tie these pins to GND.
GND
Ground. Connect to ground plane on PCB.
15
RST
Device reset input (active low).
16
17
18
19
20
SEN
SCLK
SDIO
RCLK
Serial enable input (active low).
Serial clock input.
Serial data input/output.
External reference oscillator input.
Digital and I/O supply voltage.
V
D
21
Analog supply voltage. May be connected directly to battery.
Bypass capacitor.
V
A
22
23
24
DBYP
ROUT/[DOUT] Right audio line output in analog output mode.
LOUT/[DFS] Left audio line output in analog output mode.
28
Rev. 1.2
Si4704/05-D60
6. Ordering Guide
1
Description
Package
Type
Operating
Temperature/Voltage
Part Number
Si4704-D60-GM
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
FM Broadcast Radio Receiver
2
Si4704-D60-GU
Si4705-D60-GM
SSOP
Pb-free
QFN
Pb-free
–20 to 85 °C
2.7 to 5.5 V
FM Broadcast Radio Receiver with
RDS/RBDS
2
Si4705-D60-GU
SSOP
Pb-free
Notes:
1. Add an “(R)” at the end of the device part number to denote tape and reel option.
2. SSOP devices operate down to V = 2 V at 25 °C.
A
Rev. 1.2
29
Si4704/05-D60
7. Package Outline
7.1. Si4704/05-D60 QFN
Figure 12 illustrates the package details for the Si4704/05-D60. Table 14 lists the values for the dimensions shown
in the illustration.
Figure 12. 20-Pin Quad Flat No-Lead (QFN)
Table 14. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.20
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.65
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
30
Rev. 1.2
Si4704/05-D60
7.2. Si4704/05-D60 SSOP
Figure 13 illustrates the package details for the Si4704/05-D60. Table 15 lists the values for the dimensions shown
in the illustration.
Figure 13. 24-Pin SSOP
Table 15. Package Dimensions
Dimension
Min
—
Nom
—
Max
1.75
0.25
0.30
0.25
A
A1
b
0.10
0.20
0.10
—
—
c
—
D
8.65 BSC
6.00 BSC
3.90 BSC
0.635 BSC
—
E
E1
e
L
0.40
0°
1.27
8°
L2
θ
0.25 BSC
—
aaa
bbb
ccc
ddd
0.20
0.18
0.10
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.2
31
Si4704/05-D60
8. PCB Land Pattern
8.1. Si4704/05-D60 QFN
Figure 14 illustrates the PCB land pattern details for the Si4704/05-D60-GM QFN. Table 16 lists the values for the
dimensions shown in the illustration.
Figure 14. PCB Land Pattern
32
Rev. 1.2
Si4704/05-D60
Table 16. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.2
33
Si4704/05-D60
8.2. Si4704/05-D60 SSOP
Figure 15 illustrates the PCB land pattern details for the Si4704/05-D60-GU SSOP. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 15. PCB Land Pattern
Table 17. PCB Land Pattern Dimensions
Dimension
Min
Max
C
E
5.20
5.30
0.635 BSC
X
0.30
1.50
0.40
1.60
Y1
General:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design:
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly:
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
34
Rev. 1.2
Si4704/05-D60
9. Top Markings
9.1. Si4704/05-D60 Top Marking (QFN)
0560
DTTT
0460
DTTT
YWW YWW
9.2. Top Marking Explanation (QFN)
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
04 = Si4704, 05 = Si4705-D60.
60 = Firmware Revision 6.0.
D = Revision D Die.
Firmware Revision
Die Revision
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code.
Circle = 0.5 mm Diameter Pin 1 Identifier.
(Bottom-Left Justified)
Y = Year
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and work week of the mold date.
WW = Workweek
Rev. 1.2
35
Si4704/05-D60
9.3. Si4704/05-D60 Top Marking (SSOP)
470XD60GU
YYWWTTTTTT
9.4. Top Marking Explanation (SSOP)
Mark Method:
YAG Laser
Part Number
Die Revision
Firmware Revision
Package Type
4704 = Si4704; 4705 = Si4705-D60.
D = Revision D die.
Line 1 Marking:
60 = Firmware Revision 6.0.
GU = 24-pin SSOP Pb-free package
YY = Year
Line 2 Marking:
WW = Work week
TTTTTT = Manufacturing code
Assigned by the Assembly House.
36
Rev. 1.2
Si4704/05-D60
10. Additional Reference Resources
Contact your local sales representatives for more information or to obtain copies of the following references:
EN55020 Compliance Test Certificate
AN332: Si47xx Programming Guide
AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines
AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure
Si47xx EVB User’s Guide
Customer Support Site: www.silabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for complete access. Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support
request.
Rev. 1.2
37
Si4704/05-D60
DOCUMENT CHANGE LIST:
Revision 0.4 to Revision 1.0
Updated application schematic.
Updated pin descriptions.
Revision 1.0 to Revision 1.1
Updated front page pin assignments.
Updated Table 6, “Digital Audio Interface
Characteristics,” on page 11.
Updated Table 9, “Reference Clock and Crystal
Characteristics,” on page 15.
Added Table 10, “Thermal Conditions,” on page 15.
Updated Section "5. Pin Descriptions" on page 27.
Updated Section "5.1. Si4704/05-D60-GM" on page
27.
Updated Section "5.2. Si4704/05-D60-GU" on page
28.
Revision 1.1 to Revision 1.2
Deleted the AUXIN feature.
Updated Table 3, “Reset Timing Characteristics.”
Updated Table 10, “Thermal Conditions.”
Updated Section 4.19, “Reset, Powerup, and
Powerdown.”
38
Rev. 1.2
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Connected.
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Disclaimer
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
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