Si4720-B20-GM [SILICON]
BROADCAST FM RADIO TRANSCEIVER FOR PORTABLE APPLICATIONS;
| 型号： | Si4720-B20-GM |
| 厂家： | 
SILICON |
| 描述： | BROADCAST FM RADIO TRANSCEIVER FOR PORTABLE APPLICATIONS |
| 文件： | 总48页 (文件大小：1857K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4720/21-B20
BROADCAST FM RADIO TRANSCEIVER FOR PORTABLE APPLICATIONS
Features
Full FM RX and TX in 3 x 3 QFN Adjustable seek parameters
Worldwide FM RX band support
Adjustable mono/stereo blend
Adjustable soft mute
Compliant with worldwide FM TX
regulations
Advanced modulation control
Audio dynamic range control
Audio silence detector
Excellent real-world performance
Supports integrated TX/RX
antenna
Ordering Information:
Programmable transmit output
Programmable reference clock
See page 42.
voltage
input
Frequency synthesizer with
2-wire and 3-wire control
integrated VCO
interface
Pin Assignments
Integrated LDO regulator
2.7 to 5.5 V supply voltage
Si4720/21
2
Minimal BOM (15 mm )
3 x 3 x 0.55 mm 20-pin Pb-free
(Top View)
QFN package
Digital audio output
(Si4721 only)
RDS/RDBS encoder/decoder
(Si4721 only)
Digital audio input
Applications
Cellular handsets/hands-free
MP3 players
Wireless speakers/microphone
Satellite digital audio radios
Personal computers/notebooks
20 19 18 17
NC
FMI
1
16
2
15 RIN/DOUT
14 LOUT/DFS
13 ROUT/DIN
12 GND
Portable media players
RFGND
TXO
3
4
5
GND
PAD
Description
RST
The Si4720/21 integrates the complete tuner and transmit functions for
FM broadcast reception and standards-compliant, unlicensed FM
broadcast stereo transmission. Users must comply with local radio
frequency (RF) transmission regulations.
6
11 VDD
7
8
9
10
Functional Block Diagram
Patents pending
Notes:
1. To ensure proper operation and FM
transceiver performance, follow the
guidelines in “AN383: 3 mm x 3 mm
QFN Universal Layout Guide.”
Silicon Laboratories will evaluate
schematics and layouts for qualified
customers.
2. Place the Si4720/21 as close as
possible to the antenna jack, and
keep the FMI trace as short as
possible.
Si4720/21
Tx/Rx Ant
TXO
LIN/DFS
L1
120 nH
RIN/DOUT
ROUT/DIN
Rx Ant*
ADC
ADC
DAC
DAC
FMI
LNA
AGC
PGA
AFC
DSP
RFGND
VDD
LOUT/DFS
2.7–5.5 V
CONTROL
INTERFACE
LDO
GPO
C1 GND
22 uF
*Note: Dedicated Rx antenna is optional
Rev. 1.0 2/08
Copyright © 2008 by Silicon Laboratories
Si4720/21-B20
.
Si4720/21-B20
2
Rev. 1.0
Si4720/21-B20
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.1. Test Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.2. Test Circuit Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1. Analog Audio Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2. Typical Application Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.3. Digital Audio Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.4. Typical Application Schematic Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4. Universal AM/FM RX/FM TX Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1. Universal AM/FM RX/FM TX Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.2. Application Schematics and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.4. Integrated Antenna Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.5. Receiver Digital Audio Interface (Si4721 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.6. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.7. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.8. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.9. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.10. RDS/RBDS Processor (Si4721 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.11. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.12. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.13. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.14. FM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.15. Receive Power Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.16. Transmitter Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.17. Line Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.18. Audio Dynamic Range Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.19. Audio Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.20. Pre-emphasis and De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.21. RDS/RBDS Processor (Si4721 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.22. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.23. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.24. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.25. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.26. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.27. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7. Pin Descriptions: Si4720/21-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Rev. 1.0
3
Si4720/21-B20
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
9.1. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
9.2. Si4720/21 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
9.3. Si4721 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
10. Package Outline: Si4720/21-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
11. PCB Land Pattern: Si4720/21-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
12. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4
Rev. 1.0
Si4720/21-B20
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol Test Condition
Min
2.7
1.5
10
Typ
—
Max
5.5
3.6
—
Unit
V
Supply Voltage
V
DD
Interface Supply Voltage
V
—
V
IO
DDRISE
Power Supply Power-Up Rise Time
Interface Power Supply Power-Up Rise Time
Ambient Temperature
V
—
µs
µs
C
V
10
—
—
IORISE
T
–20
25
85
A
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Supply Voltage
Symbol
Value
–0.5 to 5.8
–0.5 to 3.9
10
Unit
V
V
DD
Interface Supply Voltage
V
V
IO
IN
3
Input Current
I
mA
V
3
Input Voltage
V
T
–0.3 to (V + 0.3)
IN
IO
Operating Temperature
Storage Temperature
–40 to 95
–55 to 150
0.4
C
C
OP
T
STG
4
RF Input Level
V
PK
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended
operating conditions for extended periods may affect device reliability.
2. The Si4720/21 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2/INT, and GPO3.
4. At RF input pin FMI.
Rev. 1.0
5
Si4720/21-B20
Table 3. DC Characteristics
Parameter
FM Receiver
Symbol
Test Condition
Min
Typ
Max
Unit
RX Supply Current
I
I
—
—
—
—
—
19.2
19.8
320
22
23
mA
mA
µA
RX
1
RX Supply Current
Low SNR level
RX
RX Interface Supply Current
I
600
23
IORX
2
RX RDS Supply Current
I
Analog Output Mode
Digital Output Mode
19.9
18.0
mA
mA
FM
2
RX Supply Current
I
20.5
FMD
FM Transmitter
TX Supply Current
I
—
—
18.8
320
22.8
600
mA
µA
TX
TX Interface Supply Current
I
IOTX
FM Transmitter from Digital Audio Input
TX Supply Current
I
DCLK = 3.072 MHz
DCLK = 3.072 MHz
—
—
18.3
320
—
—
mA
µA
DTX
TX Interface Supply Current
I
DIO
FM Transmitter in Receive Power Scan Mode
RX Supply Current
I
—
—
16.8
400
—
—
mA
µA
RX
RX Interface Supply Current
Supplies and Interface
I
IORPS
V
V
Powerdown Current
Powerdown Current
I
Powerdown mode
—
—
10
3
20
10
µA
µA
DD
DDPD
I
SCLK, RCLK inactive
Powerdown mode
IO
IOPD
3
High Level Input Voltage
V
0.7 x V
–0.3
–10
—
—
—
—
—
—
VIO + 0.3
V
V
IH
IO
3
Low Level Input Voltage
High Level Input Current
V
0.3 x V
10
IL
IO
3
I
V
= V = 3.6 V
µA
µA
V
IH
IN
IO
3
Low Level Input Current
I
V
= 0 V, V = 3.6 V
–10
10
IL
IN
IO
4
High Level Output Voltage
V
I
= 500 µA
0.8 x VIO
—
—
OH
OUT
OUT
4
Low Level Output Voltage
V
I
= –500 µA
0.2 x V
V
OL
IO
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2/INT, and GPO3.
4. For output pins SDIO, GPO1, GPO2/INT, and GPO3.
6
Rev. 1.0
Si4720/21-B20
Table 4. Reset Timing Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
100
30
Typ
—
Max
—
Unit
µs
RST Pulse Width and GPO1, GPO2/INT Setup to RST
GPO1, GPO2/INT Hold from RST
Important Notes:
t
SRST
t
—
—
ns
HRST
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.
tHRST
tSRST
70%
30%
RST
70%
30%
GPO1
70%
30%
GPO2/
INT
Figure 1. Reset Timing Parameters for Busmode Select
Rev. 1.0
7
Si4720/21-B20
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
0
Typ
—
Max
400
—
Unit
kHz
µs
SCLK Frequency
SCLK Low Time
SCLK High Time
f
SCL
t
1.3
0.6
0.6
—
LOW
t
—
—
µs
HIGH
SCLK Input to SDIO Setup
t
t
—
—
µs
SU:STA
(START)
SCLK Input to SDIO Hold (START)
SDIO Input to SCLK Setup
0.6
100
0
—
—
—
—
—
—
—
—
µs
ns
ns
µs
µs
ns
HD:STA
SU:DAT
t
t
4,5
SDIO Input to SCLK Hold
900
—
HD:DAT
SU:STO
SCLK input to SDIO Setup (STOP)
STOP to START Time
t
0.6
1.3
t
—
BUF
SDIO Output Fall Time
t
250
f:OUT
Cb
-----------
20 + 0.1
1 pF
SDIO Input, SCLK Rise/Fall Time
t
t
—
300
ns
f:IN
r:IN
Cb
-----------
1 pF
20 + 0.1
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
C
—
—
—
—
50
50
pF
ns
b
t
SP
1. When VIO = 0 V, SCLK and SDIO are low-impedance. 2-wire control interface is I2C compatible.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4720/21 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.
8
Rev. 1.0
Si4720/21-B20
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
SCLK
SDIO
70%
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tr:IN
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
SDIO
A6-A0,
R/W
D7-D0
D7-D0
START
ADDRESS + R/W
ACK
DATA
ACK
DATA
ACK
STOP
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
Rev. 1.0
9
Si4720/21-B20
Table 6. 3-Wire Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
SCLK Frequency
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
f
CLK
SCLK High Time
t
25
25
20
10
10
2
HIGH
SCLK Low Time
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
SEN Input to SCLKHold
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
—
ns
S
t
—
ns
HSDIO
t
—
ns
HSEN
t
Read
Read
25
25
10
ns
CDV
t
2
ns
CDZ
t , t
—
ns
R
F
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHSDIO
tHIGH
tLOW
tHSEN
tS
70%
30%
tS
SEN
A6-A5,
R/W,
A4-A1
70%
30%
A7
A0
D15
D14-D1
D0
SDIO
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
70%
30%
SCLK
SEN
tHSDIO
tCDV
tHSEN
tS
tCDZ
70%
30%
tS
70%
30%
A6-A5,
R/W,
A4-A1
A7
A0
D15
D14-D1
D0
SDIO
½ Cycle Bus
Turnaround
Address In
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
10
Rev. 1.0
Si4720/21-B20
Table 7. SPI Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
0
Typ
—
—
—
—
—
—
—
—
—
Max
2.5
—
Unit
MHz
ns
SCLK Frequency
f
CLK
SCLK High Time
t
25
25
15
10
5
HIGH
SCLK Low Time
t
—
ns
LOW
SDIO Input, SEN to SCLKSetup
SDIO Input to SCLKHold
SEN Input to SCLKHold
SCLKto SDIO Output Valid
SCLKto SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
t
—
ns
S
t
—
ns
HSDIO
t
—
ns
HSEN
t
Read
Read
2
25
25
10
ns
CDV
t
2
ns
CDZ
t
t
—
ns
R, F
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
70%
SCLK
30%
tR
tF
tHIGH
tLOW
tHSDIO
tHSEN
70%
30%
tS
SEN
tS
70%
30%
C7
C6–C1
C0
D7
D6–D1
D0
SDIO
Control Byte In
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
70%
30%
SCLK
tCDV
tS
tHSEN
tHSDIO
70%
30%
tS
SEN
tCDZ
70%
30%
SDIO
C7
C6–C1
C0
D7
D6–D1
D0
16 Data Bytes Out
(SDIO or GPO1)
Bus
Turnaround
Control Byte In
Figure 7. SPI Control Interface Read Timing Parameters
Rev. 1.0
11
Si4720/21-B20
Table 8. Digital Audio Interface Characteristics (Receive)
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition
Min
26
10
10
5
Typ
—
Max
1000
—
Unit
ns
DCLK Cycle Time
t
DCT
DCH
DCLK pulse width high
t
—
ns
DCLK pulse width low
t
—
—
ns
DCL
DFS set-up time to DCLK rising edge
DFS hold time from DCLK rising edge
DOUT propagation delay from DCLK falling edge t
t
—
—
ns
SU:DFS
HD:DFS
t
5
—
—
ns
0
—
12
ns
PD:DOUT
tDCH
tDCL
DCLK
DFS
tDCT
tHD:DFS
tSU:DFS
DOUT
tPD:OUT
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
12
Rev. 1.0
Si4720/21-B20
Table 9. FM Receiver Characteristics1,2
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
76
Typ
—
Max
108
3.5
Unit
MHz
Input Frequency
f
RF
Sensitivity with Headphone Net-
(S+N)/N = 26 dB
(S+N)/N = 26 dB
—
2.2
µV EMF
3,4,5
work
3,4,5,6
Sensitivity with 50 Network
—
—
1.1
15
—
—
µV EMF
µV EMF
6
RDS Sensitivity
f = 2 kHz,
RDS BLER < 5%
6
TXO Receiver Mode Sensitivity
—
3
3.5
4
—
5
µV EMF
6,7
LNA Input Resistance
k
6,7
LNA Input Capacitance
4
5
6
pF
6,8
Input IP3
100
40
35
60
35
72
—
—
15
25
55
—
—
70
45
10
105
50
50
70
—
80
—
—
—
—
63
58
0.1
75
50
—
—
—
—
—
—
90
1
dBµV EMF
3,4,6,7
m = 0.3
±200 kHz
±400 kHz
In-band
dB
dB
dB
dB
AM Suppression
Adjacent Channel Selectivity
Alternate Channel Selectivity
6
Spurious Response Rejection
3,4,7
mV
Audio Output Voltage
RMS
3,7,9
dB
Hz
kHz
dB
dB
dB
%
Audio Output L/R Imbalance
Audio Frequency Response Low
6
–3 dB
–3 dB
30
—
—
—
—
0.5
80
54
—
6
Audio Frequency Response High
7,9
Audio Stereo Separation
3,4,5,7,10
Audio Mono S/N
4,5,7,10,11
Audio Stereo S/N
3,7,9
Audio THD
6
De-emphasis Time Constant
FM_DEEMPHASIS = 2
FM_DEEMPHASIS = 1
Single-ended
µs
µs
6,10
R
k
Audio Output Load Resistance
L
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f = 2 x f – f . AGC is disabled. Refer to "7. Pin Descriptions: Si4720/21-GM" on page 41.
0
1
2
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. At temperature 25 °C.
Rev. 1.0
13
Si4720/21-B20
Table 9. FM Receiver Characteristics1,2 (Continued)
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
—
Typ
—
Max
50
Unit
pF
6,10
C
Single-ended
Audio Output Load Capacitance
L
6
Seek/Tune Time
RCLK tolerance
= 100 ppm
—
—
80
ms/channel
6
Powerup Time
From powerdown
—
—
—
110
3
ms
dB
12
RSSI Offset
Input levels of 8 and
60 dBµV at RF Input
–3
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f = 2 x f – f . AGC is disabled. Refer to "7. Pin Descriptions: Si4720/21-GM" on page 41.
0
1
2
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. At temperature 25 °C.
14
Rev. 1.0
Si4720/21-B20
Table 10. FM Transmitter Characteristics1
Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, 75 µs pre-emphasis,
unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
Parameters are tested in production unless otherwise specified.
Parameter
Symbol
Test Condition
Min
76
Typ
—
Max
108
3.5
Unit
MHz
kHz
2
Transmit Frequency Range
f
RF
Transmit Frequency Accuracy and
–3.5
—
2,3
Stability
2
Transmit Voltage Accuracy
V
V
= 103–117 dBµV
= 102, 118 dBµV
–2.5
–2.5
—
—
—
2.5
2.5
dB
dB
RF
RF
Transmit Voltage Accuracy
Transmit Voltage Temperature Coef-
–0.075
–0.025
dB/°C
2
ficient
Transmit Channel Edge Power
Transmit Adjacent Channel Power
Transmit Alternate Channel Power
Transmit Emissions
> ±100 kHz,
pre-emphasis off
—
—
—
—
–20
–26
–26
dBc
dBc
dBc
> ±200 kHz,
pre-emphasis off
–30
–30
> ±400 kHz,
pre-emphasis off
In-band (76–108 MHz)
—
—
—
70
45
58
—
53
5
–30
—
dBc
pF
pF
µs
2
Output Capacitance Max
C
C
TUNE
TUNE
2
Output Capacitance Min
—
2
Pre-emphasis Time Constant
TX_PREMPHASIS = 75 µs
TX_PREMPHASIS = 50 µs
75
50
63
80
54
—
µs
2
Audio SNR Mono
f = 22.5 kHz, Mono,
dB
limiter off
Audio SNR Stereo
f = 22.5 kHz,
fpilot = 6.75 kHz, Stereo,
limiter off
53
—
58
—
dB
%
Audio THD Mono
f = 75 kHz, Mono,
0.1
0.5
limiter off
Notes:
1. FM transmitter performance specifications are subject to adherence to Silicon Laboratories guidelines in “AN383:
Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers. Tested with test schematic (L = 120 nH, Q > 30) shown in Figure 10 on page 19.
2. Guaranteed by characterization.
3. No measurable fRF/VDD at VDD of 500 mVpk-pk at 100 Hz to 10 kHz.
Rev. 1.0
15
Si4720/21-B20
Table 10. FM Transmitter Characteristics1 (Continued)
Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, 75 µs pre-emphasis,
unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
Parameters are tested in production unless otherwise specified.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
2
Audio THD Stereo
f = 22.5 kHz,
fpilot = 6.75 kHz, Stereo,
limiter off
—
0.1
0.5
%
2
Audio Stereo Separation
left channel only
30
40
—
—
30
35
50
—
—
—
—
—
dB
dB
ms
Sub Carrier Rejection Ratio
SCR
2
Powerup Settling Time
110
0.636
15 k
2
Input Signal Level
V
V
PK
AI
2
Frequency Flatness
Mono, ±1.5 dB,
f = 75 kHz, 0, 50, 75 µs
pre-emphasis, limiter off
Hz
Hz
Hz
2
High Pass Corner Frequency
Mono, –3 dB, f = 75 kHz,
0, 50, 75 µs pre-emphasis,
limiter off
5
—
—
30
2
Low Pass Corner Frequency
Mono, –3 dB, f = 75 kHz,
0, 50, 75 µs pre-emphasis,
limiter off
15 k
16 k
Audio Imbalance
Mono
–1
—
—
1
dB
%
2
Pilot Modulation Rate Accuracy
f = 68.25 kHz,
–10
10
fpilot = 6.75 kHz, Stereo
2
Audio Modulation Rate Accuracy
f = 68.25 kHz,
–10
—
10
%
fpilot = 6.75 kHz, Stereo
2
Input Resistance
LIATTEN[1:0] = 11
50
—
—
60
10
54
—
—
—
k
pF
2
Input Capacitance
Received Noise Level Accuracy
60 dBµV input, T = 25 ºC
dBuV
A
2
(Si4720/21 Only)
Notes:
1. FM transmitter performance specifications are subject to adherence to Silicon Laboratories guidelines in “AN383:
Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers. Tested with test schematic (L = 120 nH, Q > 30) shown in Figure 10 on page 19.
2. Guaranteed by characterization.
3. No measurable fRF/VDD at VDD of 500 mVpk-pk at 100 Hz to 10 kHz.
16
Rev. 1.0
Si4720/21-B20
Table 11. Digital Audio Interface Characteristics (Transmit)
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
DCLK pulse width high
Symbol Test Condition
Min
10
10
5
Typ
—
Max
—
Unit
ns
t
DCH
DCLK pulse width low
t
—
—
ns
DCL
DFS set-up time to DCLK rising edge
DFS hold time from DCLK rising edge
DIN set-up time from DCLK rising edge
DIN hold time from DCLK rising edge
t
t
—
—
ns
SU:DFS
HD:DFS
5
—
—
ns
t
5
—
—
ns
SU:DIN
t
5
—
—
ns
HD:DIN
t
t
R
—
—
—
10
ns
DCLK, DFS, DIN, Rise/Fall time
F
1,2
1.0
40.0
MHz
DCLK Tx Frequency
Notes:
1. Guaranteed by characterization.
2. The DCLK frequency may be set below the minimum specification if DIGITAL_INPUT_SAMPLE_RATE is first set to 0
(disable).
DCLK
tR
tF
tHD:DFS
tSU:DFS
DFS
DIN
tSU:DIN
tHD:DIN
Figure 9. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.0
17
Si4720/21-B20
Table 12. FM Receive Power Scan Characteristics1
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Tune and Signal Strength Measurement
Time per Channel
—
—
80
ms
2
Notes:
1. Settling time for ac coupling capacitors on the audio input pins after Receive to Transmit transition can take a few
hundred milliseconds. The actual settling time depends on the values of the ac-coupling capacitors. Using digital audio
input mode avoids this settling time.
2. Guaranteed by characterization.
Table 13. Reference Clock and Crystal Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock
1
RCLK Supported Frequencies
31.130
–50
1
32.768
—
40,000
50
kHz
2
RCLK Frequency Tolerance
ppm
REFCLK_PRESCALE
—
4095
REFCLK
31.130
32.768
34.406
kHz
Crystal Oscillator
Crystal Oscillator Frequency
—
–100
—
32.768
—
—
kHz
ppm
pF
2
Crystal Frequency Tolerance
100
3.5
Board Capacitance
—
Notes:
1. The Si4720/21 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. See “AN332: Si4704/05/06/1x/2x/3x/4x FM
Transmitter/AM/FM/SW/LW/WB Receiver Programming Guide” for more details.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.
18
Rev. 1.0
Si4720/21-B20
2. Test Circuit
2.1. Test Circuit Schematic
C2
VIO
0.47 µF
LIN
RIN
C3
0.47 µF
1
2
3
4
5
15
14
13
12
11
NC
RIN
LOUT
ROUT
GND
VDD
FMI
FMI
TX Antenna
C4
LOUT
ROUT
U1
Si4720/21
RFGND
TXO
RST
2 pF
L1
120 nH
VBATTERY
2.7 to 5.5 V
VTXOUT
C1
22 nF
50
R1
RST
SEN
SCLK
SDIO
RCLK
X1
RCLK
VIO
1.5 to 3.6 V
C5
C6
Notes:
1. Si4720/21 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the guidelines in
“AN383: 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. LIN, RIN line inputs must be ac-coupled.
Figure 10. Test Circuit Schematic
2.2. Test Circuit Bill of Materials
Table 14. Si4720/21 Test Circuit Bill of Materials
Component(s)
C1
Value/Description
Supply bypass capacitor, 22 nF, 20%, Z5U/X7R
AC Coupling Capacitor, 0.47 µF
Supplier(s)
Murata
Murata
AVX
C2, C3
C4
2 pF, ±.05 pF, 06035JZR0AB
C5, C6
Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
Venkel
L1
R1
X1
U1
120 nH inductor, Qmin = 30
49.9 , 5%
Murata
Murata
32.768 kHz crystal (Optional: for crystal oscillator option)
Si4720/21 FM Radio Transceiver
Epson
Silicon Laboratories
Rev. 1.0
19
Si4720/21-B20
3. Typical Application Schematic
3.1. Analog Audio Inputs/Outputs
C2
VIO
0.47 µF
LIN
RIN
C3
0.47 µF
1
15
14
13
12
11
NC
RIN
LOUT
ROUT
GND
VDD
RX Antenna
TX/RX Antenna
2
3
4
5
FMI
LOUT
ROUT
U1
Si4720/21
RFGND
TXO
RST
L1
120 nH
VBATTERY
2.7 to 5.5 V
C1
22 nF
RST
SEN
SCLK
SDIO
RCLK
X1
RCLK
VIO
1.5 to 3.6 V
C4
C5
Notes:
1. Si4720/21 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the guidelines in
“AN383: 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. LIN, RIN line inputs must be ac-coupled.
5. Dedicated RX antenna at FMI input optional.
Figure 11. Analog Audio Inputs/Outputs (LIN, RIN, LOUT, ROUT
)
3.2. Typical Application Bill of Materials
Table 15. Si4720/21 Typical Application Bill of Materials
Component(s)
C1
Value/Description
Supplier(s)
Murata
Supply bypass capacitor, 22 nF, 20%, Z5U/X7R
AC Coupling Capacitor, 0.47 µF
C2, C3
Murata
C4, C5
Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
Venkel
L1
X1
U1
120 nH inductor, Qmin = 30
32.768 kHz crystal (Optional: for crystal oscillator option)
Si4720/21 FM Radio Transceiver
Murata
Epson
Silicon Laboratories
20
Rev. 1.0
Si4720/21-B20
3.3. Digital Audio Inputs/Outputs
R1
VIO
DCLK
DFS
DOUT
DFS
R2
DIN
1
15
14
13
12
11
NC
DOUT
DFS
DIN
R3
RX Antenna
TX/RX Antenna
2
3
4
5
FMI
U1
Si4720/21
RFGND
TXO
GND
VDD
RST
L1
120 nH
VBATTERY
C1
2.7 to 5.5 V
22 nF
RST
SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V
Notes:
1. Si4720/21 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the
guidelines in “AN383: Si47xx 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. Dedicated RX antenna at FMI input optional.
Figure 12. Digital Audio Inputs (DIN, DFS, DCLK)
3.4. Typical Application Schematic Bill of Materials
Table 16. Si4720/21 Bill of Materials
Component(s)
Value/Description
Supply bypass capacitor, 22 nF, 20%, Z5U/X7R
AC Coupling Capacitor, 0.47 µF
120 nH inductor, Qmin = 30
2 k Resistor
Supplier(s)
Murata
C1
C2, C3
L1
Murata
Murata
R1, R2
R3
Any
600 Resistor
Any
U1
Si4720/21 FM Radio Transceiver
Silicon Laboratories
Rev. 1.0
21
Si4720/21-B20
4. Universal AM/FM RX/FM TX Application Schematic
Figure 13 shows an application schematic that supports the Si47xx family of 3 mm x 3 mm QFN products,
including the Si4702/3/4/5 FM receivers, Si471x FM transmitters, Si472x FM transceivers, and Si473x AM/FM
receivers.
FB1
2.5 k @ 100 MHz
R 2
T 5
S 1
Right
Audio
U2
Headphone Amplifier
Left
Audio
FB2
2.5 k @ 100 MHz
Si4702/03: Populate R12, R13, R21, C14, and C15
Si4704/05/1x/2x/3x Analog: Populate C7, C8, C14
and C15 as shown
Si4704/05/1x/2x/3x Digital: Populate R16, R17,
R18, R19, and R20 as shown
J1 HP Jack
R16
2 k
VBATTERY
2.7 to 5.5 V
System Component
GPIO3
GPIO2
GPIO1
C4
1 nF
LHEADPHONE
270 nH
R13
0
C7/R17
0.39 uF/ 2 k
LIN
System Component
FM Embedded RX/TX Antenna
RIN
R12
0
C8/R18
0.39 uF/ 600
R14
L1
D3
0
10 nH
C14/R19
0.39 uF/ 0
C17/R21
3.3pF/0
D4
1
2
3
4
5
15
14
13
12
11
LSHORT
NC
GND/RIN/DOUT
120 nH
FMI
LOUT/DFS
ROUT/DIN
GND
U1
Si47xx
RFGND
TXO/AMI
RST
System Component
C15/R20
System Component
0.39 uF/ 0
VDD
AM Ferrite Antenna
VBATTERY
2.7 to 5.5 V
System Components
C1
22 nF
LFERRITE
180–
600 uH
C16
470 nF
D5
RST
SEN
SCLK
SDIO
RCLK
VIO
Figure 13. Universal AM/FM RX/FM TX Application Schematic
Following the schematic and layout recommendations detailed in “AN383: Universal Antenna Selection and Layout
Guidelines” will result in optimal performance with the minimal application schematic shown in Figure 13. “Universal
AM/FM RX/FM TX Application Schematic”. System components are those that are likely to be present for any tuner
or transmitter design.
22
Rev. 1.0
Si4720/21-B20
4.1. Universal AM/FM RX/FM TX Bill of Materials
The bill of materials for the expanded application schematic shown in Figure 13 is provided in Table 17. Refer to
the individual device layout guides and antenna interface guides for a discussion of the purpose of each
component.
Table 17. Universal AM/FM/RX/FM TX Bill of Materials
Designator
Description
Note
C1
U1
Supply bypass capacitor, 22 nF, 10%, Z5U/X7R, 0402
Silicon Laboratories Si47xx, 3 mm x 3 mm, 20 pin, QFN
R12, R13, R19, 0 jumper, 0402
R12, R13, and R21 for
Si4702/03 Only
R20, R21
C16
AM antenna ac coupling capacitor, 470 nF, 20%, Z5U/X7R
AM Ferrite Antenna
AM Ferrite Antenna
LFERRITE AM Ferrite loop stick, 180–600 µH
FB1,FB2
Ferrite bead, 2.5 k @ 100 MHZ, 0603, Murata BLM18BD252SN1D Headphone Antenna
LHEADPHONE Headphone antenna matching inductor, 270 nH, 0603, Q>15, Murata Headphone Antenna
LQW18ANR27J00D
LSHORT
Embedded antenna matching inductor, 120 nH, 0603, Q>30, Murata Embedded Antenna
LQW18ANR12J00D
R14
C2
Embedded antenna jumper, 2.2 , 0402
Optional
Optional
Optional
Supply bypass capacitor, 22 nF, 10%, Z5U/X7R, 0402
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R, 0402
C3
C5, C6
R7-R11
C12, C13
X1
Headphone amp output shunt capacitor, 100 pF, 10%, Z5U/X7R, 0402 Optional
Current limiting resistor, 20 –2 k, 0402
Optional
Crystal load capacitor, 22 pF, 5%, COG
Optional
Crystal, Epson FC-135
Optional
C7, C8
D1-D5
C11
Si47xx input ac coupling capacitor, 0.39 µF, X7R/X5R, 0402
ESD Diode, SOT23-3, California Micro Devices CM1214-01ST
Supply bypass capacitor, 100 nF, 10%, Z5U/X7R, 0402
System Component
System Component
Headphone Amplifier
C4
Headphone antenna ac coupling capacitor, 1 nF, 10%, Z5U/X7R, 0402 Headphone Antenna
Headphone amp output ac coupling capacitor, 125 uF, X7R, 0805 Headphone Amplifier
Headphone amp input ac coupling capacitor, 0.39 µF, X7R/X5R, 0402 Headphone Amplifier
C9, C10
C14, C15
R1,R2,R3,R4 Headphone amp feedback/gain resistor, 20 k, 0402
Headphone Amplifier
Headphone Amplifier
Headphone Amplifier
System Component
System Component
R5, R6
U2
Headphone amp bleed resistor, 100 k, 0402
Headphone amplifier, National Semiconductor, LM4910MA
Current limiting resistor, 2 k0402
R16, R17
R18
Current limiting resistor, 600 , 0402
L1
VCO filter inductor, 10 nH, 0603, Q30, Murata, LQW18ANR01J00D Optional
C17
VCO filter capacitor, 3.3 pF, 0402, COG, Venkel,
C0402COG2503R3JN
Optional
Rev. 1.0
23
Si4720/21-B20
5. Functional Description
5.1. Overview
Si4720
Tx/Rx Ant
TXO
LIN
L1
120 nH
RIN
Rx Ant*
FMI
ADC
ADC
DAC
DAC
ROUT
LNA
PGA
AFC
DSP
RFGND
AGC
LOUT
2.7–5.5 V
VDD
CONTROL
INTERFACE
LDO
GPO
C1 GND
22 uF
*Note: Dedicated Rx antenna is optional
Figure 14. Functional Block Diagram
The Si4720/21 is the first single-chip FM radio bypass capacitor, and a PCB space of approximately
2
transceiver. The proven and patented digital 15 mm . The Si4720/21 is layout compatible with
architecture of the Si4720/21 combines the functionality Silicon Laboratories' Si470x FM radio receivers, Si473x
of the Si470x FM radio receiver with the Si471x FM AM/FM radio receivers, and the Si471x FM radio
transmitter, offering full FM receive and transmit transmitter solutions, allowing a single PCB layout to
capabilities in a single, ultra-small 3x3x0.55 mm QFN accommodate a variety of music features. High yield
package. The device leverages Silicon Laboratories’ manufacturability, unmatched performance, easy
highly successful and proven FM technology and offers design-in, and software programmability are key
unmatched integration and performance. FM receiver advantages of the Si4720.
and transmit functionality may be added to any portable
The Si4720/21’s integrated receive power scan function
device by using this single chip. As with the Si470x and
shares the same antenna as the transmitter allowing for
Si471x products, the Si4720/21 offers industry leading
a compact printed circuit board design. The device
size, performance, low power consumption, and ease of
operates in half duplex mode, meaning the transmitter
and receiver do not operate at the same time.
use.
The Si4720/21 is the first FM radio transceiver
The Si4720/21 performs FM modulation in the digital
integrated circuit to support a small loop antenna, which
domain to achieve high fidelity, optimal performance
can be integrated into the enclosure or PCB of a
versus power consumption, and flexibility of design. The
portable device. This feature enables applications that
onboard DSP provides modulation adjustment and
also include Bluetooth functionality to perform FM radio
audio dynamic range control for optimum sound quality.
reception without cables. For portable navigation
The Si4721 supports the European Radio Data System
devices, the Si4720’s antenna architecture permits
(RDS) and the US Radio Broadcast Data System
integration of the traffic messaging antenna into the
(RBDS) including all the symbol encoding, block
enclosure of the portable device, and eliminates the
synchronization, and error correction functions. Using
need for external antenna cables.
this feature, the Si4721 enables data such as artist
The Si4720's digital integration reduces the required
name and song title to be transmitted to an RDS/RBDS
external components of traditional offerings, resulting in
receiver.
a solution requiring only an external inductor and
24
Rev. 1.0
Si4720/21-B20
The transmit output (TXO) connects directly to the The Si4720/21 reference clock is programmable,
transmit antenna with only one external inductor to supporting many RCLK inputs as shown in Table 10.
provide harmonic filtering. The output is programmable
The S4720/21 are part of a family of broadcast audio
over a 10 dB voltage range in 1 dB steps. The TXO
solutions offered in standard, 3 x 3 mm 20-pin QFN
output pin can also be configured for loop antenna
packages. All solutions are layout compatible, allowing
support. Users are responsible for complying with local
a single PCB to accommodate various feature offerings.
regulations on RF transmission (FCC, ETSI, ARIB,
The Si4720/21 includes line inputs to the on-chip
etc.).
analog-to-digital converters (ADC), a programmable
The digital audio interface operates in slave mode and
reference clock input, and a configurable digital audio
2
supports a variety of MSB-first audio data formats
interface. The chip supports I C-compliant 2-wire, 8-bit
2
including I S and left-justified modes. The interface has
SPI, and a 3-wire control interface.
three pins: digital data input (DIN), digital frame
5.2. Application Schematics and Operating
Modes
synchronization input (DFS), and
a
digital bit
synchronization input clock (DCLK). The Si4720/21
supports a number of industry-standard sampling rates
including 32, 40, 44.1, and 48 kHz. The digital audio
interface enables low-power operation by eliminating
the need for redundant DACs and ADCs on the audio
baseband processor.
The application schematic for the Si4720/21 is shown in
Section "3. Typical Application Schematic" on page 20.
The Si4720/21 supports selectable analog, digital, or
concurrent analog and digital audio output modes. In
the analog output mode, pin 13 is ROUT, pin 14 is
LOUT, and pin 17 is GPO3. In the digital output mode,
pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK.
Concurrent analog and digital audio output mode
requires pins 13, 14, 15, 16, and 17. In addition to
output mode, there is a clocking mode to clock the
Si4720/21 from a reference clock or crystal oscillator.
The user sets the operating modes with commands as
described in Section "6. Commands and Properties" on
page 36.
The Si4720/21 includes a low-noise stereo line input
(LIN/RIN) with programmable attenuation. To ensure
optimal audio performance, the Si4720/21 has a
transmit line input property that allows the user to
specify the peak amplitude of the analog input required
to reach maximum deviation level. The deviation levels
of the audio, pilot, and RDS/RBDS signals can be
independently programmed to customize FM transmitter
designs. The Si4720/21 has a programmable low audio
level and high audio level indicators that allows the user
to selectively enable and disable the carrier based on
the presence of audio content. In addition, the device
provides an overmodulation indicator to allow the user
to dynamically set the maximum deviation level. The
Si4720/21 has a programmable audio dynamic range
control that can be used to reduce the dynamic range of
the audio input signal and increase the volume at the
receiver. These features can dramatically improve the
end user’s listening experience.
5.3. FM Receiver
The Si4720/21 FM receiver is based on the proven
Si4700/01/02/03 FM radio receiver. The part leverages
Silicon Laboratories' proven and patented Si4700/01 FM
broadcast radio receiver digital architecture, delivering
superior RF performance and interference rejection. The
proven digital techniques provide excellent sensitivity in
weak signal environments while providing superb
selectivity and inter-modulation immunity in strong signal
environments.
The Si4720/21 is reset by applying a logic low on the
RST pin. This causes all register values to be reset to
their default values. The digital input/output interface
The FM receiver supports the worldwide FM broadcast
band (76 to 108 MHz) with channel spacings of 50–
200 kHz. The Low-IF architecture utilizes a single
converter stage and digitizes the signal using a high-
resolution analog-to-digital converter. The resulting
digital signals are further processed through an on-chip
DSP for digital channel selection, FM demodulation, and
ultimately stereo audio output. The audio output can be
directed either to an external headphone amplifier via
analog in/out or to other system ICs through digital audio
supply (V ) provides voltage to the RST, SEN, SDIO,
IO
RCLK, DIN, DFS, and DCLK pins and can be connected
to the audio baseband processor's supply voltage to
save power and remove the need for voltage level
translators. RCLK is not required for register operation.
2
interface (I S).
Rev. 1.0
25
Si4720/21-B20
5.4. Integrated Antenna Support
5.5. Receiver Digital Audio Interface
(Si4721 Only)
The Si4720/21 is the first FM receiver to support the fast
growing trend to integrate the FM receiver antenna into
the device enclosure. The chip is designed with this
function in mind from the outset, with multiple
international patents pending, thus it is superior to many
other options in price, board space, and performance.
The digital audio interface operates in slave mode and
supports three different audio data formats:
2
I S
Left-Justified
DSP Mode
The Si4720/21 supports an internal RX antenna
allowing for "wire free" listening to FM over Bluetooth.
The user can receive FM over the integrated RX
antenna and stream it via Bluetooth to a Bluetooth-
enabled headset.
5.5.1. Audio Data Formats
2
In I S mode, by default the MSB is captured on the
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
Testing indicates that using Silicon Laboratories'
patented techniques provides FM performance over an
integrated antenna that can be very similar in many key
metrics to performance using standard FM receive
antennas (e.g., wired headset). Refer to “AN383:
Antenna Selection and Universal Layout Guidelines” for
additional details on the implementation of support for
an integrated antenna.
In Left-Justified mode, by default the MSB is captured
on the first rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is high, and the right channel is
transferred when the DFS is low.
Figure 15 shows a conceptual block diagram of the
Si4720/21 architecture used to support the short
antenna. The headphone/dedicated FM receive
antenna is therefore optional. Host software can detect
the presence of a headphone antenna and switch
between the integrated antenna if desired.
In DSP mode, the DFS becomes a pulse with a width of
1DCLK period. The left channel is transferred first,
followed right away by the right channel. There are two
options in transferring the digital audio data in DSP
mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
Headphone
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
Ant*
FMI
LNA
RFGND
AGC
Short/
Embedded
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
LPI
Ant
L1
120 nH
5.5.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs on the audio
baseband processor.
*Note: Dedicated RX antenna is optional.
Figure 15. Conceptual Block Diagram of the
Si4720/21 Short Antenna Support
26
Rev. 1.0
Si4720/21-B20
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
I2S
RIGHT CHANNEL
(OMODE = 0000)
1 DCLK
1 DCLK
n-2
DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 16. I2S Digital Audio Format
INVERTED
DCLK
(OFALL = 1)
(OFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
n-2
Left-Justified
(OMODE = 0110)
DOUT
1
2
3
n-2
n-1
n
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 17. Left-Justified Digital Audio Format
(OFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DOUT
1
2
3
2
n-1
n
(OMODE = 1100)
(OMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2nd rising edge)
MSB
LSB
MSB
LSB
Figure 18. DSP Digital Audio Format
5.6.1. Stereo Decoder
5.6. Stereo Audio Processing
The
Si4720/21's
integrated
stereo
decoder
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961, and is used worldwide. Today's
MPX signal format consists of left + right (L+R) audio,
left – right (L–R) audio, a 19 kHz pilot tone, and
RDS/RBDS data as shown in Figure 19 below.
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The Si4721 uses frequency information from the 19 kHz
stereo pilot to recover the 57 kHz RDS/RBDS signal.
Mono Audio
5.6.2. Stereo-Mono Blending
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Stereo/mono status can be
monitored with the FM_RSQ_STATUS command. Mono
0
15 19 23
38
53 57
Frequency (kHz)
operation
can
be
forced
with
the
Figure 19. MPX Signal Spectrum
FM_BLEND_MONO_THRESHOLD property.
Rev. 1.0
27
Si4720/21-B20
during reception. The tuning frequency can be directly
programmed using the FM_TUNE_FREQ and
command. The Si4720/21 supports channel spacing of
50, 100, or 200 kHz in FM receiver mode.
5.7. De-Emphasis
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
5.12. Seek
transmitted,
a
pre-emphasis filter is applied to
Seek tuning will search up or down for a valid channel.
Valid channels are found when the receive signal
strength indicator (RSSI) and the signal-to-noise ratio
(SNR) values exceed the set threshold. Using the SNR
qualifier rather than solely relying on the more
traditional RSSI qualifier can reduce false stops and
increase the number of valid stations detected. Seek is
initiated using the FM_SEEK_START command. The
RSSI and SNR threshold settings are adjustable using
properties (see Table 15).
accentuate the high audio frequencies. The Si4720/21
incorporates a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The de-
emphasis time constant is programmable to 50 or 75 µs
and is set by the FM_DEEMPHASIS property.
5.8. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted. Volume is
adjusted digitally with the RX_VOLUME property.
Two seek options are available. The device will either
wrap or stop at the band limits. If the seek operation is
unable to find a channel, the device will indicate failure
and return to the channel selected before the seek
operation began.
5.9. Soft Mute
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
5.13. Reference Clock
conditions. The softmute attenuation level is adjustable The Si4720/21 reference clock is programmable,
using the FM_SOFT_MUTE_MAX_ATTENUATION supporting RCLK frequencies in Table 13. Refer to
property.
Table 3, “DC Characteristics,” on page 6 for switching
voltage levels and Table 9, “FM Receiver
Characteristics,” on page 13 for frequency tolerance
5.10. RDS/RBDS Processor (Si4721 Only)
The Si4721 implements an RDS/RBDS* processor for information.
symbol decoding, block synchronization, error
detection, and error correction.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "3. Typical Application
Schematic" on page 20. This mode is enabled using the
POWER_UP command. Refer to Table 21 "Si472x
Property Summary".
The Si4721 device is user configurable and provides an
optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
The Si4721 reports RDS decoder synchronization
status and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors or that the block checkword
contains errors.
The Si4720/21 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4720/21 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4720/21 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The seek/tune complete
(STC) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
5.11. Tuning
The frequency synthesizer uses Silicon Laboratories’
proven technology, including a completely integrated
VCO. The frequency synthesizer generates the
quadrature local oscillator signal used to downconvert
the RF input to a low intermediate frequency. The VCO
frequency is locked to the reference clock and adjusted
with an automatic frequency control (AFC) servo loop
28
Rev. 1.0
Si4720/21-B20
frequency deviation of 75 kHz corresponds to 100
percent modulation). Frequency deviation is related to
the amplitude of the MPX signal by a gain constant,
5.14. FM Transmitter
The transmitter (TX) integrates a stereo audio ADC to
convert analog audio signals to high fidelity digital
signals. Alternatively, digital audio signals can be
applied to the Si4720/21 directly to reduce power
consumption by eliminating the need to convert audio
K
, as given by the following equation:
VCO
f = KVCOAm
baseband signals to analog and back again to digital. where f is the frequency deviation; K
is the
VCO
Digital signal processing is used to perform the stereo voltage-to-frequency gain constant, and A is the
m
MPX encoding and FM modulation to a low digital IF. amplitude of the MPX message signal. For a fixed
Transmit baseband filters suppress out-of-channel
K
, the amplitude of all the subchannel signals within
VCO
noise and images from the digital low-IF signal. A the MPX message signal must be scaled to give the
quadrature single-sideband mixer up-converts the appropriate total frequency deviation.
digital IF signal to RF, and internal RF filters suppress
noise and harmonics to support the harmonic emission
requirements of cellular phones, GPS, WLAN, and other
wireless standards.
MPX Encoder
RDS(t)
L(t)
C2
C0
57 kHz
m(t)
The TXO output has over 10 dB of output level control,
programmable in approximately 1 dB steps. This large
output range enables a variety of antennas to be used
for transmit, such as a monopole stub antenna or a loop
antenna. The 1 dB step size provides fine adjustment of
the output voltage.
Frequency
Tripler
C1
C0
Frequency
Doubler
38 kHz
19 kHz
R(t)
The TXO output requires only one external 120 nH
inductor. The inductor is used to resonate the antenna
and is automatically calibrated within the integrated
circuit to provide the optimum output level and
frequency response for supported transmit frequencies.
Users are responsible for adjusting their system’s
radiated power levels to comply with local regulations
on RF transmission (FCC, ETSI, ARIB, etc.).
Figure 20. MPX Encoder
Figure 20 shows a conceptual block diagram of an MPX
encoder used to generate the MPX signal. L(t) and R(t)
denote the time domain waveforms from the left and
right audio channels, and RDS(t) denotes the time
domain waveform of the RDS/RBDS signal.
The MPX message signal can be expressed as follows:
5.15. Receive Power Scan
m(t) = C [L(t) + R(t)] + C cos(2
19 kHz)
38 kHz)
57 kHz)
0
1
The Si4720/21 is the industry’s first FM transmitter with
integrated receive functionality to measure received
signal strength. This has been designed to specifically
handle various antenna lengths including integrated
PCB antennas, wire antennas, and loop antennas,
allowing it to share the same antenna as the transmitter.
The receive function reuses the on-chip varactor from
the transmitter to optimize the receive signal power
applied to the front-end amplifier. Auto-calibration of the
varactor occurs with each tune command for consistent
performance across the FM band.
+ C [L(t) – R(t)] cos(2
0
+ C RDS(t) cos(2
2
where C , C , and C are gains used to scale the
0
1
2
amplitudes of the audio signals (L(t) ± R(t)), the 19 kHz
pilot tone, and the RDS subcarrier respectively, to
generate the appropriate modulation level. To achieve
the
modulation
levels
of
Figure 20
with
K
= 75 kHz/V, C would be set to 0.45; C would be
VCO
0
1
set to 0.1, and C would be set to 0.0267 giving a peak
2
audio frequency deviation of 0.9 x 75 kHz = 67.5 kHz, a
5.15.1. Stereo Encoder
peak
pilot
frequency
deviation
of
Figure 19 shows an example modulation level
breakdown for the various components of a typical MPX
signal.
0.1 x 75 kHz = 7.5 kHz, and a peak RDS frequency
deviation of 0.0267 x 75 kHz = 2.0025 kHz for a total
peak frequency deviation of 77.0025 kHz.
The total modulation level for the MPX signal shown in
Figure 19, assuming no correlation, is equal to the
arithmetic sum of each of the subchannel levels
resulting in 102.67 percent modulation or a peak
frequency deviation of 77.0025 kHz (an instantaneous
In the Si4720/21, the peak audio, pilot, and RDS
frequency deviations can be programmed directly with
the Transmit Audio, Pilot, and RDS Deviation
commands with an accuracy of 10 Hz. For the example
in Figure 20, the Transmit Audio Deviation is
Rev. 1.0
29
Si4720/21-B20
programmed with the value 6750, the Transmit Pilot In Left-Justified mode, the MSB is captured on the first
Deviation with 750, and the Transmit RDS Deviation rising edge of DCLK following each DFS transition. The
with 200, generating peak audio frequency deviations of remaining bits of the word are sent in order, down to the
67.5 kHz, peak pilot deviations of 7.5 kHz, and peak LSB. The Left Channel is transferred first when the DFS
RDS deviations of 2.0 kHz for a total peak frequency is high, and the Right Channel is transferred when the
deviation of 77 kHz. The total peak transmit frequency DFS is low.
deviation of the Si4720/21 can range from 0 to 100 kHz
In DSP mode, the DFS becomes a pulse with a width of
and is equal to the arithmetic sum of the Transmit
1 DCLK period. The Left Channel is transferred first,
Audio, Pilot, and RDS deviations. Users must comply
followed right away by the Right Channel. There are two
with local regulations on radio frequency transmissions.
options in transferring the digital audio data in DSP
Each of the individual deviations (transmit audio, pilot, mode: the MSB of the left channel can be transferred on
and RDS) can be independently programmed; however, the first rising edge of DCLK following the DFS pulse or
the total peak frequency deviation cannot exceed on the second rising edge.
100 kHz.
In all audio formats, depending on the word size, DCLK
The Si4720/21 provides an overmodulation indicator to frequency and sample rates, there may be unused
allow the user to dynamically set the maximum DCLK cycles after the LSB of each word before the next
deviation level. If the instantaneous frequency exceeds DFS transition and MSB of the next word.
the
deviation
level
specified
by
the
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
TX_AUDIO_DEVIATION property, the SQINT interrupt
bit (and optional interrupt) will be set.
5.16.2. Audio Sample Rates
5.16. Transmitter Digital Audio Interface
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
eliminating the need for redundant DACs and ADCs on
the audio baseband processor. The sampling rate is
selected using the DIGITAL_INPUT_SAMPLE_RATE
property.
The digital audio interface operates in slave mode and
supports 3 different audio data formats:
2
1. I S
2. Left-Justified
3. DSP Mode
5.16.1. Audio Data Formats
The device supports DCLK frequencies above 1 MHz.
After powerup the DIGITAL_INPUT_SAMPLE_RATE
property defaults to 0 (disabled). After DCLK is
2
In I S mode, the MSB is captured on the second rising
edge of DCLK following each DFS transition. The
remaining bits of the word are sent in order, down to the
LSB. The Left Channel is transferred first when the DFS
is low, and the Right Channel is transferred when the
DFS is high.
supplied,
property should be set to the desired audio sample rate
such as 32, 40, 44.1, or 48 kHz. The
the
DIGITAL_INPUT_SAMPLE_RATE
DIGITAL_INPUT_SAMPLE_RATE property must be set
to 0 before DCLK is removed or the DCLK frequency
drops below 1 MHz. A device reset is required if this
requirement is not followed.
INVERTED
(IFALL = 1)
DCLK
(IFALL = 0)
DCLK
DFS
LEFT CHANNEL
RIGHT CHANNEL
I2S
(IMODE = 0000)
1 DCLK
1 DCLK
n-2
DIN/DOUT
1
2
3
n-1
n
n-2
n-1
1
2
3
n
MSB
LSB
MSB
LSB
Figure 21. I2S Digital Audio Format
30
Rev. 1.0
Si4720/21-B20
INVERTED
DCLK
(IFALL = 1)
(IFALL = 0)
DCLK
DFS
LEFT CHANNEL
n-2
RIGHT CHANNEL
Left-Justified
(IMODE = 0110)
DIN/DOUT
1
2
3
n-1
n
n-2
n-1
n
1
2
3
MSB
LSB
MSB
LSB
Figure 22. Left-Justified Digital Audio Format
(IFALL = 0)
DCLK
DFS
RIGHT CHANNEL
n-2
LEFT CHANNEL
n-2
DIN/DOUT
1
2
3
2
n-1
n
(IMODE = 1100)
(IMODE = 1000)
1
2
3
2
n-1
n
(MSB at 1st rising edge)
MSB
LSB
MSB
LSB
LEFT CHANNEL
n-2
1 DCLK
RIGHT CHANNEL
n-2
DIN/DOUT
1
3
n-1
n
1
3
n-1
n
(MSB at 2nd rising edge)
MSB
LSB
MSB
LSB
Figure 23. DSP Digital Audio Format
The line attenuation code is chosen by picking the
lowest Peak Input Voltage in Table 18 that is just above
the expected peak input voltage coming from the audio
baseband processor. For example, if the expected peak
input voltage from the audio baseband processor is
400 mV, the user chooses LIATTEN[1:0] = 10 since the
Peak Input Voltage of 416 mV associated with
LIATTEN[1:0] = 10 is just greater than the expected
peak input voltage of 400 mV. The user also enters
400 mV into the LILEVEL[9:0] to associate this input
level to the maximum frequency deviation level
programmed into the audio deviation property. Note that
selecting a particular value of LIATTEN[1:0] changes
the input resistance of the LIN and RIN pins. This
feature is used for cases where the expected peak input
level exceeds the maximum input level of the LIN and
RIN pins.
5.17. Line Input
The Si4720/21 provides left and right channel line inputs
(LIN and RIN). The inputs are high-impedance and low-
capacitance, suited to receiving line level signals from
external audio baseband processors. Both line inputs
are low-noise inputs with programmable attenuation.
Passive and active anti-aliasing filters are incorporated
to prevent high frequencies from aliasing into the audio
band and degrading performance.
To ensure optimal audio performance, the Si4720/21
has a TX_LINE_INPUT_LEVEL property that allows the
user to specify the peak amplitude of the analog input
(LILEVEL[9:0]) required to reach the maximum
deviation level programmed in the audio deviation
property, TX_AUDIO_DEVIATION. A corresponding line
input attenuation code, LIATTEN[1:0], is also selected
by the expected peak amplitude level. Table 18 shows
the line attenuation codes.
The maximum analog input level is 636 mVpK. If the
analog input level from the audio baseband processor
exceeds this voltage, series resistors must be inserted
in front of the LIN and RIN pins to attenuate the voltage
such that it is within the allowable operating range. For
example, if the audio baseband's expected peak
Table 18. Line Attenuation Codes
LIATTEN[1:0]
Peak Input
Voltage [mV] Resistance [k]
RIN/LIN Input
amplitude is 900 mV and the V supply voltage is 1.8 V,
IO
00
01
10
11
190
301
416
636
396
100
74
the designer can use 30 k series resistors in front of
the LIN and RIN pins and select LIATTEN[1:0] = 11. The
resulting expected peak input voltage at the LIN/RIN
pins is 600 mV, since this is just a voltage divider
between the LIN/RIN input resistance (see Table 18,
60 k for this example) and the external resistor. Note
that the Peak Input Voltage corresponding to the chosen
60
Rev. 1.0
31
Si4720/21-B20
LIATTEN[1:0] code still needs to satisfy the condition of
being just greater than the attenuated voltage. In this
example, a line attenuation code of LIATTEN[1:0] = 11
has a Peak Input Voltage of 636 mV, which is just
greater than the expected peak attenuated voltage of
600 mV. Also, the expected peak attenuated voltage is
entered into the LILEVEL[9:0] parameter. Again, in this
example, 600 mV is entered into LILVEVEL[9:0]. This
example shows one possible solution, but many other
solutions exist. The optimal solution is to apply the
largest possible voltage to the LIN and RIN pins for
signal-to-noise considerations; however, practical
resistor values may limit the choices.
Input [dBFS]
–50 –40
–90
–80
–70
–60
–30
–20
–10
0
Compression
2:1 dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
Threshold
= –40 dB
No
Compression
M = 1
M = 1
Gain
= 20 dB
Note that the TX_LINE_INPUT_LEVEL parameter will
affect the high-pass filter characteristics of the ac-
coupling capacitors and the resistance of the audio
inputs.
The Si4720/21 has a programmable low audio level and
high audio level indicators that allows the user to
selectively enable and disable the carrier based on the
presence of audio content. The TX_ASQ_LEVEL_LOW
and TX_ASQ_LEVEL_HIGH parameters set the low
level and high level thresholds in dBFS, respectively.
The time required for the audio level to be below the low
threshold is set with the TX_ASQ_DURATION_LOW
parameter, and similarly, the time required for the audio
level to be above the high threshold is set with the
TX_ASQ_DURATION_HIGH parameter.
Figure 24. Audio Dynamic Range Transfer
Function
For input signals below the threshold of –40 dBFS, the
output signal is amplified or gained up by 20 dB relative
to an uncompressed signal. Audio inputs above the
threshold are compressed by a 2 to 1 dB ratio, meaning
that every 2 dB increase in audio input level above the
threshold results in an audio output increase of 1 dB. In
this example, the input dynamic range of 90 dB is
reduced to an output dynamic range of 70 dB.
Figure 25 shows the time domain characteristics of the
audio dynamic range controller. The attack rate sets the
speed with which the audio dynamic range controller
responds to changes in the input level, and the release
rate sets the speed with which the audio dynamic range
controller returns to no compression once the audio
input level drops below the threshold.
5.18. Audio Dynamic Range Control
The Si4720/21 includes digital audio dynamic range
control with programmable gain, threshold, attack rate,
and release rate. The total dynamic range reduction is
set by the gain value and the audio output compression
above
the
threshold
is
equal
to
Threshold/(Gain + Threshold) in dB. The gain specified
cannot be larger than the absolute value of the
threshold. This feature can also be disabled if audio
compression is not desired.
Threshold
Audio
Input
The audio dynamic range control can be used to reduce
the dynamic range of the audio signal, which improves
the listening experience on the FM receiver. Audio
dynamic range reduction increases the transmit volume
by decreasing the peak amplitudes of audio signals and
increasing the root mean square content of the audio
signal. In other words, it amplifies signals below a
threshold by a fixed gain and compresses audio signals
Audio
Output
above
a
threshold
by
the
ratio
of
Threshold/(Gain + Threshold). Figure 24 shows an
example transfer function of an audio dynamic range
controller with the threshold set at –40 dBFS and a
Gain = 20 dB relative to an uncompressed transfer
function.
Attack
time
Release
time
Figure 25. Time Domain Characteristics of the
Audio Dynamic Range Controller
32
Rev. 1.0
Si4720/21-B20
controller to burst data into the BCD buffer, which
emulates a FIFO. The data does not repeat, but, when
the buffer is nearly empty, the Si4721 signals the
outside device to initiate another data burst. This mode
permits the outside device to use any RDS functionality
(including open data applications) that it wants.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
5.19. Audio Limiter
The 4720/21 also includes a digital audio limiter. The
audio limiter prevents over-modulation of the FM
transmit output by dynamically attenuating peaks in the
audio input signal that exceed a programmable
threshold. The limiter threshold is set to the
programmed audio deviation + ten percent. The
threshold ensures that the output signal audio deviation
does not exceed the programmed levels, avoiding
audible artifacts or distortion in the target FM receiver,
and complying with FCC or ETSI regulatory standards.
5.22. Tuning
The frequency synthesizer uses Silicon Laboratories’
proven technology including a completely integrated
VCO. The frequency synthesizer generates the
quadrature local oscillator signal used to upconvert the
low intermediate frequency to RF. The VCO frequency
is locked to the reference clock and adjusted with an
automatic frequency control (AFC) servo loop during
transmission. The tuning frequency can be directly
programmed with commands. For example, to tune to
98.1 MHz, the user writes the TX_TUNE_FREQ
command with an argument = 9810. The Si4720/21
supports channel spacing of 50, 100, or 200 kHz.
The limiter performs as a peak detector with an attack
rate set to one audio sample, resulting in an almost
immediate attenuation of the input peak. The recover
rate is programmable to the customer’s preference, and
is set by default to 5 ms. This is the recommended
setting to avoid audible pumping or popping. Refer to
“AN332: Universal Programming Guide.”
5.20. Pre-emphasis and De-emphasis
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
5.23. Reference Clock
The Si4720/21 reference clock is programmable,
supporting RCLK frequencies from 31.130 kHz to
40 MHz. The RCLK frequency divided by an integer
number (the prescaler value) must fall in the range of
31,130 to 34,406 Hz. Therefore, the range of RCLK
frequencies is not continuous below frequencies of
311.3 kHz. The default RCLK frequency is 32.768 kHz.
Please refer to “AN332: Universal Programming Guide”
for using other RCLK frequencies.
transmitted,
a
pre-emphasis filter is applied to
accentuate the high audio frequencies. All FM receivers
incorporate a de-emphasis filter that attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The pre-
emphasis time constant is programmable to 50 or 75 µs
and is set by using the TX_PREEMPHASIS property.
5.21. RDS/RBDS Processor (Si4721 Only)
5.24. Control Interface
The Si4721 implements an RDS/RBDS* processor for
symbol encoding, block synchronization, and error
correction. Digital data can be transmitted with the
Si4721 RDS/RBDS encoding feature.
A serial port slave interface is provided; this allows an
external controller to send commands to the Si4720/21
and receive responses from the device. The serial port
can operate in three bus modes: 2-wire mode, SPI
mode, or 3-wire mode. The Si4720/21 selects the bus
mode by sampling the state of the GPO1 and
GPO2/INT pins on the rising edge of RST. The GPO1
pin includes an internal pull-up resistor that is
connected while RST is low, and the GPO2/INT pin
includes an internal pull-down resistor that is connected
while RST is low. Therefore, it is only necessary for the
user to actively drive pins that differ from these states.
RDS transmission is supported with three different
modes. The first mode is the simplest mode and
requires no additional user support except for pre-
loading the desired RDS PI and PTY codes and up to
12 8-byte PS character strings. The Si4721 will transmit
the PI code and rotate through the transmission of the
PS character strings with no further control required
from outside the device. The second mode allows for
more complicated transmissions. The PI and PTY
codes are written to the device as in mode 1. The
remaining blocks (B, C, and D) are written to a 252 byte
buffer. This buffer can hold 42 sets of BCD blocks. The
Si4721 creates RDS groups by creating block A from
the PI code, concatenating blocks BCD from the buffer,
and rotating through the buffer. The BCD buffer is
circular; so, the pattern is repeated until the buffer is
changed. Finally, the third mode allows the outside
Table 19. Bus Mode Select on Rising Edge of
RST
Bus Mode
2-Wire
SPI
GPO1
GPO2/INT
1
0
1
1 (must drive)
0
3-Wire
0 (must drive)
Rev. 1.0
33
Si4720/21-B20
After the rising edge of RST, the pins, GPO1 and and Write Timing Diagram,” on page 9.
GPO2/INT, are used as general-purpose output (O) pins
as described in Section “5.15. GPO Outputs”. In any
5.24.2. SPI Control Interface Mode
When selecting SPI mode, the user must ensure that a
rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
bus mode, commands may only be sent after V and
IO
V
supplies are applied.
DD
5.24.1. 2-Wire Control Interface Mode
SPI bus mode uses the SCLK, SDIO, and SEN pins for
read/write operations. For reads, the user can choose to
receive data from the device on either SDIO or GPO1. A
transaction begins when the user drives SEN low. The
user then pulses SCLK eight times while driving an 8-bit
control byte (MSB first) serially on SDIO. The device
captures the data on rising edges of SCLK. The control
byte must have one of these values:
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
2-wire bus mode uses only the SCLK and SDIO pins for
signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a seven bit
device address followed by a read/write bit (read = 1,
write = 0). The Si4720/21 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
0x48 = write eight command/argument bytes (user
drives write data on SDIO)
0x80 = read status byte (device drives read data on
SDIO)
0xA0 = read status byte (device drives read data on
GPO1)
0xC0 = read 16 response bytes (device drives read data
on SDIO)
Although the Si4720/21 responds to only a single
device address, this address can be changed with the
SEN pin (note that the SEN pin is not used for signaling
in 2-wire mode). When SEN = 0, the seven-bit device
address is 0010001. When SEN = 1, the address is
1100011.
0xE0 = read 16 response bytes (device drives read data
on GPO1)
When writing a command, after the control byte has
been written, the user must drive exactly eight data
bytes (a command byte and seven argument bytes) on
SDIO. The data will be captured by the device on the
rising edges of SCLK. After all eight data bytes have
been written, the user raises SEN after the last falling
edge of SCLK to end the transaction.
For write operations, the user then sends an eight bit
data byte on SDIO, which is captured by the device on
rising edges of SCLK. The Si4720/21 acknowledges
each data byte by driving SDIO low for one cycle, on the
next falling edge of SCLK. The user may write up to
eight data bytes in a single two-wire transaction. The
first byte is a command, and the next seven bytes are
arguments.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high). In SPI
mode, this is done by sending control byte 0x80 or
0xA0, followed by reading a single byte on SDIO or
GPO1. The Si4720/21 changes the state of SDIO or
GPO1 after the falling edges of SCLK. Data should be
captured by the user on the rising edges of SCLK. After
the status byte has been read, the user raises SEN after
the last falling edge of SCLK to end the transaction.
For read operations, after the Si4720/21 has
acknowledged the control byte, it drives an eight-bit
data byte on SDIO, changing the state of SDIO on the
falling edge of SCLK. The user acknowledges each data
byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. If
a
data byte is not
When reading a response, the user must read exactly
16 data bytes after sending the control byte. It is
recommended that the user keep SEN low until all bytes
have transferred. However, it will not disrupt the
protocol if SEN temporarily goes high at any time, as
long as the user does not change the state of SCLK
while SEN is high. After 16 bytes have been read, the
user raises SEN after the last falling edge of SCLK to
end the transaction.
acknowledged, the transaction ends. The user may
read up to 16 data bytes in a single two-wire
transaction. These bytes contain the response data
from the Si4720/21.
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
to
Table 5,
“2-Wire
Control
Interface
1,2,3
Characteristics
,” on page 8, Figure 2, “2-Wire
At the end of any SPI transaction, the user must drive
SEN high after the final falling edge of SCLK. At any
Control Interface Read and Write Timing Parameters,”
on page 9, and Figure 3, “2-Wire Control Interface Read
34
Rev. 1.0
Si4720/21-B20
time during a transaction, if SEN is sampled high by the
device on a rising edge of SCLK, the transaction will be
aborted. When SEN is high, SCLK may toggle without
affecting the device.
5.26. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset and place it in powerdown mode.
For details on timing specifications and diagrams, refer
to Figure 6 and Figure 7 on page 11.
A powerdown mode is available to reduce power
consumption when the part is idle. Putting the device in
5.24.3. 3-Wire Control Interface Mode
When selecting 3-wire mode, the user must ensure that powerdown mode will disable analog and digital circuitry
a rising edge of SCLK does not occur within 300 ns and keep the bus active. For more information
before the rising edge of RST.
concerning Reset, Powerup, Powerdown, and
Initialization, refer to “AN332: Universal Programming
Guide.”
3-wire bus mode uses the SCLK, SDIO and SEN pins.
A transaction begins when the system controller drives
SEN low. Next, the system controller drives a 9-bit
control word on SDIO, which is captured by the device
on rising edges of SCLK. The control word is comprised
of a three bit chip address (A7:A5 = 101b), a read/write
bit (write = 0, read = 1), the chip address (A4 = 0), and a
four bit register address (A3:A0).
5.27. Programming with Commands
To ease development time and offer maximum
customization, the Si4720/21 provides a simple yet
powerful software interface to program the transmitter.
The device is programmed using commands,
arguments, properties, and responses.
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
To perform an action, the user writes a command byte
and associated arguments causing the chip to execute
the given command. Commands control actions, such
as powering up the device, shutting down the device, or
tuning to a station. Arguments are specific to a given
command and are used to modify the command. For
example, after the TX_TUNE_FREQ command,
arguments are required to set the tune frequency. A
complete list of commands is available in Table 17,
“Si471x Command Summary,” on page 30.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turnaround. Next,
the Si4720/21 drives the 16-bit read data word serially
on SDIO, changing the state of SDIO on each rising
edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after powerup. Examples of
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
properties
are
TX_PREEMPHASIS
and
GPO_CONFIGURE. A complete list of properties is
available in Table 21, “Si472x Property Summary,” on
page 37.
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 10, Figure 4, “3-Wire Control Interface Write
Timing Parameters,” on page 10, and Figure 5, “3-Wire
Control Interface Read Timing Parameters,” on page
10.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. At a minimum, all commands provide a one-byte
status update indicating interrupt and clear-to-send
status information. For a detailed description of using
the commands and properties of the Si4720/21, see
“AN332: Universal Programming Guide.”
5.25. GPO Outputs
The Si4720/21 provides three general-purpose output
pins. The GPO pins can be configured to output a
constant low, constant high, or high-Z. The GPO pins
are multiplexed with the bus mode pins or DCLK
depending on the application schematic of the device.
GPO2/INT can be configured to provide interrupts for
seek and tune complete, receive signal quality, and
RDS.
Rev. 1.0
35
Si4720/21-B20
6. Commands and Properties
Table 20. Si472x Command Summary
Cmd
Name
Description
Transmit Commands
Power up device and mode selection. Modes include FM transmit
and analog/digital audio interface configuration.
0x01
POWER_UP
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x30
0x31
0x32
GET_REV
POWER_DOWN
SET_PROPERTY
GET_PROPERTY
GET_INT_STATUS
PATCH_ARGS
Returns revision information on the device.
Power down device.
Sets the value of a property.
Retrieves a property’s value.
Read interrupt status bits.
Reserved command used for patch file downloads.
Reserved command used for patch file downloads.
Tunes to given transmit frequency.
PATCH_DATA
TX_TUNE_FREQ
TX_TUNE_POWER
TX_TUNE_MEASURE
Sets the output power level and tunes the antenna capacitor.
Measure the received noise level at the specified frequency.
Queries the status of a previously sent TX Tune Freq, TX Tune
Power, or TX Tune Measure command.
0x33
0x34
0x35
TX_TUNE_STATUS
TX_ASQ_STATUS
TX_RDS_BUFF
Queries the TX status and input audio signal metrics.
Queries the status of the RDS Group Buffer and loads new data into
buffer.
0x36
0x80
0x81
TX_RDS_PS
GPIO_CTL
GPIO_SET
Set up default PS strings.
Configures GPO1, 2, and 3 as output or Hi-Z.
Sets GPO1, 2, and 3 output level (low or high).
Receive Commands
0x01
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x20
0x21
POWER_UP
Power up device and mode selection.
Returns revision information on the device.
Power down device.
GET_REV
POWER_DOWN
SET_PROPERTY
GET_PROPERTY
GET_INT_STATUS
PATCH_ARGS
Sets the value of a property.
Retrieves a property’s value.
Reads interrupt status bits.
Reserved command used for patch file downloads.
Reserved command used for patch file downloads.
Selects the FM tuning frequency.
Begins searching for a valid frequency.
PATCH_DATA
FM_TUNE_FREQ
FM_SEEK_START
Queries the status of previous FM_TUNE_FREQ or FM_-
SEEK_START command.
0x22
0x23
FM_TUNE_STATUS
FM_RSQ_STATUS
Queries the status of the Received Signal Quality (RSQ) of the cur-
rent channel.
36
Rev. 1.0
Si4720/21-B20
Table 20. Si472x Command Summary (Continued)
Returns RDS information for current channel and reads an entry
from RDS FIFO (Si4721 only).
0x24
FM_RDS_STATUS
0x27
0x28
0x80
0x81
FM_AGC_STATUS
FM_AGC_OVERRIDE
GPIO_CTL
Queries the current AGC settings
Override AGC setting by disabling and forcing it to a fixed value
Configures GPO1, 2, and 3 as output or Hi-Z.
Sets GPO1, 2, and 3 output level (low or high).
GPIO_SET
Table 21. Si472x Property Summary
Prop
Name
Description
Default
Transmit Properties
0x0001
GPO_IEN
DIGITAL_INPUT _FORMAT
Enables interrupt sources.
0x0000
0x0000
0x0101
Configures the digital input format.
Configures the digital input sample rate in 1 Hz steps.
Default is 0.
0x0103 DIGITAL_INPUT _SAMPLE_RATE
0x0000
Sets frequency of the reference clock in Hz. The range is
31130 to 34406 Hz, or 0 to disable the AFC. Default is
32768 Hz.
0x0201
REFCLK_FREQ
0x8000
0x0202
0x2100
REFCLK_PRESCALE
Sets the prescaler value for the reference clock.
0x0001
0x0003
Enable transmit multiplex signal components.
Default has pilot and L-R enabled.
TX_COMPONENT_ENABLE
Configures audio frequency deviation level. Units are in
10 Hz increments. Default is 6825 (68.25 kHz).
0x2101
0x2102
TX_AUDIO_DEVIATION
TX_PILOT_DEVIATION
0x1AA9
0x02A3
Configures pilot tone frequency deviation level. Units are
in 10 Hz increments. Default is 675 (6.75 kHz)
Si4721 Only. Configures the RDS/RBDS frequency
0x2103
0x2104
TX_RDS_DEVIATION
deviation level. Units are in 10 Hz increments. Default is 0x00C8
2 kHz.
Configures maximum analog line input level to the
LIN/RIN pins to reach the maximum deviation level pro-
grammed into the audio deviation property TX Audio
TX_LINE_INPUT_LEVEL
0x327C
Deviation. Default is 636 mV
.
PK
Sets line input mute. L and R inputs may be inde-
pendently muted. Default is not muted.
0x2105
0x2106
0x2107
TX_LINE_INPUT_MUTE
TX_PREEMPHASIS
0x0000
0x0000
0x4A38
Configures pre-emphasis time constant.
Default is 0 (75 µS).
Configures the frequency of the stereo pilot. Default is
19000 Hz.
TX_PILOT_FREQUENCY
Enables audio dynamic range control and limiter.
0x2200
TX_ACOMP_ENABLE
0x0002
Default is 2 (limiter is enabled, audio dynamic range
control is disabled).
Sets the threshold level for audio dynamic range control.
Default is –40 dB.
0x2201
0x2202
TX_ACOMP_THRESHOLD
TX_ACOMP_ATTACK_TIME
0xFFD8
0x0000
Sets the attack time for audio dynamic range control.
Default is 0 (0.5 ms).
Rev. 1.0
37
Si4720/21-B20
Table 21. Si472x Property Summary (Continued)
Prop
Name
Description
Default
Sets the release time for audio dynamic range control.
Default is 4 (1000 ms).
0x2203
TX_ACOMP_RELEASE_TIME
0x0004
Sets the gain for audio dynamic range control.
Default is 15 dB.
0x2204
0x2205
TX_ACOMP_GAIN
0x000F
0x0066
0x0000
TX_LIMITER_RELEASE_TIME
Sets the limiter release time. Default is 102 (5.01 ms)
Configures measurements related to signal quality met-
rics. Default is none selected.
0x2300 TX_ASQ_INTERRUPT_SOURCE
Configures low audio input level detection threshold.
This threshold can be used to detect silence on the
incoming audio.
0x2301
0x2302
0x2303
0x2304
TX_ASQ_LEVEL_LOW
TX_ASQ_DURATION_LOW
TX_ASQ_LEVEL_HIGH
0x0000
Configures the duration which the input audio level must
be below the low threshold in order to detect a low audio 0x0000
condition.
Configures high audio input level detection threshold.
This threshold can be used to detect activity on the
incoming audio.
0x0000
0x0000
Configures the duration which the input audio level must
be above the high threshold in order to detect a high
audio condition.
TX_ASQ_DURATION_HIGH
Si4721 Only. Configure RDS interrupt sources. Default
is none selected.
0x2C00 TX_RDS_INTERRUPT_SOURCE
0x0000
0x40A7
0x0003
0x2C01
0x2C02
TX_RDS_PI
Si4721 Only. Sets transmit RDS program identifier.
Si4721 Only. Configures mix of RDS PS Group with
RDS Group Buffer.
TX_RDS_PS_MIX
Si4721 Only. Miscellaneous bits to transmit along with
RDS_PS Groups.
0x2C03
TX_RDS_PS_MISC
0x1008
Si4721 Only. Number of times to repeat transmission of
0x2C04 TX_RDS_PS_REPEAT_COUNT a PS message before transmitting the next PS mes-
sage.
0x0003
0x0001
0x2C05 TX_RDS_PS_MESSAGE_COUNT Si4721 Only. Number of PS messages in use.
Si4721 Only. RDS Program Service Alternate Fre-
quency. This provides the ability to inform the receiver of
a single alternate frequency using AF Method A coding
and is transmitted along with the RDS_PS Groups.
0x2C06
0x2C07
TX_RDS_PS_AF
0xE0E0
0x0000
Si4721 Only. Number of blocks reserved for the FIFO.
Note that the value written must be one larger than the
desired FIFO size.
TX_RDS_FIFO_SIZE
Receive Properties
0x0001
GPO_IEN
Enables interrupt sources.
0x0000
0x0000
DIGITAL_OUTPUT_
FORMAT
0x0102
0x0104
Configure digital audio outputs (Si4721 only)
DIGITAL_OUTPUT_
SAMPLE_RATE
Configure digital audio output sample rate (Si4721 only) 0x0000
38
Rev. 1.0
Si4720/21-B20
Table 21. Si472x Property Summary (Continued)
Prop
Name
Description
Default
Sets frequency of reference clock in Hz. The range is
31130 to 34406 Hz, or 0 to disable the AFC. Default is
32768 Hz.
0x0201
REFCLK_FREQ
0x8000
0x0202
0x1100
REFCLK_PRESCALE
FM_DEEMPHASIS
Sets the prescaler value for RCLK input.
0x0001
0x0002
Sets deemphasis time constant. Default is 75 µs.
Sets RSSI threshold for stereo blend (Full stereo above
FM_BLEND_STEREO_THRESH- threshold, blend below threshold). To force stereo set this
0x1105
0x1106
0x0031
0x001E
OLD
to 0. To force mono set this to 127. Default value is
49 dBµV.
Sets RSSI threshold for mono blend (Full mono below
threshold, blend above threshold). To force stereo set this
to 0. To force mono set this to 127. Default value is
30 dBµV.
FM_BLEND_MONO_
THRESHOLD
Selects the antenna type and the pin to which it is con-
nected. (Si4721 only).
0x1107
0x1108
0x1200
0x1201
0x1202
0x1203
0x1204
0x1207
0x1300
0x1302
0x1303
0x1400
0x1401
0x1402
0x1403
0x1404
FM_ANTENNA_INPUT
0x0000
0x001E
0x0000
0x007F
0x0000
0x007F
0x0000
0x0081
0x0040
0x0010
FM_MAX_TUNE_
ERROR
Sets the maximum freq error allowed before setting the
AFC rail (AFCRL) indicator. Default value is 30 kHz.
FM_RSQ_INT_
SOURCE
Configures interrupt related to Received Signal Quality
metrics.
FM_RSQ_SNR_HI_
THRESHOLD
Sets high threshold for SNR interrupt.
Sets low threshold for SNR interrupt.
Sets high threshold for RSSI interrupt.
Sets low threshold for RSSI interrupt.
FM_RSQ_SNR_LO_
THRESHOLD
FM_RSQ_RSSI_HI_
THRESHOLD
FM_RSQ_RSSI_LO_
THRESHOLD
FM_RSQ_BLEND_
THRESHOLD
Sets the blend threshold for blend interrupt when bound-
ary is crossed.
Sets the attack and decay rates when entering and leav-
ing soft mute.
FM_SOFT_MUTE_RATE
FM_SOFT_MUTE_
MAX_ATTENUATION
Sets maximum attenuation during soft mute (dB). Set to 0
to disable soft mute. Default is 16 dB.
FM_SOFT_MUTE_
SNR_THRESHOLD
Sets SNR threshold to engage soft mute. Default is 4 dB. 0x0004
FM_SEEK_BAND_
BOTTOM
Sets the bottom of the FM band for seek.
0x222E
Default is 8750 (87.5 MHz).
Sets the top of the FM band for seek.
0x2A26
FM_SEEK_BAND_TOP
Default is 10790 (107.9 MHz).
FM_SEEK_FREQ_
SPACING
Selects frequency spacing for FM seek.
0x000A
Default value is 10 (100 kHz).
FM_SEEK_TUNE_
SNR_THRESHOLD
Sets the SNR threshold for a valid FM Seek/Tune.
Default value is 3 dB.
0x0003
FM_SEEK_TUNE_
RSSI_TRESHOLD
Sets the RSSI threshold for a valid FM Seek/Tune.
0x0014
Default value is 20 dBµV.
Rev. 1.0
39
Si4720/21-B20
Table 21. Si472x Property Summary (Continued)
Prop
Name
Description
Default
0x1500
RDS_INT_SOURCE
Configures RDS interrupt behavior (Si4721 only).
0x0000
Sets the minimum number of RDS groups stored in the
receive FIFO required before RDSRECV is set (Si4721
only).
RDS_INT_FIFO_
COUNT
0x1501
0x0000
0x1502
0x4000
RDS_CONFIG
RX_VOLUME
Configures RDS setting (Si4721 only).
Sets the output volume.
0x0000
0x003F
Mutes the audio output. L and R audio outputs may be
muted independently.
0x4001
RX_HARD_MUTE
0x0000
40
Rev. 1.0
Si4720/21-B20
7. Pin Descriptions: Si4720/21-GM
20 19 18 17
NC
1
16
FMI 2
RFGND 3
TXO 4
15 RIN/DOUT
14 LOUT/DFS
13 ROUT/DIN
12 GND
GND
PAD
RST 5
6
11 VDD
7
8
9
10
Pin Number(s)
Name
NC
Description
1, 20
No connect. Leave floating.
FM RF input.
2
FMI
3
RFGND
TXO
RF ground. Connect to ground plane on PCB.
FM transmit output connection to transmit antenna.
Device reset (active low) input.
4
5
RST
6
SEN
Serial enable input (active low).
7
SCLK
Serial clock input.
8
SDIO
Serial data input/output.
9
RCLK
VIO
External reference oscillator input.
10
I/O supply voltage.
11
VDD
Supply voltage. May be connected directly to battery.
Right audio line output—digital input data.
Left audio line output—digital frame synchronization.
Right audio line input—digital output data.
Left audio line input—digital frame synchronization.
13
ROUT/DIN
LOUT/DFS
RIN/DOUT
LIN/DFS
14
15
16
17
GPO3/DCLK General purpose output—digital bit synchronous clock.
18
19
GPO2/INT
GPO1
General purpose output—interrupt request.
General purpose output.
12, GND PAD
GND
Ground. Connect to ground plane on PCB.
Rev. 1.0
41
Si4720/21-B20
8. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4720-B20-GM Broadcast FM Radio Transceiver for Portable Applica-
tions
QFN
Pb-free
–20 to 85 °C
Si4721-B20-GM Broadcast FM Radio Transceiver for Portable Applica-
tions with RDS/RBDS Encoder/Decoder
QFN
Pb-free
–20 to 85 °C
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
42
Rev. 1.0
Si4720/21-B20
9. Package Markings (Top Marks)
9.1. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
20 = Si4720; 21 = Si4721
20 = Firmware Revision 2.0
B = Revision B Die
Firmware Revision
Die Revision
Line 2 Marking:
Line 3 Marking:
TTT = Internal Code
Internal tracking code.
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year
WW = ‘Workweek
Assigned by the Assembly House. Corresponds to the last
significant digit of the year and workweek of the mold date.
9.2. Si4720/21 Top Mark
9.3. Si4721 Top Mark
Rev. 1.0
43
Si4720/21-B20
10. Package Outline: Si4720/21-GM
Figure 26 illustrates the package details for the Si4720. Table 22 lists the values for the dimensions shown in the
illustration.
Figure 26. 20-Pin Quad Flat No-Lead (QFN)
Table 22. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Nom
Min
Max
Min
Max
A
A1
b
0.50
0.00
0.20
0.27
0.55
0.02
0.60
0.05
0.30
0.37
f
2.53 BSC
L
0.35
0.00
—
0.40
—
0.45
0.10
0.05
0.05
0.08
0.10
0.10
0.25
L1
c
0.32
aaa
bbb
ccc
ddd
eee
—
D
3.00 BSC
1.70
—
—
D2
e
1.65
1.75
—
—
0.50 BSC
3.00 BSC
1.70
—
—
E
—
—
E2
1.65
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
44
Rev. 1.0
Si4720/21-B20
11. PCB Land Pattern: Si4720/21-GM
Figure 27 illustrates the PCB land pattern details for the Si4720-GM. Table 23 lists the values for the dimensions
shown in the illustration.
Figure 27. PCB Land Pattern
Rev. 1.0
45
Si4720/21-B20
Table 23. PCB Land Pattern Dimensions
Symbol
Millimeters
Min Max
2.71 REF
1.60 1.80
Symbol
Millimeters
Min
Max
D
D2
e
GE
W
2.10
—
—
0.34
0.28
0.50 BSC
2.71 REF
X
—
E
Y
0.61 REF
E2
f
1.60
2.53 BSC
2.10
1.80
ZE
ZD
—
—
3.31
3.31
GD
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification.
3. This land pattern design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a fabrication allowance of 0.05 mm.
Note: Solder Mask Design
1. All metal pads are to be non-solder-mask-defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 mm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component standoff.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for small body components.
46
Rev. 1.0
Si4720/21-B20
12. Additional Reference Resources
Si47xx Evaluation Board User’s Guide
AN307: Si4712/13/20/21 Receive Power Scan
AN332: Universal Programming Guide
AN341: Si4720/21 Evalution Board Quick Start Guide
AN383: Universal Antenna Selection and Layout Guidelines
AN388: Universal Evaluation Board Test Procedure
Si4720/21 Customer Support Site: www.mysilabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, send mysilabs user name and request for access to
fminfo@silabs.com.
Rev. 1.0
47
Smart.
Connected.
Energy-Friendly
Products
www.silabs.com/products
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
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