Si51219 [SILICON]
Timing Selector Guide;型号: | Si51219 |
厂家: | SILICON |
描述: | Timing Selector Guide |
文件: | 总20页 (文件大小:2006K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Timing Selector Guide
SPRING 2014
10
YE AR
10 YEAR
OPERATING LIFE
BEST-IN-CLASS STABILITY
OVER TEMPERATURE
2 WEEK LEAD TIMES
THE INDUSTRY'S BEST
LOW-COST, HIGH-VOLUME
CMOS FOUNDRIES
2 / CLOCK AND OSCILL ATOR SELEC TOR
Clock and Oscillator Timing IC Solutions
Silicon Labs is a one stop shop providing a complete portfolio of
clocks, buffers, oscillators and jitter attenuating clocks.
One-Stop-Shop — industry-leading portfolio of oscillators, clock
generators, clock buffers and jitter attenuating clocks
Fast — custom oscillators and clocks in minutes, not months
Clock Tree Services — receive clock tree design guidance from Silicon
Labs’ timing experts in under 48 hours
Support — expert technical support and deep applications knowledge
to accelerate your development schedules
Flexible — Silicon Labs’ clocks and oscillators support any combination
of frequencies, minimizing BOM count and complexity
Customized — our flagship products are highly customizable over the
web and ship in days, not weeks
Performance — highly-integrated, low jitter timing solutions simplify
design and optimize system performance
CLOCK AND OSCILL ATOR SELEC TOR / 3
Clock Generation
WEB-CONFIGURABLE FACTORY-CUSTOMIZED CLOCK GENERATORS AVAILABLE AT: www.silabs.com/custom-timing
Any-Frequency, Any-Output Differential/CMOS Clocks
Silicon Labs’ differential + LVCMOS clock generators provide any rate, any output frequency synthesis. Any
combination of output frequencies can be generated exactly with 0 ppm error. Independent signal format and
VDDO options provide integrated level translation, supporting LVPECL/LVDS/HCSL/LVCMOS clock generation up
to 710 MHz with sub 1 ps rms phase jitter.
Si5338 FEATURES
• Generates any frequency on any output, from 160 kHz
to 350 MHz and select frequencies to 710 MHz
• Exact clock synthesis (0 ppm error)
• Low phase jitter: 1 ps rms
• I2C programmable or pin-controlled
• Excellent PSRR, no discrete components
• Spread spectrum clock generation
• Crystal or clock input
• 4 differential outputs or 8 single-ended outputs
• Any format, on any output: LVPECL, LVDS, HCSL,
LVCMOS, HSTL, SSTL and CML
• User-definable control pins: Powerdown,
Output Enable, Frequency Select, Spread Select
• Factory-customizable clocks w/2 week lead times
www.silabs.com/custom-timing
• Independent VDDO per output eliminates external
level translators (1.5, 1.8, 2.5, 3.3 V)
25 MHz 1.8 V CMOS
25 MHz 1.8 V CMOS
66.6 MHz ±5% 3.3 V CMOS
100 MHz 2.5 V LVPECL
25 MHz
1.544 MHz/2.048 MHz 3.3 V CMOS
CLOCK
PHASE
INPUT
OUTPUT
PART NUMBER CONTROL INPUT/
OUTPUTS
JITTER
(RMS)
VDD
VDDO
OUTPUT
PACKAGE
QFN24
FREQUENCY (MHZ)
FREQUENCY (MHZ)
0.16 - 710 MHz
0.16 - 350 MHz
0.16 - 200 MHz
5 - 710 (Clock),
8 - 30 (Xtal)
LVCMOS, LVDS, LVPECL,
HCSL, SSTL, HSTL
Si5334
Si5335
Si5338
Pin
Pin
I2C
1/4
1/4
1/4
1.0 ps
1.0 ps
1.0 ps
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
10 - 350 (Clock),
25/27 (Xtal)
LVCMOS, LVDS, LVPECL,
HCSL, SSTL, HSTL, CML
1 - 350 MHz
QFN24
0.16 - 710 MHz
0.16 - 350 MHz
0.16 - 200 MHz
5 - 710 (Clock),
8 - 30 (Xtal)
LVCMOS, LVDS, LVPECL,
HCSL, SSTL, HSTL, CML
QFN24
4 / CLOCK AND OSCILL ATOR SELEC TOR
Tiny CMOS Clocks
Silicon Labs’ highly flexible, factory and I2C programmable tiny clock LVCMOS generators can be customized to generate
multiple frequencies with significantly lower jitter, lower power and smaller size than competing solutions. Customization
options are available for frequency selection, output enable control, or minimizing EMI, including customizable spread
percentage, modulation rate, output impedance and rise time/fall time.
Si512xx TINY CLOCK FEATURES
• Up to three customizable output frequencies from
3 to 200 MHz
• Customizable drive strengths (four levels
for each output)
• Accepts 8 to 48 MHz crystal or 3 to 166 MHz external
reference clock
• Customizable control pins (PD#/OE/SSON#/FS)
• Supply range: 1.8 V for Si51214;
2.5 to 3.3 V for other devices
• Low cycle-to-cycle jitter: <150 ps
• Low power: 2.3 mA (typ) at 48 MHz output,
25 MHz xtal in and VDD = 3.3 V
• Ultra-compact packages
• 6-pin TDFN (1.2 mm x 1.4 mm x 0.75 mm)
• 8-pin TDFN (1.6 mm x 1.4 mm x 0.75 mm)
• Factory programmable OTP
• Center spread modulation from 0.25 to 1.0%,
with 0.125% resolution
• Programmable spread modulation rate from 30 - 62 kHz
• Two week sample lead time
38 MHz/
40 MHz
27 MHz
12 MHz
12 MHz
74.25 MHz/
74.1758 MHz
CLOCK
PERIOD
INPUT
OUTPUT
PART NUMBER
CONTROL
INPUT/
JITTER
(PP)
VDD
VDDO
OUTPUT
PACKAGE
FREQUENCY (MHz)
3 - 166 (Clock), 8 - 48 (Xtal)
3 - 166 (Clock), 8 - 48 (Xtal)
3 - 166 (Clock), 8 - 48 (Xtal)
3 - 166 (Clock), 8 - 48 (Xtal)
25/27 (Xtal)
FREQUENCY (MHz)
OUTPUTS
Si51210
Si51211
Si51214
Si51219
Si5350A
Si5350C
Si5351A
Pin
Pin
Pin
Pin
Pin
Pin
I2C
1/2
1/3
1/2
1/3
1/3
1/3
1/3
3 to 200 MHz
3 to 200 MHz
—
—
2.5 to 3.3 V
2.5 to 3.3 V
1.8 V
—
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
TDFN6
TDFN8
1.8, 2.5, 3.3 V
—
3 to 133 MHz
—
TDFN6
3 to 200 MHz
—
2.5 to 3.3 V
2.5, 3.3 V
2.5, 3.3 V
2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
TSSOP8
MSOP10
MSOP10
MSOP10
8 kHz to 160 MHz
8 kHz to 160 MHz
8 kHz to 160 MHz
100 ps
100 ps
100 ps
10 - 100 (Clock), 25/27 (Xtal)
25/27 (Xtal)
CLOCK AND OSCILL ATOR SELEC TOR / 5
Any-Frequency, Any-Output CMOS Clocks
Silicon Labs’ highly flexible factory and I2C programmable LVCMOS clock generators can be customized to generate
multiple independent non-integer-related frequencies with equivalent frequency synthesis capability of 8 PLLs, with exact
frequency synthesis (0 ppm error), significantly lower jitter, lower power and smaller size than competing solutions. Factory
customization options are available to minimize EMI, including configurable edge rates, output impedance, output skew
and spread spectrum.
Si5350 FEATURES
• Generates any frequency on any output,
8 kHz to 160 MHz
• Excellent PSRR: no discrete components
• Two week sample lead time for any custom clock
• Integrated load capacitors
• Exact clock synthesis: 0 ppm error
• Similar frequency flexibility as 8 independent PLLs
• Crystal or clock input
• Spread spectrum clock generation
-0.1 to -2.5% down, 0.1 to 1.5% center
• User-definable control pins Powerdown,
Output Enable, Spread Enable, Frequency
Select control pins
• <100 ps pk-pk period jitter
• Glitchless switching between output frequencies
• I2C programmable or pin-controlled
DVD Drive
S-Video/CVBS
Component
Video
Headphones
Microphone
CLOCK
INPUT/
OUTPUTS
INPUT
FREQUENCY
(MHz)
PERIOD
JITTER
(PP)
OUTPUT
FREQUENCY (MHz)
PART NUMBER CONTROL
VDD
VDDO
OUTPUT
PACKAGE
Si5350A/51A
Si5350B/51B
Si5350C/51C
Si5355
Pin/I2C
Pin/I2C
Pin/I2C
Pin
1/8
1/8
1/8
1/8
25/27 (Xtal)
25/27 (Xtal)
8 kHz - 160 MHz
8 kHz - 160 MHz
8 kHz - 160 MHz
1 - 200 MHz
100 ps
100 ps
100 ps
2.5, 3.3 V
2.5, 3.3 V
2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
LVCMOS
LVCMOS
LVCMOS
LVCMOS
QFN20
QFN20
QFN20
QFN24
10 - 100 (Clock),
25/27 (Xtal)
5 - 200 (Clock)
25/27 (Xtal)
50 ps
1.8, 2.5, 3.3 V
6 / CLOCK AND OSCILL ATOR SELEC TOR
PCI Express Clock Generators (PCIe)
Silicon Labs offers the lowest power, highest performance PCI-Express clock generators in the market. All devices in the
portfolio feature low power push-pull output buffer technology, providing benefits of low power consumption, reduced
external terminating resistors and smaller packaging. To optimize performance, the devices support programmable drive
strength, rise/fall times and output impedance. Basic HCSL PCIe and high-performance differential clocks and buffers are
available. Support for down spread spectrum clock generation is also provided.
PCIe CLOCK FEATURES
• Full portfolio of PCI Express (PCIe) Gen 1/2/3 clocks
and buffers
• Available hardware strapping pin for spread enable
• I2C/SMBus programmable
• All products utilize push-pull HCSL output buffers
• Fully integrated termination resistors on
PCIe outputs
• Also supports LVPECL, LVDS, or CML levels
• Industrial temperature grade
• Individual output enable control
• Low power consumption
• Small form factor QFN packaging
• Programmable spread spectrum
100 MHz HCSL
100 MHz HCSL
100 MHz HCSL
100 MHz HCSL
100 MHz HCSL
CLOCK
INPUT
FREQUENCY
(MHz)
OUTPUT
FREQUENCY
(MHz)
PHASE
JITTER
(RMS)
PART NUMBER CONTROL INPUT/
OUTPUTS
VDD
VDDO
OUTPUT
PACKAGE
Si52142
Si52143
Pin/I2C
Pin/I2C
Pin/I2C
Pin/I2C
Pin/I2C
Pin
1/3
1/5
1/4
1/6
1/9
1/1
1/2
1/4
25 MHz
25 MHz
100 MHz, 25 MHz
100 MHz, 25 MHz
100 MHz
1.0 ps
1.0 ps
1.0 ps
1.0 ps
1.0 ps
1.0 ps
1.0 ps
1.0 ps
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
HSCL, LVCMOS
HSCL, LVCMOS
HSCL
QFN24
QFN24
Si52144
25 MHz
QFN24
Si52146
25 MHz
100 MHz
HSCL
QFN32
Si52147
25 MHz
100 MHz
HSCL
QFN48
SL28SRC01
SL28SRC02
SL28SRC04
14.318 MHz
14.318 MHz
14.318 MHz
100 MHz
HCSL
TSSOP16
TSSOP20
TSSOP24
Pin
100 MHz
HCSL
Pin
100 MHz
HCSL
5 - 710 (Clock),
8 - 30 (Xtal)
LVCMOS, LVDS, LVPECL, HCSL,
SSTL, HSTL
Si5334
Si5335
Si5338
Pin
Pin
I2C
1/4
1/4
1/4
0.16 - 710 MHz
1 - 350 MHz
1.0 ps
1.0 ps
1.0 ps
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
QFN24
QFN24
QFN24
10 - 350 (Clock),
25/27 (Xtal)
LVCMOS, LVDS, LVPECL, HCSL,
SSTL, HSTL, CML
5 - 710 (Clock)
8 - 30 (Xtal)
LVPECL, LVDS, LVCMOS, HCSL,
SSTL, HSTL
0.16 - 710 MHz
CLOCK AND OSCILL ATOR SELEC TOR / 7
CMOS Clock Generator + VCXOs
These integrated clock + VCXO devices feature an integrated voltage controlled oscillator (VCXO), while eliminating the
need for custom, pullable crystals. Free-running and VCXO clocks can be generated by one device, making them ideal for
cost-sensitive consumer applications.
Si5350B/51B FEATURES
• Generates any frequency on any output, 8 kHz to 160 MHz
• Exact clock synthesis: 0 ppm error
• Excellent PSRR: no discrete components
• Two week sample lead time for any custom clock
• Integrated load capacitors
• Similar frequency flexibility as 8 independent PLLs
• Accepts crystal and analog control voltage input (VCXO)
• <100 ps pk-pk period jitter for any configuration
• Glitchless switching between output frequencies
• Integrated VCXO uses standard non-pullable crystal
• I2C programmable or pin-controlled
• Spread spectrum clock generation
-0.5 to -2.5% down, 0.1 to 1.5% center
• User-definable control pins Powerdown,
Output Enable, Spread Enable or Frequency
Select control pins
Satellite
Remote Control
—OR—
CLOCK
PART NUMBER CONTROL INPUT/
OUTPUTS
INPUT
FREQUENCY
(MHz)
PERIOD
JITTER
(PP)
OUTPUT
FREQUENCY (MHz)
VDD
VDDO
OUTPUT
PACKAGE
25/27 (Xtal)
VCXO
Si5350B
Si5351B
SL38000
SL38160
Pin
I2C
1/3 or 8
1/8
8 kHz - 160 MHz
100 ps
100 ps
—
2.5, 3.3 V
2.5, 3.3 V
1.8, 2.5, 3.3 V LVCMOS
1.8, 2.5, 3.3 V LVCMOS
1.8, 2.5, 3.3 V LVCMOS
1.8, 2.5, 3.3 V LVCMOS
MSOP10/QFN20
QFN20
25/27 (Xtal)
VCXO
8 kHz - 160 MHz
3 - 200 MHz
3 - 166 (Clock),
8 - 48 (Xtal)
Pin/I2C
Pin/I2C
1/12
1/8
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
TSSOP28
TSSOP16
3 - 166 (Clock),
8 - 48 (Xtal)
3 - 200 MHz
—
8 / CLOCK AND OSCILL ATOR SELEC TOR
Embedded Intel x86 Clocks
Silicon Labs offers an family of Intel-compliant x86 clocks for embedded computing, communications and industrial
applications. These system main clock generators support a wide variety of chipsets and processors. They provide all the
necessary clock generation for the CPU, memory controller (chipset north bridge), I/O controller (chipset south bridge)
as well as the latest timing requirements for industry standards such as SATA, USB, LAN, PCI Express and legacy PCI.
EMBEDDED INTEL x86 CLOCK FEATURES
• Clocking support for Intel processors
• Integrated LAN clock for cost/space/component
savings
• Multi-PLL platform for independent, asynchronous
signal generation
• Integrated IEEE1394 clock for cost/space
component savings
• Low power consumption push-pull differential buffers
• Available true differential current steering buffers
• Signal power management for notebook applications
• Dynamic enable/disable for PCIe hot plug applications
• Integrated voltage regulator and damping resistors
on differential clocks
• 8-step programmable slew rate control for rise
time and fall time control
• Dynamic independent PLL overclocking for
enthusiast applications
• Underclocking capabilities for power management
support and debugging
• Integrates external graphics clocking requirements
• Available center spread LCD clock for optimized
display screen EMI reduction
• Best in the industry pread pectrum technology
for optimum system EMI reduction
BCLK/HPLL, 100 MHz
DOT 96, 96 MHz
LPC
3 PCIe x 1
PCIe x 1
PCIe, 100 MHz
HCSL
5
SATA75, 75 MHz
USB-48, 48 MHz
SYSCLK-25, 25 MHz
PCI, 33.3 MHz
PCI Devices
2
CLOCK AND OSCILL ATOR SELEC TOR / 9
Embedded Intel x86 Clocks (cont.)
CLOCK
PART NUMBER CONTROL INPUT/
OUTPUTS
INPUT
FREQUENCY
(MHz)
OUTPUT
FREQUENCY (MHz)
VDD
VDDO
OUTPUT
PACKAGE
SL28EB636A
12 MHz, 14.318 MHz, 25 MHz, 27 MHz, 33
MHz, 48 MHz, 75 MHz, 96 MHz,
83.33 MHz-166 MHz, 100 MHz
SL28EB717
SL28EB719
SL28EB731A
SL28EB740
SL28EB742
SL28EB742A
Pin/I2C
Pin/I2C
1/13
1/13
25 MHz
25 MHz
3.3 V
3.3 V
3.3 V
3.3 V
LVCMOS, HCSL
LVCMOS, HCSL
48QFN
12 MHz, 14.318 MHz, 25 MHz, 27 MHz, 33
MHz, 48 MHz, 75 MHz, 96 MHz,
83.33 MHz-166 MHz, 100 MHz
TSSOP48
12 MHz, 14.318 MHz, 25 MHz,
33 MHz, 48 MHz, 75 MHz, 96 MHz,
83.33 MHz-166 MHz, 100 MHz
Pin/I2C
Pin/I2C
1/16
1/16
25 MHz
3.3 V
3.3 V
3.3 V
3.3 V
LVCMOS, HCSL
LVCMOS, HCSL
TSSOP56
QFN56
14.3 MHz, 33 MHz, 48 MHz, 96 MHz, 100
MHz, 133 MHz, 166 MHz
14.318 MHz
10 / CLOCK AND OSCILL ATOR SELEC TOR
EMI Reduction Clocks
Silicon Labs’ programmable spread spectrum clock generators feature a wide range of programming options allowing
system designers to minimize EMI at the application level. Configurable parameters include spread spectrum percentage/
modulation rate, programmable edge rates, programmable output impedance and programmable skew.
EMI REDUCTION CLOCK FEATURES
• Output frequencies from 1 to 200 MHz
• CLKOUT, REFCLK or SSCLK output options
• CLKIN or XO input options
• On-chip programmable crystal capacitive
load (CL): 8 to 20 pF
• User-definable control pins Powerdown,
Output Enable, Spread Enable, Frequency
Select, Spread Select control pins
• 7 programmable tr/tf options
• 8 to 48 MHz crystal input range
• 1 to 166 MHz clock input range
• Spread percent from 0 to 5.0%
• Down or center spread options
• Smallest SSCG clock on the market
(TDFN6 1.2 mm x 1.4 mm)
• Spread modulation frequency from 16 to 128 kHz
WLAN
—OR—
LCD Panel
CLOCK
PART NUMBER CONTROL INPUT/
OUTPUTS
INPUT
FREQUENCY
(MHz)
OUTPUT
FREQUENCY
(MHz)
PHASE
JITTER
(RMS)
VDD
VDDO
OUTPUT
PACKAGE
SL15300
Pin
1/4
1/2
3 - 166 (Clock), 8 - 48 (Xtal)
27 (Xtal)
3 - 200 MHz
—
—
1.8, 2.5, 3.3 V
3.3 V
—
—
LVCMOS
TSSOP8
TDFN10
SL16020DC
Pin/I2C
27 MHz, 100 MHz
LVCMOS
LVCMOS, LVDS,
Si5335
Pin
1/4
10 - 350 (Clock), 25/27 (Xtal)
1 - 350 MHz
1.0 ps
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V LVPECL, HCSL, SSTL,
HSTL, CML
QFN24
Si51210
Si51211
Si51214
Pin
Pin
Pin
1/2
2/3
1/2
3 - 166 (Clock), 8 - 48 (Xtal)
3 - 166 (Clock), 8 - 48 (Xtal)
3 - 166 (Clock), 8 - 48 (Xtal)
3 - 200 MHz
3 - 200 MHz
3 - 200 MHz
—
—
—
2.5 - 3.3 V
2.5 - 3.3 V
1.8 V
—
1.8, 2.5, 3.3 V
—
LVCMOS
LVCMOS
LVCMOS
TDFN6
TDFN8
TDFN6
Si51219
Si52142
Si52143
Si52144
Si52146
Si52147
Pin
2/3
1/3
1/5
1/4
1/6
1/9
3 - 166 (Clock), 8 - 48 (Xtal)
3 - 200 MHz
100 MHz, 25 MHz
100 MHz, 25 MHz
100 MHz
—
2.5 - 3.3 V
3.3 V
1.8, 2.5, 3.3 V
3.3 V
LVCMOS
HSCL, LVCMOS
HSCL, LVCMOS
HSCL
TSSOP8
QFN24
QFN24
QFN24
QFN32
QFN48
Pin/I2C
Pin/I2C
Pin/I2C
Pin/I2C
Pin/I2C
25 MHz
25 MHz
25 MHz
25 MHz
25 MHz
1.0 ps
1.0 ps
1.0 ps
1.0 ps
1.0 ps
3.3 V
3.3 V
3.3 V
3.3 V
100 MHz
3.3 V
3.3 V
HSCL
100 MHz
3.3 V
3.3 V
HSCL
CLOCK AND OSCILL ATOR SELEC TOR / 11
Clock Distribution
WEB-CONFIGURABLE CUSTOM CLOCK BUFFERS AVAILABLE AT: www.silabs.com/ClockBuilder
Fanout Buffers/Level Translators
Silicon Labs’ low jitter clock buffers produce multiple copies of an input clock at the same frequency with minimal additive
jitter. LVDS, LVPECL, HCSL, CML, LVCMOS, SSTL and HSTL buffers are available, including devices that support multiple
formats per device.
UNIVERSAL BUFFER FEATURES
• Wide operating frequency DC - 1.25 GHz
• 2-10 differential or 4-20 LVCMOS outputs
• Universal input stage accepts any differential or single-
ended input
• Pin-selectable signal format per bank (LVPECL,
Gbe PHY
Low Power LVPECL, LVDS, CML, HCSL, LVCMOS)
• Ultra-low additive jitter: 45 fs rms (12 kHz - 20 MHz)
Gbe PHY
FPGA
• 2:1 mux with glitchless clock switching
• Synchronous output enable/Individual output enable
• Integrated voltage level translation
• Selectable LVCMOS drive strength to tailor jitter
and EMI performance
SoC/MPU
• Optional output clock division: div-1, div-2, div-4
• Low output-output skew: <50 ps
• Excellent PSRR
• Independent VDD and VDDO: 1.8, 2.5 or 3.3 V
CLOCK ADDITIVE
INPUT
FREQUENCY
(MHz)
OUTPUT
FREQUENCY
(MHz)
PART NUMBER CONTROL INPUT/
JITTER
VDD
VDDO
OUTPUT
PACKAGE
OUTPUTS (RMS)
Si53302
Si53301
Si53306
Si53315
Pin
Pin
2/10
2/6
100 fs
100 fs
1 - 725 MHz
1 - 725 MHz
1 - 725 MHz
1 - 725 MHz
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5 V
1.8, 2.5 V
LVCMOS, LVDS, LVPECL, HCSL, CML
LVCMOS, LVDS, LVPECL, HCSL, CML
QFN44
QFN44
Pin
2/10
100 fs
1 - 1250 MHz
1 - 1250 MHz
1.8, 2.5, 3.3 V
1.8, 2.5 V
LVCMOS, LVDS, LVPECL, HCSL, CML
QFN44
Si53320
Si53360
Pin
Pin
2/10
1/8
1/2
1/4
1/6
1/9
1/4
1/4
1/5
1/9
1/9
2/4
100 fs
100 fs
1.0 ps
1.0 ps
1.0 ps
1.0 ps
—
1 - 725 MHz
1 - 200 MHz
100 MHz
1 - 725 MHz
1 - 200 MHz
100 MHz
2.5, 3.3 V
1.8, 2.5, 3.3 V
3.3 V
2.5, 3.3 V
1.8, 2.5 V
3.3 V
3.3 V
3.3 V
3.3 V
—
LVPECL
LVCMOS
HCSL
TSSOP20
TSSOP16
QFN24
Si53152
Pin/I2C
Pin/I2C
Pin/I2C
Pin/I2C
Pin
Si53154
100 MHz
100 MHz
3.3 V
HCSL
QFN24
Si53156
100 MHz
100 MHz
3.3 V
HCSL
QFN32
Si53159
100 MHz
100 MHz
3.3 V
HCSL
QFN48
SL2304NZ
SL23EP04NZ
SL2305NZ
SL2309NZ
SL23EP09NZ
SL28PCIe14
1 - 140 MHz
DC - 220 MHz
1 - 140 MHz
DC - 140 MHz
1 - 220 MHz
25 MHz/100 MHz
1 - 140 MHz
DC - 220 MHz
1 - 140 MHz
DC - 140 MHz
1 - 220 MHz
100 MHz
3.3 V
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
HCSL
8TSSOP/8SOIC
TSSOP8
Pin
—
2.5 V, 3.3 V
3.3 V
—
Pin
—
—
TSSOP8/SOIC8
SOIC16
Pin
—
3.3 V
3.3 V
—
Pin
Pin/I2C
—
2.5 V, 3.3 V
3.3 V
TSSOP16/SOIC16
QFN32
1.0 ps
3.3 V
Si5330
Si5330F
Si5335
Pin
Pin
Pin
Pin
1/4
1/8
1/4
1/3
150 fs
—
5 - 710 MHz
5 - 200 MHz
1 - 350 MHz
10 - 52 MHz
5 - 710 MHz
5 - 200 MHz
1 - 350 MHz
10 - 52 MHz
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
—
LVPECL, LVDS, HCSL, SSTL, HSTL
LVCMOS
QFN24
QFN24
QFN24
TDFN10
LVCMOS, LVDS, LVPECL,
HCSL, SSTL, HSTL,CML
150 fs
—
SL18860DC
LVCMOS
12 / CLOCK AND OSCILL ATOR SELEC TOR
Zero Delay Buffers
Silicon Labs’ zero delay clock buffers are used in applications that require zero propagation delay between the input and
output clocks. Silicon Labs’ zero delay buffers provide low power consumption and simplify the distribution of spread
spectrum clocks.
ZERO DELAY BUFFER FEATURES
• Low propagation delay
• Low output-to-output skew
• Low device-to-device skew
• Low output jitter
• Drive strength options
• Wide operation frequency from 10 to 220 MHz
• 3.3 V to 2.5 V power supply range
• Low power dissipation
RJ-45 Port 1
25 MHz
RJ-45 Port 2
25 MHz
25 MHz
RJ-45 Port 15
25 MHz
RJ-45 Port 16
CLOCK
PART NUMBER CONTROL INPUT/
OUTPUTS
INPUT
FREQUENCY
(MHz)
PHASE
JITTER
(RMS)
OUTPUT
FREQUENCY (MHz)
VDD
VDDO
OUTPUT
PACKAGE
SL2305
SL2309
Pin
Pin
Pin
Pin
Pin
Pin
1/5
1/9
1/4
1/5
1/8
1/9
1 - 140 MHz
10 - 140 MHz
10 - 220 MHz
10 - 220 MHz
10 - 220 MHz
10 - 220 MHz
1 - 140 MHz
10 - 140 MHz
10 - 220 MHz
10 - 220 MHz
10 - 220 MHz
10 - 220 MHz
—
—
—
—
—
—
3.3 V
—
—
—
—
—
—
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
TSSOP8/SOIC8
TSSOP16/SOIC16
SOIC8
3.3 V
SL23EP04
SL23EP05
SL23EP08
SL23EP09
2.5 V, 3.3 V
2.5 V, 3.3 V
2.5 V, 3.3 V
2.5 V, 3.3 V
TSSOP8/SOIC8
TSSOP16/SOIC16
TSSOP16/SOIC16
CLOCK AND OSCILL ATOR SELEC TOR / 13
PCI Express Clock Buffers (PCIe)
Silicon Labs offers the lowest power, highest performance PCI-Express clock generators in the market. All devices in the
portfolio feature low power push-pull output buffer technology, providing benefits of low power consumption, reduced
external terminating resistors and smaller packaging. To optimize performance, the devices support programmable drive
strength, rise/fall times and output impedance. Basic HCSL PCIe and high-performance differential clocks and buffers are
available. Support for down spread spectrum clock generation is also provided.
PCIe CLOCK FEATURES
• Full portfolio of PCI Express (PCIe) Gen 1/2/3 clocks
and buffers
• Available hardware strapping pin for spread enable
• I2C/SMBus programmable
• All products utilize push-pull HCSL output buffers
• Fully integrated termination resistors on
PCIe outputs
• Also supports LVPECL, LVDS, or CML levels
• Industrial temperature grade
• Individual output enable control
• Low power consumption
• Small form factor QFN packaging
• Programmable spread spectrum
100 MHz HCSL
100 MHz HCSL
100 MHz HCSL
100 MHz HCSL
100 MHz HCSL
CLOCK
INPUT
FREQUENCY
(MHz)
OUTPUT
FREQUENCY
(MHz)
PHASE
JITTER
(RMS)
PART NUMBER CONTROL INPUT/
OUTPUTS
VDD
VDDO
OUTPUT
PACKAGE
Si53102
Si53154
—
1/2
1/4
1/6
1/9
1/4
1/8
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
0.5 ps
1.0 ps
1.0 ps
1.0 ps
—
2.5, 3.3 V
3.3 V
—
HSCL
HSCL
HSCL
HSCL
HCSL
HCSL
TDFN8
QFN24
Pin/I2C
Pin/I2C
Pin/I2C
Pin/I2C
Pin/I2C
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Si53156
3.3 V
QFN32
Si53159
3.3 V
QFN48
CY28400-2
CY28800
3.3 V
SSOP28/TSSOP28
SSOP48
—
3.3 V
14 / CLOCK AND OSCILL ATOR SELEC TOR
Jitter Attenuators/Clock Cleaners
REQUEST SAMPLES AND DOWNLOAD DOCUMENTATION AT: www.silabs.com/clocks
Silicon Labs’ precision clocks generate any output frequency from any input frequency while providing jitter attenuation
and clock distribution in high-performance timing applications requiring sub 0.5 ps jitter performance. The devices accept
multiple clock inputs ranging from 2 kHz to 710 MHz and generate multiple low jitter, independent, synchronous clock outputs
ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The precision clocks are based on Silicon Labs’ proven
third-generation DSPLL® technology, which generates any output frequency from any input frequency with 300 fs rms jitter
performance in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components.
JITTER ATTENUATOR FEATURES
• Generates any output frequency from any input frequency
• Ultra-low jitter: 290 fs RMS
• Best-in-class PSRR
• I2C/SPI or pin-controlled
• 1-DSPLL and 4-DSPLL versions available
• Integrated loop filter with selectable loop bandwidth
• Hitless switching with phase buildout (auto/manual)
• Freerun or synchronous operating modes
• User-selectable output clock signal format
(LVPECL, LVDS, CML, CMOS)
• Single supply: 1.8, 2.5 or 3.3 V 10% operation
• Easy-to-use DSPLLsim* configuration software
*see page 16 for more about our DSPLLsim software
TX
RX
CLOCK
INPUT
OUTPUT
FREQUENCY
(MHz)
JITTER
(12 KHz TO
20 MHz)
PART
NUMBER PLLS
# OF
PLL
HITLESS DIGITAL FREE SIGNAL
CONTROL INPUTS/ FREQUENCY
PACKAGE
BANDWIDTH SWITCHING HOLD RUN FORMAT
OUTPUTS
(MHz)
Si5315
Si5317
Si5319
Si5324
Si5326
Si5327
Si5368
Si5369
Si5374
Si5375
Si5376
1
1
1
1
1
1
1
1
4
4
4
Pin
Pin
2/2
0.008 - 644
0.008 - 644
1 - 710
450 fs rms typ
290 fs rms typ
300 fs rms typ
290 fs rms typ
300 fs rms typ
500 fs rms typ
300 fs rms typ
300 fs rms typ
410 fs rms typ
410 fs rms typ
410 fs rms typ
60 Hz - 8 kHz
60 Hz - 8 kHz
60 Hz - 8 kHz
4 Hz - 525 Hz
60 Hz - 8 kHz
4 Hz - 525 Hz
60 Hz - 8 kHz
4 Hz - 525 Hz
4 Hz - 525 Hz
60 Hz - 8 kHz
60 Hz - 8 kHz
•
•
•
QFN36
QFN36
QFN36
QFN36
QFN36
QFN36
TQFP100
TQFP100
BGA80
BGA80
BGA80
1/2
1/1
2/2
2/2
2/2
4/5
4/5
8/8
4/4
8/8
1
-
710
I2C/SPI
I2C/SPI
I2C/SPI
I2C/SPI
I2C/SPI
I2C/SPI
I2C
0.002 710
-
0.002 - 1417
0.002 - 1417
0.002 - 1417
0.002 - 808
0.002 - 1417
0.002 - 1417
0.002 - 808
0.002 - 808
0.002 - 808
•
•
•
•
•
•
•
•
•
0.002 - 710
0.002 - 710
0.002 - 710
0.002 - 710
0.002 - 710
0.002 - 710
0.002 - 710
0.002 - 710
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CMOS,
LVDS,
LVPECL,
CML
I2C
I2C
•
CLOCK AND OSCILL ATOR SELEC TOR / 15
Synchronous Ethernet Clock
REQUEST SAMPLES AND DOWNLOAD DOCUMENTATION AT: www.silabs.com/synce
SyncE is used to distribute accurate timing in GbE, 10 GbE, 40 GbE and 100 GbE Carrier Ethernet systems. Every Carrier
Ethernet switch/router requires a high-performance SyncE clock to distribute timing and provide a low jitter Ethernet PHY
reference clock. The Si5328 is the industry’s lowest jitter, fully compliant SyncE clock, making it ideal for Ethernet PHYs
from GbE to 100 GbE. Operating from a single 2.5 or 3.3 V supply, the Si5328 is ideal for providing clock multiplication,
wander filtering and jitter attenuation, in high-performance Synchronous Ethernet-enabled switches and routers.
SYNCE CLOCK FEATURES
• Fully compliant with SyncE clock requirements (ITU G.8262)
• Generates any output frequency (8 kHz to 808 MHz) from
any input frequency (8 kHz to 710 MHz)
• Integrated loop filter with selectable loop bandwidths:
0.1 Hz; 1 to 10 Hz
• Compact factor 6 mm x 6 mm QFN
• Dual clock outputs with 0.3 ps RMS jitter and any signal
format (LVDS, LVPECL, CML, CMOS)
• Reprogrammable to any frequency without BOM changes
25 MHz System CLK
Telecom or Ethernet System backplane
Switch
SoC
REFCLK 125
MHz Switch
RX
CLK
RX
CLK
RX
CLK
RX
CLK
125 MHz TXCLK
to each PHY
TCXO
Data
Data
Data
Data
INPUT CLOCK
FREQUENCY
RANGE
OUTPUT CLOCK
FREQUENCY
RANGE
PHASE
JITTER
(RMS TYP)
EEC OPTION 1 AND 2
WANDER FILTERING
PART NUMBER
# OF INPUTS
# OUTPUT CLOCKS
PACKAGE
Si5328B
Si5328C
2
2
8 kHz - 710 MHz
8 kHz - 346 MHz
2
2
8 kHz - 808 MHz
0.3 ps
Yes
Yes
8 kHz - 346 MHz 0.3 ps
16 / CLOCK AND OSCILL ATOR SELEC TOR
XOs/VCXOs
REQUEST CUSTOM PART NUMBERS AND SAMPLES AT: www.silabs.com/VCXOpartnumber
Silicon Labs’ crystal oscillators and voltage controlled crystal oscillators (XO/VCXOs) leverage advanced DSPLL® circuitry to provide
a low jitter clock at any frequency from 100 kHz to 1.4 GHz. Unlike a traditional XO, where a different crystal is required for each
output frequency, Silicon Labs’ XO/VCXOs use one fixed frequency crystal to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability, while providing best-in-
class jitter performance and supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments. All
devices are factory configurable for a wide variety of user specifications including frequency, supply voltage, output format and
stability, thereby eliminating long lead times associated with custom oscillators.
XO/VCXO FEATURES
Cable
Equalizer
• Wide frequency range: 100 kHz to 1.4 GHz
• Samples of any XO/VCXO available in 2 weeks
• Superior jitter performance: <0.3 ps rms
• Excellent frequency stability with superior
initial accuracy
3G/HD/
SD-SDI
Cable
Driver
YCbCr
YCbCr
Pclk, HVF
• Single, dual, quad and I2C programmable
3G/HD/
SD-SDI
configurations
HSYNC
• LVPECL, LVDS, CML, HCSL and CMOS options
• 1.8, 2.5, or 3.3 V options
Genlock
Sync Input
• Industry standard, ROHS-compliant 5 x 7 mm
and 3.2 x 5 mm packages and pinouts
• Industrial temperature range: -40 to 85 °C
Master Sync
Generator
Fixed Frequency XO/VCXOs
RMS PHASE
JITTER
STABILITY/APR
(PPM)
PART NUMBER
TYPE
FREQUENCY
FREQUENCY RANGE
OUTPUT FORMAT
PACKAGE
Si510/1
Si512/3
Si515
XO
XO
Single
Dual
0.8 ps
0.8 ps
1.0 ps
1.0 ps
0.3 ps
0.3 ps
0.3 ps
0.5 ps
0.5 ps
0.5 ps
0.5 ps
0.7 ps
0.7 ps
±30, ±50, ±100
±30 to ±100
LVPECL,
LVDS,
5 mm x 7 mm and
3.2 mm x 5 mm
6-pad
0.1 - 250 MHz
HCSL,
Dual CMOS,
LVCMOS,
VCXO
VCXO
XO
Single
Dual
Si516
Si530/1
Si532/3
Si534
Single
Dual
5 x 7 mm 6-pad
5 x 7 mm 6-pad
5 x 7 mm 8-pad
5 x 7 mm 6-pad
5 x 7 mm 6-pad
5 x 7 mm 8-pad
5 x 7 mm 6-pad
5 x 7 mm 6-pad
5 x 7 mm 8-pad
XO
10 - 1417 MHz
10 - 1417 MHz
10 - 810 MHz
±20, ±31.5, ±61.5
±12 to ±375
XO
Quad
Single
Dual
Si550
VCXO
VCXO
VCXO
XO
LVPECL,
LVDS,
Si552
CML,
LVCMOS
Si554
Quad
Single
Single
Quad
Si590/1
Si595
±20, ±30, ±50, ±100
±10 to ±370
VCXO
VCXO
Si597
I2C Programmable XO/VCXOs
FREQUENCY
RANGE
TUNING
RESOLUTION
RMS PHASE
JITTER
STABILITY/APR
(PPM)
OUTPUT
FORMAT
SUPPLY
VOLTAGE (V)
PART NUMBER
TYPE
PACKAGE
HCSL, LVPECL, LVDS,
LVCMOS, Dual CMOS,
5 x 7 mm/
Si514
XO
0.1 - 250 MHz
26 PPT
0.8 ps
±30, ±50, ±100
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
3.2 x 5 mm 6-pad
Si570
Si571
Si598
Si599
XO
VCXO
XO
0.3 ps
0.5 ps
0.5 ps
0.7 ps
±20, ±31.5, ±62.5
±12 to ±375
5 x 7 mm 8-pad
5 x 7 mm 8-pad
5 x 7 mm 8-pad
5 x 7 mm 8-pad
LVPECL, LVDS,
CML, LVCMOS
10 - 1417 MHz
10 - 810 MHz
80 PPT
28 PPT
±30, ±50, ±100
±10 to ±370
LVPECL, LVDS,
CML, LVCMOS
1.8, 2.5, 3.3 V
VCXO
CLOCK AND OSCILL ATOR SELEC TOR / 17
Hardware and Software Support
FULL DOCUMENTATION, SOFTWARE AND APPLICATION NOTES ARE AVAILABLE AT: www.silabs.com/timing
Clock and Oscillator Development Kits
Silicon Labs offers complete tools to help designers throughout the entire development process. Both clock and
oscillator solutions offer hardware and software platforms to easily set up, configure and evaluate overall device
performance.
Custom Clock Generator Configurator
The ClockBuilder Desktop software allows you to configure a
custom clock and generate the NVM file the factory needs in order
to manufacture the custom part.
Configuration and control of Silicon Labs clock generators is mainly
handled through the I2C/SMBus interface. The device also provides
the option of storing a user-definable clock configuration in its
non-volatile memory (NVM), which becomes the default clock
configuration at power-up. Changes to the default configuration
can always be made through the I2C interface.
Si5374/5/6 JITTER
Si5338 CLOCK GENERATION
Si52144 PCI EXPRESS
EVALUATION BOARD
ATTENUATING CLOCK
EVALUATION BOARD
EVALUATION BOARD
18 / CLOCK AND OSCILL ATOR SELEC TOR
Silicon Labs Makes Finding the Right Part Easy!
QUICKLY BUY OR SAMPLE PRODUCTS ON OUR WEBSITE AT www.silabs.com/custom-timing
Clock and Oscillator Design Services
Silicon Labs offers the industry’s broadest portfolio of
embedded clocks and oscillators for communications,
computing, broadcast video and consumer applications
with the shortest lead times in the industry, with no
minimum order quantities or NRE fees. Silicon Labs also
provides a comprehensive clock tree design service to
simplify component selection. Propsals are generated
within three business days.
Parametric Search iPad App
Take the parametric search mobile! The Silicon Labs Parametric Search iPad app
makes it easy to find exactly what you need for your next embedded design.
Quickly jump between microcontroller, clock, oscillator, digital isolator, and
isolated gate driver product families. Filter results using common technical and
application requirements. Access data sheets and other documentation directly
in the app and download to iBooks for offline access. Browse detailed product
information – features, applications, block diagrams and even order samples and
development kits, all from within the app. Offline access available—refresh data
the next time you’re connected to the Internet. www.silabs.com/parametric-search
Industry’s Shortest Lead Times
Low-jitter, high-performance, custom samples are available overnight, and to help you get to market
faster, production quantities ship in less than 2–4 weeks. Silicon Labs’ complete portfolio of industry-
leading XOs, VCXOs, clock generators, jitter attenuating clocks and clock buffers set a new standard for
flexibility, performance and lead time.
2 WEEK
LEAD
TIMES
Traditional Solution - 10 to 16 weeks
Quartz Blank Fab
Assembly
Blank Processing
Hermetic Seal & Test
Enter
Order
Cleaning
X-Ray
Plating
Die Attach
Wirebond
Frequency Fine Tune
Vacuum Bake
Seal
Final Test
Crystal Cut
Lapping
Polishing
Unprogrammed Stock
S
i
5
9
x
Enter
Order
Final
Programming
Silicon Labs Solution - 2 to 4 weeks
Silicon Labs’ products are designed and
manufactured to ISO 9001, ISO 14001
and ISO/TS 16949 standards.
ISO 9001
ISO 14001
ISO/TS 16949
Quality Management System
Design and Manufacture of Integrated Circuits
Certificate Registration No: 951 08 4762
Environmental Management System
Design and Manufacture of Integrated Circuits
Certificate Registration No: 951 09 4998
Quality Management System for
Manufacture of Integrated Circuits and Re-
lated Products for Automotive Applications
Certificate Registration No.: 12 111 33114 TMS
IATF Certificate No.: 0080212
XX%
© 2014, Silicon Laboratories Inc. ClockBuilder, DSPLL, MultiSynth, Silicon Labs and the Silicon Labs logo are trademarks or registered trademarks of Silicon Laboratories Inc. All other product or service names
are the property of their respective owners. For the most up to date information please see your sales representative or visit our website at www.silabs.com.
WEB, June 2014, Rev I SEL-CLK
SILICON LABS
| 400 W. CESAR CHAVEZ | AUSTIN, TX 78701 | USA | +1 (512) 416-8500 | SILABS.COM
相关型号:
SI52111-A1-GM2
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229, TDFN-10
SILICON
SI52111-A1-GT
Processor Specific Clock Generator, 100MHz, CMOS, PDSO8, ROHS COMPLIANT, MO-153AA, TSSOP-8
SILICON
SI52111-A1-GTR
Processor Specific Clock Generator, 100MHz, CMOS, PDSO8, ROHS COMPLIANT, MO-153AA, TSSOP-8
SILICON
SI52111-A2-GM2
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229, TDFN-10
SILICON
SI52111-A2-GM2R
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229, TDFN-10
SILICON
SI52111-B3-GM2
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229, TDFN-10
SILICON
©2020 ICPDF网 联系我们和版权申明