Si5324B-C-GM_技术文档

Si5324

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/

JITTER ATTENUATOR

Features



Generates any frequency from

2 kHz to 945 MHz and select

frequencies to 1.4 GHz from an

input frequency of 2 kHz to

710 MHz

Ultra-low jitter clock outputs as low

as 290 fs rms (12 kHz–20 MHz),

320 fs rms (50 kHz–80 MHz)

Integrated loop filter with

selectable loop bandwidth

(4– 525 Hz)



Freerun, Digital Hold operation

Configurable signal format per

output (LVPECL, LVDS, CML,

CMOS)

Support for ITU G.709 and custom

FEC ratios (255/238, 255/237,

255/236, 239/237, 66/64, 239/238,

15/14, 253/221, 255/238)



LOL, LOS, FOS alarm outputs



I²C or SPI programmable

On-chip voltage regulator with high

PSNR

Single supply 1.8 ±5%, 2.5 ±10%,

or 3.3 V ±10%



Meets ITU-T G.8251 and Telcordia

GR-253-CORE jitter specification

Hitless input clock switching with

phase build-out

Ordering Information:



See page 63.



Small size: 6 x 6 mm 36-lead QFN

Pb-free, ROHS-compliant

Pin Assignments

Applications



Broadcast video –3G/HD/SD-SDI,  1/2/4/8/10G Fibre Channel line

Genlock cards

Packet Optical Transport Systems  GbE/10/40/100G Synchronous

36 35 34 33 32 31 30 29 28

RST

NC

1

2

3

4

5

6

7

8

9

27 SDI

26

(P-OTS), MSPP

Ethernet (LAN/WAN)

Data converter clocking

Wireless base stations

Test and measurement

A2_SS

25 A1

INT_C1B

C2B

OTN/OTU-1/2/3/4 Asynchronous

Demapping (Gapped Clock)

SONET OC-48/192/768,

SDH/STM-16/64/256 line cards



24

23

A0

GND

Pad

VDD

XA

SDA_SDO

22 SCL

XB

21

20

CS_CA

GND

NC

19 GND

10 11 12 13 14 15 16 17 18

Description

The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier

for applications requiring sub 1 ps jitter performance with loop bandwidths

between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging

from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz

to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided

down separately from a common source. The Si5324 can also use its

external reference as a clock source for frequency synthesis. The device

provides virtually any frequency translation combination across this

operating range. The Si5324 input clock frequency and clock multiplication

ratio are programmable via an I²C or SPI interface. The Si5324 is based on

Silicon Laboratories' 3rd-generation DSPLL^®technology, which provides

any-frequency synthesis and jitter attenuation in a highly integrated PLL

solution that eliminates the need for external VCXO and filter components.

The DSPLL loop bandwidth is digitally programmable, providing jitter

performance optimization at the application level. The Si5324 is ideal for

providing clock multiplication and jitter attenuation in high performance

timing applications.

Rev. 1.0 1/13

Si5324

Functional Block Diagram

Xtal or Refclock

÷ N31

÷ N32

CKIN1

CKIN2

÷ NC1_LS

÷ NC2_LS

CKOUT1

CKOUT2

®

DSPLL

÷N1_HS

Xtal/Refclock

÷ N2

Loss of Signal/

Frequency Offset

Loss of Lock

VDD (1.8, 2.5, or 3.3 V)

GND

Control

Signal Detect

I²C/SPI Port

Clock Select

Skew Adjust

Device Interrupt

Rate Select

2

Rev. 1.0

Si5324

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.2. Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.3. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.1. ICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

8. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

10.1. Si5324 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Rev. 1.0

3

Si5324

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Ambient Temperature

T

-40

25

85

C

V

A

Supply Voltage during

Normal Operation

V

3.3 V Nominal

2.97

3.3

3.63

DD

2.5 V Nominal

1.8 V Nominal

2.25

1.71

2.5

1.8

2.75

1.89

V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.

V

SIGNAL +

Single-Ended

Peak-to-Peak Voltage

V

_ICM, V_OCM

Differential I/Os

V_ISE,V_OSE

SIGNAL –

(SIGNAL +) – (SIGNAL –)

Differential Peak-to-Peak Voltage

V ,V_OD

ID

V_ICM, V_OCM

t

SIGNAL +

SIGNAL –

V = (SIGNAL+) – (SIGNAL–)

ID

Figure 1. Differential Voltage Characteristics

80%

20%

CKIN, CKOUT

t_F

t_R

Figure 2. Rise/Fall Time Characteristics

4

Rev. 1.0

Si5324

Table 2. DC Characteristics

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

1

Supply Current

I

LVPECL Format

622.08 MHz Out

—

251

279

mA

DD

Both CKOUTs Enabled

LVPECL Format

622.08 MHz Out

1 CKOUT Enabled

—

217

204

194

165

243

234

220

—

mA

CMOS Format

19.44 MHz Out

Both CKOUTs Enabled

CMOS Format

19.44 MHz Out

1 CKOUT Enabled

Disable Mode

2

CKINn Input Pins

Input Common Mode

Voltage (Input Thresh-

old Voltage)

V

1.8 V ± 5%

2.5 V ± 10%

3.3 V ± 10%

Single-ended

0.9

1

—

40

—

1.4

1.7

1.95

60

V

ICM

1.1

20

0.2

V

Input Resistance

CKN

kΩ

RIN

Single-Ended Input

Voltage Swing

(See Absolute Specs)

V

f

< 212.5 MHz

—

V

ISE

CKIN

PP

See Figure 1.

> 212.5 MHz

0.25

0.2

—

CKIN

See Figure 1.

< 212.5 MHz

CKIN

Differential Input

Voltage Swing

(See Absolute Specs)

V

ID

See Figure 1.

fCKIN > 212.5 MHz

See Figure 1.

0.25

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥ 2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference

Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Rev. 1.0

5

Si5324

Table 2. DC Characteristics (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

3,5

Output Clocks (CKOUTn)

Common Mode

CKO

LVPECL 100  load line-

V

1.42

–

—

V –1.25

DD

V

VCM

DD

to-line

Differential Output

Swing

CKO

LVPECL 100  load line-

1.1

0.5

1.9

0.93

500

—

V

VD

PP

to-line

Single Ended Output

Swing

CKO

LVPECL 100  load line-

—

V

VSE

PP

to-line

Differential Output

Voltage

CKO

CML 100  load line-to-

350

—

425

mV

VD

PP

line

Common Mode Output

Voltage

CML 100  load line-to-

V

-0.36

DD

V

VCM

line

Differential Output

Voltage

CKO

LVDS

100  load line-to-line

500

350

1.125

—

700

425

1.2

900

500

1.275

—

mV

VD

PP

Low Swing LVDS

100  load line-to-line

Common Mode Output

Voltage

CKO

LVDS 100 load line-to-

V

VCM

line

Differential Output

Resistance

CKO

CML, LVPECL, LVDS

200



RD

Output Voltage Low

CKO

CMOS

—

0.4

—

V

VOLLH

Output Voltage High

V

= 1.71 V

0.8 x

VOHLH

DD

CMOS

V

DD

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥ 2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference

Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

6

Rev. 1.0

Si5324

Table 2. DC Characteristics (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

CKO

Test Condition

Min

Typ

Max

Unit

Output Drive Current

(CMOS driving into

ICMOS[1:0] = 11

—

7.5

—

mA

IO

V

= 1.8 V

DD

CKO

or CKO

high. CKOUT+ and

CKOUT– shorted

externally)

for output low

VOL

ICMOS[1:0] = 10

= 1.8 V

—

5.5

3.5

1.75

32

—

mA

for output

VOH

V

DD

ICMOS[1:0] = 01

= 1.8 V

V

DD

ICMOS[1:0] = 00

= 1.8 V

V

DD

ICMOS[1:0] = 11

= 3.3 V

V

DD

ICMOS[1:0] = 10

= 3.3 V

24

V

DD

ICMOS[1:0] = 01

= 3.3 V

16

V

DD

ICMOS[1:0] = 00

8

V

= 3.3 V

DD

2-Level LVCMOS Input Pins

Input Voltage Low

Input Voltage High

Notes:

V

= 1.71 V

= 2.25 V

= 2.97 V

= 1.89 V

= 2.25 V

= 3.63 V

—

0.5

0.7

0.8

—

V

IL

DD

—

V

1.4

1.8

2.5

IH

—

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥ 2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference

Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Rev. 1.0

7

Si5324

Table 2. DC Characteristics (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

3-Level Input Pins

Input Voltage Low

Symbol

Test Condition

Min

Typ

Max

Unit

4

V

—

0.15 x V

0.55 x V

V

ILL

DD

Input Voltage Mid

Input Voltage High

V

0.45 x

IMM

V

DD

V

0.85 x

—

V

IHH

ILL

V

DD

Input Low Current

Input Mid Current

Input High Current

I

See Note 4

–20

–2

—

+2

20

µA

I

IMM

I

—

IHH

LVCMOS Output Pins

Output Voltage Low

V

IO = 2 mA

—

0.4

—

V

OL

V

= 1.71 V

DD

Output Voltage Low

Output Voltage High

Notes:

IO = 2 mA

= 2.97 V

V

DD

V

IO = –2 mA

= 1.71 V

V

–

DD

0.4

OH

V

DD

IO = –2 mA

= 2.97 V

V

–

—

DD

0.4

V

DD

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal VDD ≥ 2.5 V.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference

Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

8

Rev. 1.0

Si5324

Table 3. AC Characteristics

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Single-Ended Reference Clock Input Pin XA (XB with cap to GND)

Input Resistance

XA

RATE[1:0] = LM, ML, MH,

or HM, ac coupled

—

12

—

k

RIN

Input Voltage Swing

XA

RATE[1:0] = LM, ML, MH,

or HM, ac coupled

0.5

1.2

V

VPP

PP

Differential Reference Clock Input Pins (XA/XB)

Input Voltage Swing

XA/XB

RATE[1:0] = LM, ML, MH,

or HM

0.5

—

2.4

V

VPP

PP

CKINn Input Pins

Input Frequency

CKN

0.002

40

—

710

60

MHz

%

F

Input Duty Cycle

(Minimum Pulse Width)

CKN

Whichever is smaller

(i.e., the 40% / 60%

limitation applies only

to high frequency

clocks)

DC

2

—

3

ns

pF

ns

Input Capacitance

CKN

—

CIN

Input Rise/Fall Time

CKN

20–80%

11

TRF

See Figure 2

CKOUTn Output Pins

(See ordering section for speed grade vs frequency limits)

Output Frequency

(Output not configured

for CMOS or

CKO

N1  6

N1 = 5

N1 = 4

0.002

970

—

945

1134

1.4

MHz

GHz

MHz

F

Disabled)

1.213

—

Maximum Output

Frequency in CMOS

Format

212.5

F

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit

the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

to submit a technical support request regarding the lock time of your frequency plan.

Rev. 1.0

9

Si5324

Table 3. AC Characteristics (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Rise/Fall

(20–80 %) @

622.08 MHz output

CKO

Output not configured for

CMOS or Disabled

See Figure 2

—

230

350

ps

TRF

Output Rise/Fall

(20–80%) @

212.5 MHz output

CMOS Output

—

8

2

ns

ps

V

= 1.71

DD

C

= 5 pF

LOAD

Output Rise/Fall

(20–80%) @

212.5 MHz output

CMOS Output

= 2.97

V

DD

C

= 5 pF

LOAD

Output Duty Cycle

Uncertainty @

622.08 MHz

CKO

100  Load

Line-to-Line

Measured at 50% Point

(Not for CMOS)

+/-40

DC

LVCMOS Input Pins

Minimum Reset Pulse

Width

t

1

µs

RSTMN

Reset to Microproces-

sor Access Ready

t

10

ms

READY

LVCMOS Output Pins

Rise/Fall Times

t

C

= 20pf

LOAD

—

25

—

ns

RF

See Figure 2

LOSn Trigger Window

LOS

From last CKINn to 

Internal detection of LOSn

N3 ≠ 1

4.5 x N3

T

CKIN

TRIG

Time to Clear LOL after

LOS Cleared

t

LOS to LOL

Fold = Fnew

—

10

—

ms

CLRLOL

Stable Xa/XB reference

Notes:

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit

the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

to submit a technical support request regarding the lock time of your frequency plan.

10

Rev. 1.0

Si5324

Table 3. AC Characteristics (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Device Skew

Symbol

Test Condition

Min

Typ

Max

Unit

Output Clock Skew

t

 of CKOUTn to  of

CKOUT_m, CKOUTn

and CKOUT_m at same

frequency and signal

format

—

100

ps

SKEW

PHASEOFFSET = 0

CKOUT_ALWAYS_ON = 1

SQ_ICAL = 1

Phase Change due to

Temperature Variation

t

Max phase changes from

–40 to +85 °C

—

300

500

ps

TEMP

1

PLL Performance

(fin = fout = 622.08 MHz; BW = 7 Hz; LVPECL, XAXB = 114.285 MHz)

2

Lock Time

t

Start of ICAL to of LOL

—

0.8

4.2

1.0

5.0

s

LOCKMP

2

Settle Time

t

Start of ICAL to Fout within

5 ppm of final value

SETTLE

Output Clock Phase

Change

t

After clock switch

—

200

—

ps

P_STEP

f3  128 kHz

Closed Loop Jitter

Peaking

J

—

0.05

—

0.1

—

dB

PK

Jitter Tolerance

J

Jitter Frequency Loop

5000/BW

ns pk-pk

TOL

Bandwidth

CKO

100 Hz Offset

1 kHz Offset

—

–90

–106

–121

–132

–88

—

dBc/Hz

dBc

Phase Noise

fout = 622.08 MHz

PN

10 kHz Offset

100 kHz Offset

1 MHz Offset

—

Subharmonic Noise

Spurious Noise

Notes:

SP

Phase Noise @ 100 kHz

Offset

–76

SUBH

SPUR

Max spur @ n x F3

(n  1, n x F3 < 100 MHz)

—

–93

–70

dBc

1. Input to output phase skew after an ICAL is not controlled and can assume any value.

2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit

the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

to submit a technical support request regarding the lock time of your frequency plan.

Rev. 1.0

11

Si5324

Table 4. Microprocessor Control

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

2

I C Bus Lines (SDA, SCL)

Input Voltage Low

VIL

—

0.25 x V

V

I2C

DD

Input Voltage High

VIH

0.7 x V

0.1 x V

V

DD

I2C

DD

Hysteresis of Schmitt

trigger inputs

VHYS

V

= 1.8V

DD

—

I2C

DD

V

= 2.5 or 3.3 V

0.05 x V

—

DD

Output Voltage Low

VOL

V

= 1.8 V

0.2 x V

DD

I2C

DD

IO = 3 mA

= 2.5 or 3.3 V

IO = 3 mA

—

0.4

V

DD

12

Rev. 1.0

Si5324

Table 4. Microprocessor Control (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

SPI Specifications

Duty Cycle, SCLK

Cycle Time, SCLK

Rise Time, SCLK

Fall Time, SCLK

Low Time, SCLK

High Time, SCLK

t

SCLK = 10 MHz

40

100

—

60

—

25

—

25

%

ns

DC

t

c

t

20–80%

20–20%

80–80%

r

t

—

f

t

30

—

lsc

t

hsc

Delay Time, SCLK Fall

to SDO Active

t

d1

d2

d3

Delay Time, SCLK Fall

to SDO Transition

t

—

25

20

25

20

25

—

25

—

ns

Delay Time, SS Rise

to SDO Tri-state

t

Setup Time, SS to

SCLK Fall

t

su1

Hold Time, SS to

SCLK Rise

t

h1

Setup Time, SDI to

SCLK Rise

t

su2

Hold Time, SDI to

SCLK Rise

t

h2

Delay Time between

Slave Selects

t

cs

Rev. 1.0

13

Si5324

Table 5. Jitter Generation

*

Parameter

Symbol

Min

Typ

Max

GR-253-

Specification

Unit

Test Condition

Measurement

Filter

DSPLL

2

BW

Jitter Gen

OC-192

JGEN

0.02–80 MHz

120 Hz

—

4.2

.27

3.7

.14

4.4

.26

3.5

.27

6.2

.42

30

N/A

10

ps

PP

ps

rms

4–80 MHz

6.4

ps

PP

0.31

6.9

N/A

10

ps

rms

0.05–80 MHz

0.12–20 MHz

ps

PP

0.41

5.4

1.0

ps

rms

PP

Jitter Gen

OC-48

JGEN

40.2

4.02

ps

0.41

rms

*Note: Test conditions:

1. fIN = fOUT = 622.08 MHz

2. Clock input: LVPECL

3. Clock output: LVPECL

4. PLL bandwidth: 120 Hz

5. 114.285 MHz 3rd OT crystal used as XA/XB input

6. _DD= 2.5 V

V

7. T_A= 85 °C

Table 6. Thermal Characteristics

(V_DD= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Value

Unit

Thermal Resistance Junction to Ambient



Still Air

32

C°/W

JA

JC

Thermal Resistance Junction to Case



Still Air

14

C°/W

14

Rev. 1.0

Si5324

Table 7. Absolute Maximum Ratings*

Parameter

Symbol

Test Condition

Min

Typ

Max

3.8

Unit

DC Supply Voltage

V

–0.5

—

V

DD

LVCMOS Input Voltage

V

–0.3

0

V

+0.3

DD

V

DIG

CKINn Voltage Level Limits

XA/XB Voltage Level Limits

Operating Junction Temperature

Storage Temperature Range

CKN

—

V

DD

VIN

XA

0

1.2

V

VIN

T

–55

2

150

—

ºC

kV

JCT

T

STG

ESD HBM Tolerance

(100 pF, 1.5 k); All pins except

CKIN+/CKIN–

ESD MM Tolerance; All pins

except CKIN+/CKIN–

150

750

100

—

V

ESD HBM Tolerance

(100 pF, 1.5 k); CKIN+/CKIN–

ESD MM Tolerance;

CKIN+/CKIN–

Latch-up Tolerance

JESD78 Compliant

*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions specified in the operation sections of this data sheet. Exposure to absolute maximum rating

conditions for extended periods of time may affect device reliability.

Rev. 1.0

15

Si5324

2. Typical Application Circuits

C₄

C₁

1 µF

System

Power

0.1 µF

Ferrite

Supply

Bead

C₂

C₃

0.1 µF

V_DD= 3.3 V

130 

82 

130 

82 

0.1 µF

CKIN1+

CKIN1–

CKOUT1+

CKOUT1–

+

–

100 

0.1 µF

Clock Outputs

Input

Clock

Sources*

CKOUT2+

CKOUT2–

+

–

V_DD= 3.3 V

100 

130 

82 

130 

82 

0.1 µF

CKIN2+

CKIN2–

INT_C1B

C2B

Interrupt/CKIN_1 Invalid Indicator

CKIN_2 Invalid Indicator

Si5324

XA

XB

Option 1:

LOL

PLL Loss of Lock Indicator

114.285 MHz Crystal

V_DD

15 k

A[2:0]

SDA

SCL

Serial Port Address

RATE[1:0]²

XA

Crystal/Ref Clk Rate

15 k

I2C Interface

Serial Data

Serial Clock

0.1 µF

Option 2:

Refclk+

Refclk–

0.1 µF

XB

CS_CA

Clock Select/Clock Active

Control Mode (L)

Reset

CMODE

RST

1. Assumes differential LVPECL termination (3.3 V) on clock inputs.

Notes:

2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).

2

Figure 3. Si5324 Typical Application Circuit (I C Control Mode)

16

Rev. 1.0

Si5324

C₄

C₁

1 µF

System

Power

Supply

0.1 µF

Ferrite

Bead

C₂

C₃

0.1 µF

V_DD= 3.3 V

130 

82 

130 

82 

0.1 µF

CKOUT1+

CKOUT1–

+

–

CKIN1+

100 

CKIN1–

0.1 µF

Clock Outputs

Input

Clock

Sources*

CKOUT2+

CKOUT2–

+

–

V_DD= 3.3 V

100 

130 

82 

130 

82 

0.1 µF

CKIN2+

CKIN2–

INT_C1B

C2B

Interrupt/CLKIN_1 Invalid Indicator

CLKIN_2 Invalid Indicator

Si5324

XA

XB

Option 1:

LOL

PLL Loss of Lock Indicator

114.285 MHz Crystal

V_DD

SS

SDO

SDI

Slave Select

15 k

RATE[1:0]²

XA

Crystal/Ref Clk Rate

15 k

Serial Data Out

SPI Interface

0.1 µF

Option 2:

Serial Data In

Serial Clock

Refclk+

Refclk–

0.1 µF

SCLK

XB

Control Mode (H)

Reset

CMODE

CS_CA

Clock Select/Clock Active

RST

1. Assumes differential LVPECL termination (3.3 V) on clock inputs.

Notes:

2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).

Figure 4. Si5324 Typical Application Circuit (SPI Control Mode)

Rev. 1.0

17

Si5324

3. Functional Description

Xtal or Refclock

÷ N31

÷ N32

CKIN1

CKIN2

÷ NC1_LS

÷ NC2_LS

CKOUT1

CKOUT2

®

DSPLL

÷N1_HS

Xtal/Refclock

÷ N2

Loss of Signal/

Frequency Offset

Loss of Lock

VDD (1.8, 2.5, or 3.3 V)

GND

Control

Signal Detect

I²C/SPI Port

Clock Select

Skew Adjust

Device Interrupt

Rate Select

Figure 5. Si5324 Functional Block Diagram

The Si5324 is a low loop bandwidth, jitter-attenuating The Si5324 supports hitless switching between the two

clock multiplier for high performance applications. The

Si5324 accepts two input clocks ranging from 2 kHz to

710 MHz and generates two output clocks ranging from

2 kHz to 945 MHz and select frequencies to 1.4 GHz.

The Si5324 can also use its external reference as a

clock source for frequency synthesis. The device

provides virtually any frequency translation combination

across this operating range. Independent dividers are

available for each input clock and output clock, so the

Si5324 can accept input clocks at different frequencies

and it can generate output clocks at different

frequencies. The Si5324 input clock frequency and

clock multiplication ratio are programmable through an

synchronous input clocks in compliance with Telcordia

GR-253-CORE that greatly minimizes the propagation

of phase transients to the clock outputs during an input

clock transition (maximum 200 ps phase change).

Manual and automatic revertive and non-revertive input

clock switching options are available. The Si5324

monitors both input clocks for loss-of-signal (LOS) and

provides a LOS alarm when it detects missing pulses on

either input clock. The device monitors the lock status of

the PLL. The lock detect algorithm works by

continuously monitoring the phase of the input clock in

relation to the phase of the feedback clock. Due to the

low loop bandwidth of the part, the LOL indicator clears

before the loop fully settles.

2

I C or SPI interface. Silicon Laboratories offers a PC-

based software utility, DSPLLsim, that can be used to

determine the optimum PLL divider settings for a given

input frequency/clock multiplication ratio combination

The Si5324 also monitors frequency offset alarms

(FOS), which indicate if an input clock is within a

that minimizes phase noise and power consumption. specified frequency ppm accuracy relative to the

This

utility

can

be

downloaded

from

frequency of an XA/XB reference clock. Both Stratum

3/3E and SONET Minimum Clock (SMC) FOS

thresholds are supported.

http://www.silabs.com/timing.

The Si5324 is based on Silicon Laboratories' 3rd-

generation DSPLL technology, which provides any-

®

The Si5324 provides a digital hold capability that allows

the device to continue generation of a stable output

clock when the selected input reference is lost. During

digital hold, the DSPLL generates an output frequency

based on a historical average frequency that existed a

fixed amount of time before the error event occurred,

eliminating the effects of phase and frequency

transients that may occur immediately preceding digital

hold.

frequency synthesis and jitter attenuation in a highly

integrated PLL solution that eliminates the need for

external VCXO and loop filter components. The Si5324

PLL loop bandwidth is digitally programmable and

supports a range from 4 Hz to 525 Hz. A fast lock

feature is available to reduce lock times inherent with

low loop bandwidth PLLs. The DSPLLsim software

utility can be used to calculate valid loop bandwidth

settings for

a given input clock frequency/clock

multiplication ratio.

18

Rev. 1.0

Si5324

The Si5324 has two differential clock outputs. The this issue, a stable external reference, TXCO, OCXO, or

signal format of each clock output is independently

programmable to support LVPECL, LVDS, CML, or

CMOS loads. When configured for CMOS, four clock

outputs are available. If not required, the second clock

output can be powered down to minimize power

consumption. In addition, the phase of one output clock

may be adjusted in relation to the phase of the other

output clock. The resolution varies from 800 ps to 2.2 ns

depending on the PLL divider settings. The DSPLLsim

software utility determines the phase offset resolution

for a given combination of input clock and multiplication

thermally-isolated crystal is recommended.

For example, with a 20 ppm oscillator as the reference

on the XA/XB pins, temperature changes cause the

oscillator to change frequency slightly. Although the

Si5324 is locked to its input on CLKIN, it also uses the

XA/XB as a reference.

If there is a need to use a reference oscillator instead of

a crystal, Silicon Labs does not recommend using

MEMS based oscillators. Instead, Silicon Labs

recommends the Si530EB121M109DG, which is a very

ratio. For system-level debugging, a bypass mode is low-jitter/wander, LVPECL, 2.5 V crystal oscillator. The

available which drives the output clock directly from the

input clock, bypassing the internal DSPLL. The device is

powered by a single 1.8, 2.5, or 3.3 V supply with best-

in-class PSNR.

very low loop BW of the Si5324 means that it can be

susceptible to XAXB reference sources that have high

wander. Experience has shown that in spite of having

low jitter, some MEMs oscillators have high wander, and

these devices should be avoided. Contact Silicon Labs

for details.

3.1. External Reference

An external, high quality 38.88 MHz clock or a low-cost

114.285 MHz 3rd overtone crystal or external reference

is used as part of a fixed-frequency oscillator within the

DSPLL. This external reference is required for the

device to perform jitter attenuation. Specific

recommendations can be found in the Family Reference

Manual.

3.2. Additional Documentation

Consult the Silicon Laboratories Any-Frequency

Precision Clock Family Reference Manual (FRM) for

detailed information about the Si5324. Additional design

support is available from Silicon Laboratories through

your distributor.

In digital hold, the DSPLL remains locked and tracks the

external reference. Note that crystals can have

temperature sensitivities.

Silicon Laboratories offers a PC-based software utility

called DSPLLsim to simplify device configuration,

including frequency planning and loop bandwidth

selection. The FRM and this utility can be downloaded

from http://www.silabs.com/timing.

Due to the low bandwidth capabilities of this part, any

low-frequency wander or instability on the external

reference will transfer to the output clocks. To address

Rev. 1.0

19

Si5324

3.3. Typical Phase Noise Performance

Figure 6. Broadcast Video

Table 8. Broadcast Video Jitter¹

2

Jitter (Peak-Peak)

Jitter (RMS)

Jitter Bandwidth

10 Hz to 20 MHz

Notes:

1. Number of samples: 8.91E9.

5.24 ps

484 fs

2. Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-

offs per Telecordia GR-253-CORE.

20

Rev. 1.0

Si5324

Figure 7. OTN/SONET/SDH Phase Noise

Note: Phase noise plot uses brick wall integration.

Table 9. SONET Jitter

Jitter Bandwidth*

Jitter, RMS

266 fs

SONET_OC48, 12 kHz to 20 MHz

SONET_OC192_A, 20 kHz to 80 MHz

SONET_OC192_B, 4 MHz to 80 MHz

SONET_OC192_C, 50 kHz to 80 MHz

Brick Wall_800 Hz to 80 MHz

283 fs

155 fs

275 fs

287 fs

*Note: Jitter integration bands include low-pass (–20 dB/Dec) and hi-pass (–60 dB/Dec) roll-offs

per Telecordia GR-253-CORE.

Rev. 1.0

21

Si5324

Figure 8. Wireless Base Station Phase Noise

Table 10. Wireless Base Station Jitter*

Jitter Bandwidth

Jitter (peak-peak)

Jitter (RMS)

581 fs

10 Hz to 20 MHz

7.28 ps

Note: Number of samples: 8.91E9

22

Rev. 1.0

Si5324

4. Register Map

All register bits that are not defined in this map should always be written with the specified Reset Values. The

writing to these bits of values other than the specified Reset Values may result in undefined device behavior.

Registers not listed, e.g. Register 64, should never be written to.

Register

D7

D6

D5

D4

D3

D2

D1

D0

0

FREE_RUN

CKOUT_

BYPASS_REG

ALWAYS_ON

1

CK_PRIOR2[1:0]

CK_PRIOR1[1:0]

2

BWSEL_REG[3:0]

3

CKSEL_REG[1:0]

AUTOSEL_REG[1:0]

ICMOS[1:0]

DHOLD

SQ_ICAL

4

HST_DEL[4:0]

5

6

SFOUT2_REG[2:0}

SFOUT1_REG[2:0]

FOSREFSEL[2:0]

7

8

HLOG_2[1:0]

HLOG_1[1:0]

HIST_AVG[4:0]

9

10

11

19

20

21

22

23

24

25

31

32

33

34

35

36

40

41

42

43

44

45

46

DSBL2_ REG

DSBL1_ REG

PD_CK2

LOCK[T2:0]

LOL_PIN

PD_CK1

FOS_EN

FOS_THR[1:0]

VALTIME[1:0]

CK2_BAD_PIN CK1_ BAD_ PIN

INT_PIN

CKSEL_PIN

INT_POL

CK1_ACTV_PIN

LOL_POL

CK_ACTV_ POL CK_BAD_ POL

LOS2_MSK

LOS1_MSK

FOS1_MSK

LOSX_MSK

LOL_MSK

FOS2_MSK

N1_HS[2:0]

NC1_LS[19:16]

NC1_LS[15:8]

NC1_LS[7:0]

NC2_LS[19:16]

NC2_LS[15:8]

NC2_LS[7:0]

N2_HS[2:0]

N2_LS[19:16]

N2_LS[15:8]

N2_LS[7:0]

N31[18:16]

N31[15:8]

N31[7:0]

N32[18:16]

Rev. 1.0

23

Si5324

Register

D7

D6

D5

D4

D3

N32[15:8]

N32[7:0]

D2

D1

D0

47

48

55

CLKIN2RATE[2:0]

CLKIN1RATE[2:0]

128

129

130

CK2_ACTV_REG CK1_ACTV_REG

LOS2_INT

FOS2_INT

LOS1_INT

FOS1_INT

LOSX_INT

LOL_INT

DIGHOLD-

VALID

131

132

134

135

136

137

LOS2_FLG

FOS1_FLG

LOS1_FLG

LOL_FLG

LOSX_FLG

FOS2_FLG

PARTNUM_RO[11:4]

PARTNUM_RO[3:0]

ICAL

REVID_RO[3:0]

RST_REG

FASTLOCK

LOS1_EN [1:1]

FOS1_EN

138

139

142

143

LOS2_EN [1:1]

FOS2_EN

LOS2_EN[0:0] LOS1_EN[0:0]

INDEPENDENTSKEW1[7:0]

INDEPENDENTSKEW2[7:0]

Table 11. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table

CKOUT_ALWAYS_ON

SQ_ICAL

Results

0

1

CKOUT OFF until after the first ICAL

CKOUT OFF until after the first successful

ICAL (i.e., when LOL is low)

1

0

1

CKOUT always ON, including during an ICAL

CKOUT always ON, including during an ICAL.

Use these settings to preserve output-to-output

skew

24

Rev. 1.0

Si5324

5. Register Descriptions

Register 0.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

FREE_RUN

CKOUT_

ALWAYS_ON

BYPASS_

REG

Type

R

R/W

R

R/W

R

Reset value = 0001 0100

Bit

7

Name

Function

Reserved

Reserved.

6

FREE_RUN Free Run.

Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB

reference.

0: Disable

1: Enable

5

CKOUT_

CKOUT Always On.

ALWAYS_ON

This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on

and ICAL is not complete or successful. See Table 11 on page 24.

0: Squelch output until part is calibrated (ICAL).

1: Provide an output.

Notes:

1. The frequency may be significantly off until the part is calibrated.

2. Must be 1 to control output to output skew.

4:2

1

Reserved

Reserved.

BYPASS_

REG

Bypass Register.

This bit enables or disables the PLL bypass mode. Use only when the device is in digital

hold or before the first ICAL. Bypass mode is not supported for CMOS output clocks.

0: Normal operation

1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL.

0

Reserved

Reserved.

Rev. 1.0

25

Si5324

Register 1.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CK_PRIOR2 [1:0]

R/W

CK_PRIOR1 [1:0]

R/W

R

Reset value = 1110 0100

Bit

7:4

3:2

Name

Function

Reserved

Reserved.

CK_PRIOR2 CK_PRIOR 2.

[1:0]

Selects which of the input clocks will be 2nd priority in the autoselection state machine.

00: CKIN1 is 2nd priority.

01: CKIN2 is 2nd priority.

10: Reserved

11: Reserved

1:0

CK_PRIOR1 CK_PRIOR 1.

[1:0]

Selects which of the input clocks will be 1st priority in the autoselection state machine.

00: CKIN1 is 1st priority.

01: CKIN2 is 1st priority.

10: Reserved

11: Reserved

Register 2.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

BWSEL_REG [3:0]

R/W

R

Reset value = 0100 0010

Bit

Name

BWSEL_REG BWSEL_REG.

Function

7:4

[3:0]

Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After

BWSEL_REG is written with a new value, an ICAL is required for the change to take

effect.

3:0

Reserved

Reserved.

26

Rev. 1.0

Si5324

Register 3.

Bit

D7

D6

D5

DHOLD

R/W

D4

SQ_ICAL

R/W

D3

D2

D1

D0

Name

Type

CKSEL_REG [1:0]

R/W

R

Reset value = 0000 0101

Bit

Name

Function

7:6

CKSEL_REG CKSEL_REG.

[1:0]

If the device is operating in register-based manual clock selection mode

(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input clock

will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00, the CS_CA

input pin continues to control clock selection and CKSEL_REG is of no consequence.

00: CKIN_1 selected.

01: CKIN_2 selected.

10: Reserved

11: Reserved

5

DHOLD

DHOLD.

Forces the part into digital hold. This bit overrides all other manual and automatic clock

selection controls.

0: Normal operation.

1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the

input clocks.

4

SQ_ICAL

Reserved

SQ_ICAL.

This bit determines if the output clocks will remain enabled or be squelched (disabled)

during an internal calibration. See Table 11 on page 24.

0: Output clocks enabled during ICAL.

1: Output clocks disabled during ICAL.

3:0

Reserved.

Rev. 1.0

27

Si5324

Register 4.

Bit

D7

D6

D5

D4

D3

D2

HIST_DEL [4:0]

R/W

D1

D0

Name

Type

AUTOSEL_REG [1:0]

R/W

R

Reset value = 0001 0010

Bit

Name

AUTOSEL_ AUTOSEL_REG [1:0].

Function

7:6

REG [1:0]

Selects method of input clock selection to be used.

00: Manual (either register or pin controlled, see CKSEL_PIN)

01: Automatic Non-Revertive

10: Automatic Revertive

11: Reserved

5

Reserved

Reserved.

4:0

HIST_DEL HIST_DEL [4:0].

[4:0]

Selects amount of delay to be used in generating the history information used for Digital

Hold.

Register 5.

Bit

D7

ICMOS [1:0]

R/W

D6

D5

D4

D3

D2

D1

D0

Name

Type

R

Reset value = 1110 1101

Bit

Name

Function

7:6

ICMOS [1:0] ICMOS [1:0].

When the output buffer is set to CMOS mode, these bits determine the output buffer drive

strength. The first number below refers to 3.3 V operation; the second to 1.8 V operation.

These values assume CKOUT+ is tied to CKOUT-.

00: 8mA/2mA.

01: 16mA/4mA

10: 24mA/6mA

11: 32mA/8mA

5:0

Reserved

Reserved.

28

Rev. 1.0

Si5324

Register 6.

Bit

D7

D6

D5

D4

SFOUT2_REG [2:0]

R/W

D3

D2

D1

D0

Name

Type

SFOUT1_REG [2:0]

R/W

R

Reset value = 0010 1101

Bit

7:6

5:3

Name

Function

Reserved

Reserved.

SFOUT2_

REG [2:0]

SFOUT2_REG [2:0].

Controls output signal format and disable for CKOUT2 output buffer. Bypass mode is not

supported for CMOS output clocks.

000: Reserved

001: Disable

010: CMOS

011: Low swing LVDS

100: Reserved

101: LVPECL

110: CML

111: LVDS

2:0

SFOUT1_

REG [2:0]

SFOUT1_REG [2:0].

Controls output signal format and disable for CKOUT1 output buffer. Bypass mode is not

supported for CMOS output clocks.

000: Reserved

001: Disable

010: CMOS

011: Low swing LVDS

100: Reserved

101: LVPECL

110: CML

111: LVDS

Rev. 1.0

29

Si5324

Register 7.

Bit

D7

D6

D5

D4

D3

D2

D1

FOSREFSEL [2:0]

R/W

D0

Name

Type

R

Reset value = 0010 1010

Bit

7:3

2:0

Name

Function

Reserved.

FOSREFSEL FOSREFSEL [2:0].

[2:0]

Selects which input clock is used as the reference frequency for Frequency Off-Set

(FOS) alarms.

000: XA/XB (External reference)

001: CKIN1

010: CKIN2

011: Reserved

100: Reserved

101: Reserved

110: Reserved

111: Reserved

30

Rev. 1.0

Si5324

Register 8.

Bit

D7

HLOG_2[1:0]

R/W

D6

D5

HLOG_1[1:0]

R/W

D4

D3

D2

D1

D0

Name

Type

R

Reset value = 0000 0000

Bit

Name

Function

7:6

HLOG_2 [1:0] HLOG_2 [1:0].

00: Normal operation

01: Holds CKOUT2 output at static logic 0.

Entrance and exit from this state will occur without glitches or runt pulses.

10:Holds CKOUT2 output at static logic 1.

Entrance and exit from this state will occur without glitches or runt pulses.

11: Reserved

5:4

3:0

HLOG_1 [1:0] HLOG_1 [1:0].

00: Normal operation

01: Holds CKOUT1 output at static logic 0.

Entrance and exit from this state will occur without glitches or runt pulses.

10: Holds CKOUT1 output at static logic 1.

Entrance and exit from this state will occur without glitches or runt pulses.

11: Reserved

Reserved

Reserved.

Register 9.

Bit

D7

D6

D5

HIST_AVG [4:0]

R/W

D4

D3

D2

D1

D0

Name

Type

R

Reset value = 1100 0000

Bit

Name

HIST_AVG HIST_AVG [4:0].

Function

7:3

[4:0]

Selects amount of averaging time to be used in generating the history information for

Digital Hold.

2:0

Reserved

Reserved.

Rev. 1.0

31

Si5324

Register 10.

Bit

D7

D6

D5

D4

D3

DSBL2_REG

R/W

D2

DSBL1_REG

R/W

D1

D0

Name

Type

R

Reset value = 0000 0000

Bit

7:4

3

Name

Function

Reserved

Reserved.

DSBL2_REG DSBL2_REG.

This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is

selected, the NC2_LS output divider is also powered down.

0: CKOUT2 enabled.

1: CKOUT2 disabled.

2

DSBL1_REG DSBL1_REG.

This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is

selected, the NC1_LS output divider is also powered down.

0: CKOUT1 enabled.

1: CKOUT1 disabled.

1:0

Reserved

Reserved.

Register 11.

Bit

D7

D6

D5

D4

D3

D2

D1

PD_CK2

R/W

D0

Name

Type

PD_CK1

R/W

R

Reset value = 0100 0000

Bit

7:2

1

Name

Function

Reserved

PD_CK2

Reserved.

PD_CK2.

This bit controls the powerdown of the CKIN2 input buffer.

0: CKIN2 enabled.

1: CKIN2 disabled.

0

PD_CK1

PD_CK1.

This bit controls the powerdown of the CKIN1 input buffer.

0: CKIN1 enabled.

1: CKIN1 disabled.

32

Rev. 1.0

Si5324

Register 19.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

FOS_EN

R/W

FOS_THR [1:0]

R/W

VALTIME [1:0]

R/W

LOCKT [2:0]

R/W

Reset value = 0010 1100

Bit

Name

Function

7

FOS_EN

FOS_EN.

Frequency Offset Enable globally disables FOS. See the individual FOS enables (FOS-

x_EN, register 139).

0: FOS disable

1: FOS enabled by FOSx_EN

6:5 FOS_THR [1:0] FOS_THR [1:0].

Frequency Offset at which FOS is declared:

00: ± 11 to 12 ppm (Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK

01: ± 48 to 49 ppm (SMC)

10: ± 30 ppm (SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.

11: ± 200 ppm

4:3

2:0

VALTIME [1:0] VALTIME [1:0].

Sets amount of time for input clock to be valid before the associated alarm is removed.

00: 2 ms

01: 100 ms

10: 200 ms

11: 13 seconds

LOCKT [2:0] LOCKT [2:0].

Sets retrigger interval for one shot monitoring phase detector output. One shot is trig-

gered by phase slip in DSPLL. Refer to the Family Reference Manual for more details.

To minimize lock time, the value 001 for LOCKT is recommended.

000: 106 ms

001: 53 ms

010: 26.5 ms

011: 13.3 ms

100: 6.6 ms

101: 3.3 ms

110: 1.66 ms

111: .833 ms

Rev. 1.0

33

Si5324

Register 20.

Bit

D7

D6

D5

D4

D3

CK2_BAD_PIN CK1_BAD_PIN

R/W R/W

D2

D1

LOL_PIN

R/W

D0

INT_PIN

R/W

Name

Type

R

Reset value = 0011 1110

Bit

7:4

3

Name

Function

Reserved

Reserved.

CK2_BAD_PIN CK2_BAD_PIN.

The CK2_BAD status can be reflected on the C2B output pin.

0: C2B output pin tristated

1: C2B status reflected to output pin

2

1

0

CK1_BAD_PIN CK1_BAD_PIN.

The CK1_BAD status can be reflected on the C1B output pin.

0: C1B output pin tristated

1: C1B status reflected to output pin

LOL_PIN

INT_PIN

LOL_PIN.

The LOL_INT status bit can be reflected on the LOL output pin.

0: LOL output pin tristated

1: LOL_INT status reflected to output pin

INT_PIN.

Reflects the interrupt status on the INT_C1B output pin.

0: Interrupt status not displayed on INT_C1B output pin. If CK1_BAD_PIN = 0, INT_C1B

output pin is tristated.

1: Interrupt status reflected to output pin. Instead, the INT_C1B pin indicates when

CKIN1 is bad.

34

Rev. 1.0

Si5324

Register 21.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CK1_ACTV_PIN CKSEL_ PIN

R/W R/W

R

Reset value = 1111 1111

Bit

7:2

1

Name

Function

Reserved

Reserved.

CK1_ACTV_PIN CK1_ACTV_PIN.

The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the

CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin

controlled clock selection is not being used.

0: CS_CA output pin tristated.

1: Clock Active status reflected to output pin.

0

CKSEL_PIN

CKSEL_PIN.

If manual clock selection is being used, clock selection can be controlled via the

CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when

AUTOSEL_REG = Manual.

0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection.

1: CS_CA input pin controls clock selection.

Rev. 1.0

35

Si5324

Register 22.

Bit

D7

D6

D5

D4

D3

CK_ACTV_POL

R/W

D2

CK_BAD_ POL

R/W

D1

LOL_POL

R/W

D0

INT_POL

R/W

Name

Type

R

Reset value = 1101 1111

Bit

7:4

3

Name

Function

Reserved

Reserved.

CK_ACTV_ POL CK_ACTV_POL.

Sets the active polarity for the CS_CA signals when reflected on an output pin.

0: Active low

1: Active high

2

CK_BAD_ POL

CK_BAD_POL.

Sets the active polarity for the INT_C1B and C2B signals when reflected on output

pins.

0: Active low

1: Active high

1

0

LOL_POL

INT_POL

LOL_POL.

Sets the active polarity for the LOL status when reflected on an output pin.

0: Active low

1: Active high

INT_POL.

Sets the active polarity for the interrupt status when reflected on the INT_C1B out-

put pin.

0: Active low

1: Active high

36

Rev. 1.0

Si5324

Register 23.

Bit

D7

D6

D5

D4

D3

D2

LOS2_ MSK

R/W

D1

LOS1_ MSK

R/W

D0

LOSX_ MSK

R/W

Name

Type

R

Reset value = 0001 1111

Bit

7:3

2

Name

Function

Reserved

LOS2_MSK

Reserved.

LOS2_MSK.

Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt.

Writes to this register do not change the value held in the LOS2_FLG register.

0: LOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: LOS2_FLG ignored in generating interrupt output.

1

0

LOS1_MSK

LOSX_MSK

LOS1_MSK.

Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt.

Writes to this register do not change the value held in the LOS1_FLG register.

0: LOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: LOS1_FLG ignored in generating interrupt output.

LOSX_MSK.

Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt.

Writes to this register do not change the value held in the LOSX_FLG register.

0: LOSX alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: LOSX_FLG ignored in generating interrupt output.

Rev. 1.0

37

Si5324

Register 24.

Bit

D7

D6

D5

D4

D3

D2

FOS2_MSK

R/W

D1

FOS1_MSK

R/W

D0

LOL_MSK

R/W

Name

Type

R

Reset value = 0011 1111

Bit

7:3

2

Name

Function

Reserved

Reserved.

FOS2_MSK FOS2_MSK.

Determines if the FOS2_FLG is used to in the generation of an interrupt. Writes to this

register do not change the value held in the FOS2_FLG register.

0: FOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: FOS2_FLG ignored in generating interrupt output.

1

0

FOS1_MSK FOS1_MSK.

Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this reg-

ister do not change the value held in the FOS1_FLG register.

0: FOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: FOS1_FLG ignored in generating interrupt output.

LOL_MSK

LOL_MSK.

Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this regis-

ter do not change the value held in the LOL_FLG register.

0: LOL alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).

1: LOL_FLG ignored in generating interrupt output.

38

Rev. 1.0

Si5324

Register 25.

Bit

D7

D6

N1_HS [2:0]

R/W

D5

D4

D3

D2

D1

D0

Name

Type

R

Reset value = 0010 0000

Bit

Name

Function

7:5

N1_HS [2:0] N1_HS [2:0].

Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider.

000: N1= 4

001: N1= 5

010: N1=6

011: N1= 7

100: N1= 8

101: N1= 9

110: N1= 10

111: N1= 11

4:0

Reserved

Reserved.

Register 31.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

NC1_LS [19:16]

R/W

R

Reset value = 0000 0000

Bit

7:4

3:0

Name

Function

Reserved

Reserved.

NC1_LS

[19:16]

NC1_LS [19:16].

Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

Rev. 1.0

39

Si5324

Register 32.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

NC1_LS [15:8]

R/W

Reset value = 0000 0000

Bit

Name

NC1_LS [15:8] NC1_LS [15:8].

Function

7:0

Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

Register 33.

Bit

D7

D6

D5

D4

NC1_LS [7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 0011 0001

Bit

Name

NC1_LS [19:0] NC1_LS [7:0].

Function

7:0

Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

40

Rev. 1.0

Si5324

Register 34.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

NC2_LS [19:16]

R/W

R

Reset value = 0000 0000

Bit

7:4

3:0

Name

Function

Reserved

Reserved.

NC2_LS

[19:16]

NC2_LS [19:16].

Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.

00000000000000000000=1

00000000000000000001=2

00000000000000000011=4

00000000000000000101=6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

Register 35.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

NC2_LS [15:8]

R/W

Reset value = 0000 0000

Bit

Name

NC2_LS [15:8] NC2_LS [15:8].

Function

7:0

Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

Rev. 1.0

41

Si5324

Register 36.

Bit

D7

D6

D5

D4

NC2_LS [7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 0011 0001

Bit

Name

NC2_LS [7:0] NC2_LS [7:0].

Function

7:0

Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

20

11111111111111111111 = 2

20

Valid divider values = [1, 2, 4, 6, ..., 2 ]

42

Rev. 1.0

Si5324

Register 40.

Bit

D7

D6

N2_HS [2:0]

R/W

D5

D4

D3

D2

N2_LS [19:16]

R/W

D1

D0

Name

Type

R

Reset value = 1100 0000

Bit

Name

Function

7:5

N2_HS [2:0]

N2_HS [2:0].

Sets value for N2 high speed divider which drives N2LS low-speed divider.

000: 4

001: 5

010: 6

011: 7

100: 8

101: 9

110: 10

111: 11

4

Reserved

Reserved.

3:0

N2_LS [19:16] N2_LS [19:16].

Sets value for N2 low-speed divider, which drives phase detector.

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

20

11111111111111111111 = 2

20

Valid divider values = [2, 4, 6, ..., 2 ]

Rev. 1.0

43

Si5324

Register 41.

Bit

D7

D6

D5

D4

N2_LS [15:8]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 0000 0000

Bit

Name

N2_LS [15:8] N2_LS [15:8].

Function

7:0

Sets value for N2 low-speed divider, which drives phase detector.

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

20

11111111111111111111 = 2

20

Valid divider values = [2, 4, 6, ..., 2 ]

Register 42.

Bit

D7

D6

D5

D4

N2_LS [7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 1111 1001

Bit

Name

N2_LS [7:0] N2_LS [7:0].

Function

7:0

Sets value for N2 low-speed divider, which drives phase detector.

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

20

11111111111111111111 = 2

20

Valid divider values = [2, 4, 6, ..., 2 ]

44

Rev. 1.0

Si5324

Register 43.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

N31 [18:16]

R/W

R

Reset value = 0000 0000

Bit

7:3

2:0

Name

Function

Reserved

Reserved.

N31 [18:16] N31 [18:16].

Sets value for input divider for CKIN1.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

19

1111111111111111111 = 2

19

Valid divider values = [1, 2, 3, ..., 2 ]

Register 44.

Bit

D7

D6

D5

D4

N31_[15:8]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 0000 0000

Bit

Name

N31_[15:8] N31_[15:8].

Function

7:0

Sets value for input divider for CKIN1.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

19

1111111111111111111 = 2

19

Valid divider values = [1, 2, 3, ..., 2 ]

Rev. 1.0

45

Si5324

Register 45.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

N31_[7:0]

R/W

Reset value = 0000 1001

Bit

Name

Function

7:0

N31_[7:0

N31_[7:0].

Sets value for input divider for CKIN1.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

19

1111111111111111111 = 2

19

Valid divider values = [1, 2, 3, ..., 2 ]

Register 46.

Bit

D7

D6

D5

D4

D3

D2

D1

N32_[18:16]

R/W

D0

Name

Type

R

Reset value = 0000 0000

Bit

7:3

2:0

Name

Function

Reserved

Reserved.

N32_[18:16] N32_[18:16].

Sets value for input divider for CKIN2.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

19

1111111111111111111 = 2

19

Valid divider values = [1, 2, 3, ..., 2 ]

46

Rev. 1.0

Si5324

Register 47.

Bit

D7

D6

D5

D4

N32_[15:8]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 0000 0000

Bit

Name

N32_[15:8] N32_[15:8].

Function

7:0

Sets value for input divider for CKIN2.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

19

1111111111111111111 = 2

19

Valid divider values = [1, 2, 3, ..., 2 ]

Register 48.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

N32_[7:0]

R/W

Reset value = 0000 1001

Bit

Name

Function

7:0

N32_[7:0]

N32_[7:0].

Sets value for input divider for CKIN2.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

19

1111111111111111111 = 2

19

Valid divider values = [1, 2, 3, ..., 2 ]

Rev. 1.0

47

Si5324

Register 55.

Bit

D7

D6

D5

D4

CLKIN2RATE_[2:0]

R/W

D3

D2

D1

CLKIN1RATE[2:0]

R/W

D0

Name

Type

R

Reset value = 0000 0000

Bit

7:6

5:3

Name

Function

Reserved

Reserved.

CLKIN2RATE[2:0] CLKIN2RATE_[2:0].

CKINn frequency selection for FOS alarm monitoring.

000: 10–27 MHz

001: 25–54 MHz

002: 50–105 MHz

003: 95–215 MHz

004: 190–435 MHz

005: 375–710 MHz

006: Reserved

007: Reserved

2:0

CLKIN1RATE [2:0] CLKIN1RATE[2:0].

CKINn frequency selection for FOS alarm monitoring.

000: 10–27 MHz

001: 25–54 MHz

002: 50–105 MHz

003: 95–215 MHz

004: 190–435 MHz

005: 375–710 MHz

006: Reserved

007: Reserved

48

Rev. 1.0

Si5324

Register 128.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CK2_ACTV_REG CK1_ACTV_REG

R

Reset value = 0010 0000

Bit

7:2

1

Name

Function

Reserved

Reserved.

CK2_ACTV_REG CK2_ACTV_REG.

Indicates if CKIN2 is currently the active clock for the PLL input.

0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.

1: CKIN2 is the active input clock.

0

CK1_ACTV_REG CK1_ACTV_REG.

Indicates if CKIN1 is currently the active clock for the PLL input.

0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.

1: CKIN1 is the active input clock.

Register 129.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

LOS2_INT LOS1_INT LOSX_INT

R

Reset value = 0000 0110

Bit

7:3

2

Name

Function

Reserved

Reserved.

LOS2_INT LOS2_INT.

Indicates the LOS status on CKIN2.

0: Normal operation.

1: Internal loss-of-signal alarm on CKIN2 input.

1

0

LOS1_INT LOS1_INT.

Indicates the LOS status on CKIN1.

0: Normal operation.

1: Internal loss-of-signal alarm on CKIN1 input.

LOSX_INT LOSX_INT.

Indicates the LOS status of the external reference on the XA/XB pins.

0: Normal operation.

1: Internal loss-of-signal alarm on XA/XB reference clock input.

Rev. 1.0

49

Si5324

Register 130.

Bit

D7

D6

D5

D4

D3

D2

FOS2_INT

R

D1

FOS1_INT

R

D0

LOL_INT

R

Name

Type

DIGHOLDVALID

R

Reset value = 0000 0001

Bit

7

Name

Function

Reserved

Reserved.

6

DIGHOLDVALID

Digital Hold Valid.

Indicates if the digital hold circuit has enough samples of a valid clock to meet dig-

ital hold specifications.

0: Indicates digital hold history registers have not been filled. The digital hold

output frequency may not meet specifications.

1: Indicates digital hold history registers have been filled. The digital hold output

frequency is valid.

5:3

2

Reserved

Reserved.

FOS2_INT

CKIN2 Frequency Offset Status.

0: Normal operation.

1: Internal frequency offset alarm on CKIN2 input.

1

0

FOS1_INT

LOL_INT

CKIN1 Frequency Offset Status.

0: Normal operation.

1: Internal frequency offset alarm on CKIN1 input.

PLL Loss of Lock Status.

0: PLL locked.

1: PLL unlocked.

50

Rev. 1.0

Si5324

Register 131.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

LOS2_FLG LOS1_FLG LOSX_FLG

R/W R/W R/W

R

Reset value = 0001 1111

Bit

7:3

2

Name

Function

Reserved

Reserved.

LOS2_FLG CKIN2 Loss-of-Signal Flag.

0: Normal operation.

1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOS2_MSK bit. Flag cleared by writing 0 to

this bit.

1

0

LOS1_FLG CKIN1 Loss-of-Signal Flag.

0: Normal operation

1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOS1_MSK bit. Flag cleared by writing 0 to

this bit.

LOSX_FLG External Reference (signal on pins XA/XB) Loss-of-Signal Flag.

0: Normal operation

1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOSX_MSK bit. Flag cleared by writing 0 to

this bit.

Rev. 1.0

51

Si5324

Register 132.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

FOS2_FLG FOS1_FLG LOL_FLG

R

R/W

R

Reset value = 0000 0010

Bit

7:4

3

Name

Function

Reserved

Reserved.

FOS2_FLG CLKIN_2 Frequency Offset Flag.

0: Normal operation.

1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing 0 to

this bit.

2

1

0

FOS1_FLG CLKIN_1 Frequency Offset Flag.

0: Normal operation

1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing 0 to

this bit.

LOL_FLG

Reserved

PLL Loss of Lock Flag.

0: PLL locked

1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing 0 to

this bit.

Reserved.

52

Rev. 1.0

Si5324

Register 134.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

PARTNUM_RO [11:4]

R

Reset value = 0000 0001

Bit

Name

Function

7:0

PARTNUM_RO [11:0] Device ID (1 of 2).

0000 0001 1000: Si5324

Others Reserved

Register 135.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

PARTNUM_RO [3:0]

R

REVID_RO [3:0]

R

Reset value = 1000 0010

Bit

Name

PARTNUM_RO [11:0] Device ID (2 of 2).

Function

7:4

0000 0001 1000: Si5324

Others Reserved

3:0

REVID_RO [3:0]

Indicates Revision Number of Device.

0010: Revision C

Others Reserved.

Rev. 1.0

53

Si5324

Register 136.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name RST_REG

Type R/W

Reset value = 0000 0000

ICAL

R/W

R

Bit

Name

Function

7

RST_REG

Internal Reset (Same as Pin Reset).

Note: The I²C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.

0: Normal operation.

1: Reset of all internal logic. Outputs disabled or tristated during reset.

6

ICAL

Start an Internal Calibration Sequence.

For proper operation, the device must go through an internal calibration sequence.

ICAL is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibra-

tion is complete once the LOL alarm goes low. A valid stable clock (within 100 ppm)

must be present to begin ICAL.

Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take

effect.

0: Normal operation.

1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-cali-

bration, LOL will go low.

5:0

Reserved

Reserved.

54

Rev. 1.0

Si5324

Register 137.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

FASTLOCK

R/W

Name

Type

R

Reset value = 0000 0000

Bit

7:1

0

Name

Function

Reserved

FASTLOCK

Do not modify.

This bit must be set to 1 to enable FASTLOCK. This improves initial lock time by

dynamically changing the loop bandwidth.

Register 138.

Bit

D7

D6

D5

D4

D3

D2

D1

LOS2_EN [1:1]

R/W

D0

LOS1_EN [1:1]

R/W

Name

Type

R

Reset value = 0000 1111

Bit

7:2

1

Name

Function

Reserved

Reserved.

LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).

Note: LOS2_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual

for details.

0

LOS1_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).

Note: LOS1_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual

for details.

Rev. 1.0

55

Si5324

Register 139.

Bit

D7

D6

D5

LOS2_EN [0:0] LOS1_EN [0:0]

R/W R/W

D4

D3

D2

D1

FOS2_EN FOS1_EN

R/W R/W

D0

Name

Type

R

Reset value = 1111 1111

Bit

7:6

5

Name

Function

Reserved

Reserved.

LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).

Note: LOS2_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the family reference manual

for details.

4

LOS_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).

Note: LOS1_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the family reference manual

for details.

3:2

1

Reserved

FOS2_EN

Reserved.

Enables FOS on a Per Channel Basis.

0: Disable FOS monitoring.

1: Enable FOS monitoring.

0

FOS1_EN

Enables FOS on a Per Channel Basis.

0: Disable FOS monitoring.

1: Enable FOS monitoring.

56

Rev. 1.0

Si5324

Register 142.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

INDEPENDENTSKEW1 [7:0]

R/W

Type

Reset value = 0000 0000

Bit

Name

INDEPENDENTSKEW1 [7:0] INDEPENDENTSKEW1.

Function

7:0

8 bit field that represents a twos complement of the phase offset in

terms of clocks from the high speed output divider. Default = 0.

Register 143.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

INDEPENDENTSKEW2 [7:0]

R/W

Type

Reset value = 0000 0000

Bit

Name

INDEPENDENTSKEW2 [7:0] INDEPENDENTSKEW2.

Function

7:0

8 bit field that represents a twos complement of the phase offset in terms

of clocks from the high speed output divider. Default = 0.

Rev. 1.0

57

Si5324

5.1. ICAL

The device's registers must be configured for the intended applications. After the part is configured, the part must

perform a calibration procedure when there is a stable clock on the selected CLKINn input. The calibration process

is triggered by writing a "1" to bit D6 in register 136. See the Family Reference Manual for details. In addition, after

a successful calibration operation, changing any of the Registers indicated in Table 12 requires that a calibration be

performed again by the same procedure (writing a "1" to bit D6 in register 136).

Table 12. ICAL-Sensitive Registers

Address

0

Register

BYPASS_REG

CKOUT_ALWAYS_ON

CK_PRIOR1

CK_PRIOR2

BWSEL_REG

HIST_DEL

ICMOS

0

1

2

4

5

7

FOSREFSEL

HIST_AVG

DSBL1_REG

DSBL2_REG

PD_CK1

9

10

11

19

25

31

34

40

43

46

55

PD_CK2

FOS_EN

FOS_THR

LOCKT

VALTIME

N1HS

NC1_LS

NC2_LS

N2_HS

N2_LS

N31

N32

CLKIN1RATE

CLKIN2RATE

58

Rev. 1.0

Si5324

6. Pin Descriptions

36 35 34 33 32 31 30 29 28

RST

NC

1

2

3

4

5

6

7

8

9

27 SDI

26

A2_SS

25 A1

INT_C1B

C2B

24

23

A0

GND

Pad

VDD

XA

SDA_SDO

22 SCL

XB

21

20

19

CS_CA

GND

NC

GND

10 11 12 13 14 15 16 17 18

Pin #

Pin Name I/O Signal Level

Description

1

I

LVCMOS External Reset.

RST

Active low input that performs external hardware reset of device.

Resets all internal logic to a known state and forces the device reg-

isters to their default value. Clock outputs are disabled during reset.

The part must be programmed after a reset or power-on to get a

clock output. See Family Reference Manual for details.

This pin has a weak pull-up.

No Connection.

2, 9, 14,

30, 33

NC

Leave floating. Make no external connections to this pin for normal

operation.

3

INT_C1B

O

LVCMOS Interrupt/CKIN1 Invalid Indicator.

This pin functions as a device interrupt output or an alarm output for

CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The

pin functions as a maskable interrupt output with active polarity con-

trolled by the INT_POL register bit.

If used as an alarm output, the pin functions as a LOS (and option-

ally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and

INT_PIN = 0.

0 = CKIN1 present.

1 = LOS (FOS) on CKIN1.

The active polarity is controlled by CK_BAD_POL. If no function is

selected, the pin tristates.

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

Rev. 1.0

59

Si5324

Pin #

Pin Name I/O Signal Level

C2B LVCMOS CKIN2 Invalid Indicator.

Description

4

O

This pin functions as a LOS (and optionally FOS) alarm indicator for

CKIN2 if CK2_BAD_PIN = 1.

0 = CKIN2 present.

1 = LOS (FOS) on CKIN2.

The active polarity can be changed by CK_BAD_POL. If

CK2_BAD_PIN = 0, the pin tristates.

5, 10, 32

V

Supply

Analog

Supply.

DD

The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-

itors should be associated with the following Vdd pins:

5

10

32

0.1 µF

A 1.0 µF should also be placed as close to the device as is practical.

7

6

XB

XA

I

External Crystal or Reference Clock.

External crystal should be connected to these pins to use internal

oscillator based reference. Refer to Family Reference Manual for

interfacing to an external reference. External reference must be

from a high-quality clock source (TCXO, OCXO). Frequency of crys-

tal or external clock is set by RATE[1:0] pins.

8, 31, 20,

19

GND

Supply

3-Level

Ground.

GND

Must be connected to system ground. Minimize the ground path

impedance for optimal performance of this device. Grounding these

pins does not eliminate the requirement to ground the GND PAD on

the bottom of the package.

11

15

RATE0

RATE1

I

External Crystal or Reference Clock Rate.

Three level inputs that select the type and rate of external crystal or

reference clock to be applied to the XA/XB port. Refer to the Family

Reference Manual for settings. These pins have both a weak pull-up

and a weak pull-down; they default to M.

L setting corresponds to ground.

M setting corresponds to V /2.

DD

H setting corresponds to V

.

DD

Some designs may require an external resistor voltage divider when

driven by an active device that will tri-state.

16

17

CKIN1+

CKIN1–

I

Multi

Clock Input 1.

Differential input clock. This input can also be driven with a single-

ended signal. Input frequency range is 2 kHz to 710 MHz.

12

13

CKIN2+

CKIN2–

Clock Input 2.

Differential input clock. This input can also be driven with a single-

ended signal. Input frequency range is 2 kHz to 710 MHz.

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

60

Rev. 1.0

Si5324

Pin #

Pin Name I/O Signal Level

Description

18

LOL

O

LVCMOS PLL Loss of Lock Indicator.

This pin functions as the active high PLL loss of lock indicator if the

LOL_PIN register bit is set to 1.

0 = PLL locked.

1 = PLL unlocked.

If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by

the LOL_POL bit. The PLL lock status will always be reflected in the

LOL_INT read only register bit.

21

CS_CA

I/O

LVCMOS Input Clock Select/Active Clock Indicator.

Input: In manual clock selection mode, this pin functions as the

manual input clock selector if the CKSEL_PIN is set to 1.

0 = Select CKIN1.

1 = Select CKIN2.

If CKSEL_PIN = 0, the CKSEL_REG register bit controls this func-

tion and this input tristates. If configured for input, must be tied high

or low.

Output: In automatic clock selection mode, this pin indicates which

of the two input clocks is currently the active clock. If alarms exist on

both clocks, CK_ACTV will indicate the last active clock that was

used before entering the digital hold state. The CK_ACTV_PIN reg-

ister bit must be set to 1 to reflect the active clock status to the

CK_ACTV output pin.

0 = CKIN1 active input clock.

1 = CKIN2 active input clock.

If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status will

always be reflected in the CK_ACTV_REG read only register bit.

22

23

SCL

I

LVCMOS Serial Clock.

2

This pin functions as the serial clock input for both SPI and I C

modes.

This pin has a weak pull-down.

SDA_SDO I/O

LVCMOS Serial Data.

2

In I C control mode (CMODE = 0), this pin functions as the bidirec-

tional serial data port.

In SPI control mode (CMODE = 1), this pin functions as the serial

data output.

25

24

A1

A0

I

LVCMOS Serial Port Address.

2

In I C control mode (CMODE = 0), these pins function as hardware

controlled address bits. The I C address is 1101 [A2] [A1] [A0].

2

In SPI control mode (CMODE = 1), these pins are ignored.

These pins have a weak pull-down.

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

Rev. 1.0

61

Si5324

Pin #

Pin Name I/O Signal Level

Description

26

A2_SS

I

LVCMOS Serial Port Address/Slave Select.

2

In I C control mode (CMODE = 0), this pin functions as a hardware

controlled address bit [A2].

In SPI control mode (CMODE = 1), this pin functions as the slave

select input.

This pin has a weak pull-down.

27

SDI

I

LVCMOS Serial Data In.

2

In I C control mode (CMODE = 0), this pin is ignored.

In SPI control mode (CMODE = 1), this pin functions as the serial

data input.

This pin has a weak pull-down.

29

28

CKOUT1–

CKOUT1+

O

Multi

Output Clock 1.

Differential output clock with a frequency range of 8 kHz to

1.4175 GHz. Output signal format is selected by SFOUT1_REG

register bits. Output is differential for LVPECL, LVDS, and CML

compatible modes. For CMOS format, both output pins drive identi-

cal single-ended clock outputs.

34

35

CKOUT2–

CKOUT2+

O

Output Clock 2.

Differential output clock with a frequency range of 8 kHz to

1.4175 GHz. Output signal format is selected by SFOUT2_REG

register bits. Output is differential for LVPECL, LVDS, and CML

compatible modes. For CMOS format, both output pins drive identi-

cal single-ended clock outputs.

36

CMODE

I

LVCMOS Control Mode.

2

Selects I C or SPI control mode for the Si5324.

2

0 = I C Control Mode

1 = SPI Control Mode

This pin must not be NC. Tie either high or low.

Ground Pad.

GND PAD

GND

Supply

The ground pad must provide a low thermal and electrical

impedance to a ground plane.

Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.

62

Rev. 1.0

Si5324

7. Ordering Guide

Ordering Part

Number

Output Clock Frequency

Package

ROHS6, Temperature Range

Pb-Free

Range

Si5324A-C-GM

2 kHz–945 MHz

970–1134 MHz

1.213–1.417 GHz

36-Lead 6 x 6 mm QFN

Yes

–40 to 85 °C

Si5324B-C-GM

Si5324C-C-GM

Si5324D-C-GM

2 kHz–808 MHz

2 kHz–346 MHz

2 kHz–150 MHz

36-Lead 6 x 6 mm QFN

Yes

–40 to 85 °C

Note: Add an R at the end of the device to denote tape and reel options.

Rev. 1.0

63

Si5324

Table 13. Product Selection Guide

Part

Control Number of

Input

Output

RMS Phase Jitter

PLL

Hitless

Free

Package

Number

Inputsand Frequency Frequency (12 kHz–20 MHz) Bandwidth Switching Run

(MHz)^*

Outputs

Mode

60 Hz to

8 kHz

6x6 mm

36-QFN

Si5315

Si5316

Si5317

Si5319

Si5323

Si5324

Si5326

Si5327

Si5366

Si5368

Si5369

Si5374

Si5375

1PLL, 2 | 2 0.008–644 0.008–644

0.45 ps

0.3 ps

0.5 ps

0.3 ps

0.4 ps



60 Hz to

8 kHz

6x6 mm

36-QFN

1PLL, 2 | 1

1PLL, 1 | 2

19–710

1–710

19–710

1–710

60 Hz to

8 kHz

6x6 mm

36-QFN

60 Hz to

8 kHz

6x6 mm

36-QFN

I²C/SPI 1PLL, 1 | 1 0.002–710 0.002–1417

Pin 1PLL, 2 | 2 0.008–707 0.008–1050



60 Hz to

8 kHz

6x6 mm

36-QFN



4 Hz to

525 Hz

6x6 mm

36-QFN

I²C/SPI 1PLL, 2 | 2 0.002–710 0.002–1417

I²C/SPI 1PLL, 2 | 2 0.002–710 0.002–808



60 Hz to

8 kHz

6x6 mm

36-QFN

60 Hz to

8 kHz

6x6 mm

36-QFN

60 Hz to

8 kHz

14x14 mm

100-TQFP

1PLL, 4 | 5 0.008–707 0.008–1050

60 Hz to

8 kHz

14x14 mm

100-TQFP

I²C/SPI 1PLL, 4 | 5 0.002–710 0.002–1417



4 Hz to

525 Hz

14x14 mm

100-TQFP

4 Hz to

525 Hz

10x10 mm

80-BGA

I²C

4PLL, 8 | 8 0.002–710 0.002–808

4PLL, 4 | 4 0.002–710 0.002–808

60 Hz to

8 kHz

10x10 mm

80-BGA

*Note: Maximum input and output rates may be limited by speed rating of device. See each device’s data sheet for ordering

information.

64

Rev. 1.0

Si5324

Table 14. Product Selection Guide (Si5322/25/65/67)

Low Jitter Precision Clock Multipliers (Wideband)

Si5322

Si5325

Si5365

Si5367

2

4

2

5

707

710

707

710

1050

1400

1050

1400

0.6 ps rms typ



Notes:

1. Maximum input and output rates may be limited by speed rating of device. See each device’s data sheet for ordering

information.

2. Requires external low-cost, fixed frequency 3rd overtone 114.285 MHz crystal or reference clock.

Rev. 1.0

65

Si5324

8. Package Outline: 36-Pin QFN

Figure 9 illustrates the package details for the Si5324. Table 15 lists the values for the dimensions shown in the

illustration.

Figure 9. 36-Pin Quad Flat No-lead (QFN)

Table 15. Package Dimensions

Symbol

Millimeters

Symbol

Millimeters

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

Min

0.50

—

Nom

0.60

—

Max

0.70

12º

A

A1

b

L

0.02



0.25

aaa

bbb

ccc

ddd

eee

—

0.10

0.08

0.10

0.05

D

6.00 BSC

4.10

—

D2

e

3.95

4.25

—

0.50 BSC

6.00 BSC

4.10

—

E

—

E2

3.95

4.25

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-220, variation VJJD.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

66

Rev. 1.0

Si5324

9. PCB Land Pattern

Figure 10. PCB Land Pattern Diagram

Figure 11. Ground Pad Recommended Layout

Rev. 1.0

67

Si5324

Table 16. PCB Land Pattern Dimensions

Dimension

MIN

MAX

e

E

0.50 BSC.

5.42 REF.

D

E2

D2

GE

GD

X

4.00

4.53

—

4.20

—

0.28

Y

0.89 REF.

ZE

ZD

—

6.31

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on IPC-SM-782 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the

center ground pad.

Card Assembly

10. A No-Clean, Type-3 solder paste is recommended.

11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for

Small Body Components.

68

Rev. 1.0

Si5324

10. Top Marking

10.1. Si5324 Top Marking (QFN)

10.2. Top Marking Explanation

Mark Method:

Font Size:

Laser

0.80 mm

Right-Justified

Line 1 Marking:

Line 2 Marking:

Line 3 Marking:

Si5324Q

Customer Part Number

Q = Speed Code: A, B, C, D

See Ordering Guide for options.

C-GM

C = Product Revision

G = Temperature Range –40 to 85 °C (RoHS6)

M = QFN Package

YYWWRF

YY = Year

WW = Work Week

R = Die Revision

F = Internal code

Assigned by the Assembly House. Corresponds to the year

and work week of the mold date.

Line 4 Marking:

Pin 1 Identifier

XXXX

Circle = 0.75 mm Diameter

Lower-Left Justified

Internal Code

Rev. 1.0

69

Si5324

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2



Updated Rise/Fall Time values.

Updated minimum loop BW value.



Revision 0.2 to Revision 0.25



Updated features and applications.

Changed maximum loop bandwidth to 525 Hz

(global).



Updated PLL performance specifications in Table 1.

Added Typical Video Phase Noise Plot and data.

Removed references to Si5325.

Added note to register CKOUT_ALWAYS_ON on

how to control output to output skew.



Added Product Selection Guide to Section “7.

Ordering Guide”.



Corrected typographical errors in Table 1.

Updated typical phase noise performance page.

Updated functional description.

Added additional phase noise plots to Section “3.3.

Typical Phase Noise Performance”.



Updated Register Map.

Revised Device Top Mark.

Revision 0.25 to Revision 0.3



Changed Any-Rate to Any-Frequency

Changed Table 2, “Absolute Maximum Ratings,” on

page 6.



Added Table 11, “CKOUT_ALWAYS_ON and

SQ_ICAL Truth Table,” on page 24

Added “no bypass with CMOS outputs”

Revision 0.3 to Revision 1.0



Expanded spec Tables 1 and 2 to include all

specifications in the Reference Manual.

Reordered sections to conform to data sheet quality

convention.

Added t

specification.

SETTLE



Corrected minor register map typos.

Minor changes to Table 2.

Added maximum lock and settle times to Table 3.

Added titles to Tables 8, 9, and 10.

Updated/added selection guide Tables 13 and 14.

Removed SLEEP from register map.

Added warning about MEMS reference oscillators to

"3.1. External Reference" on page 19.

70

Rev. 1.0

Si5324

NOTES:

Rev. 1.0

71

Si5324

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

Patent Notice

Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-

intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-

tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-

ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend-

ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where

personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

72

Rev. 1.0


型号：	Si5324B-C-GM
厂家：	SILICON
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Si5324B-C-GM [SILICON]

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SI5324D-C-GMR

SI5324E-C-GM

SI5324E-C-GMR

SI5325

Si5325/26-EVB

SI53254A-D01AMR

SI53254A-D02AMR

SI53258A-D01AM

SI5325A-B-GM

SI5325A-B-GMR