Si5350B-B [SILICON]
I2C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR VCXO;
| 型号： | Si5350B-B |
| 厂家： | 
SILICON |
| 描述： | I2C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR VCXO 石英晶振 压控振荡器 |
| 文件： | 总41页 (文件大小：1787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5351A/B/C-B
2
I C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK
GENERATOR + VCXO
Features
www.silabs.com/custom-timing
Generates up to 8 non-integer-related
frequencies from 2.5 kHz to 200 MHz
Glitchless frequency changes
Separate voltage supply pins provide
level translation:
10-MSOP
Core VDD: 2.5 or 3.3 V
Output VDDO: 1.8, 2.5, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
Adjustable output delay
Available in 2 packages types:
10-MSOP: 3 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compatible
I2C user definable configuration
Exact frequency synthesis at each output
(0 ppm error)
Highly linear VCXO
Optional clock input (CLKIN)
Low output period jitter: < 70 ps pp, typ
Configurable spread spectrum selectable
at each output
Operates from a low-cost, fixed frequency
crystal: 25 or 27 MHz
20-QFN
Supports HCSL compatible swing
Supports static phase offset
Programmable rise/fall time control
Ordering Information:
See page 29
Applications
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Handheld Instrumentation
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
The Si5351 is an I2C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in
cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 200 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. It eliminates the need for higher cost, custom pullable crystals while
providing reliable operation over a wide tuning range. The Si5351C offers the same
flexibility but synchronizes to an external reference clock (CLKIN).
Functional Block Diagram
Si5351C (20-QFN)
Si5351B (20-QFN)
VDDOA
CLK0
VDDOA
MultiSynth
0
MultiSynth
0
R0
R1
R2
R3
R4
R5
R6
R7
XA
R0
R1
R2
R3
R4
R5
R6
R7
XA
XB
CLK0
CLK1
PLL
A
PLL
OSC
OSC
MultiSynth
1
CLK1
MultiSynth
1
XB
VDDOB
CLK2
VDDOB
CLK2
MultiSynth
2
MultiSynth
2
PLL
B
VCXO
CLKIN
VC
MultiSynth
3
CLK3
MultiSynth
3
CLK3
VDDOC
CLK4
VDDOC
CLK4
MultiSynth
4
MultiSynth
4
SDA
SDA
SCL
I2C
I2C
MultiSynth
5
CLK5
SCL
MultiSynth
5
CLK5
INTR
VDDOD
CLK6
VDDOD
CLK6
MultiSynth
6
MultiSynth
6
OEB
Control
Logic
Control
Logic
OEB
MultiSynth
7
CLK7
SSEN
MultiSynth
7
CLK7
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si5351A/B/C-B
Si5351A/B/C-B
Table 1. The Complete Si5350/51 Clock Generator Family
Part Number
I2C or Pin
I2C
Frequency Reference
XTAL only
Programmed?
Blank
Outputs Datasheet
3
8
8
8
3
8
8
8
3
8
3
8
3
8
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5350A-B
Si5350A-B
Si5350B-B
Si5350B-B
Si5350C-B
Si5350C-B
Si5351A-B-GT
I2C
XTAL only
Blank
Si5351A-B-GM
I2C
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL only
Blank
Si5351B-B-GM
I2C
Blank
Si5351C-B-GM
I2C
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Si5351A-Bxxxxx-GT
Si5351A-Bxxxxx-GM
Si5351B-Bxxxxx-GM
Si5351C-Bxxxxx-GM
Si5350A-Bxxxxx-GT
Si5350A-Bxxxxx-GM
Si5350B-Bxxxxx-GT
Si5350B-Bxxxxx-GM
Si5350C-Bxxxxx-GT
Si5350C-Bxxxxx-GM
Notes:
I2C
XTAL only
I2C
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL only
I2C
Pin
Pin
XTAL only
Pin
XTAL and/or Voltage
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL and/or CLKIN
Pin
Pin
Pin
1. XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.
2. Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.
2
Rev. 1.0
Si5351A/B/C-B
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.3. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.4. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.5. Control Pins (OEB, SSEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5. Configuring the Si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.1. Writing a Custom Configuration to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.2. Si5351 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3. Replacing Crystals and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs . . . . . . . . . . . . . . . . . . . . . . . .20
5.5. Replacing Crystals, Crystal Oscillators, and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.6. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.7. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.1. Power Supply Decoupling/Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.3. External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.4. External Crystal Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.5. Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.6. Trace Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
9. Si5351 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9.1. Si5351A 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9.2. Si5351B 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
9.3. Si5351C 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
9.4. Si5351A 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
11. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
11.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
12. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
12.1. 10-Pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
13. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Rev. 1.0
3
Si5351A/B/C-B
14.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4
Rev. 1.0
Si5351A/B/C-B
1. Electrical Specifications
Table 2. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
–40
3.0
Typ
25
Max
85
Unit
°C
V
Ambient Temperature
T
A
3.3
2.5
1.8
2.5
3.3
3.60
2.75
1.89
2.75
3.60
Core Supply Voltage
V
DD
2.25
1.71
2.25
3.0
V
V
Output Buffer Voltage
V
V
DDOx
V
Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
VDD and VDDOx can be operated at independent voltages.
Power supply sequencing for VDD and VDDOx requires that all VDDOx be powered up either before or at the same
time as VDD.
Table 3. DC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Enabled 3 outputs
Enabled 8 outputs
Min
—
Typ
22
Max
35
Unit
mA
mA
Core Supply Current
I
DD
—
27
45
Output Buffer Supply Current
(Per Output)*
I
C = 5 pF
—
—
2.2
—
5.6
10
mA
µA
DDOx
L
CLKIN, SDA, SCL
Vin < 3.6 V
I
CLKIN
Input Current
I
VC
—
—
—
30
—
µA
VC
3.3 V VDDO, default high
drive
Output Impedance
Z
50
O
*Note: Output clocks less than or equal to 100 MHz.
Rev. 1.0
5
Si5351A/B/C-B
Table 4. AC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Power-up Time
Symbol
Test Condition
From V = V to valid
Min
Typ
Max
Unit
DD
DDmin
T
output clock, C = 5 pF,
—
2
10
ms
RDY
L
f
> 1 MHz
CLKn
From V = V
output clock, C = 5 pF,
to valid
DDmin
DD
Power-up Time, PLL Bypass
Mode
T
—
—
0.5
—
1
ms
µs
BYP
L
f
> 1 MHz
CLKn
From OEB pulled low to valid
clock output, C = 5 pF,
Output Enable Time
T
10
OE
L
f
> 1 MHz
> 1 MHz
CLKn
CLKn
Output Frequency Transition
Time
T
f
—
—
—
333
—
10
—
µs
ps/step
%
FREQ
Output Phase Offset
P
STEP
Down spread. Selectable in 0.1%
steps.
–0.1
–2.5
Spread Spectrum Frequency
Deviation
SS
DEV
Center spread. Selectable in
0.1% steps.
±0.1
30
—
±1.5
33
%
Spread Spectrum Modulation
Rate
SS
31.5
kHz
MOD
VCXO Specifications (Si5351B only)
VCXO Control Voltage Range
VCXO Gain (configurable)
Vc
0
V
/2
V
V
ppm/V
%
DD
DD
Kv
Vc = 10–90% of V , V = 3.3 V 18
—
150
+5
DD
DD
VCXO Control Voltage Linearity
KVL
Vc = 10–90% of V
–5
±30
—
—
DD
VCXO Pull Range
(configurable)
PR
V
= 3.3 V*
0
±240
—
ppm
kHz
DD
VCXO Modulation Bandwidth
10
*Note: Contact Silicon Labs for 2.5 V VCXO operation.
Table 5. Input Clock Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
MHz
V
Crystal Frequency
f
25
–0.1
—
—
—
—
27
0.3 x V
3.60
XTAL
CLKIN Input Low Voltage
CLKIN Input High Voltage
CLKIN Frequency Range
V
IL
DD
V
0.7 x V
10
V
IH
DD
f
100
MHz
CLKIN
6
Rev. 1.0
Si5351A/B/C-B
Table 6. Output Clock Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
0.0025
—
Typ
—
Max
200
15
Unit
MHz
pF
1
Frequency Range
F
CLK
Load Capacitance
C
—
L
F
F
< 160 MHz, Measured
CLK
CLK
45
40
50
50
55
60
%
%
at V /2
DD
Duty Cycle
DC
> 160 MHz, Measured
at V /2
DD
t
—
—
1
1
1.5
1.5
—
ns
ns
V
r
20%–80%, C = 5 pF,
Default high drive strength
L
Rise/Fall Time
t
f
Output High Voltage
Output Low Voltage
V
V
– 0.6
DD
—
—
OH
C = 5 pF
L
V
—
0.6
V
OL
20-QFN, 4 outputs running,
1 per VDDO
ps, pk-
pk
—
—
—
—
—
—
—
—
40
70
50
70
50
70
50
70
95
155
90
2,3
Period Jitter
J
PER
10-MSOP or 20-QFN,
all outputs running
ps, pk-
pk
20-QFN, 4 outputs running,
1 per VDDO
ps, pk
ps, pk
2,3
Cycle-to-Cycle Jitter
J
CC
10-MSOP or 20-QFN,
all outputs running
150
95
20-QFN, 4 outputs running,
1 per VDDO
ps, pk-
pk
2,3
Period Jitter VCXO
J
PER_VCXO
10-MSOP or 20-QFN,
all outputs running
ps, pk-
pk
155
90
20-QFN, 4 outputs running,
1 per VDDO
ps, pk
ps, pk
Cycle-to-Cycle Jitter
J
2,3
CC_VCXO
VCXO
10-MSOP or 20-QFN,
all outputs running
150
Notes:
1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
2. Measured over 10K cycles. Jitter is only specified at the default high drive strength (50 output impedance).
3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10 MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20 QFN package measured with clock outputs of 33.333, 74.25,
27, 24.576, 22.5792, 28.322, 125, and 48 MHz.
Rev. 1.0
7
Si5351A/B/C-B
Table 7. Crystal Requirements1,2
Parameter
Crystal Frequency
Symbol
Min
25
6
Typ
—
Max
27
Unit
MHz
pF
f
XTAL
Load Capacitance
C
—
12
L
Equivalent Series Resistance
Crystal Max Drive Level
Notes:
r
—
—
150
—
ESR
d
100
—
µW
L
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF
capacitors on XA and XB).
2. Refer to “AN551: Crystal Selection Guide” for more details.
Table 8. I2C Specifications (SCL,SDA)1
Parameter
Symbol
Test Condition
Standard Mode
100 kbps
Fast Mode
400 kbps
Unit
Min
–0.5
Max
Min
–0.5
0.7 x V
Max
0.3 x V
LOW Level
Input Voltage
0.3 x V
2
DDI2
V
V
V
ILI2C
DDI2C
C
HIGH Level
Input Voltage
0.7 x V
2
DDI2
V
3.6
3.6
—
IHI2C
DDI2C
C
Hysteresis of
Schmitt Trigger
Inputs
V
—
—
0.1
0
V
V
HYS
LOW Level
Output Voltage
(open drain or
open collector)
at 3 mA Sink
Current
2
2
V
V
= 2.5/3.3 V
0
0.4
0.4
OLI2C
DDI2C
Input Current
I
–10
—
10
4
–10
—
10
4
µA
pF
II2C
Capacitance for
Each I/O Pin
C
V
= –0.1 to V
IN DDI2C
II2C
2
I C Bus
Timeout
T
Timeout Enabled
25
35
25
35
ms
TO
Notes:
1. Refer to NXP’s UM10204 I2C-bus specification and user manual, revision 03, for further details, go to:
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2. Only I2C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.
8
Rev. 1.0
Si5351A/B/C-B
Table 9. Thermal Characteristics
Parameter
Symbol
Test Condition
Package
10-MSOP
20-QFN
Value
131
Unit
°C/W
°C/W
Thermal Resistance
Junction to Ambient
Still Air
JA
JC
119
Thermal Resistance
Junction to Case
Still Air
20-QFN
16
°C/W
Table 10. Absolute Maximum Ratings1
Parameter
DC Supply Voltage
Symbol
Test Condition
Value
–0.5 to 3.8
Unit
V
V
DD_max
V
CLKIN, SCL, SDA
VC
–0.5 to 3.8
V
IN_CLKIN
Input Voltage
V
–0.5 to (VDD+0.3)
–0.5 to 1.3 V
–55 to 150
V
IN_VC
V
Pins XA, XB
V
IN_XA/B
Junction Temperature
T
°C
J
Soldering Temperature (Pb-free
profile)
T
260
°C
2
PEAK
Soldering Temperature Time at
TPEAK (Pb-free profile)
T
20–40
Sec
2
P
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
Rev. 1.0
9
Si5351A/B/C-B
2. Detailed Block Diagrams
VDDO
VDD
Si5351A 3-Output
PLL
A
MultiSynth
R0
0
CLK0
CLK1
XA
OSC
PLL
B
XB
MultiSynth
R1
1
SDA
I2C
MultiSynth
R2
2
CLK2
Interface
SCL
10-MSOP
GND
VDD
Si5351A 8-Output
VDDOA
CLK0
MultiSynth
R0
R1
R2
R3
R4
R5
R6
R7
PLL
A
0
XA
MultiSynth
1
CLK1
OSC
VDDOB
CLK2
PLL
B
XB
MultiSynth
2
MultiSynth
3
CLK3
A0
VDDOC
CLK4
MultiSynth
4
I2C
SDA
Interface
MultiSynth
5
CLK5
SCL
VDDOD
CLK6
MultiSynth
6
OEB
Control
Logic
CLK7
MultiSynth
7
SSEN
20-QFN
GND
Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices
10
Rev. 1.0
Si5351A/B/C-B
VDD
Si5351B
VDDOA
CLK0
MultiSynth
0
R0
XA
XB
PLL
OSC
MultiSynth
1
CLK1
R1
R2
R3
R4
R5
R6
R7
VDDOB
CLK2
MultiSynth
2
VCXO
VC
MultiSynth
3
CLK3
VDDOC
CLK4
MultiSynth
4
SDA
SCL
I2C
Interface
CLK5
MultiSynth
5
VDDOD
CLK6
MultiSynth
6
OEB
Control
Logic
SSEN
CLK7
MultiSynth
7
20-QFN
GND
VDD
Si5351C
VDDOA
CLK0
MultiSynth
0
R0
R1
R2
R3
R4
R5
R6
R7
XA
XB
PLL
A
OSC
MultiSynth
1
CLK1
VDDOB
CLK2
MultiSynth
2
PLL
B
CLKIN
MultiSynth
3
CLK3
VDDOC
CLK4
MultiSynth
4
SDA
I2C
Interface
CLK5
MultiSynth
5
SCL
INTR
VDDOD
CLK6
MultiSynth
6
Control
Logic
OEB
CLK7
MultiSynth
7
20-QFN
GND
Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices
Rev. 1.0
11
Si5351A/B/C-B
3. Functional Description
2
The Si5351 is a versatile I C programmable clock generator that is ideally suited for replacing crystals, crystal
oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in
Figure 3. The device consists of an input stage, two synthesis stages, and an output stage.
The input stage accepts an external crystal (XTAL), a control voltage input (VC), or a clock input (CLKIN)
depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an
high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional
dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for
generating output frequencies as low as 2.5 kHz. Crosspoint switches at each of the synthesis stages allows total
flexibility in routing any of the inputs to any of the outputs.
Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating
synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to
synthesize clocks for multiple clock domains in a design.
Input
Stage
Synthesis
Stage 1
Synthesis
Stage 2
Output
Stage
VDDOA
Multi
Synth
0
R0
R1
R2
R3
R4
R5
R6
R7
CLK0
CLK1
Multi
Synth
1
Div
CLKIN
PLL A
VDDOB
Multi
Synth
2
(SSC)
CLK2
CLK3
XA
XB
PLL B
(VCXO)
Multi
Synth
3
OSC
XTAL
VDDOC
Multi
Synth
4
CLK4
CLK5
Multi
Synth
5
VCXO
VC
VDDOD
Multi
Synth
6
CLK6
CLK7
Multi
Synth
7
Figure 3. Si5351 Block Diagram
12
Rev. 1.0
Si5351A/B/C-B
3.1. Input Stage
3.1.1. Crystal Inputs (XA, XB)
The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of
the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating
asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or
27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
Internal load capacitors are provided to eliminate the need for external components when connecting a crystal to
the Si5351. The total internal XTAL load capacitance (C ) can be selected to be 0, 6, 8, or 10 pF. Crystals with
L
alternate load capacitance requirements are supported using additional external load capacitance 2 pF (e.g., by
using 4 pF capacitors on XA and XB) as shown in Figure 4. Refer to application note AN551 for crystal
recommendations.
XA
XB
Optional internal
load capacitance
0, 6, 8,10 pF
Optional additional
external load
capacitance
(< 2 pF)
Figure 4. External XTAL with Optional Load Capacitors
3.1.2. External Clock Input (CLKIN)
The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs.
CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to
30 MHz.
3.1.3. Voltage Control Input (VC)
The VCXO architecture of the Si5351B eliminates the need for an external pullable crystal. Only a standard, low-
cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 4 on page 6 for VCXO specification details.
A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 5 on page 14.
Rev. 1.0
13
Si5351A/B/C-B
3.2. Synthesis Stages
The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply
the lower frequency input references to a high-frequency intermediate clock. The second stage uses high-
resolution MultiSynth fractional dividers to generate the required output frequencies. Only two unique frequencies
above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz
(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,
125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs
(CLKS4-7).
A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input.
This allows each of the PLLs to lock to a different source for generating independent free-running and synchronous
clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second
stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows
any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread
spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.
All VCXO outputs are generated by PLLB only. The Multisynth high-resolution dividers synthesizes the VCXO
output’s center frequency up to 112.5 MHz. The center frequency is then controlled (or pulled) by the VC input. An
interesting feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This
creates a VCXO with multiple output frequencies controlled from one VC input as shown in Figure 5.
Frequencies down to 2.5 kHz can be generated by applying the R divider at the output of the Multisynth (see
Figure 5 below).
Fixed Frequency
Crystal (non-pullable)
XA
XB
Multi
The clock frequency
generated from CLK0 is
controlled by the VC input
OSC
R0
Synth
0
CLK0
CLK1
CLK2
VC
Multi
Synth
1
Control
Voltage
R1
R2
VCXO
Additional MultiSynths
can be “linked” to the
VCXO to generate
additional clock
Multi
Synth
2
frequencies
Figure 5. Using the Si5351 as a Multi-Output VCXO
14
Rev. 1.0
Si5351A/B/C-B
3.3. Output Stage
An additional level of division (R) is available at the output stage for generating clocks as low as 2.5 kHz. All output
drivers generate CMOS level outputs with separate output voltage supply pins (VDDOx) allowing a different voltage
signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks.
3.4. Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its
frequency, which effectively reduces the overall amplitude of its radiated energy. Note that spread spectrum is not
available on clocks synchronized to PLLB or to the VCXO.
The Si5351 supports several levels of spread spectrum allowing the designer to chose an ideal compromise
between system performance and EMI compliance.
Reduced
Amplitude
and EMI
Reduced
Amplitude
and EMI
Center
Frequency
Amplitude
fc
fc
fc
No Spread
Spectrum
Center Spread
Down Spread
Figure 6. Available Spread Spectrum Profiles
3.5. Control Pins (OEB, SSEN)
The Si5351 offers control pins for enabling/disabling clock outputs and spread spectrum.
3.5.1. Output Enable (OEB)
The output enable pin allows enabling or disabling outputs clocks. Output clocks are enabled when the OEB pin is
held low, and disabled when pulled high. When disabled, the output state is configurable as output high, output low,
or high-impedance.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is pulled low. When OEB is pulled high, the clock is allowed to complete its full clock cycle before
going into a disabled state.
3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only
This control pin allows disabling the spread spectrum feature for all outputs that were configured with spread
spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient method of
evaluating the effect of using spread spectrum clocks during EMI compliance testing.
Rev. 1.0
15
Si5351A/B/C-B
4. I2C Interface
Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
2
2
I C interface. The following is a list of the common features that are controllable through the I C interface. For a
2
complete listing of available I C registers and programming steps, please see “AN619: Manually Generating an
Si5351 Register Map.”
Read Status Indicators
Crystal Reference Loss of signal, LOS_XTAL, reg0[3]
CLKIN Loss of signal, LOS_CLKIN, reg0[4]
PLLA and/or PLLB Loss of lock, LOL_A or LOL_B, reg0[6:5]
Configuration of multiplication and divider values for the PLLs, MultiSynth dividers
Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)
Control of the cross point switch selection for each of the PLLs and MultiSynth dividers
Set output clock options
Enable/disable for each clock output
Invert/non-invert for each clock output
Output divider values (2n, n=1.. 7)
Output state when disabled (stop hi, stop low, Hi-Z)
Output phase offset
2
The I C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
2
The I C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7.
Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
2
I C specification.
VDD
>1k
>1k
Si5351
SCL
SDA
I2C Bus
4.7 k
INTR
A0
I2C Address Select:
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)
Figure 7. I2C and Control Signals
The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that
2
require more than one Si5351 on a single I C bus.
6
5
4
3
2
1
0
Slave Address
1
1
0
0
0
0
0/1
A0
Figure 8. Si5351 I2C Slave Address
16
Rev. 1.0
Si5351A/B/C-B
Data is transferred MSB first in 8-bit words as specified by the I C specification. A write command consists of a 7-
bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write
burst operation is also shown where every additional data word is written using to an auto-incremented address.
2
Write Operation – Single Byte
S
Slv Addr [6:0]
0
A
Reg Addr [7:0]
A
Data [7:0]
A
A
P
Write Operation - Burst (Auto Address Increment)
Slv Addr [6:0] Reg Addr [7:0] Data [7:0]
S
0
A
A
Data [7:0] A P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
From slave to master
From master to slave
P– STOPcondition
Figure 9. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 10.
Read Operation – Single Byte
S
Slv Addr [6:0]
0
A
Reg Addr [7:0]
A
P
P
S
Slv Addr [6:0]
1
A
Data [7:0]
N
Read Operation - Burst (Auto Address Increment)
S
S
Slv Addr [6:0]
Slv Addr [6:0]
0
1
A
A
Reg Addr [7:0]
Data [7:0]
A P
A
Data [7:0]
N P
Reg Addr +1
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
From slave to master
From master to slave
P– STOPcondition
Figure 10. I2C Read Operation
AC and DC electrical specifications for the SCL and SDA pins are shown in Table 8. The timing specifications and
2
2
timing diagram for the I C bus is compatible with the I C-Bus Standard. SDA timeout is supported for compatibility
with SMBus interfaces.
Rev. 1.0
17
Si5351A/B/C-B
5. Configuring the Si5351
2
The Si5351 is a highly flexible clock generator which is entirely configurable through its I C interface. The device’s
default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time
programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for
applications that need a clock present at power-up (e.g., for providing a clock to a processor).
Power-Up
NVM
(OTP)
RAM
Default
Config
I2C
Figure 11. Si5351 Memory Configuration
During a power cycle the contents of the NVM are copied into random access memory (RAM), which sets the
device configuration that will be used during normal operation. Any changes to the device configuration after
2
power-up are made by reading and writing to registers in the RAM space through the I C interface.
5.1. Writing a Custom Configuration to RAM
To simplify device configuration, Silicon Labs has released the ClockBuilder Desktop. The software serves two
purposes: to configure the Si5351 with optimal configuration based on the desired frequencies and to control the
EVB when connected to a host PC.
The optimal configuration can be saved from the software in text files that can be used in any system, which
2
configures the device over I C. ClockBuilder Desktop can be downloaded from www.silabs.com/ClockBuilder and
runs on Windows XP, Windows Vista, and Windows 7.
2
Once the configuration file has been saved, the device can be programmed via I C by following the steps shown in
Figure 12.
18
Rev. 1.0
Si5351A/B/C-B
Disable Outputs
Set CLKx_DIS high; Reg. 3 = 0xFF
Powerdown all output drivers
Reg. 16, 17, 18, 19, 20, 21, 22, 23 =
0x80
Set interrupt masks
(see register 2 description)
Write new configuration to device using
the contents of the register map
Register
Map
generated by ClockBuilder Desktop. This
step also powers up the output drivers.
Use ClockBuilder
, 149-170 and 183)
(Registers 15-92
Desktop v3.1 or later
Apply PLLA and PLLB soft reset
Reg. 177 = 0xAC
Enable desired outputs
(see Register 3)
Figure 12. I2C Programming Procedure
Rev. 1.0
19
Si5351A/B/C-B
5.2. Si5351 Application Examples
The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show
how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs.
5.3. Replacing Crystals and Crystal Oscillators
Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies
for replacing crystals and crystal oscillators. A 3-output version packaged in a small 10-MSOP is also available for
applications that require fewer clocks. An example is shown in Figure 13.
XA
XB
CLK0
CLK1
Multi
Synth
0
125 MHz
48 MHz
Ethernet
PHY
OSC
PLL
27 MHz
Multi
Synth
1
USB
Controller
CLK2
CLK3
Multi
Synth
2
28.322 MHz
74.25 MHz
HDMI
Port
Multi
Synth
3
CLK4
CLK5
Multi
Synth
4
74.25/1.001 MHz
24.576 MHz
Video/Audio
Processor
Multi
Synth
5
Multi
Synth
6
CLK6
CLK7
22.5792 MHz
33.3333 MHz
Multi
Synth
7
CPU
Si5351A
Note: Si5351A replaces crystals, XOs, and PLLs.
Figure 13. Using the Si5351A to Replace Multiple Crystals, Crystal Oscillators, and PLLs
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs
The Si5351B combines free-running clock generation and a VCXO in a single package for cost sensitive video
applications. An example is shown in Figure 14.
Free-running
Clocks
Ethernet
PHY
XA
XB
CLK0
CLK1
Multi
Synth
0
125 MHz
OSC
PLL
27 MHz
Multi
Synth
1
48 MHz
USB
Controller
CLK2
CLK3
Multi
Synth
2
28.322 MHz
74.25 MHz
HDMI
Port
Multi
Synth
3
VC
VCXO
CLK4
CLK5
Multi
Synth
4
74.25/1.001 MHz
24.576 MHz
Video/Audio
Processor
Multi
Synth
5
Si5351B
VCXO Clock
Outputs
Note: FBW = 10 kHz
Figure 14. Using the Si5351B to Replace Crystals, Crystal Oscillators, VCXOs, and PLLs
20
Rev. 1.0
Si5351A/B/C-B
5.5. Replacing Crystals, Crystal Oscillators, and PLLs
The Si5351C generates synchronous clocks for applications that require a fully integrated PLL instead of a VCXO.
Because of its dual PLL architecture, the Si5351C is capable of generating both synchronous and free-running
clocks. An example is shown in Figure 15.
Free-running
Clocks
Ethernet
PHY
XA
XB
CLK0
CLK1
Multi
Synth
0
125 MHz
48 MHz
OSC
PLL
25 MHz
Multi
Synth
1
USB
Controller
CLK2
CLK3
Multi
Synth
2
28.322 MHz
74.25 MHz
HDMI
Port
Multi
Synth
3
CLKIN
PLL
54 MHz
CLK4
CLK5
Multi
Synth
4
74.25/1.001 MHz
24.576 MHz
Video/Audio
Processor
Multi
Synth
5
Si5351C
Synchronous
Clocks
Figure 15. Using the Si5351C to Replace Crystals, Crystal Oscillators, and PLLs
5.6. Applying a Reference Clock at XTAL Input
The Si5351 can be driven with a clock signal through the XA input pin. This is especially useful when in need of
generating clock outputs in two synchronization domains. With the Si5351C, one reference clock can be provided
at the CLKIN pin and at XA.
VIN = 1 VPP
25/27 MHz
Multi
Synth
0
PLLA
PLLB
XA
Multi
Synth
1
0.1 µF
OSC
XB
Multi
Synth
N
Note: Float the XB input while driving
the XA input with a clock
Figure 16. Si5351 Driven by a Clock Signal
Rev. 1.0
21
Si5351A/B/C-B
5.7. HCSL Compatible Outputs
The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).
The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
must also be inverted to generate a differential pair. See register setting CLKx_INV.
ZO = 50
R1
Multi
Synth
0
PLLA
PLLB
0
0
511
240
R2
OSC
HCSL
CLKIN
ZO = 50
R1
Multi
Synth
1
511
240
R2
Multi
Synth
N
Note: The complementary -180 degree
out of phase output clock is generated
using the INV function
Figure 17. Si5351 Output is HCSL Compatible
22
Rev. 1.0
Si5351A/B/C-B
6. Design Considerations
The Si5351 is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance. Refer to “AN554: Si5350/51 PCB Layout Guide” for
additional layout recommendations.
6.1. Power Supply Decoupling/Filtering
The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage
regulators to help minimize the number of external bypass components. All that is recommended is one 0.1 to
1.0 µF decoupling capacitor per power supply pin. This capacitor should be mounted as close to the VDD and
VDDOx pins as possible without using vias.
6.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be
powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.
6.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
6.4. External Crystal Load Capacitors
The Si5351 provides the option of using internal and external crystal load capacitors. If internal load capacitance is
insufficient, capacitors of value < 2 pF may be used to increased equivalent load capacitance. If external load
capacitors are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection
Guide” for more details.
6.5. Unused Pins
Unused voltage control pin should be tied to GND.
Unused CLKIN pin should be tied to GND.
Unused XA/XB pins should be left floating. Refer to "5.6. Applying a Reference Clock at XTAL Input" on page 21
when using XA as a clock input pin.
Unused output pins (CLK0–CLK7) should be left floating.
Unused VDDOx pins should be tied to VDD.
6.6. Trace Characteristics
The Si5351A/B/C features various output current drive strengths. It is recommended to configure the trace
characteristics as shown in Figure 18 when the default high drive strength is used.
ZO = 50 ohms
R = 0 ohms
CLK
(Optional resistor for
EMI management)
Figure 18. Recommended Trace Characteristics with Default Drive Strength Setting
Rev. 1.0
23
Si5351A/B/C-B
7. Register Map Summary
For many applications, the Si5351's register values are easily configured using ClockBuilder Desktop software.
However, for customers interested in using the Si5351 in operating modes beyond the capabilities available with
ClockBuilder™, refer to “AN619: Manually Generating an Si5351 Register Map” for a detailed description of the
Si5351 registers and their usage.
8. Register Descriptions
Refer to “AN619: Manually Generating an Si5351 Register Map” for a detailed description of Si5351 registers.
24
Rev. 1.0
Si5351A/B/C-B
9. Si5351 Pin Descriptions
9.1. Si5351A 20-pin QFN
XA
XB
1
2
3
4
5
15
14
13
12
11
CLK7
VDDOD
CLK0
GND
PAD
A0
SCL
SDA
CLK1
VDDOA
Figure 19. Si5351A 20-QFN Top View
Table 11. Si5351A Pin Descriptions
Pin
Number
1
Pin Name
Function
Pin Type
XA
XB
1
I
I
Input pin for external crystal.
Input pin for external crystal.
Output clock 0.
2
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
A0
13
O
O
O
O
O
O
O
O
I
12
Output clock 1.
9
Output clock 2.
8
Output clock 3.
19
Output clock 4.
17
Output clock 5.
16
Output clock 6.
15
Output clock 7.
2
3
I C address bit.
2
SCL
4
I
I C bus serial clock input. Pull-up to VDD core with 1 k
2
SDA
5
I/O
I
I C bus serial data input. Pull-up to VDD core with 1 k
SSEN
OEB
6
Spread spectrum enable. High = enabled, Low = disabled.
Output driver enable. Low = enabled, High = disabled.
Core voltage supply pin. See 6.2.
7
I
VDD
20
P
P
P
P
P
P
VDDOA
VDDOB
VDDOC
VDDOD
GND
11
Output voltage supply pin for CLK0 and CLK1. See 6.2.
Output voltage supply pin for CLK2 and CLK3. See 6.2.
Output voltage supply pin for CLK4 and CLK5. See 6.2.
Output voltage supply pin for CLK6 and CLK7. See 6.2.
Ground. Use multiple vias to ensure a solid path to GND.
10
18
14
Center Pad
1. I = Input, O = Output, P = Power.
2. Input pins are not internally pulled up.
Rev. 1.0
25
Si5351A/B/C-B
9.2. Si5351B 20-Pin QFN
CLK7
XA
XB
1
2
3
4
5
15
14
13
12
11
VDDOD
CLK0
GND
PAD
VC
CLK1
SCL
SDA
VDDOA
Figure 20. Si5351B 20-QFN Top View*
Table 12. Si5351B Pin Descriptions
Pin
Pin Name
1
Function
Input pin for external crystal
Pin Type
Number
XA
XB
1
I
I
2
Input pin for external crystal
Output clock 0
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
VC
13
O
O
O
O
O
O
O
O
I
12
Output clock 1
9
Output clock 2
8
Output clock 3
19
Output clock 4
17
Output clock 5
16
Output clock 6
15
Output clock 7
3
VCXO control voltage input
2
SCL
4
I
I C bus serial clock input. Pull-up to VDD core with 1 k
2
SDA
5
I/O
I
I C bus serial data input. Pull-up to VDD core with 1 k
SSEN
OEB
6
Spread spectrum enable. High = enabled, Low = disabled.
Output driver enable. Low = enabled, High = disabled.
Core voltage supply pin
7
I
VDD
20
P
P
P
P
P
P
VDDOA
VDDOB
VDDOC
VDDOD
GND
11
Output voltage supply pin for CLK0 and CLK1. See 6.2
Output voltage supply pin for CLK2 and CLK3. See 6.2
Output voltage supply pin for CLK4 and CLK5. See 6.2
Output voltage supply pin for CLK6 and CLK7. See 6.2
Ground
10
18
14
Center Pad
1. I = Input, O = Output, P = Power
2. Input pins are not internally pulled up.
26
Rev. 1.0
Si5351A/B/C-B
9.3. Si5351C 20-Pin QFN
XA
XB
1
2
3
4
5
15 CLK7
14 VDDOD
GND
PAD
13
12
INTR
SCL
SDA
CLK0
CLK1
11 VDDOA
Table 13. Si5351C Pin Descriptions
Pin
1
Number
Pin Name
Function
Input pin for external crystal.
Pin Type
20-QFN
XA
1
2
I
XB
I
Input pin for external crystal.
Output clock 0.
Output clock 1.
Output clock 2.
Output clock 3.
Output clock 4.
Output clock 5.
Output clock 6.
Output clock 7.
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
INTR
13
12
9
O
O
O
O
O
O
O
O
O
8
19
17
16
15
3
Interrupt pin. Open drain active low output, requires a pull-up
resistor greater than 1 k
2
SCL
SDA
4
I
I/O
I
I C bus serial clock input. Pull-up to VDD core with 1 k
2
5
I C bus serial data input. Pull-up to VDD core with 1 k
CLKIN
OEB
6
PLL clock input.
7
I
Output driver enable. Low = enabled, High = disabled.
Core voltage supply pin
VDD
20
P
P
P
P
P
P
VDDOA
VDDOB
VDDOC
VDDOD
GND
11
Output voltage supply pin for CLK0 and CLK1. See 6.2
Output voltage supply pin for CLK2 and CLK3. See 6.2
Output voltage supply pin for CLK4 and CLK5. See 6.2
Output voltage supply pin for CLK6 and CLK7. See 6.2
Ground.
10
18
14
Center Pad
Notes:
1. I = Input, O = Output, P = Power.
2. Input pins are not internally pulled up.
Rev. 1.0
27
Si5351A/B/C-B
9.4. Si5351A 10-Pin MSOP
VDD
XA
CLK0
CLK1
GND
1
2
3
10
9
XB
8
SCL
SDA
VDDO
CLK2
4
5
7
6
Figure 21. Si5351A 10-MSOP Top View
Table 14. Si5351A 10-MSOP Pin Descriptions
Pin
Number
Pin Name
Pin Type*
Function
10-MSOP
XA
2
3
I
I
Input pin for external crystal.
Input pin for external crystal.
Output clock 0.
XB
CLK0
CLK1
CLK2
SCL
10
9
O
O
O
I
Output clock 1.
6
Output clock 2.
2
4
Serial clock input for the I C bus. This pin must be pulled-up using a pull-
up resistor of at least 1 k.
2
SDA
5
I/O
Serial data input for the I C bus. This pin must be pulled-up using a pull-up
resistor of at least 1 k.
VDD
1
7
P
P
Core voltage supply pin.
VDDO
Output voltage supply pin for CLK0, CLK1, and CLK2. See "6.2. Power
Supply Sequencing" on page 23.
GND
8
P
Ground.
*Note: I = Input, O = Output, P = Power
28
Rev. 1.0
Si5351A/B/C-B
10. Ordering Information
Factory pre-programmed Si5351 devices (e.g., with bootup frequencies) can be requested using the ClockBuilder
web-based utility available at: www.silabs.com/ClockBuilder. A unique part number is assigned to each custom
configuration as indicated in Figure 22. Blank, un-programmed Si5351 devices (with no boot-up frequency) do not
contain a custom code.
Figure 22. Device Part Numbers
An evaluation kit containing ClockBuilder Desktop software and hardware enable easy evaluation of the Si5351A/B/
C. The orderable part numbers for the evaluation kits are provided in Figure 23.
Figure 23. Si5351A/B/C Evaluation Kit
Rev. 1.0
29
Si5351A/B/C-B
11. Package Outlines
Figure 24 shows the package details for the Si5351 in a 20-QFN package. Table 15 lists the values for the
dimensions shown in the illustration.
11.1. 20-pin QFN
C
D2
A
D
B
D2/2
A1
L
E
E2
E2/2
b
A
e
Figure 24. 20-pin QFN Package Drawing
30
Rev. 1.0
Si5351A/B/C-B
Table 15. Package Dimensions
Dimension
Min
0.80
0.00
0.20
Nom
0.85
Max
0.90
0.05
0.30
A
A1
b
—
0.25
D
4.00 BSC
2.70
D2
e
2.65
2.75
0.50 BSC
4.00 BSC
2.70
E
E2
L
2.65
0.35
—
2.75
0.45
0.10
0.40
aaa
—
bbb
ccc
ddd
—
—
—
—
—
—
0.10
0.08
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.0
31
Si5351A/B/C-B
12. Land Pattern: 20-Pin QFN
Figure 25 shows the recommended land pattern details for the Si5351 in a 20-Pin QFN package. Table 16 lists the
values for the dimensions shown in the illustration.
Figure 25. 20-Pin QFN Land Pattern
32
Rev. 1.0
Si5351A/B/C-B
Table 16. PCB Land Pattern Dimensions
Symbol
C1
Millimeters
4.0
C2
4.0
E
0.50 BSC
0.30
X1
X2
2.70
Y1
0.80
Y2
2.70
Notes:
General
1. All dimensions shown are in millimeters
(mm) unless otherwise noted.
2. This land pattern design is based on IPC-
7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask
defined (NSMD). Clearance between the
solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-
polished stencil with trapezoidal walls should
be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm
(5 mils).
6. The ratio of stencil aperture to land pad size
should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on
1.30 mm pitch should be used for the center
ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is
recommended.
9. The recommended card reflow profile is per
the JEDEC/IPC J-STD-020 specification for
Small Body components.
Rev. 1.0
33
Si5351A/B/C-B
12.1. 10-Pin MSOP Package Outline
Figure 26 illustrates the package details for the Si5351 in a 10-pin MSOP package. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 26. 10-pin MSOP Package Drawing
34
Rev. 1.0
Si5351A/B/C-B
Table 17. 10-MSOP Package Dimensions
Dimension
Min
—
Nom
Max
1.10
0.15
0.95
0.33
0.23
A
A1
A2
b
—
—
0.00
0.75
0.17
0.08
0.85
—
c
—
D
3.00 BSC
4.90 BSC
3.00 BSC
0.50 BSC
0.60
E
E1
e
L
0.40
0.80
L2
q
0.25 BSC
—
0
8
aaa
bbb
ccc
ddd
—
—
—
—
—
0.20
0.25
0.10
0.08
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.0
35
Si5351A/B/C-B
13. Land Pattern: 10-Pin MSOP
Figure 27 shows the recommended land pattern details for the Si5351 in a 10-Pin MSOP package. Table 18 lists
the values for the dimensions shown in the illustration.
Figure 27. 10-Pin MSOP Land Pattern
36
Rev. 1.0
Si5351A/B/C-B
Table 18. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
Max
C1
E
4.40 REF
0.50 BSC
G1
X1
Y1
Z1
3.00
—
—
0.30
1.40 REF
—
5.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-
020C specification for Small Body components.
Rev. 1.0
37
Si5351A/B/C-B
14. Top Marking
14.1. 20-Pin QFN Top Marking
Figure 28. 20-Pin QFN Top Marking
14.2. Top Marking Explanation
Mark Method:
Pin 1 Mark:
Laser
Filled Circle = 0.50 mm Diameter
(Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Line 2 Mark Format:
Device Part Number
TTTTTT = Mfg Code*
Si5351
Manufacturing Code from the Assembly Purchase
Order Form.
Line 3 Mark Format:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the assembly date.
*Note: The code shown in the “TTTTTT” line does not correspond to the orderable part number or frequency plan. It is used
for package assembly quality tracking purposes only.
38
Rev. 1.0
Si5351A/B/C-B
14.3. 10-Pin MSOP Top Marking
Figure 29. 10-Pin MSOP Top Marking
14.4. Top Marking Explanation
Mark Method:
Pin 1 Mark:
Laser
Mold Dimple (Bottom-Left Corner)
0.60 mm (24 mils)
Device Part Number
TTTT = Mfg Code*
Font Size:
Line 1 Mark Format
Line 2 Mark Format:
Si5351
Line 2 from the “Markings” section of the Assembly
Purchase Order form.
Line 3 Mark Format:
YWW = Date Code
Assigned by the Assembly House.
Y = Last Digit of Current Year (Ex: 2013 = 3)
WW = Work Week of Assembly Date.
*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for
package assembly quality tracking purposes only.
Rev. 1.0
39
Si5351A/B/C-B
DOCUMENT CHANGE LIST
Revision 0.75 to Revision 1.0
Extended frequency range from 8 MHz-160 MHz to
2.5 kHz-200 MHz.
Updated block diagrams for clarity.
Added complete Si5350/1 family table, Table 1.
Added top mark information.
Added land pattern drawings.
Added PowerUp Time, PLL Bypass mode, Table 4.
Clarified Down Spread step sizes in Table 4.
Updated max jitter specs (typ unchanged) in Table 6.
Clarified power supply sequencing requirement,
Section 6.2.
40
Rev. 1.0
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
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www.silabs.com/CBPro
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www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
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相关型号：
SI5350C-A-GM
Processor Specific Clock Generator, 133MHz, CMOS, 4 X 4 MM, MO-220VGGD-8, QFN-20
SILICON
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