SiM3C156-B-GQ [SILICON]
High-Performance, Low-Power, 32-Bit Precision32â¢; 高性能，低功耗， 32位Precision32â ?? ¢
| 型号： | SiM3C156-B-GQ |
| 厂家： | 
SILICON |
| 描述： | High-Performance, Low-Power, 32-Bit Precision32⢠|
| 文件： | 总90页 (文件大小：805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiM3C1xx
High-Performance, Low-Power, 32-Bit Precision32™
MCU Family with up to 256 kB of Flash
32-bit ARM® Cortex™-M3 CPU
Low Power Features
-
-
-
80 MHz maximum frequency
-
-
-
-
-
-
85 nA current mode with voltage supply monitor enabled
350 nA current mode with RTC (internal oscillator)
620 nA current mode with RTC (external oscillator)
10 µs wakeup (lowest power mode); 1.5 µs analog setting time
275 µA/MHz active current
Single-cycle multiplication, hardware division support
Nested vectored interrupt control (NVIC) with 16 levels of
interrupt priority
Memory
Clocks can be gated off from unused peripherals to save power
-
-
-
32–256 kB Flash, in-system programmable
2 x 12-Bit Analog-to-Digital Converters
8–32 kB SRAM (including 4 kB retention SRAM)
-
-
-
-
Up to 28 input channels
External bus interface supports up to 16 MB of external mem-
ory and a parallel LCD interface with QVGA resolution
Up to 250 ksps 12-bit mode or 1 Msps 10-bit mode
Single, simultaneous, and interleaving modes supported
Power Management
Channel sequencer enables automatic multiplexing of multiple
channels without firmware intervention
-
-
-
Low drop-out (LDO) regulator
Power-on reset circuit and brownout detectors
5-to-3.3 V voltage regulator supports up to 150 mA to drive the
device directly from up to 5 V supply
-
Internal VREF or external VREF supported
2 x 10-Bit Digital-to-Analog Converters
-
-
DMA support for waveform generation
-
-
Programmable external regulator supports up to 3.6 V,
1000 mA
Four-word circular buffer to enable 12-bit mode
Multiple power modes supported for low power optimization
16-Channel Capacitance-to-Digital Converter
Clock Sources
-
-
Supports buttons, sliders, wheels, and capacitive proximity
Fast conversion time; <1 µA wake-on-touch average current
-
Internal oscillator with PLL: Fine frequency resolution up to
80 MHz; spread-spectrum mode for reduced EMI
Two Low-Current Comparators
-
-
-
-
-
-
Low power internal oscillator: 20 MHz and 2.5 MHz modes
Integrated 6-bit programmable reference voltage
400 nA current consumption in low power mode
Low frequency internal oscillator: 16.4 kHz
External oscillators: Crystal, RC, C, CMOS and RTC Crystal
Flexible clock divider: Reduce frequency by up to 128x from
any clock source
16-Channel DMA Controller
-
Supports ADC, DAC, I2C, I2S, SPI, USART, AES, EPCA,
128/192/256-bit Hardware AES Encryption
capacitive sensing, external triggers, and timers
-
Hardware-supported Electronic Codebook (ECB), Cipher-Block
Chaining (CBC) and Counter (CTR) algorithms
Up to 65 Flexible I/O
-
Up to 59 contiguous GPIO with two priority crossbars providing
flexibility in pin assignments; 12 x 5 V tolerant GPIO
-
All cipher operations can be performed without any firmware
intervention for a set of 4-word blocks (up to 32 kB)
-
Up to 6 programmable high drive capable (5–300 mA, 1.8–6 V)
I/O can drive LEDs, power MOSFETs, buzzers, etc.
16/32-bit CRC
-
Hardware support for common 32-bit and 16-bit polynomials
Communication Interfaces
Timers/Counters
-
-
2 x USARTs and 2 x UARTs with IrDA and ISO7816 SmartCard
3 x SPIs, 2 x I2C, I2S (receive and transmit)
-
-
-
2 x 32-bit or 4 x 16-bit timers with capture/compare
2 x 16-bit, 2-channel counters with capture/compare/PWM
On-Chip Debugging
-
16-bit, 6-channel counter with capture/compare/PWM and
dead-time controller with differential outputs
16-bit low power timer/pulse counter operational in the lowest
power mode
Serial wire debug (SWD) and JTAG allow for full-speed, non-
intrusive debug
-
-
-
Serial wire viewer (SWV) available in 64 / 80 / 92-pin packages
Cortex-M3 embedded trace macrocell (ETM) in 80 / 92-pin
packages
-
-
32-bit real time clock (RTC) with multiple alarms
Watchdog timer
Temperature Range: –40 to +85 °C
Package Options
Current-to-Voltage Converter
-
Supports up to 6 mA input range
-
-
-
QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm)
TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm)
LGA option: 92-pin (7 x 7 mm)
Supply Voltage
-
-
2.7 to 5.5 V (regulator enabled)
1.8 to 3.6 V (regulator disabled)
Preliminary Rev. 0.8 2/12
Copyright © 2012 by Silicon Laboratories
SiM3C1xx
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
SiM3C1xx
Table of Contents
1. Related Documents and Conventions ...............................................................................4
1.1. Related Documents........................................................................................................4
1.1.1. SiM3U1xx/SiM3C1xx Reference Manual...............................................................4
1.1.2. Hardware Access Layer (HAL) API Description ....................................................4
1.1.3. ARM Cortex-M3 Reference Manual.......................................................................4
1.2. Conventions ...................................................................................................................4
2. Typical Connection Diagrams ............................................................................................5
2.1. Power .............................................................................................................................5
3. Electrical Specifications......................................................................................................6
3.1. Electrical Characteristics................................................................................................6
3.2. Thermal Conditions ......................................................................................................28
3.3. Absolute Maximum Ratings..........................................................................................28
4. Precision32™ SiM3C1xx System Overview ....................................................................31
4.1. Power ...........................................................................................................................33
4.1.1. LDO and Voltage Regulator (VREG0).................................................................33
4.1.2. Voltage Supply Monitor (VMON0) .......................................................................33
4.1.3. External Regulator (EXTVREG0) ........................................................................33
4.1.4. Power Management Unit (PMU)..........................................................................33
4.1.5. Device Power Modes...........................................................................................34
4.2. I/O.................................................................................................................................36
4.2.1. General Features.................................................................................................36
4.2.2. High Drive Pins (PB4)..........................................................................................36
4.2.3. 5 V Tolerant Pins (PB3).......................................................................................36
4.2.4. Crossbars ............................................................................................................36
4.3. Clocking........................................................................................................................37
4.3.1. PLL (PLL0)...........................................................................................................38
4.3.2. Low Power Oscillator (LPOSC0) .........................................................................38
4.3.3. Low Frequency Oscillator (LFOSC0)...................................................................38
4.3.4. External Oscillators (EXTOSC0)..........................................................................38
4.4. Data Peripherals...........................................................................................................39
4.4.1. 16-Channel DMA Controller.................................................................................39
4.4.2. 128/192/256-bit Hardware AES Encryption (AES0) ............................................39
4.4.3. 16/32-bit CRC (CRC0).........................................................................................39
4.5. Counters/Timers and PWM..........................................................................................40
4.5.1. Programmable Counter Array (EPCA0, PCA0, PCA1)........................................40
4.5.2. 32-bit Timer (TIMER0, TIMER1)..........................................................................40
4.5.3. Real-Time Clock (RTC0) .....................................................................................41
4.5.4. Low Power Timer (LPTIMER0)............................................................................41
4.5.5. Watchdog Timer (WDTIMER0)............................................................................41
4.6. Communications Peripherals .......................................................................................42
4.6.1. External Memory Interface (EMIF0).....................................................................42
4.6.2. USART (USART0, USART1)...............................................................................42
4.6.3. UART (UART0, UART1)......................................................................................42
4.6.4. SPI (SPI0, SPI1)..................................................................................................43
2
Preliminary Rev. 0.8
SiM3C1xx
4.6.5. I2C (I2C0, I2C1)...................................................................................................43
4.6.6. I2S (I2S0).............................................................................................................44
4.7. Analog ..........................................................................................................................45
4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1)..............................45
4.7.2. Sample Sync Generator (SSG0) .........................................................................45
4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1) ............................................45
4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0)............................46
4.7.5. Low Current Comparators (CMP0, CMP1)..........................................................46
4.7.6. Current-to-Voltage Converter (IVC0)...................................................................46
4.8. Reset Sources..............................................................................................................47
4.9. Security ........................................................................................................................48
4.10.On-Chip Debugging .....................................................................................................48
5. Pin Definitions and Packaging Information.....................................................................49
5.1. SiM3C1x7 Pin Definitions.............................................................................................49
5.2. SiM3C1x6 Pin Definitions.............................................................................................57
5.3. SiM3C1x4 Pin Definitions.............................................................................................64
6. Ordering Information.........................................................................................................68
6.1. LGA-92 Package Specifications...................................................................................70
6.1.1. LGA-92 Solder Mask Design ...............................................................................72
6.1.2. LGA-92 Stencil Design ........................................................................................72
6.1.3. LGA-92 Card Assembly.......................................................................................72
6.2. TQFP-80 Package Specifications ................................................................................73
6.2.1. TQFP-80 Solder Mask Design.............................................................................76
6.2.2. TQFP-80 Stencil Design......................................................................................76
6.2.3. TQFP-80 Card Assembly.....................................................................................76
6.3. QFN-64 Package Specifications ..................................................................................77
6.3.1. QFN-64 Solder Mask Design...............................................................................79
6.3.2. QFN-64 Stencil Design........................................................................................79
6.3.3. QFN-64 Card Assembly.......................................................................................79
6.4. TQFP-64 Package Specifications ................................................................................80
6.4.1. TQFP-64 Solder Mask Design.............................................................................83
6.4.2. TQFP-64 Stencil Design......................................................................................83
6.4.3. TQFP-64 Card Assembly.....................................................................................83
6.5. QFN-40 Package Specifications ..................................................................................84
6.5.1. QFN-40 Solder Mask Design...............................................................................86
6.5.2. QFN-40 Stencil Design........................................................................................86
6.5.3. QFN-40 Card Assembly.......................................................................................86
7. Revision Specific Behavior...............................................................................................87
7.1. Revision Identification ..................................................................................................87
7.2. Comparator Rising/Falling Edge Flags in Debug Mode (CMP0, CMP1)......................88
7.2.1. Problem ...............................................................................................................88
7.2.2. Impacts ................................................................................................................88
7.2.3. Workaround .........................................................................................................88
7.2.4. Resolution............................................................................................................88
Contact Information ................................................................................................................90
Preliminary Rev. 0.8
3
SiM3C1xx
1. Related Documents and Conventions
1.1. Related Documents
This data sheet accompanies several documents to provide the complete description of the SiM3C1xx device
family.
1.1.1. SiM3U1xx/SiM3C1xx Reference Manual
The Silicon Laboratories SiM3U1xx/SiM3C1xx Reference Manual provides detailed functional descriptions for the
SiM3C1xx devices.
1.1.2. Hardware Access Layer (HAL) API Description
The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read
each bit in the SiM3C1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual.
1.1.3. ARM Cortex-M3 Reference Manual
The ARM-specific features like the Nested Vector Interrupt Controller are described in the ARM Cortex-M3
reference documentation. The online reference manual can be found here:
http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3.
1.2. Conventions
The block diagrams in this document use the following formatting conventions:
Internal Module
Other Internal
Peripheral Block
External Memory
Block
DMA Block
Memory Block
External to MCU
Block
Input_Pin
Output_Pin
Functional Block
Internal_Input_Signal
Internal_Output_Signal
REGn_NAME / BIT_NAME
Figure 1.1. Block Diagram Conventions
4
Preliminary Rev. 0.8
SiM3C1xx
2. Typical Connection Diagrams
This section provides typical connection diagrams for SiM3C1xx devices.
2.1. Power
Figure 2.1 shows a typical connection diagram for the power pins of the SiM3C1xx devices when the internal
regulator is in use.
SiM3C1xx Device
5 V (in)
VREGn
VREGIN
3.3 V (out)
VIOHD
VDD
1 uF and 0.1 uF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
VIO
VSS
VSSHD
Figure 2.1. Connection Diagram with Voltage Regulator Used
Figure 2.2 shows a typical connection diagram for the power pins of the SiM3C1xx devices when the internal
regulator is not used.
SiM3C1xx Device
1.8-3.6 V (in)
VREGn
VREGIN
VIOHD
1 uF and 0.1 uF bypass
capacitors required for
VDD
each power pin placed
as close to the pins as
possible.
VIO
VSS
VSSHD
Figure 2.2. Connection Diagram with Voltage Regulator Not Used
Preliminary Rev. 0.8
5
SiM3C1xx
3. Electrical Specifications
3.1. Electrical Characteristics
All electrical parameters in all tables are specified under the conditions listed in Table 3.1, unless stated otherwise.
Table 3.1. Recommended Operating Conditions
Parameter
Symbol
Conditions
Min
1.8
4
Typ
—
—
—
—
—
—
—
Max
3.6
5.5
3.6
Units
Operating Supply Voltage on VDD
Operating Supply Voltage on VREGIN
V
V
V
V
V
V
DD
V
EXTVREG0 Not Used
EXTVREG0 Used
REGIN
3.0
1.8
2.7
1.8
Operating Supply Voltage on VIO
Operating Supply Voltage on VIOHD
V
V
DD
IO
V
HV Mode (default)
LV Mode
6.0
3.6
IOHD
V
V
Voltage on I/O pins, Port Bank 0, 1
and 2 I/O
V
V
V
IN
SS
IO
Voltage on I/O pins, Port Bank 3 I/O
and RESET
V
SiM3C1x7
PB3.0–PB3.7 and
RESET
V
V +2.0
V
V
—
—
IN
SS
IO
SiM3C1x7
PB3.8 - PB3.11
V
Lowest
of
SS
V +2.0
IO
or
V
REGIN
SiM3C1x6
PB3.0–PB3.5 and
RESET
V
V +2.0
V
V
—
—
SS
IO
V
Lowest
of
SiM3C1x6
PB3.6–PB3.9
SS
V +2.0
IO
or
V
REGIN
SiM3C1x4
RESET
V
V +2.0
V
V
—
—
SS
IO
SiM3C1x4
PB3.0–PB3.3
V
Lowest
of
SS
V +2.0
IO
or
V
REGIN
Voltage on I/O pins, Port Bank 4 I/O
V
V
V
V
—
—
—
—
—
IN
SSHD
0
IOHD
80
System Clock Frequency (AHB)
Peripheral Clock Frequency (APB)
Operating Ambient Temperature
Operating Junction Temperature
f
MHz
MHz
°C
AHB
f
0
50
APB
T
–40
–40
85
A
T
105
°C
J
Note: All voltages with respect to V
.
SS
6
Preliminary Rev. 0.8
SiM3C1xx
Table 3.2. Power Consumption
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Digital Core Supply Current
2,3,4,5
Normal Mode
—Full speed
I
I
I
I
I
I
F
F
= 80 MHz,
= 40 MHz
—
33
36.5
mA
DD
DD
DD
DD
DD
DD
AHB
with code executing from Flash,
peripheral clocks ON
APB
F
= F
= 20 MHz
—
—
—
10.5
2.0
22
13.3
3.8
mA
mA
mA
AHB
APB
APB
F
= F
= 2.5 MHz
AHB
2,3,4,5
Normal Mode
—Full speed
F
= 80 MHz,
= 40 MHz
24.9
AHB
with code executing from Flash,
peripheral clocks OFF
F
APB
F
= F
= 20 MHz
—
—
—
7.8
1.2
10
3
mA
mA
mA
AHB
APB
APB
F
= F
= 2.5 MHz
AHB
2,3,4,6
Power Mode 1
—Full speed
F
= 80 MHz,
= 40 MHz
30.5
35.5
AHB
with code executing from RAM,
peripheral clocks ON
F
APB
F
= F
= 20 MHz
—
—
—
8.5
1.7
20
10
3.5
23
mA
mA
mA
AHB
APB
APB
F
= F
= 2.5 MHz
AHB
2,3,4,6
Power Mode 1
—Full speed
F
= 80 MHz,
= 40 MHz
AHB
with code executing from RAM,
peripheral clocks OFF
F
APB
F
= F
= 20 MHz
—
—
—
5.3
1.0
19
7.3
2.8
22
mA
mA
mA
AHB
APB
APB
F
= F
= 2.5 MHz
AHB
2,3,4
Power Mode 2
—Core halted
F
= 80 MHz,
= 40 MHz
AHB
with peripheral clocks ON
F
APB
F
= F
= 20 MHz
—
—
—
—
7.8
1.3
9.7
3
mA
mA
µA
AHB
APB
APB
F
V
V
= F
= 2.5 MHz
AHB
2,3
Power Mode 3
= 1.8 V, T = 25 °C
175
250
—
—
DD
DD
A
= 3.0 V, T = 25 °C
µA
A
Notes:
1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the
DD
functions increases supply current by the specified amount.
3. Includes all peripherals that cannot have clocks gated in the Clock Control module.
4. Includes supply current from internal regulator and PLL0OSC (>20 MHz) or LPOSC0 (<=20 MHz).
5. Flash execution numbers use 2 wait states for 80 MHz and 0 wait states at 20 MHz or less.
6. RAM execution numbers use 0 wait states for all frequencies.
7. IDAC output current and IVC input current not included.
8. Bias current only. Does not include dynamic current from oscillator running at speed.
Preliminary Rev. 0.8
7
SiM3C1xx
Table 3.2. Power Consumption (Continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
2,3
Power Mode 9 —Low Power
I
RTC Disabled,
—
85
—
nA
DD
Shutdown with VREG0 disabled,
powered through VDD and VIO
V
= 1.8 V, T = 25 °C
A
DD
RTC w/ 16.4 kHz LFO,
= 1.8 V, T = 25 °C
—
—
—
—
—
—
—
—
350
620
145
500
800
300
650
950
—
—
—
—
—
—
—
—
nA
nA
nA
nA
nA
nA
nA
nA
V
DD
A
RTC w/ 32.768 kHz Crystal,
V
V
= 1.8 V, T = 25 °C
DD
A
RTC Disabled,
= 3.0 V, T = 25 °C
DD
A
RTC w/ 16.4 kHz LFO,
= 3.0 V, T = 25 °C
V
DD
A
RTC w/ 32.768 kHz Crystal,
V
= 3.0 V, T = 25 °C
DD
A
2,3
Power Mode 9 —Low Power
I
RTC Disabled,
VREGIN
Shutdown with VREG0 in low-
power mode, VDD and VIO pow-
ered through VREG0 (Includes
VREG0 current)
VREGIN = 5 V, T = 25 °C
A
RTC w/ 16.4 kHz LFO,
VREGIN = 5 V, T = 25 °C
A
RTC w/ 32.768 kHz Crystal,
VREGIN = 5 V, T = 25 °C
A
VIOHD Current (High-drive I/O dis-
abled)
I
HV Mode (default)
LV Mode
—
—
2.5
2
5
µA
nA
VIOHD
—
Notes:
1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the
DD
functions increases supply current by the specified amount.
3. Includes all peripherals that cannot have clocks gated in the Clock Control module.
4. Includes supply current from internal regulator and PLL0OSC (>20 MHz) or LPOSC0 (<=20 MHz).
5. Flash execution numbers use 2 wait states for 80 MHz and 0 wait states at 20 MHz or less.
6. RAM execution numbers use 0 wait states for all frequencies.
7. IDAC output current and IVC input current not included.
8. Bias current only. Does not include dynamic current from oscillator running at speed.
8
Preliminary Rev. 0.8
SiM3C1xx
Table 3.2. Power Consumption (Continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Analog Peripheral Supply Currents
Voltage Regulator (VREG0)
I
Normal Mode, T = 25 °C
BGDIS = 0, SUSEN = 0
—
—
—
—
—
—
300
—
—
650
—
µA
µA
µA
µA
nA
nA
VREGIN
A
Normal Mode, T = 85 °C
A
BGDIS = 0, SUSEN = 0
Suspend Mode, T = 25 °C
75
—
A
BGDIS = 0, SUSEN = 1
Suspend Mode, T = 85 °C
115
—
A
BGDIS = 0, SUSEN = 1
Sleep Mode, T = 25 °C
90
—
A
BGDIS = 1, SUSEN = X
Sleep Mode, T = 85 °C
500
A
BGDIS = 1, SUSEN = X
External Regulator (EXTVREG0)
I
Regulator
—
—
—
—
—
—
215
7
250
—
µA
µA
mA
µA
µA
nA
EXTVREG
Current Sensor
PLL0 Oscillator (PLL0OSC)
I
Operating at 80 MHz
Operating at 20 MHz
Operating at 2.5 MHz
Operating at 16.4 kHz,
1.75
190
40
1.86
—
PLLOSC
Low-Power Oscillator (LPOSC0)
I
LPOSC
—
Low-Frequency Oscillator
(LFOSC0)
I
215
—
LFOSC
T = 25 °C
A
Operating at 16.4 kHz,
—
—
500
nA
T = 85 °C
A
Notes:
1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the
DD
functions increases supply current by the specified amount.
3. Includes all peripherals that cannot have clocks gated in the Clock Control module.
4. Includes supply current from internal regulator and PLL0OSC (>20 MHz) or LPOSC0 (<=20 MHz).
5. Flash execution numbers use 2 wait states for 80 MHz and 0 wait states at 20 MHz or less.
6. RAM execution numbers use 0 wait states for all frequencies.
7. IDAC output current and IVC input current not included.
8. Bias current only. Does not include dynamic current from oscillator running at speed.
Preliminary Rev. 0.8
9
SiM3C1xx
Table 3.2. Power Consumption (Continued)
Parameter
Symbol
Conditions
Min
—
—
—
—
—
—
—
—
—
Typ
3.8
840
185
65
Max
4.7
950
220
80
Units
mA
µA
8
External Oscillator (EXTOSC0)
I
FREQCN = 111
FREQCN = 110
FREQCN = 101
FREQCN = 100
FREQCN = 011
FREQCN = 010
FREQCN = 001
FREQCN = 000
EXTOSC
µA
µA
25
30
µA
10
15
µA
5
10
µA
3
8
µA
SARADC0,
SARADC1
I
Sampling at 1 Msps, highest
power mode settings.
1.2
1.5
mA
SARADC
Sampling at 250 ksps, lowest
power mode settings.
—
390
510
µA
Temperature Sensor
Internal SAR Reference
VREF0
I
—
—
—
—
—
—
—
—
—
—
75
680
160
75
0.5
3
105
750
190
100
—
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
TSENSE
I
Normal Power Mode
Low Power Mode
REFFS
I
REFP
Comparator 0 (CMP0),
Comparator 1 (CMP1)
I
CMPMD = 11
CMPMD = 10
CMP
—
CMPMD = 01
10
25
55
75
—
CMPMD = 00
—
Capacitive Sensing (CAPSENSE0)
I
Continuous Conversions
80
CS
7
IDAC0 ,
I
90
IDAC
7
IDAC1
7
IVC0
I
I
= 0
IN
—
—
1.5
15
1.9
25
µA
µA
IVC
Voltage Supply Monitor (VMON0)
I
VMON
Notes:
1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the
DD
functions increases supply current by the specified amount.
3. Includes all peripherals that cannot have clocks gated in the Clock Control module.
4. Includes supply current from internal regulator and PLL0OSC (>20 MHz) or LPOSC0 (<=20 MHz).
5. Flash execution numbers use 2 wait states for 80 MHz and 0 wait states at 20 MHz or less.
6. RAM execution numbers use 0 wait states for all frequencies.
7. IDAC output current and IVC input current not included.
8. Bias current only. Does not include dynamic current from oscillator running at speed.
10
Preliminary Rev. 0.8
SiM3C1xx
Table 3.2. Power Consumption (Continued)
Parameter
Flash Current on VDD
Write Operation
Erase Operation
Notes:
Symbol
Conditions
Min
Typ
Max
Units
I
—
—
—
—
8
mA
mA
FLASH-W
I
15
FLASH-E
1. Perhipheral currents drop to zero when peripheral clock and peripheral are disabled, unless otherwise noted.
2. Currents are additive. For example, where I is specified and the mode is not mutually exclusive, enabling the
DD
functions increases supply current by the specified amount.
3. Includes all peripherals that cannot have clocks gated in the Clock Control module.
4. Includes supply current from internal regulator and PLL0OSC (>20 MHz) or LPOSC0 (<=20 MHz).
5. Flash execution numbers use 2 wait states for 80 MHz and 0 wait states at 20 MHz or less.
6. RAM execution numbers use 0 wait states for all frequencies.
7. IDAC output current and IVC input current not included.
8. Bias current only. Does not include dynamic current from oscillator running at speed.
Table 3.3. Power Mode Wake Up Times
Parameter
Symbol
Conditions
Min
—
Typ
425
1.35
12
Max
—
Units
µs
Power Mode 3 Fast Wake Time
Power Mode 3 Wake Time
Power Mode 9 Wake Time
t
PM3FW
t
t
—
—
ms
PM3
PM9
—
—
µs
Preliminary Rev. 0.8
11
SiM3C1xx
Table 3.4. Reset and Supply Monitor
Parameter
Symbol
Conditions
Early Warning
Reset
Min
2.10
1.95
1.81
1.70
4.2
—
Typ
2.20
2.05
1.85
1.74
4.4
1.4
1
Max
2.30
2.1
Units
V
V
High Supply Monitor Threshold
(VDDHITHEN = 1)
V
VDDMH
DD
V
V
Low Supply Monitor Threshold
(VDDHITHEN = 0)
V
Early Warning
Reset
1.88
1.77
4.6
V
DD
VDDML
V
V
Supply Monitor Threshold
V
Early Warning
Rising Voltage on V
V
REGIN
VREGM
Power-On Reset (POR) Threshold
V
—
V
POR
DD
Falling Voltage on V
0.8
10
1.3
V
DD
V
Ramp Time
t
Time to V > 1.8 V
—
3000
100
µs
ms
DD
RMP
DD
Reset Delay from POR
t
Relative to V
>
DD
3
—
POR
V
POR
Reset Delay from non-POR source
t
Time between release
of reset source and
code execution
—
10
—
µs
RST
RESET Low Time to Generate Reset
t
50
—
—
—
1
ns
RSTL
Missing Clock Detector Response
Time (final rising edge to reset)
t
F
> 1 MHz
0.4
ms
MCD
AHB
Missing Clock Detector Trigger
Frequency
F
—
—
7.5
2
13
—
kHz
µs
MCD
MON
V
Supply Monitor Turn-On Time
t
DD
12
Preliminary Rev. 0.8
SiM3C1xx
Table 3.5. On-Chip Regulators
Parameter
Symbol
Conditions
Min
Typ
Max
Units
3.3 V Regulator Characteristics (VREG0, Supplied from VREGIN Pin)
Output Voltage (at VDD pin) 4 < V < 5.5
V
3.2
3.2
2.3
3.3
3.3
2.8
3.4
3.4
3.6
V
V
V
DDOUT
REGIN
BGDIS = 0, SUSEN = 0
4 < V < 5.5
REGIN
BGDIS = 0, SUSEN = 1
4 < V < 5.5
REGIN
BGDIS = 1, SUSEN = X
= 500 µA
I
DDOUT
4 < V
< 5.5
2.1
2.65
3.3
V
REGIN
BGDIS = 1, SUSEN = X
= 5 mA
I
DDOUT
Output Current (at VDD pin)*
I
4 < V
< 5.5
REGIN
—
—
—
—
150
5
mA
mA
DDOUT
BGDIS = 0, SUSEN = X
4 < V < 5.5
REGIN
BGDIS = 1, SUSEN = X
Output Load Regulation
Output Capacitance
V
BGDIS = 0
—
1
0.1
—
1
mV/mA
µF
DDLR
C
10
VDD
*Note: Total current VREG0 is capable of providing. Any current consumed by the SiM3C1xx reduces the current available to
external devices powered from VDD.
Preliminary Rev. 0.8
13
SiM3C1xx
Table 3.6. External Regulator
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input Voltage Range (at VRE-
GIN)
V
3.0
—
3.6
V
REGIN
Output Voltage (at
EXREGOUT)
V
Programmable in
100 mV steps
1.8
—
3.6
V
EXREGOUT
NPN Current Drive
PNP Current Drive
I
400 mV Dropout
12
–6
—
—
—
—
mA
mA
NPN
I
V
> V
-
PNP
EXREGBD
REGIN
1.5 V
EXREGBD Voltage (PNP
Mode)
V
V
>= 3.5 V
V
–
—
—
V
EXREGBD
REGIN
REGIN
2.0
V
< 3.5 V
1.5
—
—
—
—
V
REGIN
Standalone Mode Output
Current
I
400mV Dropout
11.5
mA
EXTREGBD
External Capacitance with
External BJT
C
4.7
—
—
1
—
—
µF
BJT
Standalone Mode Load Reg-
ulation
LR
mV/mA
STAND-
ALONE
Standalone Mode External
Capacitance
C
47
—
—
nF
STAND-
ALONE
Current Limit Range
Current Limit Accuracy
Foldback Limit Accuracy
Current Sense Resistor
Internal Pull-Down
Internal Pull-Up
I
1 Sense Resistor
10
—
—
—
—
—
—
—
—
—
10
5
720
10
20
1
mA
%
LIMIT
%
R
SENSE
R
—
—
k
k
PD
R
PU
Current Sensor
Sensing Pin Voltage
V
V
Measured at
EXTREGSP or
EXTREGSN pin
2.2
10
—
V
V
EXTREGSP
EXTREGSN
REGIN
Differential Sensing Voltage
V
(V
-
—
8
1600
mV
DIFF
EXTREGSP
EXTREGSN
V
)
Current at EXTREGSN Pin
Current at EXTREGSP Pin
I
—
—
—
—
A
A
EXTREGSN
I
V
x 2
DIFF
EXTREGSP
00 + 12
14
Preliminary Rev. 0.8
SiM3C1xx
Table 3.7. Flash Memory
Parameter
Symbol
Conditions
One 16-bit Half Word
One Page
Min
20
Typ
21
Max
22
Units
µs
1
Write Time
t
WRITE
ERASE
1
Erase Time
t
20
21
22
ms
t
Full Device
20
21
22
ms
ERALL
V
Voltage During Programming
V
1.8
20k
TBD
—
3.6
—
V
DD
PROG
Endurance (Write/Erase Cycles)
N
TBD
TBD
Cycles
Years
WE
2
Retention
t
T = 85 °C, 1k Cycles
—
RET
A
Notes:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple AHB clock cycles.
2. Additional Data Retention Information is published in the Quarterly Quality and Reliability Report.
Table 3.8. Internal Oscillators
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Phase-Locked Loop (PLL0OSC)
Calibrated Output Frequency*
f
Full Temperature and
Supply Range
77
—
—
79
430
95
80
—
—
MHz
PLL0OSC
Power Supply Sensitivity*
Temperature Sensitivity*
PSS
T = 25 °C,
ppm/V
ppm/°C
PLL0OSC
PLL0OSC
PLL0OSC
A
Fout = 79 MHz
TS
V
= 3.3 V,
DD
Fout = 79 MHz
Adjustable Output Frequency
Range
f
23
—
—
80
—
MHz
µs
Lock Time
t
f
= 20 MHz,
1.7
PLL0LOCK
REF
PLL0OSC
f
= 80 MHz,
M=24, N=99,
LOCKTH = 0
f
= 32 kHz,
—
91
—
µs
REF
f
= 80 MHz,
PLL0OSC
M=0, N=2440,
LOCKTH = 0
Preliminary Rev. 0.8
15
SiM3C1xx
Table 3.8. Internal Oscillators
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Low Power Oscillator (LPOSC0)
Oscillator Frequency
f
Full Temperature and
Supply Range
19
20
20
21
MHz
MHz
MHz
LPOSC
T = 25 °C,
19.6
2.375
20.4
2.625
A
V
= 3.3 V
DD
Divided Oscillator Frequency
f
Full Temperature and
Supply Range
2.5
LPOSCD
Power Supply Sensitivity
Temperature Sensitivity
PSS
T = 25 °C
—
—
0.5
55
—
—
%/V
LPOSC
A
TS
V
= 3.3 V
ppm/°C
LPOSC
DD
Low Frequency Oscillator (LFOSC0)
Oscillator Frequency
f
Full Temperature and
Supply Range
13.4
15.8
16.4
16.4
19.7
17.3
kHz
kHz
LFOSC
T = 25 °C,
A
V
= 3.3 V
DD
Power Supply Sensitivity
Temperature Sensitivity
PSS
T = 25 °C
—
—
2.4
0.2
—
—
%/V
LFOSC
A
TS
V
= 3.3 V
%/°C
LFOSC
DD
RTC0 Oscillator (RTC0OSC)
Missing Clock Detector Trigger
Frequency
f
—
8
15
55
kHz
%
RTCMCD
RTC Robust Duty Cycle Range
DC
25
—
RTC
*Note: PLL0OSC in free-running oscillator mode
Table 3.9. External Oscillator
Parameter
Symbol
Conditions
Min
Typ
Max
Units
External Input CMOS Clock
Frequency
f
0
—
50
MHz
CMOS
External Input CMOS Clock High Time
External Input CMOS Clock Low Time
t
9
9
—
—
—
—
ns
ns
CMOSH
t
CMOSL
16
Preliminary Rev. 0.8
SiM3C1xx
Table 3.10. SAR ADC
Parameter
Symbol
Conditions
12 Bit Mode
Min
Typ
12
10
—
Max
Units
Bits
Bits
V
Resolution
N
bits
10 Bit Mode
Supply Voltage Requirements
(VDD)
V
High Speed Mode
Low Power Mode
12 Bit Mode
2.2
1.8
—
3.6
3.6
250
1
ADC
—
V
Throughput Rate
(High Speed Mode)
f
f
—
ksps
Msps
ksps
ksps
ns
S
S
10 Bit Mode
—
—
Throughput Rate
(Low Power Mode)
12 Bit Mode
—
—
62.5
250
—
10 Bit Mode
—
—
Tracking Time
t
High Speed Mode
Low Power Mode
High Speed Mode
Low Power Mode
230
450
—
—
TRK
SAR
CNV
—
—
ns
SAR Clock Frequency
Conversion Time
f
—
16.24
4
MHz
MHz
ns
—
—
t
10-Bit Conversion,
SAR Clock = 16 MHz,
APB Clock = 40 MHz.
762.5
Sample/Hold Capacitor
Input Pin Capacitance
Input Mux Impedance
C
Gain = 1
Gain = 0.5
—
—
—
—
—
—
1
5
2.5
18
20
300
550
—
—
—
—
—
—
—
pF
pF
pF
pF
SAR
C
High Quality Inputs
Normal Inputs
High Quality Inputs
Normal Inputs
IN
R
MUX
Voltage Reference Range
Input Voltage Range*
V
V
V
REF
DD
V
Gain = 1
0
—
V
V
IN
REF
Gain = 0.5
0
—
2xV
V
REF
Power Supply Rejection Ratio
DC Performance
PSRR
—
70
—
dB
ADC
Integral Nonlinearity
INL
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
—
—
–1
—
±1
±1.9
±0.5
1.8
LSB
LSB
LSB
LSB
±0.2
±0.7
±0.2
Differential Nonlinearity
(Guaranteed Monotonic)
DNL
±0.5
*Note: Absolute input pin voltage is limited by the lower of the supply at VDD and VIO.
Preliminary Rev. 0.8
17
SiM3C1xx
Table 3.10. SAR ADC (Continued)
Parameter
Symbol
Conditions
Min
–2
Typ
0
Max
2
Units
LSB
Offset Error (using AGND)
E
12 Bit Mode, VREF =2.4 V
10 Bit Mode, VREF =2.4 V
OFF
–1
0
1
LSB
Offset Temperatue Coefficient
Slope Error
TC
—
0.004
—
LSB/°C
%
OFF
E
12 Bit Mode
–0.07 –0.02
0.02
M
Dynamic Performance with External Reference or Internal Reference in High Speed Mode, 10 kHz Sine
Wave Input 1dB below full scale, Max throughput
Signal-to-Noise
SNR
SNDR
THD
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
62
58
62
58
—
—
—
—
66
60
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise Plus Distortion
66
60
Total Harmonic Distortion (Up to
5th Harmonic)
78
77
Spurious-Free Dynamic Range
SFDR
–79
–74
Dynamic Performance with Internal Reference in Low Power Mode, 10 kHz Sine Wave Input 1dB below full
scale, Max throughput
Signal-to-Noise
SNR
SNDR
THD
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
TBD
TBD
TBD
TBD
—
66
60
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise Plus Distortion
66
60
Total Harmonic Distortion (Up to
5th Harmonic)
78
—
77
Spurious-Free Dynamic Range
SFDR
—
–72
–71
—
*Note: Absolute input pin voltage is limited by the lower of the supply at VDD and VIO.
18
Preliminary Rev. 0.8
SiM3C1xx
Table 3.11. IDAC
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Static Performance
Resolution
N
10
Bits
LSB
LSB
bits
Integral Nonlinearity
INL
—
—
±0.5
±0.5
±2
±1
Differential Nonlinearity (Guaranteed
Monotonic)
DNL
Output Compliance Range
Full Scale Output Current
V
—
2.0
1.00
495
—
—
2.046
1.023
511.5
250
V
– 1.0
DD
V
mA
OCR
I
2 mA Range
1 mA Range
0.5 mA Range
2.10
1.05
525
—
OUT
mA
µA
Offset Error
E
nA
OFF
Full Scale Error Tempco
VDD Power Supply Rejection Ratio
TC
2 mA Range
2 mA Range
—
100
—
ppm/°C
ppm/V
k
FS
—
-220
1
—
Test Load Impedance (to V
)
R
—
—
SS
TEST
Dynamic Performance
Output Settling Time to 1/2 LSB
min output to max
output
—
—
1.2
3
—
—
µs
µs
Startup Time
Preliminary Rev. 0.8
19
SiM3C1xx
Table 3.12. Capacitive Sense
Parameter
Symbol
Conditions
12-bit Mode
13-bit Mode
14-bit Mode
16-bit Mode
Min
—
Typ
25
27
29
33
45
Max
—
Units
µs
Single Conversion Time
(Default Configuration)
t
single
—
—
µs
—
—
µs
—
—
µs
Maximum External Capacitive Load
C
C
Highest Gain Setting
(default)
—
—
pF
L
L
Lowest Gain Setting
—
—
500
50
—
—
pF
Maximum External Series Imped-
ance
Highest Gain Setting
(default)
k
Table 3.13. Current-to-Voltage Converter (IVC)
Parameter
Supply Voltage (VDD)
Symbol
Conditions
Min
2.2
Typ
—
Max
3.6
Units
V
V
DDIVC
Input Pin Voltage
Minimum Input Current (source)
Integral Nonlinearity
Full Scale Output
Slope
V
2.2
—
VDD
—
V
IN
IN
I
100
–0.6
—
—
µA
%
INL
—
0.6
IVC
IVCOUT
V
1.65
1.66
—
V
M
Input Range 1 mA
(INxRANGE = 101)
1.62
1.73
V/mA
IVC
Input Range 2 mA
(INxRANGE = 100)
810
540
400
320
265
—
830
550
415
330
275
—
855
565
425
340
285
500
mV/mA
mV/mA
mV/mA
mV/mA
mV/mA
ns
Input Range 3 mA
(INxRANGE = 011)
Input Range 4 mA
(INxRANGE = 010)
Input Range 5 mA
(INxRANGE = 001)
Input Range 6 mA
(INxRANGE = 000)
Settling Time to 0.1%
V
IVCOUT
20
Preliminary Rev. 0.8
SiM3C1xx
Table 3.14. Voltage Reference Electrical Characteristics
V
= 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Internal Fast Settling Reference
Output Voltage
V
–40 to +85 °C,
1.62
1.65
1.68
V
REFFS
V
= 1.8–3.6 V
DD
Temperature Coefficient
Turn-on Time
TC
—
—
—
50
—
—
1.5
—
ppm/°C
µs
REFFS
t
REFFS
Power Supply Rejection
PSRR
400
ppm/V
REFFS
On-Chip Precision Reference (VREF0)
Valid Supply Range
V
VREF2X = 0
VREF2X = 1
1.8
2.7
—
—
3.6
3.6
V
V
V
DD
Output Voltage
V
25 °C ambient,
VREF2X = 0
1.195
1.2
1.205
REFP
25 °C ambient,
VREF2X = 1
2.39
2.4
2.41
V
Short-Circuit Current
Temperature Coefficient
Load Regulation
I
—
—
—
—
25
10
—
—
mA
SC
TC
LR
ppm/°C
ppm/µA
VREFP
VREFP
Load = 0 to 200 µA to
VREFGND
4.5
Load Capacitor
Turn-on Time
C
Load = 0 to 200 µA to
VREFGND
0.1
—
—
—
—
µF
VREFP
t
4.7 µF tantalum, 0.1 µF
ceramic bypass
3.8
ms
VREFPON
0.1 µF ceramic bypass
VREF2X = 0
—
—
—
200
320
560
—
—
—
µs
Power Supply Rejection
PSRR
ppm/V
ppm/V
VREFP
VREF2X = 1
External Reference
Input Current
I
Sample Rate = 250 ksps;
VREF = 3.0 V
—
5.25
—
µA
EXTREF
Preliminary Rev. 0.8
21
SiM3C1xx
Table 3.15. Temperature Sensor
Parameter
Offset
Symbol
Conditions
T = 0 °C
Min
—
Typ
760
±14
2.8
TBD
1
Max
—
Units
mV
V
E
OFF
A
Offset Error*
Slope
T = 0 °C
—
—
mV
OFF
A
M
—
—
mV/°C
µV/°C
°C
Slope Error*
Linearity
E
—
—
M
—
—
Turn-on Time
—
1.8
—
µs
*Note: Represents one standard deviation from the mean.
22
Preliminary Rev. 0.8
SiM3C1xx
Table 3.16. Comparator
Parameter
Symbol
Conditions
+100 mV Differential
–100 mV Differential
+100 mV Differential
–100 mV Differential
CMPHYP = 00
CMPHYP = 01
CMPHYP = 10
CMPHYP = 11
CMPHYN = 00
CMPHYN = 01
CMPHYN = 10
CMPHYN = 11
CMPHYP = 00
CMPHYP = 01
CMPHYP = 10
CMPHYP = 11
CMPHYN = 00
CMPHYN = 01
CMPHYN = 10
CMPHYN = 11
CMPHYP = 00
CMPHYP = 01
CMPHYP = 10
CMPHYP = 11
CMPHYN = 00
CMPHYN = 01
CMPHYN = 10
CMPHYN = 11
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
100
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
Response Time, CMPMD = 00
(Highest Speed)
t
RESP0
150
ns
Response Time, CMPMD = 11
(Lowest Power)
t
1.4
µs
RESP3
3.5
µs
Positive Hysterisis
Mode 0 (CPMD = 00)
HYS
0.37
7.9
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
CP+
16.7
32.8
0.37
–7.9
–16.1
–32.7
0.47
5.85
12
Negative Hysterisis
Mode 0 (CPMD = 00)
HYS
CP-
Positive Hysterisis
Mode 1 (CPMD = 01)
HYS
CP+
24.4
0.47
–6.0
–12.1
–24.6
0.66
4.55
9.3
Negative Hysterisis
Mode 1 (CPMD = 01)
HYS
CP-
Positive Hysterisis
Mode 2 (CPMD = 10)
HYS
CP+
19
Negative Hysterisis
Mode 2 (CPMD = 10)
HYS
0.6
CP-
–4.5
–9.5
–19
Preliminary Rev. 0.8
23
SiM3C1xx
Table 3.16. Comparator (Continued)
Parameter
Positive Hysterisis
Symbol
HYS
Conditions
CMPHYP = 00
CMPHYP = 01
CMPHYP = 10
CMPHYP = 11
CMPHYN = 00
CMPHYN = 01
CMPHYN = 10
CMPHYN = 11
Min
—
Typ
1.37
3.8
7.8
15.6
1.37
–3.9
–7.9
–16
—
Max
—
Units
mV
mV
mV
mV
mV
mV
mV
mV
V
CP+
Mode 3 (CPMD = 11)
—
—
—
—
—
—
Negative Hysterisis
Mode 3 (CPMD = 11)
HYS
—
—
CP-
—
—
—
—
—
—
Input Range (CP+ or CP–)
Input Pin Capacitance
V
–0.25
—
V
+0.25
DD
IN
C
PB2 Pins
PB3 Pins
7.5
10.5
75
—
—
—
—
5
pF
CP
—
pF
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Offset Voltage
CMRR
—
dB
CP
PSRR
—
72
dB
CP
V
T = 25 °C
–5
—
0
mV
µV/°C
bits
OFF
A
Input Offset Tempco
TC
3.5
6
—
OFF
Reference DAC Resolution
N
Bits
24
Preliminary Rev. 0.8
SiM3C1xx
Table 3.17. Port I/O
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Standard I/O (PB0, PB1, and PB2) and 5 V Tolerant I/O (PB3)
Output High Voltage
V
Low Drive, I = –2 mA
V
V
– 0.7
—
—
—
—
—
—
V
V
V
V
OH
OH
IO
IO
High Drive, I = –5 mA
– 0.7
OH
Output Low Voltage
V
Low Drive, I = 3 mA
—
0.6
0.6
OL
OL
High Drive,
—
I
= 12.5 mA
OL
Output Rise Time
Output Fall Time
Input High Voltage
t
C = TBD
C = TBD
TBD
TBD
—
—
TBD
TBD
—
ns
ns
V
R
t
F
V
1.8 <= V <= 2.0
0.7 x V
IO
—
IH
IO
2.0 <= V <= 3.6
V
– 0.6
IO
—
—
V
IO
Input Low Voltage
Pin Capacitance
V
—
—
0.6
—
V
IL
C
PB0, PB1 and PB2 Pins
PB3 Pins
—
—
4
pF
pF
µA
µA
µA
IO
7
—
Weak Pull-Up Current
(Input Voltage = 0 V)
I
V
V
= 1.8
= 3.6
–6
–30
–1
–3.5
–20
—
–2
PU
IO
IO
–10
1
Input Leakage
I
0 < V < V
IN IO
LK
(Pullups off or Analog)
Input Leakage Current of Port
I
V
< V < V +2.0 V
0
0
5
5
150
150
µA
µA
L
IO
IN
IO
Bank 3 I/O, V above V
(pins without EXREG
functions)
IN
IO
V
< V < V
IN REGIN
IO
(pins with EXREG
functions)
High Drive I/O (PB4)
Output High Voltage
V
Standard Mode, Low
V
– 0.7
– 0.7
—
—
—
—
50
300
1
—
—
V
V
OH
IOHD
IOHD
Drive, I = -3mA
OH
Standard Mode, High
V
Drive, I = -10mA
OH
Output Low Voltage
Output Rise Time
V
Standard Mode, Low
—
0.6
0.6
—
V
OL
Drive, I = 3mA
OH
Standard Mode, High
—
—
—
—
—
V
Drive, I = 12.5mA
OH
t
Slew Rate Mode 0,
ns
ns
µs
µs
R
V
= 5V
IOHD
Slew Rate Mode 1,
= 5V
—
V
IOHD
Slew Rate Mode 2,
= 5V
—
V
IOHD
Slew Rate Mode 3,
= 5V
3
—
V
IOHD
Preliminary Rev. 0.8
25
SiM3C1xx
Table 3.17. Port I/O (Continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output Fall Time
t
Slew Rate Mode 0,
—
50
—
ns
F
V
= 5V
IOHD
Slew Rate Mode 1,
= 5V
—
—
—
300
1
—
—
—
ns
µs
µs
V
IOHD
Slew Rate Mode 2,
= 5V
V
IOHD
Slew Rate Mode 3,
= 5V
3
V
IOHD
Input High Voltage
V
1.8 V<= V
<= 2.0 V 0.7 x V
IOHD
—
—
—
—
—
V
V
V
IH
IOHD
2.0 V<= V
<= 6 V
V
– 0.6
IOHD
IOHD
Input Low Voltage
V
—
0.6
IL
N-Channel Sink Current Limit
I
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Mode 8
Mode 9
Mode 10
Mode 11
Mode 12
Mode 13
Mode 14
Mode 15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.76
2.34
3.52
4.69
7.03
9.38
14.06
18.75
28.13
37.5
56.25
75
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
400
mA
SINKL
(2.7 V <= V
<= 6 V,
IOHD
V
= 0.8V)
OL
112.5
150
225
300
Total N-Channel Sink Current on
P4.0-P4.5 (DC)
I
—
mA
SINKLT
26
Preliminary Rev. 0.8
SiM3C1xx
Table 3.17. Port I/O (Continued)
Parameter
Symbol
Conditions
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Mode 8
Mode 9
Mode 10
Mode 11
Mode 12
Mode 13
Mode 14
Mode 15
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
0.88
1.17
1.76
2.34
3.52
4.69
7.03
9.38
14.06
18.75
28.13
37.5
56.25
75
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
400
Units
P-Channel Source Current Limit
(2.7 V <= VIOHD <= 6 V,
I
mA
SRCL
V
= VIOHD - 0.8V)
OH
112.5
150
Total P-Channel Source Current on
P4.0-P4.5 (DC)
I
—
mA
SRCLT
Pin Capacitance
C
—
30
—
pF
µA
IO
Weak Pull-Up Current in Low Volt-
age Mode
I
V
V
V
= 1.8 V
= 3.6 V
= 2.7 V
–6
–3.5
–2
PU
IOHD
IOHD
IOHD
–30
–15
–30
–1
–20
–10
–20
—
–10
–5
µA
µA
µA
µA
Weak Pull-Up Current in High Volt-
age Mode
I
PU
V
= 6 V
–10
1
IOHD
Input Leakage (Pullups off)
I
LK
Preliminary Rev. 0.8
27
SiM3C1xx
3.2. Thermal Conditions
Table 3.18. Thermal Conditions
Parameter
Symbol
Conditions
Min
—
Typ
35
40
25
30
30
Max
—
Units
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal Resistance*
LGA-92 Packages
TQFP-80 Packages
QFN-64 Packages
TQFP-64 Packages
QFN-40 Packages
JA
—
—
—
—
—
—
—
—
*Note: Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
3.3. Absolute Maximum Ratings
Stresses above those listed under Table 3.19 may cause permanent damage to the device. This is a stress rating
only and functional operation of the devices at those or any other conditions above those indicated in the operation
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect
device reliability.
Table 3.19. Absolute Maximum Ratings
Parameter
Ambient Temperature Under Bias
Storage Temperature
Symbol
Conditions
Min
–55
–65
Max
125
150
4.2
Units
°C
T
BIAS
T
°C
STG
Voltage on VDD
V
V
V
V
V
V
V
V
V
–0.3
V
DD
SS
SS
SS
SS
SS
SS
SS
SS
Voltage on VREGIN
V
EXTVREG0 Not Used
EXTVREG0 Used
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
6.0
3.6
4.2
6.5
5.8
V
V
V
V
V
V
V
V
REGIN
Voltage on VIO
V
IO
Voltage on VIOHD
V
IOHD
Voltage on I/O pins, non Port Bank 3 I/
O
V
RESET, V > 3.3 V
IN
IO
V +2.5
RESET, V < 3.3 V
IO
IO
Port Bank 0, 1, and 2 I/O
Port Bank 4 I/O
V +0.3
IO
V
–0.3
V
+0.3
IOHD
SSHD
*Note: VSS and VSSHD provide separate return current paths for device supplies, but are not isolated. They must always be
connected to the same potential on board.
28
Preliminary Rev. 0.8
SiM3C1xx
Table 3.19. Absolute Maximum Ratings (Continued)
Parameter
Symbol
Conditions
Min
Max
Units
Voltage on I/O pins, Port Bank 3 I/O
V
SiM3C1x7, PB3.0–
V
V
V
–0.3
5.8
V
IN
SS
SS
SS
PB3.7, V > 3.3 V
IO
SiM3C1x7, PB3.0–
–0.3
–0.3
V +2.5
V
V
IO
PB3.7, V < 3.3 V
IO
SiM3C1x7, PB3.8 -
PB3.11
Lowest of
V +2.5,
IO
V
+0.3,
REGIN
or 5.8
SiM3C1x6, PB3.0–
V
V
V
–0.3
–0.3
–0.3
5.8
V
V
V
SS
SS
SS
PB3.5, V > 3.3 V
IO
SiM3C1x6, PB3.0–
V +2.5
IO
PB3.5, V < 3.3 V
IO
Lowest of
SiM3C1x6, PB3.6–
PB3.9
V +2.5,
IO
V
+0.3,
REGIN
or 5.8
SiM3C1x4, PB3.0–
PB3.3
V
–0.3
Lowest of
V
SS
V +2.5,
IO
V
+0.3,
REGIN
or 5.8
Total Current Sunk into Supply Pins
I
V
, V
, V , V
IOHD
—
400
—
mA
mA
SUPP
DD
REGIN
IO
Total Current Sourced out of Ground
Pins
I
V
V
400
VSS
SS, SSHD
Current Sourced or Sunk by Any I/O
Pin
I
PB0, PB1, PB2, PB3,
and RESET
–100
100
mA
PIO
PB4
–300
–100
300
100
mA
mA
Current Injected on Any I/O Pin
Total Injected Current on I/O Pins
I
PB0, PB1, PB2, PB3,
and RESET
INJ
PB4
–300
–400
300
400
mA
mA
I
Sum of all I/O and
RESET
INJ
*Note: VSS and VSSHD provide separate return current paths for device supplies, but are not isolated. They must always be
connected to the same potential on board.
Preliminary Rev. 0.8
29
SiM3C1xx
Table 3.19. Absolute Maximum Ratings (Continued)
Parameter
Power Dissipation at T = 85 °C
Symbol
Conditions
Min
Max
Units
P
LGA-92 Package
—
570
mW
A
D
TQFP-80 Package
QFN-64 Package
TQFP-64 Package
QFN-40 Package
—
—
—
—
500
800
650
650
mW
mW
mW
mW
*Note: VSS and VSSHD provide separate return current paths for device supplies, but are not isolated. They must always be
connected to the same potential on board.
30
Preliminary Rev. 0.8
SiM3C1xx
4. Precision32™ SiM3C1xx System Overview
The SiM3C1xx Precision32™ devices are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted
features are listed below. Refer to Table 6.1 for specific product feature selection and part ordering numbers.
Core:
32-bit ARM Cortex-M3 CPU.
80 MHz maximum operating frequency.
Branch target cache and prefetch buffers to minimize wait states.
Memory: 32–256 kB Flash; in-system programmable, 8–32 kB SRAM (including 4 kB retention SRAM,
which preserves state in PM9 mode).
Power:
Low drop-out (LDO) regulator for CPU core voltage.
Power-on reset circuit and brownout detectors.
3.3 V output LDO for direct power from 5 V supplies.
External transistor regulator.
Power Management Unit (PMU).
I/O: Up to 65 total multifunction I/O pins:
Up to six programmable high-power capable (5–300 mA, 1.8–5 V).
Up to twelve 5 V tolerant general purpose pins.
Two flexible peripheral crossbars for peripheral routing.
Clock Sources:
Internal oscillator with PLL: 23–80 MHz with ± 1.5% accuracy in free-running mode.
Low-power internal oscillator: 20 MHz and 2.5 MHz modes.
Low-frequency internal oscillator: 16.4 kHz.
External RTC crystal oscillator: 32.768 kHz.
External oscillator: Crystal, RC, C, CMOS clock modes.
Programmable clock divider allows any oscillator source to be divided by binary factor from 1-128.
Data Peripherals:
16-Channel DMA Controller.
128/192/256-bit Hardware AES Encryption.
16/32-bit CRC.
Timers/Counters and PWM:
6-channel Enhanced Programmable Counter Array (EPCAn) supporting advanced PWM and capture/compare.
2 x 2-channel Standard Programmable Counter Array (PCAn) supporting PWM and capture/compare.
2 x 32-bit Timers - can be split into 4 x 16-bit Timers, support PWM and capture/compare.
Real Time Clock (RTCn).
Low Power Timer.
Watchdog Timer.
Communications Peripherals:
External Memory Interface.
2 x USARTs and 2 x UARTs with IrDA and ISO7816 SmartCard support.
3 x SPIs.
2 x I2C.
I2S (receive and transmit).
Analog:
2 x 12-Bit Analog-to-Digital Converters (SARADC).
2 x 10-Bit Digital-to-Analog Converter (IDAC).
16-Channel Capacitance-to-Digital Converter (CAPSENSE).
2 x Low-Current Comparators (CMP).
1 x Current-to-Voltage Converter (IVC) module with two channels.
On-Chip Debugging
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the SiM3C1xx devices
are truly standalone system-on-a-chip solutions. The Flash memory is reprogrammable in-circuit, providing non-
Preliminary Rev. 0.8
31
SiM3C1xx
volatile data storage and allowing field upgrades of the firmware. User firmware has complete control of all
peripherals and may individually shut down and gate the clocks of any or all peripherals for power savings.
The on-chip debugging interface (SWJ-DP) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and
modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog
and digital peripherals are fully functional while debugging.
Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port
I/O and RESET pins are powered from the IO supply voltage. The SiM3C1xx devices are available in 40-pin or 64-
pin QFN, 64-pin or 80-pin TQFP, or 92-pin LGA packages. All package options are lead-free and RoHS compliant.
See Table 6.1 for ordering information. A block diagram is included in Figure 4.1.
Analog
SARADC0
IDAC0
Watchdog
Timer
(WDTIMER0)
Debug /
Programming
Hardware
Core
SARADC1
IDAC1
ARM Cortex M3
Power On Reset /
PMU
Comparator 0 Comparator 1
IVC0
Memory
Voltage Supply
32/64/128/256 kB Flash
4/12/28 kB RAM
Monitor (VMON0)
Capacitive Sensing 0
I/O
Power
4 kB retention RAM
EMIF
Low Dropout Regulator (LDO0)
Voltage Regulator (VREG0)
DMA
Crossbars
External Regulator (EXTVREG0)
Power Management Unit (PMU)
16-Channel Controller
Peripheral Crossbar
Standard I/O pins
5 V tolerant pins
High Drive pins
Clocking
Digital
Real-Time Clock (RTC0OSC)
Low Frequency Oscillator (LFOSC0)
Low Power Oscillator (LPOSC0)
External Oscillator Control (EXTOSC0)
Phase-Locked Loop (PLL0OSC)
Peripheral Clock Control (CLKCTRL)
USART0 USART1
UART0
UART1
SPI0
I2C0
SPI1
SPI2
I2C1
Clock Control
I2S0
EPCA0
PCA0
AES0
CRC0
PCA1
Timer 0
Timer 1
Low Power Timer (LPTIMER0)
DMA access available for these peripherals
Figure 4.1. Precision32™ SiM3C1xx Family Block Diagram
32
Preliminary Rev. 0.8
SiM3C1xx
4.1. Power
4.1.1. LDO and Voltage Regulator (VREG0)
The SiM3C1xx devices include two internal regulators: the core LDO Regulator and the Voltage Regulator
(VREG0).
The LDO Regulator converts a 1.8–3.6 V supply to the core operating voltage of 1.8 V. This LDO consumes little
power and provides flexibility in choosing a power supply for the system.
The Voltage Regulator regulates from 5.5 to 2.7 V and can serve as an input to the LDO. This allows the device to
be powered from up to a 5.5 V supply without any external components other than bypass capacitors.
4.1.2. Voltage Supply Monitor (VMON0)
The SiM3C1xx devices include a voltage supply monitor which allows devices to function in known, safe operating
condition without the need for external hardware. The supply monitor includes additional circuitry that can monitor
the main supply voltage and the VREGIN input voltage divided by 4 (VREGIN / 4).
The supply monitor module includes the following features:
Main supply “VDD Low” (VDD below the early warning threshold) notification.
Holds the device in reset if the main VDD supply drops below the VDD Reset threshold.
VREGIN divided by 4 (VREGIN / 4) supply “VREGIN Low” notification.
4.1.3. External Regulator (EXTVREG0)
The External Regulator provides all the circuitry needed for a high-power regulator except the power transistor
(NPN or PNP) and current sensing resistor (if current limiting is enabled).
The External Regulator module has the following features:
Interfaces with either an NPN or PNP external transistor that serves as the pass device for the high current
regulator.
Automatic current limiting.
Automatic foldback limiting.
Sources up to 1 A for use by external circuitry.
Variable output voltage from 1.8–3.6 V in 100 mV steps.
4.1.4. Power Management Unit (PMU)
The Power Management Unit on the SiM3C1xx manages the power systems of the device. On power-up, the PMU
ensures the core voltages are a proper value before core instruction execution begins. It also recognizes and
manages the various wake sources for low-power modes of the device.
The PMU module includes the following features:
Up to 16 pin wake inputs can wake the device from Power Mode 9.
The Low Power Timer, RTC0 (alarms and oscillator fail), Comparator 0, and the RESET pin can also serve
as wake sources for Power Mode 9.
All PM9 wake sources (except for the RESET pin) can also reset the Low Power Timer or RTC0 modules.
Disables the level shifters to pins and peripherals to further reduce power usage in PM9. These level
shifters must be re-enabed by firmware after exiting PM9.
Provides a PMU_Asleep signal to a pin as an indicator that the device is in PM9.
Preliminary Rev. 0.8
33
SiM3C1xx
4.1.5. Device Power Modes
The SiM3C1xx devices feature four low power modes in addition to normal operating mode. Several peripherals
provide wake up sources for these low power modes, including the Low-Power Timer (LPT0), RTC0 (alarms and
oscillator failure notification), Comparator 0, and PMU Pin Wake. All power modes are detailed in Table 4.1.
Table 4.1. SiM3C1xx Power Modes
Mode
Description
Mode Entrance
Mode Exit
Core operating at full
speed
Normal
Code executing from
Flash
Core operating at full
speed
Power Mode 1
(PM1)
Execute code from RAM
WFI or WFE instruction
Jump to code in Flash
NVIC or WIC wakeup
Code executing from
RAM
Core halted
Power Mode 2
(PM2)
AHB and APB operate
at full speed for
peripherals
All clocks stopped
except LFOSC0 or
RTC0OSC
DMACTRL0
disabled
Fast wake mode
AHB and APB set to
enabled in PM3CN
Power Mode 3
Fast Wake
(PM3FW)
Low Power Oscillator
NVIC or WIC wakeup
AHB switched to
Low Power
Core clock set to
LFOSC0 or RTC0OSC
Oscillator
WFI or WFE
instruction
DMACTRL0
disabled
Power Mode 3
(PM3)
Clocks disabled in
All clocks stopped
NVIC or WIC wakeup
PM3CN
WFI or WFE
instruction
SLEEPDEEP set in
the ARM System
Control Register
Requires a reset defined by
the PMU as a wake up
source
Power Mode 9
(PM9)
Low power shutdown
WFI or WFE
instruction
In addition, all peripherals can have their clocks disconnected to reduce power consumption whenever a peripheral
is not being used using the clock control (CLKCTRL) registers.
34
Preliminary Rev. 0.8
SiM3C1xx
4.1.5.1. Normal Mode
Normal mode encompasses the typical full-speed operation. The power consumption of the device in this mode will
vary depending on AHB/APB clock speeds and the settings of CLKCTRL and the peripherals.
4.1.5.2. Power Mode 1
Power Mode 1 occurs when the core executes code from RAM instead of Flash. The power consumption of the
device is slightly less than normal mode when in PM1.
4.1.5.3. Power Mode 2
In Power Mode 2, the core halts and the peripherals run at full speed. To place the device in this mode, the clock
settings in CLKCTRL should remain the same as Normal or Power Mode 1 and the core should execute a wait-for-
interrupt (WFI) or wait-for-event (WFE) instruction. If the WFI instruction is called from an interrupt service routine,
the interrupt that wakes the device from PM2 must be of a sufficient priority to be recognized by the core.
4.1.5.4. Power Mode 3 Fast Wake
Power Mode 3 Fast Wake occurs when all the clocks are stopped except for the LFOSC0 or RTC0OSC. The core
and the peripherals are halted in this mode.
The following sequence places the device in Power Mode 3 Fast Wake:
1. All DMA channels must be disabled by using the global enable/disable DMAEN in the DMA Controller
(DMACTRL0).
2. Firmware should enable PM3 Fast Wake in the PM3CN register and set the core clock to run off of the
LFOSC0 or RTC0OSC to achieve the lowest power.
3. CLKCTRL CONTROL register settings must be modified to set the AHB and APB clocks to the Low Power
Oscillator.
4. Firmware should then execute a WFI or WFE instruction.
If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3FW
must be of a sufficient priority to be recognized by the core.
By keeping the core clock running at a slow frequency in PM3 and changing the AHB and APB clocks to the Low
Power Oscillator, the device can wake up faster than in standard Power Mode 3 at the expense of higher power
consumption.
4.1.5.5. Power Mode 3
Power Mode 3 occurs when all the clocks are stopped, and the core and the peripherals are halted.
The following sequence places the device in Power Mode 3:
1. All DMA channels must be disabled by using the global enable/disable DMAEN in the DMA Controller
(DMACTRL0).
2. Firmware should disable PM3 Fast Wake in the PM3CN register.
3. Firmware should then execute a WFI or WFE instruction.
If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3 must
be of a sufficient priority to be recognized by the core.
4.1.5.6. Power Mode 9
In Power Mode 9, the core and all peripherals are halted, all clocks are stopped, and the pins and peripherals are
set to a lower power mode. In addition, standard RAM contents are not preserved, though retention RAM contents
are still available after exiting the power mode. This mode provides the lowest power consumption for the device,
but requires an appropriate reset to exit. The available reset sources to wake from PM9 are controlled by the
Power Management Unit (PMU).
To enter this mode, firmware must write the SLEEPDEEP bit in the ARM System Control Register. Firmware must
then execute a WFI or WFE instruction. The core will remain in PM9 until an enabled reset source occurs.
Preliminary Rev. 0.8
35
SiM3C1xx
4.2. I/O
4.2.1. General Features
The SiM3C1xx ports have the following features:
Push-pull or open-drain output modes and analog or digital modes.
Option for high or low output drive strength.
Port Match allows the device to recognize a change on a port pin value.
Internal pull-up resistors are enabled or disabled on a port-by-port basis.
Two external interrupts with up to 16 inputs provide monitoring capability for external signals.
Internal Pulse Generator Timer (PB2 only) to generate simple square waves.
A subset of pins can also serve as inputs to the Port Mapped Level Shifters available on the High Drive
Pins.
4.2.2. High Drive Pins (PB4)
The High Drive pins have the following additional features:
Programmable safe state: high, low, or high impedance.
Programmable drive strength and slew rates.
Programmable current limiting.
Powered from a separate source (VIOHD, which can be up to 6 V) from the rest of the device.
Supports various functions, including GPIO, UART1 pins, EPCA0 pins, or Port Mapped Level Shifting.
4.2.3. 5 V Tolerant Pins (PB3)
The 5 V tolerant pins can be connected to external circuitry operating at voltages above the device supply without
needing extra components to shift the voltage level.
4.2.4. Crossbars
The SiM3C1xx devices have two Crossbars with the following features:
Flexible peripheral assignment to port pins.
Pins can be individually skipped to move peripherals as needed for design or layout considerations.
The Crossbars have a fixed priority for each I/O function and assign these functions to the port pins. When a digital
resource is selected, the least-significant unassigned port pin is assigned to that resource. If a port pin is assigned,
the Crossbars skip that pin when assigning the next selected resource. Additionally, the Crossbars will skip port
pins whose associated bits in the PBSKIPEN registers are set. This provides some flexibility when designing a
system: pins involved with sensitive analog measurements can be moved away from digital I/O and peripherals
can be moved around the chip as needed to ease layout constraints.
36
Preliminary Rev. 0.8
SiM3C1xx
4.3. Clocking
The SiM3C1xx devices have two system clocks: AHB and APB. The AHB clock services memory peripherals and
is derived from one of seven sources: the RTC0 Oscillator, the Low Frequency Oscillator, the Low Power Oscillator,
the divided Low Power Oscillator, the External Oscillator, and the PLL0 Oscillator. In addition, a divider for the AHB
clock provides flexible clock options for the device. The APB clock services data peripherals and is synchronized
with the AHB clock. The APB clock can be equal to the AHB clock (if AHB is less than or equal to 50 MHz) or set to
the AHB clock divided by two.
Clock Control allows the AHB and APB clocks to be turned off to unused peripherals to save system power. Any
registers in a peripheral with disabled clocks will be unable to be accessed until the clocks are enabled. Most
peripherals have clocks off by default after a power-on reset.
Clock Control
RTC0
Oscillator
RAM
DMA
LFOSC0
AHB clock
Flash
LPOSC0
AHB Clock
Divider
EMIF
PLL0 Registers
External
Oscillator
PBCFG and
PB0/1/2/3/4
USART0
USART1
UART0
APB clock
PLL0
Oscillator
APB Clock
Divider
Preliminary Rev. 0.8
37
SiM3C1xx
4.3.1. PLL (PLL0)
The PLL module consists of a dedicated Digitally-Controlled Oscillator (DCO) that can be used in Free-Running
mode without a reference frequency, Frequency-Locked to a reference frequency, or Phase-Locked to a reference
frequency. The reference frequency for Frequency-Lock and Phase-Lock modes can use one of multiple sources
(including the external oscillator) to provide maximum flexibility for different application needs. Because the PLL
module generates its own clock, the DCO can be locked to a particular reference frequency and then moved to
Free-Running mode to reduce system power and noise.
The PLL module includes the following features:
Five output ranges with output frequencies ranging from 23 to 80 MHz.
Multiple reference frequency inputs.
Three output modes: free-running DCO, frequency-locked, and phase-locked.
Ability to sense the rising edge or falling edge of the reference source.
DCO frequency LSB dithering to provide finer average output frequencies.
Spectrum spreading to reduce generated system noise.
Low jitter and fast lock times.
Ability to suspend all output frequency updates (including dithering and spectrum spreading) using the
STALL bit during jitter-sensitive operations.
4.3.2. Low Power Oscillator (LPOSC0)
The Low Power Oscillator is the default AHB oscillator on SiM3C1xx devices and enables or disables
automatically, as needed.
The Low Power Oscillator has the following features:
20 MHz and divided 2.5 MHz frequencies available for the AHB clock.
Automatically starts and stops as needed.
4.3.3. Low Frequency Oscillator (LFOSC0)
The low frequency oscillator (LFOSC0) provides a low power internal clock source running at approximately
16.4 kHz for the RTC0 timer and other peripherals on the device. No external components are required to use the
low frequency oscillator
4.3.4. External Oscillators (EXTOSC0)
The EXTOSC0 external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC
network. A CMOS clock may also provide a clock input. The external oscillator output may be selected as the AHB
clock or used to clock other modules independent of the AHB clock selection.
The External Oscillator control has the following features:
Support for external crystal, RC, C, or CMOS oscillators.
Support external CMOS frequencies from 10 kHz to 50 MHz and external crystal frequencies from 10 kHz
to 30 MHz.
Various drive strengths for flexible crystal oscillator support.
Internal frequency divide-by-two option available.
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Preliminary Rev. 0.8
SiM3C1xx
4.4. Data Peripherals
4.4.1. 16-Channel DMA Controller
The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without
spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the
system, as the device can spend more time in low-power modes.
The DMA controller has the following features:
Utilizes ARM PrimeCell uDMA architecture.
Implements 16 channels.
DMA crossbar supports SARADC0, SARADC1, IDAC0, IDAC1, I2C0, I2S0, SPI0, SPI1, USART0,
USART1, AES0, EPCA0, external pin triggers, and timers.
Supports primary, alternate, and scatter-gather data structures to implement various types of transfers.
Access allowed to all AHB and APB memory space.
4.4.2. 128/192/256-bit Hardware AES Encryption (AES0)
The basic AES block cipher is implemented in hardware. The integrated hardware support for Cipher Block
Chaining (CBC) and Counter (CTR) algorithms results in identical performance, memory bandwidth, and memory
footprint between the most basic Electronic Codebook (ECB) algorithm and these more complex algorithms. This
hardware accelerator translates to more core bandwidth available for other functions or a power savings for low-
power applications.
The AES module includes the following features:
Operates on 4-word (16-byte) blocks.
Supports key sizes of 128, 192, and 256 bits for both encryption and decryption.
Generates the round key for decryption operations.
All cipher operations can be performed without any firmware intervention for a set of 4-word blocks (up to
32 kB).
Support for various chained and stream-ciphering configurations with XOR paths on both the input and
output.
Internal 4-word FIFOs to facilitate DMA operations.
Integrated key storage.
Hardware acceleration for Cipher-Block Chaining (CBC) and Counter (CTR) algorithms utilizing integrated
counterblock generation and previous-block caching.
4.4.3. 16/32-bit CRC (CRC0)
The CRC module is designed to provide hardware calculations for Flash memory verification and communications
protocols.
The CRC module supports four common polynomials. The supported 32-bit polynomial is 0x04C11DB7 (IEEE
802.3). The three supported 16-bit polynomials are 0x1021 (CCITT-16), 0x3D65 (IEC16-MBus), and 0x8005
(ZigBee, 802.15.4, and USB).
The CRC module includes the following features:
Support for four common polynomials (one 32-bit and three 16-bit options).
Byte-level bit reversal for the CRC input.
Byte-order reorientation of words for the CRC input.
Word or half-word bit reversal of the CRC result.
Ability to configure and seed an operation in a single register write.
Support for single-cycle parallel (unrolled) CRC computation for 32- or 8-bit blocks.
Capability to CRC 32 bits of data per peripheral bus (APB) clock.
Support for DMA writes using firmware request mode.
Preliminary Rev. 0.8
39
SiM3C1xx
4.5. Counters/Timers and PWM
4.5.1. Programmable Counter Array (EPCA0, PCA0, PCA1)
The SiM3C1xx devices include two types of PCA module: Enhanced and Standard.
The Enhanced Programmable Counter Array (EPCA0) and Standard Programmable Counter Array (PCA0, PCA1)
modules are timer/counter systems allowing for complex timing or waveform generation. Multiple modules run from
the same main counter, allowing for synchronous output waveforms.
The Enhanced PCA module is multi-purpose, but is optimized for motor control applications. The EPCA module
includes the following features:
Three sets of channel pairs (six channels total) capable of generating complementary waveforms.
Center- and edge-aligned waveform generation.
Programmable dead times that ensure channel pairs are never both active at the same time.
Programmable clock divisor and multiple options for clock source selection.
Waveform update scheduling.
Option to function while the core is inactive.
Multiple synchronization triggers and outputs.
Pulse-Width Modulation (PWM) waveform generation.
High-speed square wave generation.
Input capture mode.
DMA capability for both input capture and waveform generation.
PWM generation halt input.
The Standard PCA module (PCA) includes the following features:
Two independent channels.
Center- and edge-aligned waveform generation.
Programmable clock divisor and multiple options for clock source selection.
Pulse-Width Modulation waveform generation.
4.5.2. 32-bit Timer (TIMER0, TIMER1)
Each timer module is independent, and includes the following features:
Operation as a single 32-bit or two independent 16-bit timers.
Clocking options include the APB clock, the APB clock scaled using an 8-bit prescaler, the external
oscillator, or falling edges on an external input pin (synchronized to the APB clock).
Auto-reload functionality in both 32-bit and 16-bit modes.
Up/Down count capability, controlled by an external input pin.
Rising and falling edge capture modes.
Low or high pulse capture modes.
Duty cycle capture mode.
Square wave output mode, which is capable of toggling an external pin at a given rate with 50% duty cycle.
32- or 16-bit pulse-width modulation mode.
40
Preliminary Rev. 0.8
SiM3C1xx
4.5.3. Real-Time Clock (RTC0)
The RTC0 module includes a 32-bit timer that allows up to 36 hours of independent time-keeping when used with a
32.768 kHz watch crystal. The RTC0 provides three alarm events in addition to a missing clock event, which can
also function as interrupt, reset, or wakeup sources on SiM3C1xx devices.
The RTC0 module includes internal loading capacitors that are programmable to 16 discrete levels, allowing
compatibility with a wide range of crystals.
The RTC0 output can be buffered and routed to a port bank pin to provide an accurate, low frequency clock to
other devices while the core is in its lowest power down mode. The module also includes a low power internal low
frequency oscillator that reduces low power mode current and is available for other modules to use as a clock
source.
The RTC module includes the following features:
32-bit timer (supports up to 36 hours) with three separate alarms.
Option for one alarm to automatically reset the RTC timer.
Missing clock detector.
Can be used with the internal low frequency oscillator (LFOSC0), an external 32.768 kHz crystal (no
additional resistors or capacitors necessary), or with an external CMOS clock.
Programmable internal loading capacitors support a wide range of external 32.768 kHz crystals.
Operates directly from VDD and remains operational even when the device goes into its lowest power
down mode.
The output can be buffered and routed to an I/O pin to provide an accurate, low frequency clock to other
devices while the core is in its lowest power down mode.
4.5.4. Low Power Timer (LPTIMER0)
The Low Power Timer (LPTIMER0) module runs from the clock selected by the RTC0 module, allowing the
LPTIMER0 to operate even if the AHB and APB clocks are disabled. The LPTIMER0 counter can increment using
one of two clock sources: the clock selected by the RTC0 module, or rising or falling edges of an external signal.
The Low Power Timer includes the following features:
Runs on a low-frequency clock (RTC0OSC or LFOSC0 selected in RTC0) or an external source (rising or
falling edge).
Overflow and threshold-match detection, which can generate an interrupt, reset the timer, or wake some
devices from low power modes.
Timer reset on threshold-match allows square-wave generation at a variable output frequency.
4.5.5. Watchdog Timer (WDTIMER0)
The WDTIMER0 module includes a 16-bit timer, a programmable early warning interrupt, and a programmable
reset period. The timer registers are protected from inadvertent access by an independent lock and key interface.
The watchdog timer runs from the low frequency oscillator (LFOSC0).
The Watchdog Timer has the following features:
Programmable timeout interval.
Optional interrupt to warn when the Watchdog Timer is nearing the reset trip value.
Lock-out feature to prevent any modification until a system reset.
Preliminary Rev. 0.8
41
SiM3C1xx
4.6. Communications Peripherals
4.6.1. External Memory Interface (EMIF0)
The External Memory Interface (EMIF0) allows external parallel asynchronous devices, like SRAMs and LCD
controllers, to appear as part of the system memory map. The EMIF0 module includes the following features:
Provides a memory mapped view of multiple external devices.
Support for byte, half-word and word accesses regardless of external device data-width.
Error indicator for certain invalid transfers.
Minimum external timing allows for 3 clocks per write or 4 clocks per read.
Output bus can be shared between non-muxed and muxed devices.
Available extended address output allows for up to 24-bit address with 8-bit parallel devices.
Support for 8-bit and 16-bit (muxed-mode only) devices with up to two chip-select signals.
Support for internally muxed devices with dynamic address shifting.
Fully programmable control signal waveforms.
4.6.2. USART (USART0, USART1)
The USART uses two signals (TX and RX) and a predetermined fixed baud rate to communicate with a single
device. In addition to these signals, the USART0 module can optionally use a clock (UCLK) or hardware
handshaking (RTS and CTS).
The USART module provides the following features:
Independent transmitter and receiver configurations with separate 16-bit baud rate generators.
Synchronous or asynchronous transmissions and receptions.
Clock master or slave operation with programmable polarity and edge controls.
Up to 5 Mbaud (synchronous or asynchronous, TX or RX, and master or slave) or 1 Mbaud Smartcard (TX
or RX).
Individual enables for generated clocks during start, stop, and idle states.
Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads
and writes.
Data bit lengths from 5 to 9 bits.
Programmable inter-packet transmit delays.
Auto-baud detection with support for the LIN SYNC byte.
Automatic parity generation (with enable).
Automatic start and stop generation (with separate enables).
Transmit and receive hardware flow-control.
Independent inversion correction for TX, RX, RTS, and CTS signals.
IrDA modulation and demodulation with programmable pulse widths.
Smartcard ACK/NACK support.
Parity error, frame error, overrun, and underrun detection.
Multi-master and half-duplex support.
Multiple loop-back modes supported.
Multi-processor communications support.
4.6.3. UART (UART0, UART1)
The USART uses two signals (TX and RX) and a predetermined fixed baud rate to communicate with a single
device.
The UART module provides the following features:
Independent transmitter and receiver configurations with separate 16-bit baud-rate generators.
Asynchronous transmissions and receptions.
Up to 5 Mbaud (TX or RX) or 1 Mbaud Smartcard (TX or RX).
42
Preliminary Rev. 0.8
SiM3C1xx
Internal transmit and receive FIFOs with flush capability and support for byte, half-word, and word reads
and writes.
Data bit lengths from 5 to 9 bits.
Programmable inter-packet transmit delays.
Auto-baud detection with support for the LIN SYNC byte.
Automatic parity generation (with enable).
Automatic start and stop generation.
Transmit and receive hardware flow-control.
Independent inversion correction for TX, RX, RTS, and CTS signals.
IrDA modulation and demodulation with programmable pulse widths.
Smartcard ACK/NACK support.
Parity error, frame error, overrun, and underrun detection.
Multi-master and half-duplex support.
Multiple loop-back modes supported.
4.6.4. SPI (SPI0, SPI1)
SPI is a 3- or 4-wire communication interface that includes a clock, input data, output data, and an optional select
signal.
The SPI module includes the following features:
Supports 3- or 4-wire master or slave modes.
Supports up to 10 MHz clock in master mode and 5 MHz clock in slave mode.
Support for all clock phase and slave select (NSS) polarity modes.
16-bit programmable clock rate.
Programmable MSB-first or LSB-first shifting.
8-byte FIFO buffers for both transmit and receive data paths to support high speed transfers.
Programmable FIFO threshold level to request data service for DMA transfers.
Support for multiple masters on the same data lines.
4.6.5. I2C (I2C0, I2C1)
The I2C interface is a two-wire, bi-directional serial bus. The two clock and data signals operate in open-drain
mode with external pull-ups to support automatic bus arbitration.
Reads and writes to the interface are byte oriented with the I2C interface autonomously controlling the serial
transfer of the data. Data can be transferred at up to 1/8th of the APB clock as a master or slave, which can be
faster than allowed by the I2C specification, depending on the clock source used. A method of extending the clock-
low duration is available to accommodate devices with different speed capabilities on the same bus.
The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and start/
stop control and generation.
The I2C module includes the following features:
Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
Can operate down to APB clock divided by 32768 or up to APB clock divided by 8.
Support for master, slave, and multi-master modes.
Hardware synchronization and arbitration for multi-master mode.
Clock low extending (clock stretching) to interface with faster masters.
Hardware support for 7-bit slave and general call address recognition.
Firmware support for 10-bit slave address decoding.
Ability to disable all slave states.
Programmable clock high and low period.
Programmable data setup/hold times.
Preliminary Rev. 0.8
43
SiM3C1xx
Spike suppression up to 2 times the APB period.
2
4.6.6. I S (I2S0)
2
2
The I S module receives digital data from an external source over a data line in the standard I S, left-justified, right-
justified, or time domain multiplexing format, de-serializes the data, and generates requests to transfer the data
using the DMA. The module also reads stereo audio samples from the DMA, serializes the data, and sends it out of
2
the chip on a data line in the same standard serial format for digital audio. The I S receive interface consists of 3
signals: SCK (bit clock), WS (word select or frame sync), and SD (data input). The block’s transmit interface
consists of 3 signals: SCK (bit clock), WS (word select or frame sync) and SD (data output).
2
The I S module includes the following features:
Master or slave capability.
Flexible 10-bit clock divider with 8-bit fractional clock divider provides support for various common
sampling frequencies (16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz) for up to two 32-bit
channels.
Support for DMA data transfers.
Support for various data formats.
44
Preliminary Rev. 0.8
SiM3C1xx
4.7. Analog
4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1)
The SARADC0 and SARADC1 modules on SiM3C1xx devices are Successive Approximation Register (SAR)
Analog to Digital Converters (ADCs). The key features of the SARADC module are:
Single-ended 12-bit and 10-bit modes.
Supports an output update rate of 250 k samples per second in 12-bit mode or 1 M samples per second in
10-bit mode.
Operation in low power modes at lower conversion speeds.
Selectable asynchronous hardware conversion trigger with hardware channel select.
Output data window comparator allows automatic range checking.
Support for Burst Mode, which produces one set of accumulated data per conversion-start trigger with
programmable power-on settling and tracking time.
Conversion complete, multiple conversion complete, and FIFO overflow and underflow flags and interrupts
supported.
Flexible output data formatting.
Sequencer allows up to 8 sources to be automatically scanned using one of four channel characteristic
profiles without software intervention.
Eight-word conversion data FIFO for DMA operations.
Multiple SARADC modules can work together synchronously or by interleaving samples.
Includes two internal references (1.65 V fast-settling, 1.2/2.4 V precision), support for an external
reference, and support for an external signal ground.
4.7.2. Sample Sync Generator (SSG0)
The SSG module includes a phase counter and a pulse generator. The phase counter is a 4-bit free-running
counter clocked from the SARADC module clock. Counting-up from zero, the phase counter marks sixteen equally-
spaced events for any number of SARADC modules. The ADCs can use this phase counter to start a conversion.
The programmable pulse generator creates a 50% duty cycle pulse with a period of 16 phase counter ticks. Up to
four programmable outputs available to external devices can be driven by the pulse generator with programmable
polarity and a defined output setting when the pulse generator is stopped.
The Sample Sync Generator module has the following features:
Connects multiple modules together to perform synchronized actions.
Outputs a clock synchronized to the internal sampling clock used by any number of SARADC modules to
pins for use by external devices.
Includes a phase counter, pulse generator, and up to four programmable outputs.
4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1)
The IDAC takes a digital value as an input and outputs a proportional constant current on a pin. The IDAC module
includes the following features:
10-bit current DAC with support for four timer, up to seven external I/O, on demand, and SSG0 output
update triggers.
Ability to update on rising, falling, or both edges for any of the external I/O trigger sources (DACnTx).
Supports an output update rate greater than 600 k samples per second.
Support for three full-scale output modes: 0.5 mA, 1.0 mA and 2.0 mA.
Four-word FIFO to aid with high-speed waveform generation or DMA interactions.
Individual FIFO overrun, underrun, and went-empty interrupt status sources.
Support for multiple data packing formats, including: single 10-bit sample per word, dual 10-bit samples per
word, or four 8-bit samples per word.
Support for left- and right-justified data.
Preliminary Rev. 0.8
45
SiM3C1xx
4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0)
The Capacitance Sensing module measures capacitance on external pins and converts it to a digital value. The
CAPSENSE module has the following features:
Multiple start-of-conversion sources (CSnTx).
Option to convert to 12, 13, 14, or 16 bits.
Automatic threshold comparison with programmable polarity (“less than or equal” or “greater than”).
Four operation modes: single conversion, single scan, continuous single conversion, and continuous scan.
Auto-accumulate mode that will take and average multiple samples together from a single start of
conversion signal.
Single bit retry options available to reduce the effect of noise during a conversion.
Supports channel bonding to monitor multiple channels connected together with a single conversion.
Scanning option allows the module to convert a single or series of channels and compare against the
threshold while the AHB clock is stopped and the core is in a low power mode.
4.7.5. Low Current Comparators (CMP0, CMP1)
The Comparators take two analog input voltages and output the relationship between these voltages (less than or
greater than) as a digital signal. The Low Power Comparator module includes the following features:
Multiple sources for the positive and negative poles, including VDD, VREF, and 8 I/O pins.
Two outputs are available: a digital synchronous latched output and a digital asynchronous raw output.
Programmable hysteresis and response time.
Falling or rising edge interrupt options on the comparator output.
4.7.6. Current-to-Voltage Converter (IVC0)
The IVC module provides inputs to the SARADCn modules so the input current can be measured. The IVC module
has the following features:
Two independent channels.
Programmable input ranges (1–6 mA full-scale).
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Preliminary Rev. 0.8
SiM3C1xx
4.8. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset
state, the following occur:
The core halts program execution.
Module registers are initialized to their defined reset values unless the bits reset only with a power-on
reset.
External port pins are forced to a known state.
Interrupts and timers are disabled.
Clocks to all AHB peripherals are enabled.
Clocks to all APB peripherals other than Watchdog Timer, EMIF0, and DMAXBAR are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a
power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as
long as power is not lost.
The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For
VDD Supply Monitor and power-on resets, the RESET pin is driven low until the device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. The Watchdog Timer is enabled with the Low Frequency Oscillator (LFO0) as its clock source. Program
execution begins at location 0x00000000.
Reset Sources
RESET
VDD Supply
Monitor
Missing Clock
Detector
Watchdog Timer
Software Reset
system reset
Comparator 0
Comparator 1
RTC0 Alarm
PMU / Wakeup
Core Reset
Preliminary Rev. 0.8
47
SiM3C1xx
4.9. Security
The peripherals on the SiM3C1xx devices have a register lock and key mechanism that prevents any undesired
accesses of the peripherals from firmware. Each bit in the PERIPHLOCKx registers controls a set of peripherals. A
key sequence must be written in order to the KEY register to modify any of the bits in PERIPHLOCKx. Any
subsequent write to KEY will then inhibit any accesses of PERIPHLOCKx until it is unlocked again through KEY.
Reading the KEY register indicates the current status of the PERIPHLOCKx lock state.
If a peripheral’s registers are locked, all writes will be ignored. The registers can always be read, regardless of the
peripheral’s lock state.
Peripheral Lock and Key
USART0/1,
UART0/1
SPI0/1/2
I2C0/1
EPCA0, PCA0/1
TIMER0/1
PERIPHLOCK0
PERIPHLOCK1
KEY
SARADC0/1
SSG0
4.10. On-Chip Debugging
The SiM3C1xx devices include JTAG and Serial Wire programming and debugging interfaces and ETM for
instruction trace. The JTAG interface is supported on SiM3C1x7 and SiM3C1x6 devices, and the ETM interface is
supported on SiM3C1x7 devices. The JTAG and ETM interfaces can be optionally enabled to provide more
visibility while debugging at the cost of using several Port I/O pins. Additionally, if the core is configured for Serial
Wire (SW) mode and not JTAG, then the Serial Wire Viewer (SWV) is available to provide a single pin to send out
TPIU messages on SiM3C1x7 and SiM3C1x6 devices.
Most peripherals have the option to halt or continue functioning when the core halts in debug mode.
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Preliminary Rev. 0.8
SiM3C1xx
5. Pin Definitions and Packaging Information
5.1. SiM3C1x7 Pin Definitions
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PB4.5
PB0.12
2
PB4.4
PB0.13
3
PB4.3
PB0.14
4
VSSHD
PB0.15
5
VIOHD
PB1.0
6
PB4.2
PB1.1
7
PB4.1
PB1.2/TRST
PB1.3/TDO/SWV
PB1.4/TDI
PB1.5/ETM0
PB1.6/ETM1
VIO
8
PB4.0
9
PB3.11
10
PB3.10
80-Pin TQFP
11
PB3.9
12
PB3.8
13
PB3.7
PB1.7/ETM2
PB1.8/ETM3
PB1.9/TRACECLK
SWCLK/TCK
SWDIO/TMS
PB1.10
14
PB3.6
15
PB3.5
16
PB3.4
17
PB3.3
18
PB3.2
19
PB3.1
PB1.11
20
PB3.0
PB1.12
Figure 5.1. SiM3C1x7-GQ Pinout
Preliminary Rev. 0.8
49
SiM3C1xx
D1
A48
D5
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
D8
D4
PB4.5
PB4.4
PB4.3
VIOHD
PB4.2
PB4.1
PB4.0
PB3.8
PB3.6
PB3.4
PB3.2
PB3.1
PB3.0
A1
A2
B36
B35
B34
B33
B32
B31
B30
B29
B28
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
D3
PB0.12
PB0.13
PB0.15
PB1.0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B27
B26
B25
B24
B23
B22
B21
B20
B19
PB0.14
A3
VSSHD
PB3.11
PB3.10
PB3.9
PB3.7
PB3.5
PB3.3
A4
PB1.1
PB1.3*
PB1.5*
PB1.7*
PB1.8*
A5
PB1.2*
PB1.4*
A6
92 pin LGA
(Top View)
A7
PB1.6*
VIO
A8
A9
PB1.9*
SWDIO*
PB1.10
PB1.11
PB1.12
VSS
SWCLK*
A10
A11
A12
D2
D6
B10
B11
B12
B13
B14
B15
B16
B17
B18
D7
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
*Noted pins are listed in the pinout table and 80-pin TQFP package figure with additional names.
These alternate functions are also present on the 92-pin LGA package and are identical to those on the
80-pin TQFP package.
Figure 5.2. SiM3C1x7-GM Pinout
50
Preliminary Rev. 0.8
SiM3C1xx
Table 5.1. Pin Definitions and alternate functions for SiM3C1x7
Pin Name
Type
VSS
Ground
33 B15
75 B34
VDD
VIO
Power (Core)
Power (I/O)
74 A44
32 A19
49 A29
73 A43
VREGIN
VSSHD
VIOHD
RESET
Power (Regulator) 76 A45
Ground (High Drive)
Power (High Drive)
Active-low Reset
4
5
B2
A3
80 A48
SWCLK / TCK Serial Wire / JTAG 45 B20
SWDIO / TMS Serial Wire / JTAG 44 A27
PB0.0
PB0.1
Standard I/O
Standard I/O
72 B33 XBR0
71 B32 XBR0
ADC0.0
ADC0.1
CS0.0
PB0.2
PB0.3
PB0.4
PB0.5
Standard I/O
Standard I/O
Standard I/O
Standard I/O
70 A42 XBR0
69 B31 XBR0
68 A41 XBR0
67 B30 XBR0
ADC0.2
CS0.1
ADC0.3
CS0.2
ADC0.4
CS0.3
ADC0.5
CS0.4
PB0.6
PB0.7
Standard I/O
Standard I/O
66 A40 XBR0
65 B29 XBR0
CS0.5
ADC0.6
CS0.6
IVC0.0
Preliminary Rev. 0.8
51
SiM3C1xx
Table 5.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued)
Pin Name
Type
PB0.8
Standard I/O
64 A39 XBR0
63 A38 XBR0
ADC0.7
CS0.7
IVC0.1
PB0.9
Standard I/O
ADC0.8
RTC1
PB0.10
PB0.11
Standard I/O
Standard I/O
62 A37 XBR0
61 D4 XBR0
RTC2
ADC0.9
VREFGND
PB0.12
Standard I/O
60 A36 XBR0
ADC0.10
VREF
PB0.13
PB0.14
PB0.15
PB1.0
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
59 A35 XBR0
58 B27 XBR0
57 A34 XBR0
56 A33 XBR0
55 B25 XBR0
IDAC0
IDAC1
XTAL1
XTAL2
ADC0.11
PB1.1
PB1.2/TRST Standard I/O /JTAG 54 A32 XBR0
PB1.3/TDO/ Standard I/O /JTAG/ 53 B24 XBR0
ADC0.12
ADC1.12
SWV
Serial Wire Viewer
PB1.4/TDI
Standard I/O /JTAG 52 A31 XBR0
ADC0.13
ADC1.13
PB1.5/ETM0 Standard I/O /ETM 51 B23 XBR0
PB1.6/ETM1 Standard I/O /ETM 50 A30 XBR0
PB1.7/ETM2 Standard I/O /ETM 48 B22 XBR0
PB1.8/ETM3 Standard I/O /ETM 47 B21 XBR0
ADC0.14
ADC1.14
ADC0.15
ADC1.15
ADC1.11
CS0.8
ADC1.10
CS0.9
52
Preliminary Rev. 0.8
SiM3C1xx
Table 5.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued)
Pin Name
Type
PB1.9/
TRACECLK
Standard I/O /ETM 46 A28 XBR0
ADC1.9
ADC1.8
ADC1.7
ADC1.6
PB1.10
PB1.11
PB1.12
PB1.13
PB1.14
PB1.15
PB2.0
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
43 A26 XBR0
42 A25 XBR0
41 D3 XBR0
40 A24 XBR0
39 A23 XBR0
38 A22 XBR0
37 B17 XBR1
A23m/
A15
DMA0T1
DMA0T0
A22m/
A14
A21m/
A13
A20m/
A12
ADC0T15
WAKE.0
ADC1.5
CS0.10
A19m/
A11
ADC1T15
WAKE.1
ADC1.4
CS0.11
A18m/
A10
WAKE.2
ADC1.3
CS0.12
A17m/ LSI0 Yes
A9
INT0.0
INT1.0
ADC1.2
CS0.13
WAKE.3
PB2.1
PB2.2
PB2.3
PB2.4
PB2.5
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
36 A21 XBR1
35 B16 XBR1
34 A20 XBR1
31 B14 XBR1
30 A18 XBR1
A16m/ LSI1 Yes
A8
INT0.1
INT1.1
WAKE.4
ADC1.1
CS0.14
AD15m/ LSI2 Yes
A7
INT0.2
INT1.2
WAKE.5
ADC1.0
CS0.15
PMU_Asleep
AD14m/ LSI3 Yes
A6
INT0.3
INT1.3
WAKE.6
AD13m/ LSI4 Yes
A5
INT0.4
INT1.4
WAKE.7
AD12m / LSI5 Yes
A4
INT0.5
INT1.5
Preliminary Rev. 0.8
53
SiM3C1xx
Table 5.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued)
Pin Name
Type
PB2.6
Standard I/O
29 B13 XBR1
28 A17 XBR1
27 B12 XBR1
26 A16 XBR1
25 B11 XBR1
24 A15 XBR1
23 A14 XBR1
AD11m/
A3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
INT0.6
INT1.6
PB2.7
PB2.8
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
AD10m/
A2
INT0.7
INT1.7
AD9m/
A1
PB2.9
AD8m/
A0
PB2.10
PB2.11
PB2.12
AD7m/
D7
AD6m/
D6
CMP0P.0
CMP1P.0
AD5m/
D5
CMP0N.0
CMP1N.0
RTC0OSC_OUT
PB2.13
PB2.14
PB3.0
PB3.1
PB3.2
Standard I/O
Standard I/O
22 A13 XBR1
21 D2 XBR1
20 A12 XBR1
19 A11 XBR1
18 A10 XBR1
AD4m/
D4
Yes
Yes
CMP0P.1
CMP1P.1
AD3m/
D3
CMP0N.1
CMP1N.1
5 V Tolerant I/O
5 V Tolerant I/O
5 V Tolerant I/O
AD2m/
D2
CMP0P.2
CMP1P.2
AD1m/
D1
CMP0N.2
CMP1N.2
AD0m/
D0
DAC0T0
DAC1T0
LPT0T0
CMP0P.3
CMP1P.3
PB3.3
5 V Tolerant I/O
17 B8 XBR1
WR
DAC0T1
DAC1T1
INT0.8
CMP0N.3
CMP1N.3
INT1.8
54
Preliminary Rev. 0.8
SiM3C1xx
Table 5.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued)
Pin Name
Type
PB3.4
5 V Tolerant I/O
16 A9 XBR1
15 B7 XBR1
OE
INT0.9
INT1.9
WAKE.8
CMP0P.4
CMP1P.4
PB3.5
PB3.6
PB3.7
5 V Tolerant I/O
5 V Tolerant I/O
5 V Tolerant I/O
ALEm
DAC0T2
DAC1T2
INT0.10
INT1.10
WAKE.9
CMP0N.4
CMP1N.4
14 A8 XBR1
CS0
BE1
DAC0T3
DAC1T3
INT0.11
INT1.11
WAKE.10
CMP0P.5
CMP1P.5
13 B6 XBR1
DAC0T4
DAC1T4
LPT0T1
INT0.12
INT1.12
WAKE.11
CMP0N.5
CMP1N.5
PB3.8
PB3.9
5 V Tolerant I/O
5 V Tolerant I/O
12 A7 XBR1
CS1
BE0
DAC0T5
DAC1T5
LPT0T2
INT0.13
INT1.13
WAKE.12
CMP0P.6
CMP1P.6
EXREGSP
11 B5 XBR1
DAC0T6
DAC1T6
INT0.14
INT1.14
WAKE.13
CMP0N.6
CMP1N.6
EXREGSN
PB3.10
PB3.11
5 V Tolerant I/O
5 V Tolerant I/O
10 B4 XBR1
INT0.15
INT1.15
WAKE.14
CMP0P.7
CMP1P.7
EXREGOUT
9
B3 XBR1
WAKE.15
CMP0N.7
CMP1N.7
EXREGBD
Preliminary Rev. 0.8
55
SiM3C1xx
Table 5.1. Pin Definitions and alternate functions for SiM3C1x7 (Continued)
Pin Name
Type
PB4.0
PB4.1
PB4.2
PB4.3
PB4.4
PB4.5
High Drive I/O
High Drive I/O
High Drive I/O
High Drive I/O
High Drive I/O
High Drive I/O
8
7
6
3
2
1
A6
A5
A4
A2
A1
D1
LSO0
LSO1
LSO2
LSO3
LSO4
LSO5
Note: All unnamed pins on the LGA-92 package are no-connect pins. They should be soldered to the PCB for mechanical stabil-
ity, but have no internal connections to the device.
56
Preliminary Rev. 0.8
SiM3C1xx
5.2. SiM3C1x6 Pin Definitions
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
PB4.3
PB0.9
2
VSSHD
PB0.10
3
VIOHD
PB0.11
4
PB4.2
PB0.12
5
PB4.1
PB0.13
6
PB4.0
PB0.14/TDO/SWV
PB0.15/TDI
PB1.0
7
PB3.9
8
PB3.8
64 Pin TQFP
9
PB3.7
PB1.1
10
PB3.6
VIO
11
PB3.5
PB1.2
12
PB3.4
PB1.3
13
PB3.3
SWCLK/TCK
SWDIO/TMS
PB1.4
14
PB3.2
15
PB3.1
16
PB3.0
PB1.5
Figure 5.3. SiM3C1x6-GQ Pinout
Preliminary Rev. 0.8
57
SiM3C1xx
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PB4.3
PB0.9
2
3
VSSHD
VIOHD
PB4.2
PB4.1
PB4.0
PB3.9
PB3.8
PB3.7
PB3.6
PB3.5
PB3.4
PB3.3
PB3.2
PB3.1
PB3.0
PB0.10
PB0.11
4
PB0.12
5
PB0.13
6
PB0.14/TDO/SWV
PB0.15/TDI
PB1.0
7
8
64 pin QFN
9
(TopView)
PB1.1
10
11
12
13
14
15
16
VIO
PB1.2
PB1.3
SWCLK/TCK
SWDIO/TMS
PB1.4
VSS
PB1.5
Figure 5.4. SiM3C1x6-GM Pinout
58
Preliminary Rev. 0.8
SiM3C1xx
Table 5.2. Pin Definitions and alternate functions for SiM3C1x6
Pin Name
Type
VSS
Ground
25
59
VDD
VIO
Power (Core)
Power (I/O)
58
24
39
VREGIN
VSSHD
VIOHD
RESET
Power (Regulator)
Ground (High Drive)
Power (High Drive)
Active-low Reset
60
2
3
64
36
35
57
SWCLK/TCK Serial Wire / JTAG
SWDIO/TMS Serial Wire / JTAG
PB0.0
PB0.1
PB0.2
PB0.3
PB0.4
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
XBR0
XBR0
XBR0
XBR0
XBR0
ADC0.2
CS0.1
56
55
54
53
ADC0.3
CS0.2
ADC0.4
CS0.3
ADC0.5
CS0.4
ADC0.6
CS0.5
IVC0.0
PB0.5
PB0.6
Standard I/O
Standard I/O
52
51
XBR0
XBR0
ADC0.7
CS0.6
IVC0.1
ADC0.8
CS0.7
RTC1
Preliminary Rev. 0.8
59
SiM3C1xx
Table 5.2. Pin Definitions and alternate functions for SiM3C1x6 (Continued)
Pin Name
Type
PB0.7
PB0.8
Standard I/O
Standard I/O
50
49
XBR0
XBR0
RTC2
ADC0.9
VREFGND
PB0.9
Standard I/O
Standard I/O
48
47
XBR0
XBR0
ADC0.10
VREF
PB0.10
ADC1.6
IDAC0
PB0.11
PB0.12
PB0.13
Standard I/O
Standard I/O
Standard I/O
46
45
44
43
XBR0
XBR0
XBR0
XBR0
IDAC1
XTAL1
XTAL2
PB0.14/TDO/ Standard I/O / JTAG
SWV / Serial Wire Viewer
ADC0.12
ADC1.12
PB0.15/TDI Standard I/O / JTAG
42
41
40
38
37
XBR0
XBR0
XBR0
XBR0
XBR0
ADC0.13
ADC1.13
PB1.0
PB1.1
PB1.2
PB1.3
Standard I/O
Standard I/O
Standard I/O
Standard I/O
ADC0.14
ADC1.14
ADC0.15
ADC1.15
ADC1.11
CS0.8
ADC1.10
CS0.9
PB1.4
PB1.5
PB1.6
Standard I/O
Standard I/O
Standard I/O
34
33
32
XBR0
XBR0
XBR0
ADC1.8
ADC1.7
ADC0T15
WAKE.0
ADC1.5
CS0.10
PB1.7
Standard I/O
31
XBR0
AD15m/
A7
ADC1T15
WAKE.1
ADC1.4
CS0.11
60
Preliminary Rev. 0.8
SiM3C1xx
Table 5.2. Pin Definitions and alternate functions for SiM3C1x6 (Continued)
Pin Name
Type
PB1.8
Standard I/O
30
29
28
27
XBR0
XBR0
XBR0
XBR0
AD14m/
A6
WAKE.2
WAKE.3
ADC1.3
CS0.12
PB1.9
PB1.10
PB1.11
Standard I/O
Standard I/O
Standard I/O
AD13m/
A5
ADC1.2
CS0.13
AD12m/
A4
DMA0T1
WAKE.4
ADC1.1
CS0.14
AD11m/
A3
DMA0T0
WAKE.5
ADC1.0
CS0.15
PMU_Asleep
PB1.12
PB1.13
PB1.14
PB1.15
PB2.0
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
26
23
22
21
20
19
18
XBR0
XBR0
XBR0
XBR0
XBR1
XBR1
XBR1
AD10m/
A2
WAKE.6
AD9m/
A1
AD8m/
A0
AD7m/
D7
AD6m/
D6
LSI0 Yes
LSI1 Yes
LSI2 Yes
INT0.0
INT1.0
PB2.1
AD5m/
D5
INT0.1
INT1.1
PB2.2
AD4m/
D4
INT0.2
INT1.2
CMP0N.0
CMP1N.0
RTC0OSC_OUT
PB2.3
PB3.0
PB3.1
Standard I/O
5 V Tolerant I/O
5 V Tolerant I/O
17
16
15
XBR1
XBR1
XBR1
AD3m/
D3
LSI3 Yes
INT0.3
INT1.3
CMP0P.0
CMP1P.0
AD2m/
D2
CMP0P.1
CMP1P.1
AD1m/
D1
CMP0N.1
CMP1N.1
Preliminary Rev. 0.8
61
SiM3C1xx
Table 5.2. Pin Definitions and alternate functions for SiM3C1x6 (Continued)
Pin Name
Type
PB3.2
5 V Tolerant I/O
14
13
XBR1
XBR1
AD0m/
D0
DAC0T0
DAC1T0
LPT0T0
WAKE.8
CMP0P.2
CMP1P.2
PB3.3
5 V Tolerant I/O
WR
DAC0T1
DAC1T1
INT0.4
CMP0N.2
CMP1N.2
INT1.4
WAKE.9
PB3.4
PB3.5
5 V Tolerant I/O
5 V Tolerant I/O
12
11
XBR1
XBR1
OE
INT0.5
INT1.5
WAKE.10
CMP0P.3
CMP1P.3
ALEm
DAC0T2
DAC1T2
INT0.6
CMP0N.3
CMP1N.3
INT1.6
WAKE.11
PB3.6
PB3.7
PB3.8
5 V Tolerant I/O
5 V Tolerant I/O
5 V Tolerant I/O
10
9
XBR1
XBR1
XBR1
CS0
BE1
CS1
DAC0T3
DAC1T3
INT0.7
INT1.7
WAKE.12
CMP0P.4
CMP1P.4
EXREGSP
DAC0T4
DAC1T4
INT0.8
INT1.8
WAKE.13
CMP0N.4
CMP1N.4
EXREGSN
8
DAC0T5
DAC1T5
LPT0T1
INT0.9
CMP0P.5
CMP1P.5
EXREGOUT
INT1.9
WAKE.14
62
Preliminary Rev. 0.8
SiM3C1xx
Table 5.2. Pin Definitions and alternate functions for SiM3C1x6 (Continued)
Pin Name
Type
PB3.9
5 V Tolerant I/O
7
XBR1
BE0
DAC0T6
DAC1T6
LPT0T2
INT0.10
INT1.10
WAKE.15
CMP0N.5
CMP1N.5
EXREGBD
PB4.0
PB4.1
PB4.2
PB4.3
High Drive I/O
High Drive I/O
High Drive I/O
High Drive I/O
6
5
4
1
LSO0
LSO1
LSO2
LSO3
Preliminary Rev. 0.8
63
SiM3C1xx
5.3. SiM3C1x4 Pin Definitions
1
2
30
29
28
27
26
25
24
23
22
21
PB4.3
VSSHD
VIOHD
PB4.2
PB4.1
PB4.0
PB3.3
PB3.2
PB3.1
PB3.0
PB0.4
PB0.5
PB0.6
PB0.7
PB0.8
PB0.9
SWCLK
SWDIO
PB0.10
PB0.11
3
4
5
40 pin QFN
(Top View)
6
7
8
9
VSS
10
Figure 5.5. SiM3C1x4-GM Pinout
64
Preliminary Rev. 0.8
SiM3C1xx
Table 5.3. Pin Definitions and alternate functions for SiM3C1x4
Pin Name
Type
VSS
VDD
Ground
Power (Core)
14
35
13
36
2
VIO
Power (I/O)
VREGIN
VSSHD
VIOHD
RESET
SWCLK
SWDIO
PB0.0
Power (Regulator)
Ground (High Drive)
Power (High Drive)
Active-low Reset
Serial Wire
3
40
24
23
34
Serial Wire
Standard I/O
XBR0
ADC0.8
CS0.7
RTC1
PB0.1
PB0.2
Standard I/O
Standard I/O
33
32
XBR0
XBR0
RTC2
ADC0.9
CS0.0
VREFGND
PB0.3
PB0.4
Standard I/O
Standard I/O
31
30
XBR0
XBR0
ADC0.10
CS0.1
VREF
ADC1.6
CS0.2
IDAC0
PB0.5
PB0.6
Standard I/O
Standard I/O
29
28
IDAC1
XBR0
XBR0
ADC0.0
CS0.3
XTAL1
PB0.7
Standard I/O
27
ADC0.1
CS0.4
XTAL2
Preliminary Rev. 0.8
65
SiM3C1xx
Table 5.3. Pin Definitions and alternate functions for SiM3C1x4 (Continued)
Pin Name
Type
PB0.8
Standard I/O
26
25
XBR0
XBR0
ADC0.14
ADC1.14
PB0.9
Standard I/O
ADC0.15
ADC1.15
PB0.10
PB0.11
PB0.12
Standard I/O
Standard I/O
Standard I/O
22
21
20
XBR0
XBR0
XBR0
DMA0T1
DMA0T0
ADC1.8
ADC1.7
ADC0T15
WAKE.0
ADC1.5
CS0.10
PB0.13
PB0.14
PB0.15
PB1.0
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
19
18
17
16
15
XBR0
XBR0
XBR0
XBR0
XBR0
ADC1T15
WAKE.1
ADC1.4
CS0.11
WAKE.2
WAKE.3
WAKE.4
WAKE.5
ADC1.3
CS0.12
ADC1.2
CS0.13
ADC1.1
CS0.14
PB1.1
ADC1.0
CS0.15
PMU_Asleep
PB1.2
Standard I/O
12
XBR0
CMP0N.0
CMP1N.0
RTC0OSC_OUT
PB1.3
PB3.0
Standard I/O
11
10
XBR0
XBR1
CMP0P.0
CMP1P.0
5 V Tolerant I/O
DAC0T0
DAC1T0
LPT0T0
INT0.0
CMP0P.1
CMP1P.1
EXREGSP
INT1.0
WAKE.12
66
Preliminary Rev. 0.8
SiM3C1xx
Table 5.3. Pin Definitions and alternate functions for SiM3C1x4 (Continued)
Pin Name
Type
PB3.1
5 V Tolerant I/O
9
8
7
XBR1
XBR1
XBR1
DAC0T1
DAC1T1
LPT0T1
INT0.1
INT1.1
WAKE.13
CMP0N.1
CMP1N.1
EXREGSN
PB3.2
PB3.3
5 V Tolerant I/O
5 V Tolerant I/O
DAC0T2
DAC1T2
LPT0T2
INT0.2
INT1.3
WAKE.14
CMP0P.2
CMP1P.2
EXREGOUT
DAC0T3
DAC1T3
INT0.3
CMP0N.2
CMP1N.2
EXREGBD
INT1.3
WAKE.15
PB4.0
PB4.1
PB4.2
PB4.3
High Drive I/O
High Drive I/O
High Drive I/O
High Drive I/O
6
5
4
1
Preliminary Rev. 0.8
67
SiM3C1xx
6. Ordering Information
Si M3 C 1 4 4 – B – GM
Temperature Grade and Package Type
Revision
Pin Count – 4 (40 pin), 6 (64 pin), 7 (80 or 92 pin)
Memory Size – 3 (32 kB), 4 (64 kB), 5 (128 kB), 6 (256 kB)
Feature Set – varies by family
Family – U (USB), C (Core)
Core – M3 (Cortex M3)
Silicon Labs
Figure 6.1. SiM3C1xx Part Numbering
All devices in the SiM3C1xx family have the following features:
Core: ARM Cortex-M3 with maximum operating frequency of 80 MHz.
Flash Program Memory: 32-256 kB, in-system programmable.
RAM: 8–32 kB SRAM, with 4 kB retention SRAM
I/O: Up to 65 multifunction I/O pins, including high-drive and 5 V-tolerant pins.
Clock Sources: Internal and external oscillator options.
16-Channel DMA Controller.
128/192/256-bit AES.
16/32-bit CRC.
Timers: 2 x 32-bit (4 x 16-bit).
Real-Time Clock.
Low-Power Timer.
PCA: 1 x 6 channels (Enhanced), 2 x 2 channels (Standard). PWM, capture, and clock generation
capabilites.
ADC: 2 x 12-bit 250 ksps (10-bit 1 Msps) SAR.
DAC: 2 x 10-bit IDAC.
Temperature Sensor.
Internal VREF.
16-channel Capacitive Sensing (CAPSENSE).
Comparator: 2 x low current.
Current to Voltage Converter (IVC).
Serial Buses: 2 x USART, 2 x UART, 3 x SPI, 2 x I2C, 1 x I2S.
The inclusion of some features varies across different members of the device family. The differences are detailed in
Table 6.1.
68
Preliminary Rev. 0.8
SiM3C1xx
Table 6.1. Product Selection Guide
SiM3C167-B-GM 256 32
SiM3C167-B-GQ 256 32
SiM3C166-B-GM 256 32
SiM3C166-B-GQ 256 32
SiM3C164-B-GM 256 32
SiM3C157-B-GM 128 32
SiM3C157-B-GQ 128 32
SiM3C156-B-GM 128 32
SiM3C156-B-GQ 128 32
SiM3C154-B-GM 128 32
SiM3C146-B-GM 64 16
SiM3C146-B-GQ 64 16
SiM3C144-B-GM 64 16
24 65
24 65
16 50
16 50
28
6
6
4
4
4
6
6
4
4
4
4
4
4
4
4
4
16 16 16 8/8 16
16 16 16 8/8 16
13 15 15 6/6 15
13 15 15 6/6 15
LGA-92
TQFP-80
QFN-64
TQFP-64
QFN-40
LGA-92
TQFP-80
QFN-64
TQFP-64
QFN-40
QFN-64
TQFP-64
QFN-40
QFN-64
TQFP-64
QFN-40
7
11 12 3/3 10
24 65
24 65
16 50
16 50
28
16 16 16 8/8 16
16 16 16 8/8 16
13 15 15 6/6 15
13 15 15 6/6 15
7
11 12 3/3 10
16 50
16 50
28
13 15 15 6/6 15
13 15 15 6/6 15
7
11 12 3/3 10
SiM3C136-B-GM 32
SiM3C136-B-GQ 32
SiM3C134-B-GM 32
8
8
8
16 50
16 50
28
13 15 15 6/6 15
13 15 15 6/6 15
7
11 12 3/3 10
Preliminary Rev. 0.8
69
SiM3C1xx
6.1. LGA-92 Package Specifications
Figure 6.2. LGA-92 Package Drawing
Table 6.2. LGA-92 Package Dimensions
Dimension
Min
0.74
0.25
3.15
Nominal
0.84
Max
0.94
0.35
3.25
A
b
0.30
c
3.20
D
7.00 BSC
6.50 BSC
4.00 BSC
0.50 BSC
7.00 BSC
6.50 BSC
4.00 BSC
—
D1
D2
e
E
E1
E2
aaa
bbb
ccc
ddd
eee
—
—
—
—
—
0.10
0.10
0.08
0.10
0.10
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
70
Preliminary Rev. 0.8
SiM3C1xx
Figure 6.3. LGA-92 Landing Diagram
Table 6.3. LGA-92 Landing Diagram Dimensions
Dimension
Typical
6.50
6.50
0.50
—
Max
—
C1
C2
e
—
—
f
0.35
3.20
3.20
P1
P2
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. All feature sizes shown are at Maximum Material Condition (MMC)
and a card fabrication tolerance of 0.05 mm is assumed.
3. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994
specification.
4. This land pattern design is based on the IPC-7351 guidelines.
Preliminary Rev. 0.8
71
SiM3C1xx
6.1.1. LGA-92 Solder Mask Design
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad
is to be 60 µm minimum, all the way around the pad.
6.1.2. LGA-92 Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
4. A 2 x 2 array of 1.25 mm square openings on 1.60 mm pitch should be used for the center ground pad.
6.1.3. LGA-92 Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
72
Preliminary Rev. 0.8
SiM3C1xx
6.2. TQFP-80 Package Specifications
Figure 6.4. TQFP-80 Package Drawing
Table 6.4. TQFP-80 Package Dimensions
Dimension
Min
—
Nominal
—
Max
1.20
0.15
1.05
0.27
0.20
A
A1
A2
b
0.05
0.95
0.17
0.09
—
1.00
0.20
c
—
D
14.00 BSC
12.00 BSC
0.50 BSC
14.00 BSC
12.00 BSC
D1
e
E
E1
Preliminary Rev. 0.8
73
SiM3C1xx
Table 6.4. TQFP-80 Package Dimensions (Continued)
Dimension
Min
Nominal
0.60
Max
L
0.45
0.75
L1
1.00 Ref
3.5°
0°
7°
aaa
bbb
ccc
ddd
eee
0.20
0.20
0.08
0.08
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant ADD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
74
Preliminary Rev. 0.8
SiM3C1xx
Figure 6.5. TQFP-80 Landing Diagram
Table 6.5. TQFP-80 Landing Diagram Dimensions
Dimension
Min
Max
13.40
13.40
C1
C2
E
13.30
13.30
0.50 BSC
X
0.20
1.40
0.30
1.50
Y
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. This land pattern design is based on the IPC-7351 guidelines.
Preliminary Rev. 0.8
75
SiM3C1xx
6.2.1. TQFP-80 Solder Mask Design
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad
is to be 60 µm minimum, all the way around the pad.
6.2.2. TQFP-80 Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
6.2.3. TQFP-80 Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
76
Preliminary Rev. 0.8
SiM3C1xx
6.3. QFN-64 Package Specifications
Figure 6.6. QFN-64 Package Drawing
Table 6.6. QFN-64 Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nominal
0.85
Max
0.90
0.05
0.30
A
A1
b
0.02
0.25
D
9.00 BSC
4.10
D2
e
3.95
4.25
0.50 BSC
9.00 BSC
4.10
E
E2
L
3.95
0.30
4.25
0.50
0.40
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.08
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Preliminary Rev. 0.8
77
SiM3C1xx
Figure 6.7. QFN-64 Landing Diagram
Table 6.7. QFN-64 Landing Diagram Dimensions
Dimension
mm
8.90
8.90
0.50
0.30
0.85
4.25
4.25
C1
C2
E
X1
Y1
X2
Y2
Notes:
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC).
Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
78
Preliminary Rev. 0.8
SiM3C1xx
6.3.1. QFN-64 Solder Mask Design
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad
is to be 60 µm minimum, all the way around the pad.
6.3.2. QFN-64 Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
4. A 3x3 array of 1.0 mm square openings on a 1.5 mm pitch should be used for the center ground pad.
6.3.3. QFN-64 Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Preliminary Rev. 0.8
79
SiM3C1xx
6.4. TQFP-64 Package Specifications
Figure 6.8. TQFP-64 Package Drawing
Table 6.8. TQFP-64 Package Dimensions
Dimension
Min
—
Nominal
—
Max
1.20
0.15
1.05
0.27
0.20
A
A1
A2
b
0.05
0.95
0.17
0.09
—
1.00
0.22
c
—
D
12.00 BSC
10.00 BSC
0.50 BSC
12.00 BSC
10.00 BSC
0.60
D1
e
E
E1
L
0.45
0°
0.75
7°
3.5°
80
Preliminary Rev. 0.8
SiM3C1xx
Table 6.8. TQFP-64 Package Dimensions (Continued)
Dimension
aaa
Min
—
Nominal
Max
0.20
0.20
0.08
0.08
—
—
—
—
bbb
—
ccc
—
ddd
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant ACD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Preliminary Rev. 0.8
81
SiM3C1xx
Figure 6.9. TQFP-64 Landing Diagram
Table 6.9. TQFP-64 Landing Diagram Dimensions
Dimension
Min
Max
11.40
11.40
C1
C2
E
11.30
11.30
0.50 BSC
X
0.20
1.40
0.30
1.50
Y
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. This land pattern design is based on the IPC-7351 guidelines.
82
Preliminary Rev. 0.8
SiM3C1xx
6.4.1. TQFP-64 Solder Mask Design
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad
is to be 60 µm minimum, all the way around the pad.
6.4.2. TQFP-64 Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
6.4.3. TQFP-64 Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Preliminary Rev. 0.8
83
SiM3C1xx
6.5. QFN-40 Package Specifications
Figure 6.10. QFN-40 Package Drawing
Table 6.10. QFN-40 Package Dimensions
Dimension
Min
0.80
0.00
0.18
Nominal
0.85
Max
0.90
0.05
0.30
A
A1
b
0.02
0.25
D
6.00 BSC
4.50
D2
e
4.35
4.65
0.50 BSC
6.00 BSC
4.5
E
E2
L
4.35
0.30
4.65
0.50
0.40
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.08
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
84
Preliminary Rev. 0.8
SiM3C1xx
Figure 6.11. QFN-40 Landing Diagram
Table 6.11. QFN-40 Landing Diagram Dimensions
Dimension
mm
5.90
5.90
0.50
0.30
0.85
4.65
4.65
C1
C2
E
X1
Y1
X2
Y2
Notes:
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC).
Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Preliminary Rev. 0.8
85
SiM3C1xx
6.5.1. QFN-40 Solder Mask Design
All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad
is to be 60 µm minimum, all the way around the pad.
6.5.2. QFN-40 Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
4. A 3x3 array of 1.1 mm square openings on a 1.6 mm pitch should be used for the center ground pad.
6.5.3. QFN-40 Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
86
Preliminary Rev. 0.8
SiM3C1xx
7. Revision Specific Behavior
This chapter details any known differences from behavior as stated in the device datasheet and reference manual.
All known errata for the current silicon revision are rolled into this section at the time of publication. Any errata
found after publication of this document will initially be detailed in a separate errata document until this datasheet is
revised.
7.1. Revision Identification
The Lot ID Code on the top side of the device package can be used for decoding device revision information.
Figures 7.1, 7.2, 7.3, and 7.4 show how to find the Lot ID Code on the top side of the device package.
In addition, firmware can determine the revision of the device by checking the DEVICEID registers.
SiM3C167
BGNZEB
1142
This first character identifies
the device revision
Figure 7.1. LGA-92 SiM3C1x7 Revision Information
SiM3C167
A-GQ
1131BCS701
e3
TW
This character identifies the
device revision
Figure 7.2. TQFP-80 SiM3C1x7 Revision Information
Preliminary Rev. 0.8
87
SiM3C1xx
SiM3C166
BGNZEB
1142
SiM3C166
BGNZEB
1142
This first character identifies
the device revision
Figure 7.3. SiM3C1x6 Revision Information
SIL
M3C164
BGNZ
1142+
This first character identifies
the device revision
Figure 7.4. SiM3C1x4 Revision Information
7.2. Comparator Rising/Falling Edge Flags in Debug Mode (CMP0, CMP1)
7.2.1. Problem
On Revision A and Revision B devices, if the comparator output is high, the comparator rising and falling edge
flags will both be set to 1 upon single-step or exit from debug mode.
7.2.2. Impacts
Firmware using the rising and falling edge flags to make decisions may see a false trigger of the comparator if the
output of the comparator is high during a debug session. This does not impact the non-debug operation of the
device.
7.2.3. Workaround
There is not a system-agnostic workaround for this issue.
7.2.4. Resolution
This issue exists on Revision A and Revision B devices. It may be corrected in a future device revision.
88
Preliminary Rev. 0.8
SiM3C1xx
NOTES:
Preliminary Rev. 0.8
89
SiM3C1xx
CONTACT INFORMATION
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90
Preliminary Rev. 0.8
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