TS1109-200IDT833 [SILICON]

Overcurrent and Undercurrent Detection;


型号：	TS1109-200IDT833
厂家：	SILICON
描述：	Overcurrent and Undercurrent Detection
文件：	总20页 (文件大小：855K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TS1109 Data Sheet

TS1109 Bidirectional Current-Sense Amplifier with Buffered Bipo-

lar Output

KEY FEATURES

• Low Supply Current

The TS1109 incorporates a bidirectional current-sense amplifier plus a buffered bipolar

output with an adjustable bias. The internal configuration of the TS1109 high-side cur-

rent-sense amplifier is a variation of the TS1101 bidirectional current-sense amplifier,

consuming 0.68 µA(typ) and 1.2 µA(max). The current-sense amplifier’s buffered output

consumes only 0.76 µ A(typ) and 1.3 µA(max) of supply current. With an input offset volt-

age of 150 µV(max) and a gain error of 1%(max), the TS1109 is optimized for high preci-

sion current measurements

• Current Sense Amplifier: 0.68 µA

• I

: 0.76 µA

VDD

• High Side Bidirectional Current Sense

Amplifier

• Wide CSA Input Common Mode Range: +2

V to +27 V

• Low CSA Input Offset Voltage: 150

µV(max)

Applications

• Low Gain Error: 1%(max)

• Power Management Systems

• Portable/Battery-Powered Systems

• Smart Chargers

• Two Gain Options Available:

• Gain = 20 V/V : TS1109-20

• Gain = 200 V/V : TS1109-200

• Battery Monitoring

• 8-Pin TDFN Packaging (3 mm x 3 mm)

• Overcurrent and Undercurrent Detection

• Remote Sensing

• Industrial Controls

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TS1109 Data Sheet

Ordering Information

1. Ordering Information

Table 1.1. Ordering Part Numbers

Ordering Part Number

TS1109-20IDT833

Description

Gain V/V

Bidirectional current sense amplifier with buffered bipolar output

TS1109-200 IDT833

200

Note: Adding the suffix “T” to the part number (e.g. TS1109-200IDT833T) denotes tape and reel.

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TS1109 Data Sheet

System Overview

2. System Overview

2.1 Functional Block Diagram

Figure 2.1. TS1109 Bidirectional Bipolar Buffered Current Sense Amplifier Block Diagram

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TS1109 Data Sheet

System Overview

2.2 Current Sense Amplifier + Output Buffer

The internal configuration of the TS1109 bidirectional current-sense amplifier is a variation of the TS1101 bidirectional current-sense

amplifier. The TS1109 current-sense amplifier is configured for fully differential input/output operation.

Referring to the block diagram, the inputs of the TS1109’s differential input/output amplifier are connected to RS+ and RS– across an

external R_SENSEresistor that is used to measure current. At the non-inverting input of the current-sense amplifier, the applied voltage

difference in voltage between RS+ and RS– is I_LOADx R_SENSE. Since the RS– terminal is the non-inverting input of the internal op-amp,

the current-sense op-amp action drives PMOS[1/2] to drive current across R_GAIN[A/B]to equalize voltage at its inputs.

Thus, since the M1 PMOS source is connected to the inverting input of the internal op-amp and since the voltage drop across R_GAINAis

the same as the external V_SENSE, the M1 PMOS’ drain-source current is equal to:

SENSE

DS(M 1)

GAINA

× R

LOAD

SENSE

GAINA

DS(M 1)

The drain terminal of the M1 PMOS is connected to the transimpedance amplifier’s gain resistor, R_OUT, via the inverting terminal. The

non-inverting terminal of the transimpedance amplifier is internally connected to VBIAS, therefore the output voltage of the TS1109 at

the OUT terminal is:

OUT

= V

− I

× R

OUT

BIAS

LOAD

SENSE

GAINA

When the voltage at the RS– terminal is greater than the voltage at the RS+ terminal, the external V_SENSEvoltage drop is impressed

upon R_GAINB. The voltage drop across R_GAINBis then converted into a current by the M2 PMOS. The M2 PMOS drain-source current is

the input current for the NMOS current mirror which is matched with a 1-to-1 ratio. The transimpedance amplifier sources the M2 PMOS

drain-source current for the NMOS current mirror. Therefore, the output voltage of the TS1109 at the OUT terminal is:

OUT

= V

+ I

× R

OUT

BIAS

LOAD

SENSE

GAINB

When M1 is conducting current (V_RS+> V_RS–), the TS1109’s internal amplifier holds M2 OFF. When M2 is conducting current (V_RS–

V_RS+), the internal amplifier holds M1 OFF. In either case, the disabled PMOS does not contribute to the resultant output voltage.

The current-sense amplifier’s gain accuracy is therefore the ratio match of R_OUTto R_GAIN[A/B]. For each of the two gain options availa-

ble, The following table lists the values for R_GAIN[A/B]

Table 2.1. Internal Gain Setting Resistors (Typical Values)

GAIN (V/V)

R_GAIN[A/B](Ω)

R_OUT(Ω)

40 k

Part Number

TS1109-20

2 k

200

40 k

TS1109-200

The TS1109 allows access to the inverting terminal of the transimpedance amplifier by the FILT pin, whereby a series RC filter may be

connected to reduce noise at the OUT terminal. The recommended RC filter is 4 kΩ and 0.47 µF connected in series from FILT to GND

to suppress the noise. Any capacitance at the OUT terminal should be minimized for stable operation of the buffer.

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TS1109 Data Sheet

System Overview

2.3 Sign Output

The TS1109 SIGN output indicates the load current’s direction. The SIGN output is a logic HIGH when M1 is conducting current (V_RS+

> V_RS–). Alternatively, the SIGN output is a logic LOW when M2 is conducting current (V_RS–> V_RS+). The SIGN comparator’s transfer

characteristic is illustrated in the figure below. Unlike other current-sense amplifiers that implement an OUT/SIGN arrangement, the

TS1109 exhibits no “dead zone” at I_LOADswitchover.

Figure 2.2. TS1109 Sign Output Transfer Characteristic

2.4 Selecting a Sense Resistor

Selecting the optimal value for the external R_SENSEis based on the following criteria and for each commentary follows:

1. R_SENSEVoltage Loss

2. V_OUTSwing vs. Desired V_SENSEand Applied Supply Voltage at VDD

3. Total I_LOADAccuracy

4. Circuit Efficiency and Power Dissipation

5. R_SENSEKelvin Connections

2.4.1 RSENSE Voltage Loss

For lowest IR power dissipation in R_SENSE, the smallest usable resistor value for R_SENSEshould be selected.

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TS1109 Data Sheet

System Overview

2.4.2 VOUT Swing vs. Desired VSENSE and Applied Supply Voltage at VDD

Although the Current Sense Amplifier draws its power from the voltage at its RS+ and RS– terminals, the signal voltage at the OUT

terminal is provided by a buffer, and is therefore bounded by the buffer’s output range. As shown in the Electrical Characteristics table,

the CSA Buffer has a maximum and minimum output voltage of:

= VDD

= 0.2V

− 0.2V

(min )

OUT (max )

OUT (min )

Therefore, the full-scale sense voltage should be chosen so that the OUT voltage is neither greater nor less than the maximum and

minimum output voltage defined above. To satisfy this requirement, the positive full-scale sense voltage, V_{SENSE(pos_max)}, should be

chosen so that:

VBIAS − V

OUT (min )

SENSE(pos_max )

GAIN

Likewise, the negative full-scale sense voltage, V_{SENSE(neg_min)}, should be chosen so that:

− VBIAS

OUT (max )

SENSE(neg_min )

GAIN

For best performance, R_SENSEshould be chosen so that the full-scale V_SENSEis less than ±75 mV.

2.4.3 Total Load Current Accuracy

In the TS1109’s linear region where V_OUT(min)< V_OUT< V_OUT(max), there are two specifications related to the circuit’s accuracy: a) the

TS1109 CSA’s input offset voltage (V_OS(max)= 150 µV), b) the TS1109 CSA’s gain error (GE_(max)= 1%). An expression for the

TS1109’s total error is given by:

= VBIAS − GAIN × 1 ± GE × V

± GAIN × V

SENSE OS

(

)

(

)

OUT

A large value for R_SENSEpermits the use of smaller load currents to be measured more accurately because the effects of offset voltag-

es are less significant when compared to larger V_SENSEvoltages. Due care though should be exercised as previously mentioned with

large values of R_SENSE

2.4.4 Circuit Efficiency and Power Dissipation

IR loses in R_SENSEcan be large especially at high load currents. It is important to select the smallest, usable R_SENSEvalue to minimize

power dissipation and to keep the physical size of R_SENSEsmall. If the external R_SENSEis allowed to dissipate significant power, then

its inherent temperature coefficient may alter its design center value, thereby reducing load current measurement accuracy. Precisely

because the TS1109 CSA’s input stage was designed to exhibit a very low input offset voltage, small R_SENSEvalues can be used to

reduce power dissipation and minimize local hot spots on the pcb.

2.4.5 RSENSE Kelvin Connections

For optimal V_SENSEaccuracy in the presence of large load currents, parasitic pcb track resistance should be minimized. Kelvin-sense

pcb connections between R_SENSEand the TS1109’s RS+ and RS– terminals are strongly recommended. The drawing below illustrates

the connections between the current-sense amplifier and the current-sense resistor. The pcb layout should be balanced and symmetri-

cal to minimize wiring-induced errors. In addition, the pcb layout for R_SENSEshould include good thermal management techniques for

optimal R_SENSEpower dissipation.

Figure 2.3. Making PCB Connections to R_SENSE

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TS1109 Data Sheet

System Overview

2.4.6 RSENSE Composition

Current-shunt resistors are available in metal film, metal strip, and wire-wound constructions. Wire-wound current-shunt resistors are

constructed with wire spirally wound onto a core. As a result, these types of current shunt resistors exhibit the largest self-inductance. In

applications where the load current contains high-frequency transients, metal film or metal strip current sense resistors are recommen-

ded.

2.4.7 Internal Noise Filter

In power management and motor control applications, current-sense amplifier are required to measure load currents accurately in the

presence of both externally-generated differential and common-mode noise. An example of differential-mode noise that can appear at

the inputs of a current-sense amplifier is high-frequency ripple. High-frequency ripple (whether injected into the circuit inductively or ca-

pacitively) can produce a differential-mode voltage drop across the external current-shunt resistor, R_SENSE. An example of externally-

generated, common-mode noise is the high-frequency output ripple of a switching regulator that can result in common-mode noise in-

jection into both inputs of a current-sense amplifier.

Even though the load current signal bandwidth is dc, the input stage of any current-sense amplifier can rectify unwanted, out-of-band

noise that can result in an apparent error voltage at its output. Against common-mode injection noise, the current-sense amplifier’s in-

ternal common-mode rejection ratio is 130 dB (typ).

To counter the effects of externally-injected noise, the TS1109 incorporates a 50 kHz (typ), 2nd-order differential low-pass filter as

shown in the TS1109’s block diagram, thereby eliminating the need for an external low-pass filter, which can generate errors in the

offset voltage and the gain error.

2.4.8 PC Board Layout and Power-Supply Bypassing

For optimal circuit performance, the TS1109 should be in very close proximity to the external current-sense resistor, and the pcb tracks

from R_SENSEto the RS+ and the RS– input terminals of the TS1109 should be short and symmetric. Also recommended are surface

mount resistors and capacitors, as well as a ground plane.

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TS1109 Data Sheet

Electrical Characteristics

3. Electrical Characteristics

Table 3.1. Recommended Operating Conditions¹

Parameter

Symbol

Conditions

Min

Typ

Max

Units

System Specifications

Operating Voltage Range

Common-Mode Input Range

Note:

VDD

V_CM

1.7

—

5.25

V_RS+, Guaranteed by CMRR

1. All devices 100% production tested at T_A= +25 °C. Limits over Temperature are guaranteed by design and characterization.

Table 3.2. DC Characteristics¹

Parameter

Symbol

Conditions

Min

Typ

Max

Units

System Specifications

No Load Input Supply Current

I_RS++ I_RS–

I_VDD

See Note 2

—

0.68

0.76

1.2

1.3

µA

Current Sense Amplifier

Common Mode Rejection Ratio

Input Offset Voltage (See Note 3)

CMRR

V_OS

2 V < V_RS+< 27 V

T_A= +25 °C

120

—

130

±100

—

±150

±200

—

µV

V/V

–40 °C < T_A< +85 °C

T_A= +25 °C

V_OSHysteresis (See Note 4)

Gain

V_HYS

TS1109-20

—

TS1109-200

200

±0.1

—

Positive Gain Error (See Note 5)

Negative Gain Error (See Note 5)

Gain Match (See Note 5)

GE+

GE–

T_A= +25 °C

±0.6

±1

kΩ

–40 °C < T_A< +85 °C

T_A= +25 °C

±0.6

—

±1

–40 °C < T_A< +85 °C

T_A= +25 °C

±1.4

±1

±0.6

—

–40 °C < T_A< +85 °C

From FILT to OUT

±1.4

52.8

Transfer Resistance

CSA Buffer

R_OUT

Input Bias Current

Input referred DC Offset

Offset Drift

I_{Buffer_BIAS}

V_{Buffer_OS}

TCV_{Buffer_OS}

V_{Buffer_CM}

–40 °C < T_A< +85 °C

—

0.3

—

±2.5

µV/°C

–40 °C < T_A< +85 °C

–40C < T_A< +85 °C

I_OUT= ±150 µA

—

0.6

—

Input Common Mode Range

Output Range

0.2

VDD – 0.2

V_OUT(min,max)

—

Sign Comparator Parameters

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TS1109 Data Sheet

Electrical Characteristics

Parameter

Symbol

V_{SIGN_OL}

V_{SIGN_OH}

Conditions

Min

Typ

—

Max

0.2

—

Units

Output Low Voltage

Output High Voltage

Note:

V_DD= 1.8 V, I_SINK= 35 µA

—

V_DD= 1.8 V, I_SOURCE= 35 µA VDD – 0.2

—

1. RS+ = RS– = 3.6 V, V_SENSE= (V_RS+– V_RS–) = 0 V, VDD = 3 V, VBIAS = 1.5 V, FILT connected to 4 kW and 470 nF in series to

GND. T_A= T_J= –40 °C to +85 °C unless otherwise noted. Typical values are at T_A= +25 °C.

2. Extrapolated to V_OUT= V_FILT. I_RS++ I_RS–is the total current into the RS+ and the RS– pins.

3. Input offset voltage V_OSis extrapolated from a V_OUT(+)measurement with V_SENSEset to +1 mV and a V_OUT(–)measurement with

V_SENSEset to –1 mV; Average V_OS= (V_OUT(–)– V_OUT(+))/(2 x GAIN).

4. Amplitude of V_SENSElower or higher than V_OSrequired to cause the comparator to switch output states.

5. Gain error is calculated by applying two values for V_SENSEand then calculating the error of the actual slope vs. the ideal transfer

characteristic: For GAIN = 20 V/V, the applied V_SENSEfor GE± is ±25 mV and ±60 mV. For GAIN = 200 V/V, the applied V_SENSE

for GE± is ±2.5 mV and ±6 mV.

Table 3.3. AC Characteristics

Parameter

Symbol

t_{OUT_s}

Conditions

Min

Typ

Max

Units

msec

CSA Buffer

Output Settling time

Sign Comparator

Propagation Delay

1% Final value, V_OUT= 1.3 V

Gain = 20 V/V

—

1.35

—

t_{SIGN_PD}

V_SENSE= ±1 mV

V_SENSE= ±10 mV

—

0.4

—

msec

Table 3.4. Thermal Conditions

Parameter

Symbol

Conditions

Min

Typ

Max

+85

Units

Operating Temperature Range

T_OP

–40

—

°C

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TS1109 Data Sheet

Electrical Characteristics

Table 3.5. Absolute Maximum Limits

Parameter

Symbol

V_RS+

Conditions

Min

–0.3

—

Typ

—

Max

Units

RS+ Voltage

RS– Voltage

V_RS–

Supply Voltage

VDD

OUT Voltage

V_OUT

SIGN Voltage

V_SIGN

V_FILT

V_VBIAS

_RS+– V_RS–

FILT Voltage

VDD + 0.3

VBIAS Voltage

RS+ to RS– Voltage

Short Circuit Duration: OUT to GND

Continuous Input Current (Any Pin)

Junction Temperature

Storage Temperature Range

Lead Temperature (Soldering, 10 s)

Soldering Temperature (Reflow)

ESD Tolerance

—

Continuous

–20

—

°C

150

–65

—

150

300

—

260

Human Body Model

Machine Model

—

2000

200

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TS1109 Data Sheet

Electrical Characteristics

For the following graphs, V_RS+= V_RS–= 3.6 V; VDD = 3 V; VBIAS = 1.5 V, and T_A= +25 C unless otherwise noted.

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TS1109 Data Sheet

Electrical Characteristics

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TS1109 Data Sheet

Electrical Characteristics

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TS1109 Data Sheet

Electrical Characteristics

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TS1109 Data Sheet

Typical Application Circuit

4. Typical Application Circuit

Figure 4.1. TS1109 Typical Application Circuit

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TS1109 Data Sheet

Pin Descriptions

5. Pin Descriptions

TS1109

Table 5.1. Pin Descriptions

Label

SIGN

VDD

Function

Sign output. SIGN is HIGH for V_RS+>V_RS–and LOW for V_RS–>V_RS+

External power supply pin. Connect this to the system’s VDD supply.

VBIAS Bias voltage for CSA output. When VREF is activated, leave open.

GND

OUT

FILT

RS+

Ground. Connect to analog ground.

CSA buffered output. Connect to CIN–.

Inverting terminal of CSA Buffer. Connect a series RC Filter of 4 kΩ and 0.47 µF, otherwise leave open.

External Sense Resistor Power-Side Connection.

RS–

External Sense Resistor Load-Side Connection.

Exposed Pad

EPAD

Exposed backside paddle. For best electrical and thermal performance, solder to analog ground.

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TS1109 Data Sheet

Packaging

6. Packaging

Figure 6.1. TS1109 3x3 mm 8-TDFN Package Diagram

Table 6.1. Package Dimensions

Dimension

Min

0.70

0.00

Nom

0.75

Max

0.80

0.05

0.02

0.20 REF

0.30

0.25

1.49

0.35

1.51

3.00 BSC

1.50

0.65 BSC

3.00 BSC

1.75

1.65

0.30

0.20

1.85

0.50

0.30

0.40

0.25

0.65 REF

0.10

aaa

bbb

ccc

0.05

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

4. This drawing conforms to the JEDEC Solid State Outline MO-229.

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TS1109 Data Sheet

Top Marking

7. Top Marking

Figure 7.1. Top Marking

Table 7.1. Top Marking Explanation

Mark Method

Laser

Circle = 0.50 mm Diameter (lower left corner)

0.50 mm (20 mils)

Pin 1 Mark:

Font Size:

Line 1 Mark Format:

Line 2 Mark Format:

Line 3 Mark Format:

Product ID

Note: A = 20 gain, B = 200 gain

Manufacturing code

TTTT – Mfg Code

YY = Year; WW = Work Week

Year and week of assembly

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Table of Contents

1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 Current Sense Amplifier + Output Buffer . . . . . . . . . . . . . . . . . . . . . 3

2.3 Sign Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.4 Selecting a Sense Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.4.1 RSENSE Voltage Loss . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.4.2 VOUT Swing vs. Desired VSENSE and Applied Supply Voltage at VDD. . . . . . . . . . 5

2.4.3 Total Load Current Accuracy . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4.4 Circuit Efficiency and Power Dissipation . . . . . . . . . . . . . . . . . . . . 5

2.4.5 RSENSE Kelvin Connections . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4.6 RSENSE Composition . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4.7 Internal Noise Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4.8 PC Board Layout and Power-Supply Bypassing . . . . . . . . . . . . . . . . . . 6

3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 14

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7. Top Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table of Contents 18

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TS1109-200IDT833 [SILICON]

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