TS7003ITD833 [SILICON]
ADC, Successive Approximation,;
| 型号： | TS7003ITD833 |
| 厂家： | 
SILICON |
| 描述： | ADC, Successive Approximation, 光电二极管 转换器 |
| 文件： | 总15页 (文件大小：1318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS7003
A 300ksps, Single-supply, 12-Bit Serial-output ADC
DESCRIPTION
FEATURES
Pin-Compatible, Single-channel Higher-Speed
The TS7003 – a single-supply, single-channel, 12-bit
analog-to-digital converter (ADC) - is a successive-
approximation ADC that combines a high-bandwidth
track-and-hold (T/H), a high-speed serial digital
interface, an internal +2.5V reference, and low
conversion-mode power consumption. The TS7003
operates from a single +2.7V to+3.6V supply and
draws less than 1mA at 300ksps.
Upgrade to MAX1286
Single-Supply Operation: +2.7V to +3.6V
DNL & INL: ±1LSB (max)
300ksps Sampling Rate
Low Conversion-Mode Supply Current:
0.95mA @ 300ksps
Low Supply Current in Shutdown: 0.2µA
Internal 10-MHzTrack-and-Hold
Internal ±0.6%, 30ppm/ºC +2.5V Reference
SPI/QSPI/MICROWIRE 3-Wire Serial-Interface
8-Pin, 3mm x 3mm TDFN-EP Package
Connecting
directly
to
any
SPI™/QSPI™/
MICROWIRE™ microcontrollers and other interface-
compatible computing devices, the TS7003’s 3-wire
serial interface is easy to use and doesn’t require
separate, external logic. An external serial-interface
clock controls the TS7003’s conversion process and
its output shift register operation.
APPLICATIONS
Process Control and Factory Automation
Data and Low-frequency Signal Acquisition
Portable Data Logging
In PCB-space-conscious, low-power remote-sensor
and data-acquisition applications, the TS7003 is an
excellent choice for its low-power, ease-of-use, and
small-package-footprint attributes.
Pen Digitizers & Tablet Computers
Medical Instrumentation
Battery-powered Instruments
As a pin-compatible and higher-speed upgrade to the
MAX1286, the TS7003 is fully specified over the -
40°C to +85°C temperature range and is available in
a low-profile, 8-pin 3x3mm TDFN package with an
exposed back-side paddle.
FUNCTIONAL BLOCK DIAGRAM
Page 1
© 2014 Silicon Laboratories, Inc. All rights reserved.
TS7003
ABSOLUTE MAXIMUM RATINGS
VDD to GND.................................................................... -0.3V to +6V
AIN to GND ...................................................... -0.3V to (VDD + 0.3V)
REF to GND..................................................... -0.3V to (VDD + 0.3V)
Digital Inputs to GND .................................................... -0.3V to +6V
DOUT to GND.................................................. -0.3V to (VDD + 0.3V)
DOUT Current........................................................................±25mA
Continuous Power Dissipation (TA = +70°C):
Operating Temperature Ranges:
TS7003I.............................................................. -40°C to +85°C
Storage Temperature Range.................................. -60°C to +150°C
Lead Temperature (Soldering, 10s).......................................+300°C
Soldering Temperature (Reflow) ...........................................+260°C
8-Pin TFDN33-EP (Derate 12.5mW/°C above +70°C) .1000mW
Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections
of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and
lifetime.
PACKAGE/ORDERING INFORMATION
PART
MARKING
ORDER NUMBER
TS7003ITD833
TS7003ITD833T
CARRIERQUANTITY
Tape
-----
& Reel
7003I
Tape
3000
& Reel
Lead-free Program: Silicon Labs supplies only lead-free packaging.
Consult Silicon Labs for products specified with wider operating temperature ranges.
Page 2
TS7003 Rev. 1.0
TS7003
ELECTRICAL SPECIFICATIONS
VDD = +2.7V to +3.6V; fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle, 300ksps; 4.7μF capacitor at
REF; TA = -40ºC to +85ºC, unless otherwise noted. Typical values apply at TA = +25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (See Note 1)
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
12
Bits
LSB
LSB
LSB
LSB
INL
DNL
ZE
See Note 2
No missing codes over temperature
±1.0
±1.0
±6.0
±6.0
Gain Error
GE
See Note 3
Gain-Error Temperature Coefficient
TCGE
±1.6
70
ppm/°C
DYNAMIC SPECIFICATIONS (fIN = 75kHz sine wave, 2.5VPP, fSAMPLE = 300ksps, fSCLK = 4.8MHz)
Signal-to-Noise
Plus Distortion Ratio
SINAD
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time
THD
SFDR
IMD
FPBW
FLBW
Including the 5th harmonic
-80
80
76
10
300
dB
dB
dB
MHz
kHz
fA = 73kHz, fB = 77kHz
-3dB point
SINAD > 68dB
tCONV
tACQ
tAD
See Note 4
3.3
μs
ns
ns
Track/Hold Acquisition Time
Aperture Delay
625
10
Aperture Jitter
tAJ
< 50
ps
Serial Clock Frequency
Duty Cycle
tSCLK
0.5
40
4.8
60
MHz
%
ANALOG INPUT (AIN)
Input Voltage Range
Input Capacitance
INTERNAL REFERENCE
REF Output Voltage
REF Short-Circuit Current
REF Output Tempco
Load Regulation
VIN
CINA
0
VREF
2.515
V
pF
10
VREF
2.485
2.50
15
30
3
V
mA
ppm/°C
mV/mA
μF
TA = +25°C
TCVREF
See Note 5; 0 to 0.75mA output load
5
10
Capacitive Bypass at REF
4.7
2.4
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage
VINH
VINL
VHYST
IIN
V
V
V
μA
pF
0.8
±1
0.2
15
VINL = 0V or VINH = VDD
Input Capacitance
CIND
DIGITAL OUTPUT (DOUT)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLY
VOL
VOH
IL
ISINK = 5mA
ISOURCE = 0.5mA
VCS = +3V
0.4
VDD - 0.5
V
V
μA
pF
±10
15
COUT
VCS = +3V
Positive Supply Voltage
Positive Supply Current
Shutdown Supply Current
Power-Supply Rejection
VDD
IDD
See Note 6
See Note 7; VDD = +3.6V
2.7
3.6
1.25
2
V
0.95
0.2
mA
μA
mV
ISHDN
PSR
SCLK = VDD, SHDN = GND
VDD = +2.7V to 3.6V, midscale input
±0.5
±2.5
TS7003 Rev. 1.0
Page 3
TS7003
TIMING SPECIFICATIONS
VDD = +2.7V to +3.6V, TA = -40ºC to +85ºC, unless otherwise noted.
PARAMETER
SCLK Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
SYMBOL
CONDITIONS
MIN
208
83
TYP
MAX
UNITS
ns
ns
tCP
tCH
tCL
83
ns
45
tCSS
ns
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall Ignore
0
tCSH
tCSO
ns
ns
45
45
13
tCS1
tDOH
tDOV
tDOD
ns
ns
ns
ns
CS Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to DOUT Valid
CLOAD = 20pF
CLOAD = 20pF
100
85
13
CLOAD = 20pF; Refer to Figure 2
CS Rise to DOUT Disable
CS Fall to DOUT Enable
CS Pulse-Width High
tDOE
tCSW
CLOAD = 20pF; Refer to Figure 1
85
ns
ns
100
Note 1: Tested at VDD = VDD(MIN)
.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been
calibrated.
Note 3: Internal reference, offset, and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA because of
production test limitations.
Note 6: Electrical characteristics are guaranteed from VDD(MIN) to VDD(MAX). For operations beyond this range, see Typical Operating
Characteristics.
Note 7: TS7003 tested with 20pF on DOUT and fSCLK = 4.8MHz, 0 to 3V. DOUT = full scale.
Page 4
TS7003 Rev. 1.0
TS7003
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = +3V; fSCLK = 4.8MHz; CLOAD = 20pF; 4.7μF capacitor at REF; TA = 25ºC, unless otherwise noted.
Integral Nonlinearity
Differential Nonlinearity
0.4
0.3
0.2
0.1
0
0.25
0.2
0.15
0.2
0.05
0
-0.05
-0.1
-0.1
-0.2
-0.3
-0.4
-0.15
-0.2
-0.25
0
1k
4k
5k
0
4k
5k
2k
3k
1k
2k
3k
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
Offset Error vs Supply Voltage
Offset Error vs Temperature
-0.2
-0.4
-0.6
-0.8
-1
1
0.5
0
-0.5
-1
-1.2
-1.4
-1.6
-1.8
-1.5
-2
2.7
2.88
3.06
3.24
3.42
3.6
-40
10
TEMPERATURE - ºC
85
-15
35
60
POWER SUPPLY VOLTAGE - Volt
Gain Error vs Temperature
Gain Error vs Supply Voltage
1.2
1
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.2
3.24
2.7
3.6
10
TEMPERATURE - ºC
85
2.88
3.06
3.42
-40
-15
35
60
POWER SUPPLY VOLTAGE - Volt
TS7003 Rev. 1.0
Page 5
TS7003
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = +3V; fSCLK = 4.8MHz; CLOAD = 20pF; 4.7μF capacitor at REF; TA = 25ºC, unless otherwise noted.
Internal Reference Output vs Supply Voltage
2.506
Internal Reference Output vs Temperature
2.510
2.504
2.502
2.5
2.508
2.506
2.504
2.502
2.5
2.498
2.496
2.494
2.498
2.7
2.88
3.06
3.24
3.42
3.6
-40
10
TEMPERATURE - ºC
85
-15
35
60
POWER SUPPLY VOLTAGE - Volt
Power Supply Current vs Power Supply Voltage
Power Supply Current vs Temperature
1
1
CONVERTING
0.9
CONVERTING, VDD = 3V
0.9
0.8
SCLK = 4.8MHz
0.8
CODE = 1111 1111 1111
RLOAD = ∞
C
LOAD = 10pF
0.7
0.6
0.5
0.7
0.6
0.5
STATIC
3.42
STATIC, VDD = 3V
2.7
2.88
3.06
3.24
3.6
-40
10
TEMPERATURE - ºC
85
-15
35
60
POWER SUPPLY VOLTAGE - Volt
Page 6
TS7003 Rev. 1.0
TS7003
PIN FUNCTIONS
PIN
1
2
NAME FUNCTION
VDD
AIN
Power Supply Voltage, +2.7V to +3.6V.
Analog Signal Input; Unipolar, 0 to VREF input range.
Active-Low Shutdown Input. Toggling SHDN high-to-low powers down the TS7003 and reduces
the supply current to 0.2μA (typ).
Analog and Digital Ground. Connect the TS7003’s GND pin at one and only one point to the
system analog ground plane.
Reference Voltage for Analog-to-Digital Conversion – an internal 2.5V reference output. Bypass
with a good-quality 4.7μF capacitor.
3
4
5
6
7
8
SHDN
GND
REF
Active-Low Chip Select. The CS signal initiates the conversion process on its falling edge. When
the CS input is logic high, DOUT is high impedance.
Serial-Data Output. DOUT toggles state on SCLK’s rising edge and is high impedance when CS
is logic high.
Serial-Clock Input. The SCLK signal controls the conversion process and transfers output data
at rates up to 4.8MHz.
CS
DOUT
SCLK
Figure 1: Output Loading Circuits for DOUT Enable Time (tDOE).
Figure 2: Output Loading Circuits for DOUT Disable Time (tDOD).
TS7003 Rev. 1.0
Page 7
TS7003
DESCRIPTION OF OPERATION
Converter Operation
Analog Input
The TS7003 uses an input track-and-hold (T/H) and a
successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 12-bit
output. No external-hold capacitor is needed for the
track/hold circuit. Figure 3 illustrates the TS7003 in its
simplest configuration. The TS7003 converts input
Figure 4 illustrates the sampling architecture of the
Figure 4: TS7003 Equivalent Input Circuit
Details.
analog-to-digital converter’s comparator. The full-
scale input voltage is set by the TS7003’s internal
2.5-V reference.
Figure 3: TS7003 Typical Application Circuit.
Track-and-Hold Operation
signals within the 0V to VREF range in 3.3μs including
the track-and-hold’s acquisition time. The serial
During track mode, the analog signal is acquired and
stored on the internal hold capacitor. During hold
mode, the track/hold switches SW1 and SW2 are
opened thereby maintaining a constant input level to
the converter’s SAR subcircuit.
interface requires only three digital lines (SCLK, CS,
and DOUT) and provides an easy interface to
microprocessors (μPs) and microcontrollers (μCs).
The TS7003 has two operating modes: normal and
During the acquisition phase with SW1 and SW2 on
TRACK, the input capacitor, CHOLD, is charged to the
shutdown. Toggling (or driving) the SHDN pin low
shuts down the ADCs and reduces supply current
below 1 μA when VDD ≤ 3.6V. Open-circuiting or
analog input (AIN). Toggling the CS pin low causes
the acquisition process to stop. At this instant,
track/hold switches SW1 and SW2 are moved to
HOLD position and the input side of CHOLD is then
switched to GND. Unbalancing Node ZERO at the
comparator’s input, the retained charge on CHOLD
represents a sample of the input signal applied to the
converter.
toggling (or driving) the SHDN pin high or places the
ADCs into operational mode. Toggling the CS pin to
logic low initiates a conversion where the conversion
result is available at DOUT in unipolar serial format.
The serial data stream consists of three leading zeros
followed by the data bits with the MSB first. All
transitions on the DOUT pin occur within 20ns after
the low-to-high transition of SCLK. Serial interface
timing details of the TS7003 are illustrated in Figures
8 and 9.
In hold mode and to restore Node ZERO to 0V within
the limits of the converter’s 12- bit resolution, the
output of the capacitive digital-to-analog converter
(the CDAC) is adjusted during the remainder of the
conversion cycle. In other words, the stored charge
on CHOLD is transferred to the binary-weighted CDAC
where it is converted into a digital representation of
the analog input signal. At end of the conversion
Page 8
TS7003 Rev. 1.0
TS7003
process, the input side of CHOLD is switched back to
AIN so as to be charged to the input signal again.
damage to the TS7003. However, for accurate
conversions near full scale, the input signal must not
exceed VDD by more than 50mV or be lower than
GND by 50mV.
An ADC’s acquisition time is function of how fast its
input capacitance can be charged. If an input signal’s
driving-point source impedance is high, the
acquisition time is lengthened and more time must be
allowed between conversions. The acquisition time
(tACQ) is the maximum time the ADC requires to
acquire the signal and is also the minimum time
needed for the signal to be acquired. The TS7003’s
acquisition time is calculated from the following
expression:
If the analog inputs can exceed 50mV beyond the
supplies, then the current in the forward-biased
protection diodes should be limited to less than
2mA since large fault currents can affect
conversion results.
Internal Reference Considerations
The TS7003 has an internal voltage reference that is
factory-trimmed to 2.5V. The internal reference output
is connected to the REF pin and is also connected to
the ADC’s internal CDAC. The REF output can be
used as a reference voltage source for other
components external to the ADC and can source up
to 750μA. To maintain conversion accuracy to within
1 LSB, a 4.7μF capacitor from the REF pin to GND is
recommended. While larger-valued capacitors can be
used to further reduce reference wide-band noise,
larger capacitor values can increase the TS7003’s
wake-up time when exiting from shutdown mode (see
tACQ = 9 x (RS + RIN) x 10pF
where RIN = 100Ω (the TS7003’s internal track/hold
switch resistance), RS = the input signal’s source
impedance, and tACQ is never less than 625ns.
Because of the input structure of the TS7003,
sources with output impedances of 1kΩ or less do not
affect significantly the AC performance of the
TS7003. The TS7003 can still be used in applications
where the source impedance is higher so long as a
0.01μF capacitor is connected between the analog
input and GND. Limiting the ADC’s input signal
bandwidth, the use of an external, input capacitor
forms an RC filter with the input’s source impedance.
the “Using SHDN to Reduce Operating Supply
Current” section for more information). When in
shutdown
(that
is,
when
SHDN = 0), the TS7003’s internal 2.5-V reference is
disabled.
Input Bandwidth Considerations
Serial Digital Interface
Since the TS7003’s input track-and-hold circuit
exhibits a 10 MHz small-signal bandwidth, it is
possible to measure periodic signals and to digitize
high-speed transient events with signal bandwidths
higher than the TS7003’s sampling rate by using
undersampling techniques. To avoid the aliasing of
high-frequency signals into the frequency band of
interest, the use of external anti-alias filter circuits
(discrete or integrated) is recommended. The time
constant of the external anti-alias filter should be set
so as not to interfere with the desired signal
bandwidth.
Initialization after Power-Up and Starting
Conversion
a
If the SHDN pin is not driven low upon an initial, cold-
start condition, it may take up to 2.5ms for a fully-
discharged 4.7μF reference bypass capacitor to
provide adequate charge for specified conversion
accuracy. As a result, conversions should not be
initiated during this reference capacitor charge-up
delay. To initiate a conversion, the CS pin is toggled
(or driven) low. At the CS’s falling edge, the TS7003’s
internal track-and-hold is placed in hold mode and a
conversion is initiated. Data can then be transferred
out of the ADC using an external serial clock.
Analog Input Protection
The TS7003 incorporates internal protection diodes
that clamp the analog input between VDD and GND.
These internal protection diodes allow the AIN pin to
swing from GND - 0.3V to VDD + 0.3V without causing
TS7003 Rev. 1.0
Page 9
TS7003
Using the ADC’s SHDN to Reduce Operating
Supply Current
A CS high-to-low transition initiates the conversion
sequence - the input track-and-hold samples the input
signal level, the ADC begins to convert, and the
DOUT pin changes state from high impedance to
logic low. The external SCLK signal is used to drive
the conversion process and is also used to transfer
the converted data out of the ADC as each bit of
conversion is determined.
Power consumption can be reduced significantly by
turning off the TS7003 in between conversions.
Figure 5: TS7003 Supply Current vs Conversion Rate
1k
VDD = 3V
DOUT = FS
RL = ∞
CL = 10pF
The SCLK signal transfers data after a low-to-high
transition of the third (3rd) SCLK pulse. After each
subsequent SCLK rising edge, transitions on the
DOUT pin occur in 20ns. The third rising clock edge
produces the MSB of the conversion at DOUT,
followed by the remaining bits. Since there are twelve
data bits and three leading zeros, at least fifteen
rising clock edges are needed to transfer the entire
data stream. Extra SCLK pulses occurring after the
conversion result has been completely transferred out
100
10
1
and, before to a new, low-to-high transition on CS,
produce a string trailing zeros at DOUT. In addition,
the extra SCLK pulses have no effect on converter
operation.
0.1
0.1
1
10
100
1k
CONVERSION RATE - ksps
Figure 5 illustrates the TS7003’s average supply
current versus conversion rate. The wake-up delay
Minimum conversion cycle time can be accomplished
by: (a) toggling the CS pin high after reading the
conversion result’s LSB; and (b), after the specified
minimum time defined by tCS has elapsed, toggling
time (tWAKE) is the time from when the SHDN pin is
deasserted to the time when a conversion may be
initiated (Refer to Figure 6). This delay time depends
on how long the ADC was in shutdown (Refer to
Figure 7) because the external 4.7μF reference
bypass capacitor is discharged slowly when
the CS pin low again to initiate the next conversion.
Output Data Coding and Transfer Function
SHDN = 0.
Conversion results at the TS7003’s DOUT pin are
straight binary data. Figure 10 illustrates the nominal
transfer function where code transitions occur halfway
between successive integer LSB values. If
VREF = +2.500V, then 1 LSB = 610μV or 2.500V/4096.
Timing and Control Details
The CS and SCLK digital inputs control the TS7003’s
conversion-start and data-read operations. The
ADC’s serial-interface operations are illustrated in
Figures 8 and 9.
Figure 6: TS7003 Shutdown Operation.
Page 10
TS7003 Rev. 1.0
TS7003
Figure 7: TS7003 Reference Power-Up Delay
APPLICATIONS INFORMATION
Connection to Industry-Standard Serial Interfaces
vs Duration in Shutdown Mode
2.5
The TS7003’s serial interface is fully compatible with
SPI/QSPI and MICROWIRE standard serial
interfaces (Refer to Figure 11). For serial interface
operation with these standards, the CPU’s serial
interface should be set to master mode so the CPU
then generates the serial clock. Second, the CPU’s
serial clock should be configured to operate up to
4.8MHz. The process to configure the serial clock and
data transfer operation is as follows:
CREF = 4.7µF
2
1.5
1
0.5
0
1) Using a general-purpose I/O line from the CPU, the
CS pin is driven low to start a conversion. DOUT
transitions from high impedance to logic low. The
SCLK polarity should be low to start the conversion
process correctly.
1m
TIME IN SHUTDOWN MODE - sec
1
0.1m
10m 100m
10
Figure 8: TS7003 Serial Interface Timing Sequence
Figure 9: TS7003 Serial Interface Timing Specifications in Detail.
2) Next, SCLK is activated for a minimum of 15 SCLK
cycles where the first two SCLKs produce zeros at
the DOUT pin. Data at DOUT is formatted MSB first
and DOUT transitions occur 20ns after the third (3rd)
SCLK low-to-high transition. Once the low-to-high
SCLK transition has occurred, data is valid at DOUT
TS7003 Rev. 1.0
Page 11
TS7003
4) Once the CS pin is held at logic high for at least
tCS, a new conversion cycle is started when the CS
pin is toggled low. If a conversion is aborted by
toggling the CS pin high before the current
conversion has completed, a new conversion cycle
can only be started after a the ADC has acquired the
signal (tACQ).
The CS pin must be held low and SCLK active until
all data bits are transferred out of the ADC. As shown
in Figure 8, data can be transferred in two 8-bit bytes
or continuously. The bytes contain the result of the
conversion padded with three leading 0s in the first 8-
bit byte and 1 trailing 0 in the second 8-bit byte.
Figure 10: ADC Unipolar Transfer Function
SPI and MICROWIRE Interface Details
for Straight Binary Digital Data.
When using an SPI or MICROWIRE interface, setting
[CPOL:CPHA] = [0:0] configures the microcontroller’s
serial clock and sampling edge for the TS7003. The
conversion commences on a high-to-low transition of
the CS pin. The DOUT pin transitions from a high-
impedance state to a logic low, indicating a
conversion is in progress. Two consecutive 1-byte
data reads are required to transfer the full 12-bit
result from the ADC. DOUT output data transitions
occur on the SCLK’s low-to-high transition and are
transferred into the downstream microcontroller on
the SCLK’s low-to-high transition.
The first byte contains three leading 0s and then five
bits of the conversion result. The second byte
contains the remaining seven bits of the conversion
result and one trailing zero. Refer to Figure 11 for the
circuit connections and to Figure 12 for all timing
details.
Figure 11: TS7003 Circuit Connections to
Industry-Standard Serial
QSPI Details
Using
a
QSPI
microcontroller,
setting
[CPOL:CPHA] = [0:1] configures the microcontroller’s
serial clock and sampling edge for the TS7003.
Unlike the SPI, which requires two 1-byte reads to
transfer all 12 bits of data from the ADC, the QSPI
allows a minimum number of clock cycles necessary
to transfer data from the ADC to the microcontroller.
Thus, the TS7003 requires 15 SCLK clock cycles
from the microcontroller to transfer the 12 bits of data
with no trailing zeros. As shown in Figure 13, the
conversion results contain two leading 0s followed by
the MSB-first-formatted, 12-bit data stream.
according to the tDOV (SCLK Rise to DOUT Valid)
timing specification. Valid output data can then be
transferred into µP or µCs on SCLK low-to-high
transitions.
3) At or after the 15th SCLK low-to-high transition, the
CS pin can be toggled high to halt the transfer
process. If the CS pin remains low and the SCLK is
still active, trailing zeros are transferred out after the
LSB.
Page 12
TS7003 Rev. 1.0
TS7003
Figure 12: SPI/MICROWIRE-TS7003 Serial Interface Timing Details with [CPOL:CPHA] = [0:0].
Figure 13: QSPI-TS7003 Serial Interface Timing Details with [CPOL:CPHA] = [0:1].
PCB Layout, Ground Plane Management, and
Capacitive Bypassing
(especially clock) lines are not routed parallel to one
another, and high-speed digital lines are not routed
underneath the ADC package.
For best performance, printed circuit boards should
always be used and wire-wrap boards are not
recommended. Good PC board layout techniques
ensure that digital and analog signal lines are kept
separate from each other, analog and digital
A
recommended system ground connection is
illustrated in Figure 14. A single-point analog ground
(star ground point) should be created at the ADC’s
GND and separate from the logic ground. All analog
grounds as well as the ADC’s GND pin should be
connected to the star ground. No other digital system
ground should be connected to this ground. For
lowest-noise operation, the ground return to the star
ground’s power supply should be low impedance and
as short as possible.
High-frequency noise on the VDD power supply may
affect the ADC’s high-speed comparator. Therefore, it
is necessary to bypass the VDD supply pin to the star
ground with 0.1μF and 1μF capacitors in parallel and
placed close to the ADC’s Pin 1. Component lead
lengths should be very short for optimal supply-noise
rejection. If the power supply is very noisy, an
optional 10-Ω resistor can be used in conjunction with
the bypass capacitors to form a low-pass filter as
shown in Figure 14.
Figure 14: Recommended Power Supply
Bypassing and Star Ground
Configuration.
TS7003 Rev. 1.0
Page 13
TS7003
PACKAGE OUTLINE DRAWING
8-Pin 3mm x 3mm TDFN-EP Package Outline Drawing
(N.B., Drawings are not to scale)
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