W219BHT [SILICON]
Processor Specific Clock Generator, 166MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | W219BHT |
| 厂家： | 
SILICON |
| 描述： | Processor Specific Clock Generator, 166MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
W219B
Frequency Generator for Integrated Core Logic
with 133-MHz FSB
Features
Table 1. Frequency Selections
FS4 FS3 FS2 FS1 FS0 CPU SDRAM 3V66 PCI APIC
SS
OFF
–0.6%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clock
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
75.3
95.0
113.0
95.0
75.3 37.6 18.8
63.3 31.6 15.8
86.0 43.0 21.5
75.3 37.6 18.8
75.0 37.5 18.7
73.0 36.6 18.3
70.0 35.0 17.5
72.0 36.0 18.0
68.3 34.1 17.0
70.0 35.0 17.5
69.0 34.5 17.0
70.0 35.0 17.5
129.0 129.0
150.0 113.0
150.0 150.0
110.0
110.0
• Nine copies of SDRAM clock
• Seven copies of PCI clock
140.0 140.0
144.0 108.0
• One copy of synchronous APIC clock
• Three copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of selectable 24- or 48-MHz clock
• One copy of double strength 14.31818-MHz reference
clock
68.3
102.5
105.0 105.0
138.0 138.0
140.0 105.0
66.8
100.2
66.8 33.4 16.7 ±0.45%
66.8 33.4 16.7 ±0.45%
66.8 33.4 16.7 ±0.45%
66.8 33.4 16.7 ±0.45%
100.2 100.2
133.6 133.6
133.6 100.2
157.3 118.0
160.0 120.0
146.6 110.0
• Power-down control
• SMBus interface for turning off unused clocks
78.6 39.3 19.6
80.0 40.0 20.0
73.3 36.6 18.3
61.0 30.5 15.2
84.6 42.3 21.1
81.3 40.6 20.3
78.0 39.0 19.5
76.0 38.0 19.0
80.0 40.0 20.0
78.0 39.0 19.5
83.0 41.5 20.7
89.0 44.5 22.2
66.6 33.3 16.6
66.6 33.3 16.6
66.6 33.3 16.6
66.6 33.3 16.6
OFF
OFF
Key Specifications
OFF
122.0
91.5
–0.6%
OFF
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
127.0 127.0
122.0 122.0
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
–0.6%
OFF
117.0
114.0
80.0
117.0
114.0
120.0
117.0
CPU, 3V66 Output Skew: ........................................... 175 ps
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps
PCI Output Skew: ....................................................... 500 ps
CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns
CPU to SDRAM Skew (@ 100 MHz)................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead).......................... 1.5 to 3.5 ns
PCI to APIC Skew..................................................... ± 0.5 ns
OFF
OFF
78.0
OFF
166.0 124.5
133.6 133.6
OFF
OFF
66.6
100.0
–0.6%
–0.6%
–0.6%
–0.6%
100.0 100.0
133.3 133.3
133.3 100.0
VDDQ3
Pin Configuration[1]
Block Diagram
REF2X/FS3*
X1
X2
XTAL
OSC
REF2x/FS3*
VDDQ3
X1
1
2
3
4
5
6
7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
APIC
VDDQ2
CPU0
CPU1
PLL REF FREQ
VDDQ2
CPU0:1
X2
GND
VDDQ3
3V66_0
3V66_1
3V66_2
GND
FS0*/PCI0
FS1*/PCI1
FS2*/PCI2
GND
PCI3
PCI4
VDDQ3
Divider,
Delay,
and
Phase
Control
Logic
2
GND
SDATA
SCLK
SMBus
Logic
VDDQ3
SDRAM0
SDRAM1
SDRAM2
GND
8
9
APIC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(FS0:4*)
VDDQ3
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
SDRAM8
GND
PWR_DWN#
SCLK
VDDQ3
GND
SDATA
3V66_0:2
2
PCI0/FS0*
PLL 1
PCI1/FS1*
PCI2/FS2*
PCI5
PCI6
GND
PCI3:6
5
9
^
SDRAM0:8
48MHz_0
PWR_DWN#
FS4*/48MHz_1
SI0/24_48#MHz*
VDDQ3
VDDQ3
48MHz_0
Note:
48MHz_1/FS4*
PLL2
1. Internal 250K pull-down or pull up resistors present on inputs
marked with * or ^ respectively. Design should not rely solely on
internal pull-up or pull down resistor to set I/O pins HIGH or LOW
respectively.
SI0/24_48#MHz*
/2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07220 Rev. *A
Revised December 21,2002
PRELIMINARY
W219B
I
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
REF2x/FS3
1
I/O
Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock out-
put. This pin also serves as the select strap to determine device operating frequency
as described in Table 1.
X1
3
4
I
I
Crystal Input: This pin has dual functions. It can be used as an external 14.318-
MHz crystal connection or as an external reference frequency input.
X2
Crystal Output: An input connection for an external 14.318-MHz crystal connec-
tion. If using an external reference, this pin must be left unconnected.
PCI0/FS0
11
I/O
PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI1/FS1
PCI2/FS2
12
13
I/O
I/O
PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI3:6
15, 16, 18, 19
7, 8, 9
O
O
PCI Clock 3 through 6: 3.3V 33-MHz PCI clock outputs. PCI0:6 can be individually
turned off via SMBus interface.
3V66_0:2
48MHz_0
66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled
by FS0:4 (see Table 1).
21
22
O
48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output.
48MHz_1/
FS4
I/O
48-MHz Clock Output/Frequency Selection 4: 3.3V fixed 48-MHz, non-spread
spectrum clock output. This pin also serves as the select strap to determine device
operating frequency as described in Table 1.
SIO/
24_48#MHz
23
I/O
Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device.
During power-up, it also serves as a selection strap. If it is sampled HIGH, the output
frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.
PWR_DWN#
CPU0:1
29
I
Power Down Control: LVTTL-compatible input that places the device in power-
down mode when held LOW.
45, 44
O
O
CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies
depending on the configuration of FS0:4. Voltage swing is set by VDDQ2.
SDRAM0:8
41, 40, 39, 37,
36, 35, 33, 32,
31
SDRAM Clock Outputs: 3.3V outputs for SDRAM. The operating frequency is
controlled by FS0:4 (see Table 1).
APIC
47
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs. Voltage swing set by VDDQ2.
SDATA
SCLK
25
28
I/O
I
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
VDDQ3
2, 6, 17, 24, 27,
34, 42
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buff-
ers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
VDDQ2
GND
46, 48
P
2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
5,10,14,20,26,
30, 38, 43,
G
Ground Connections: Connect all ground pins to the common system ground
plane.
Document #: 38-07220 Rev. *A
Page 2 of 15
PRELIMINARY
W219B
Output Strapping Resistor
Series Termination Resistor
Clock Load
W219B
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
10kΩ
Q
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Overview
The W219B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architec-
ture platform using graphics integrated core logic.
Functional Description
Offsets Among Clock Signal Groups
I/O Pin Operation
Figure 2 and Figure 3 represent the phase relationship among
the different groups of clock outputs from W219B when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
respectively. It should be noted that when CPU clock is oper-
ating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.
Pin # 1, 11, 12, 13, 22, and 23 are dual-purpose l/O pins. Upon
power-up the pin acts as a logic input. An external 10-kΩ strap-
ping resistor should be used. Figure 1 shows a suggested
method for strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
10 ns
20 ns
30 ns
40 ns
0 ns
CPU 66 Period
CPU 66-MHz
SDRAM 100 Period
SDRAM 100-MHz
Hub-PC
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
Figure 2. Group Offset Waveforms (66.8 CPU Clock, 100.2 SDRAM Clock)
Document #: 38-07220 Rev. *A
Page 3 of 15
PRELIMINARY
W219B
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100 Period
CPU 100-MHz
SDRAM 100 Period
SDRAM 100-MHz
3V66 66-MHz
Hub-PC
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
Figure 3. Group Offset Waveforms (100.2 CPU Clock, 100.2 SDRAM Clock)
Power-Down Control
W219B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0 ns
25 ns
50 ns
2
75 ns
Center
1
VCO Internal
CPU 100MHz
3V66 66MHz
APIC 33MHz
PCI 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 4. PWRDWN# Timing Diagram[2, 3, 4, 5]
Notes:
2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W219B.
4. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states.
5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Document #: 38-07220 Rev. *A
Page 4 of 15
PRELIMINARY
W219B
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 5.
The output clock is modulated with a waveform depicted in
Figure 6. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is ±0.45% or –0.6% of the se-
lected frequency. Figure 6 details the Cypress spreading pat-
tern. Cypress does offer options with more spread and greater
EMI reduction. Contact your local Sales representative for de-
tails on these devices.
As shown in Figure 5, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
SSFTG
EMI Reduction
Typical Clock
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Center Spread
Frequency Span (MHz)
Down Spread
Figure 5. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 6. Typical Modulation Profile
Document #: 38-07220 Rev. *A
Page 5 of 15
PRELIMINARY
W219B
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Byte Count = N
Ack
1 bit
Data Byte 1
8 bits
Ack
Data Byte 2
8 bits
Ack
1
...
Data Byte N
8 bits
Ack
1
Stop
1
1
Figure 7. An Example of a Block Write[6]
Serial Data Interface
transfer a maximum of 32 data bytes. The slave receiver ad-
dress for W219B is 11010010. Figure 7 shows an example of
a block write.
The W219B features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions.
The command code and the byte count bytes are required as
the first two bytes of any transfer. W219B expects a command
code of 0000 0000. The byte count byte is the number of ad-
ditional bytes required for the transfer, not counting the com-
mand code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement. Table 2 shows an
example of a possible byte count value.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not
allowed.
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller. The com-
mand code and byte count bytes are ignored by the W219B.
However, these bytes must be included in the data write se-
quence to maintain proper byte allocation.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the mes-
sage. If the host had 20 bytes to send, the first byte would be
the number 20 (14h), followed by the 20 bytes of data. The
byte count may not be 0. A block write command is allowed to
Table 2. Example of Possible Byte Count Value
Byte Count Byte
Notes
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0010
LSB
0000
0001
0010
0011
0100
0101
0110
0111
0000
Not allowed. Must have at least one byte.
Data for functional and frequency select register (currently byte 0 in spec)
Reads first two bytes of data. (byte 0 then byte1)
Reads first three bytes (byte 0, 1, 2 in order)
Reads first four bytes (byte 0, 1, 2, 3 in order)
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[7]
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[7]
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
Max. byte count supported = 32
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and sys-
tem power. Examples are clock outputs to unused
PCI slots.
(Reserved)
Reservedfunction for future device revision or pro- No user application. Register bit must be written as 0.
duction device testing.
Notes:
6. The acknowledgment bit is returned by the slave/receiver (W219B).
7. Bytes 6 and 7 are not defined for W219B.
Document #: 38-07220 Rev. *A
Page 6 of 15
PRELIMINARY
W219B
2. All unused register bits (reserved and N/A) should be writ-
ten to a “0” level.
Serial Configuration Map
1. The serial bits willbereadby theclock driver inthe following
order:
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current. The controller will read
back the written value.
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register (1 = Enable, 0 = Disable)[8]
Bit
Pin#
Name
Reserved
Default
Pin Function
Pin Description
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
0
0
0
0
0
1
1
0
Reserved
-
Reserved
Reserved
Reserved
Reserved
24/48 MHz
48 MHz
Reserved
-
Reserved
-
Reserved
-
23
Reserved
(Active/Inactive)
(Active/Inactive)
Reserved
21, 22
-
Reserved
Byte 1: Control Register (1 = Enable, 0 = Disable)[8]
Bit
Pin#
32
33
35
36
37
39
40
41
Name
SDRAM7
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 2: Control Register (1 = Enable, 0 = Disable)[8]
Bit
Pin#
--
Name
Reserved
PCI6
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
1
1
1
1
1
1
1
Reserved
19
18
16
15
13
12
11
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
PCI5
PCI4
PCI3
PCI2
PCI1
Bit 0
PCI0
Note:
8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
Document #: 38-07220 Rev. *A
Page 7 of 15
PRELIMINARY
W219B
Byte 3: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
SDRAM8
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
31
-
1
0
0
0
1
0
1
0
(Active/Inactive)
Reserved
Reserved
Reserved
Reserved
APIC
-
Reserved
-
Reserved
47
-
(Active/Inactive)
Reserved
Reserved
Reserved
Reserved
-
Reserved
-
Reserved
Byte 4: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
-
-
-
-
-
SEL3
SEL2
SEL1
SEL0
0
0
0
0
0
See Table 4
See Table 4
See Table 4
See Table 4
FS(0:4) Override
0 = Select operating frequency by FS(0:4) strapping
1 = Select operating frequency by SEL(0:4) bit settings
Bit 2
Bit 1
Bit 0
-
-
-
SEL4
0
0
0
See Table 4
Reserved
Test Mode
Reserved
0 = All output enable
1 = All output three-stated
Byte 5: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Reserved
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 6: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Document #: 38-07220 Rev. *A
Page 8 of 15
PRELIMINARY
W219B
Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Data Byte 4, Bit 3 = 1
Bit 2
Bit 7
Bit 6
Bit 5
Bit 4
Spread
SEL_4
SEL_3
SEL_2
SEL_1
SEL_0
CPU
75.3
SDRAM
113.0
95.0
3V66
75.3
63.3
86.0
75.3
75.0
73.0
70.0
72.0
68.3
70.0
69.0
70.0
66.8
66.8
66.8
66.8
78.6
80.0
73.3
61.0
84.6
81.3
78.0
76.0
80.0
78.0
83.0
89.0
66.6
66.6
66.6
66.6
PCI
37.6
31.6
43.0
37.6
37.5
36.6
35.0
36.0
34.1
35.0
34.5
35.0
33.4
33.4
33.4
33.4
39.3
40.0
36.6
30.5
42.3
40.6
39.0
38.0
40.0
39.0
41.5
44.5
33.3
33.3
33.3
33.3
APIC
18.8
15.8
21.5
18.8
18.7
18.3
17.5
18.0
17.0
17.5
17.0
17.5
16.7
16.7
16.7
16.7
19.6
20.0
18.3
15.2
21.1
20.3
19.5
19.0
20.0
19.5
20.7
22.2
16.6
16.6
16.6
16.6
Spectrum
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF
–0.6%
OFF
95.0
129.0
150.0
150.0
110.0
140.0
144.0
68.3
129.0
113.0
150.0
110.0
140.0
108.0
102.5
105.0
138.0
105.0
100.2
100.2
133.6
100.2
118.0
120.0
110.0
91.5
OFF
OFF
OFF
OFF
OFF
OFF
105.0
138.0
140.0
66.8
OFF
OFF
OFF
±0.45%
±0.45%
±0.45%
±0.45%
OFF
100.2
133.6
133.6
157.3
160.0
146.6
122.0
127.0
122.0
117.0
114.0
80.0
OFF
OFF
–0.6%
OFF
127.0
122.0
117.0
114.0
120.0
117.0
124.5
133.6
100.0
100.0
133.3
100.0
–0.6%
OFF
OFF
OFF
78.0
OFF
166.0
133.6
66.6
OFF
OFF
–0.6%
–0.6%
–0.6%
–0.6%
100.0
133.3
133.3
Document #: 38-07220 Rev. *A
Page 9 of 15
PRELIMINARY
W219B
DC Electrical Characteristics[9]
DC parameters must be sustainable under steady state (DC) conditions.
Absolute Maximum DC Power Supply
Parameter
VDDQ3
VDDQ2
TS
Description
3.3V Core Supply Voltage
Min.
–0.5
–0.5
–65
Max.
4.6
Unit
V
2.5V I/O Supply Voltage
Storage Temperature
3.6
V
150
°C
Absolute Maximum DC I/O
Parameter
Description
Min.
–0.5
–0.5
2000
Max.
4.6
Unit
V
Vi/o3
3.3V Core Supply Voltage
2.5V I/O Supply Voltage
Input ESD Protection
Vi/o3
3.6
V
ESD prot.
V
DC Operating Requirements
Parameter
Description
Condition
3.3V±5%
3.3V±5%
2.5V±5%
Min.
Max.
Unit
V
VDD3
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
2.5V I/O Supply Voltage
3.135
3.135
2.375
3.465
3.465
2.625
VDDQ3
V
VDDQ2
V
VDD3 = 3.3V±5%
Vih3
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current[10]
VDD3
2.0
GND – 0.3
–5
VDD + 0.3
0.8
V
V
Vil3
Iil
0<Vin<VDDQ3
+5
µA
VDDQ2 = 2.5V±5%
Voh2
2.5V Output High Voltage
2.5V Output Low Voltage
Ioh=(–1 mA)
2.0
2.4
2.4
V
V
Vol2
Iol=(1 mA)
0.4
0.4
VDDQ3 = 3.3V±5%
Voh3
3.3V Output High Voltage
3.3V Output Low Voltage
Ioh=(–1 mA)
V
V
Vol3
Iol=(1 mA)
VDDQ3 = 3.3V±5%
Vpoh3
PCI Bus Output High Voltage
PCI Bus Output Low Voltage
Ioh=(–1 mA)
V
V
Vpol3
Iol=(1 mA)
0.55
Cin
Input Pin Capacitance
Xtal Pin Capacitance
Output Pin Capacitance
Pin Inductance
5
22.5
6
pF
pF
pF
nH
°C
Cxtal
Cout
Lpin
13.5
0
0
7
Ta
Ambient Temperature
No Airflow
70
Note:
9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
10. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
Document #: 38-07220 Rev. *A
Page 10 of 15
PRELIMINARY
W219B
AC Electrical Characteristics[9]
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%
fXTL = 14.31818 MHz
66.6-MHz Host
100-MHz Host
133-MHz Host
Parameter
TPeriod
THIGH
Description
Host/CPUCLK Period
Min.
15.0
5.2
Max.
15.5
N/A
N/A
1.6
Min.
10.0
3.0
Max.
10.5
N/A
N/A
1.6
Min.
7.5
Max.
8.0
Unit
ns
Notes
11
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
1.87
1.67
0.4
N/A
N/A
1.6
ns
14
TLOW
5.0
2.8
ns
TRISE
0.4
0.4
ns
15
15
TFALL
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
THIGH
TLOW
TRISE
TFALL
SDRAM CLK Period
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
ns
ns
ns
ns
ns
11
14
SDRAM CLK High Time
SDRAM CLK Low Time
SDRAM CLK Rise Time
SDRAM CLK Fall Time
15
15
1.6
1.6
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
APIC CLK Period
60.0
25.5
25.3
0.4
64.0
N/A
N/A
1.6
60.0
25.5
25.30
0.4
N/A
N/A
N/A
1.6
60.0
25.5
25.30
0.4
64.0
N/A
N/A
1.6
ns
ns
ns
ns
ns
11
14
APIC CLK High Time
APIC CLK Low Time
APIC CLK Rise Time
APIC CLK Fall Time
15
15
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
3V66 CLK Period
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
ns
ns
ns
ns
ns
11, 13
14
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
15
15
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
PCI CLK Period
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
ns
ns
ns
ns
ns
11, 12
14
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
15
15
0.5
2.0
0.5
2.0
0.5
2.0
tpZL, tpZH
tpLZ, tpZH
Output Enable Delay (All outputs)
30.0
12.0
N/A
N/A
30.0
12.0
N/A
N/A
30.0
12.0
N/A
N/A
ns
ns
Output Disable Delay
(All outputs)
15
15
tstable
All Clock Stabilization from
Power-Up
12.0
N/A
12.0
N/A
12.0
N/A
ms
Notes:
11. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
12.
13.
T
T
HIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
LOW is measured at 0.4V for all outputs.
14. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and
operating within specification.
15.
TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification for 2.5V outputs, and Vol
=
0.4V and Voh = 2.4V for 3.3V.
Document #: 38-07220 Rev. *A
Page 11 of 15
PRELIMINARY
W219B
Group Skew and Jitter Limits
Output Group
Skew, Jitter
Pin-Pin Skew Max.
Cycle-Cycle Jitter
250 ps
Duty Cycle
45/55
Nom Vdd
2.5V
Measure Point
1.25V
1.5V
CPU
SDRAM
APIC
48MHz
3V66
175 ps
250 ps
250 ps
250 ps
175 ps
500 ps
N/A
250 ps
45/55
3.3V
500 ps
45/55
2.5V
1.25V
1.5V
500 ps
45/55
3.3V
500 ps
45/55
3.3V
1.5V
PCI
500 ps
45/55
3.3V
1.5V
REF
1000 ps
45/55
3.3V
1.5V
Test Point
Output
Buffer
Test Load
Clock Output Wave
TPERIOD
Duty Cycle
THIGH
2.0
1.25
2.5V Clocking
Interface
0.4
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
1.5
0.4
3.3V Clocking
Interface
TLOW
TRISE
TFALL
Figure 8. Output Buffer
Ordering Information
Ordering Code
Package Name
Package Type
48-pin SSOP (300 mils)
W219B
H
Intel is a registered trademark of Intel Corporation.
Document #: 38-07220 Rev. *A
Page 12 of 15
PRELIMINARY
W219B
Layout Example
+2.5V Supply
FB
+3.3V Supply
FB
VDDQ2
VDDQ3
0.005 µF
G
10 µF
10 µF
C4 0.005
G
µ
F
C1
C2
C3
G
G
G
V
G
G
1
2
3
4
48
G
G
V
G
47
46
45
G
V
G
G
G
G
V
5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
6
G
G
V
7
G
G
8
G
G
9
10
11
12
G
13
14
15
16
17
18
19
20
G
G
G
V
G
G
G
V
G
G
G
21
22
23
24
G 28
VDDQ3
(Core)
V
G
27
3.3V
G
26
5Ω
G
G
25
0.1µF
20µF
C5
C6
G
G
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB2012L-120
µF C6 = 0.1 µF
µF C2 & C4 = 0.005
Ceramic Caps C1 & C3, C5 = 10 – 22
= VIA to GND plane layer V =VIA to respective supply plane trace
G
Note: Each supply plane or strip should have a ferrite bead and capacitors
All VDD by pass capacitors = 0.1 µF
Document #: 38-07220 Rev. *A
Page 13 of 15
PRELIMINARY
W219B
Package Diagram
48-Pin Shrink Small Outline Package (SSOP, 300 mils)
Document #: 38-07220 Rev. *A
Page 14 of 15
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
W219B
Document Title: W219B Frequency Generator for Integrated Core Logic with 133-MHz FSB
Document Number: 38-07220
Issue
Orig. of
Change
REV.
**
*A
ECN NO. Date
Description of Change
110485
122837
10/21/01
12/21/02
SZV
RBI
Change from Spec number: 38-00884 to 38-07220
Add Power up Requirements to Electrical Characteristics Information
Document #: 38-07220 Rev. *A
Page 15 of 15
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