SMD5962-9459901MXX [SIMTEK]
Non-Volatile SRAM, 8KX8, 55ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28;
| 型号： | SMD5962-9459901MXX |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | Non-Volatile SRAM, 8KX8, 55ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28 CD 静态存储器 |
| 文件： | 总21页 (文件大小：834K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK12C68, STK12C68-5 (SMD5962-94599)
8Kx8 AutoStore nvSRAM
DESCRIPTION
FEATURES
• 25, 35, 45, 55 ns Read Access & Write Cycle Time The Simtek STK12C68 is a 64Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
• Non-Volatile STORE Under Hardware or Software
Control
• Automatic RECALL to SRAM on Power Up
Data transfers automatically to the non-volatile stor-
• Unlimited RECALL Cycles
age cells when power loss is detected (the STORE
operation). On power up, data is automatically
restored to the SRAM (the RECALL operation). Both
STORE and RECALL operations are also available
under software control.
• 1 Million STORE Cycles
• 100-Year Non-volatile Data Retention
• Single 5V ± 10% Power Supply
• Commercial, Industrial, Military Temperatures
The Simtek nvSRAM is the first monolithic non-vola-
tile memory to offer unlimited writes and reads. It is
the highest performance, most reliable non-volatile
memory available.
• 28-pin 330-mil SOIC, 300-mil PDIP, and 600-mil
PDIP Packages (RoHS-Compliant)
• 28-Pin CDIP and LCC Military Packages
Block Diagram
VCAP
Vcc
POWER
CONTROL
QUANTUM TRAP
128 x 512
STORE
RECALL
A5
A6
A7
A8
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
128 X 512
A9
A11
A12
SOFTWARE
DETECT
A0 – A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
Rev 2.0
Document Control #ML0008
June, 2008
1
STK12C68, STK12C68-5 (SMD5962-94599)
Packages
V C
A P
1
V C
W
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
C
A 1 2
A 7
2
3
A6
A5
H S B
A 8
HSB
A8
A 6
A 5
A 4
A 3
4
5
A 9
A 1 1
A4
A9
6
A11
A3
A2
7
(T O P )
G
A 1 0
(TOP)
A 2
G
8
A 1
A 0
E
A1
A10
9
D Q
1 0
1 1
1 2
1 3
1 4
7
A0
DQ0
DQ1
E
D Q
0
D Q
D Q
D Q
D Q
6
DQ7
D Q
D Q
1
2
5
4
3
DQ6
V S S
28-pin SOIC
28-pin DIP
28-pin LCC
Pin Descriptions
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
12
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
Power Supply
I/O
Power: 5.0V, +10%
CC
HSB
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
V
V
Power Supply
Power Supply
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
CAP
SS
Ground
Rev 2.0
Document Control #ML0008
June, 2008
2
STK12C68, STK12C68-5 (SMD5962-94599)
ABSOLUTE MAXIMUM RATINGSa
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (V + 0.5V)
CC
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . . –0.5V to (V + 0.5V)
CC
Temperature under Bias . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . .15mA
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Package Thermal Characteristics - See Website at http://www.simtek.com
DC CHARACTERISTICS
(VCC = 5.0V ± 10%)e
INDUSTRIAL
MILITARY
COMMERCIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V Current
85
75
65
--
85
75
65
55
mA
mA
mA
mA
t
t
t
t
= 25ns (commercial and industrial only)
= 35ns
= 45ns (commercial and industrial only)
= 55ns
CC
1
CC
AVAV
AVAV
AVAV
AVAV
c
I
I
Average V Current during STORE
3
3
mA
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
b
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
AVAV
CC
3
10
10
5V, 25°C, Typical
All Others Cycling, CMOS Levels
c
I
I
Average V
Cycle
Current during AutoStore
CAP
All Inputs Don’t Care
CC
4
2
2
mA
d
Average V Current
CC
(Standby, Cycling TTL Input Levels)
27
24
20
--
27
24
20
19
mA
mA
mA
mA
t
t
t
t
= 25ns, E ≥ V (commercial and industrial only)
SB
1
AVAV
AVAV
AVAV
AVAV
IH
= 35ns, E ≥ V
IH
= 45ns, E ≥ V (commercial and industrial only)
IH
= 55ns, E ≥ V
IH
d
I
I
I
V
Standby Current
E ≥ (V – 0.2V)
SB
CC
CC
2
1.5
±1
±5
2.5
±1
±5
mA
μA
μA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN
CC
Input Leakage Current
V
V
= max
CC
ILK
= V to V
CC
IN
SS
Off-State Output Leakage Current
V
V
= max
CC
OLK
= V to V , E or G ≥ V
IH
IN
SS
CC
V
V
V
V
V
T
Input Logic “1” Voltage
2.2
V
+ .5
2.2
V + .5
CC
V
V
All Inputs
All Inputs
IH
CC
Input Logic “0” Voltage
V
– .5
0.8
V – .5
SS
0.8
IL
SS
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
2.4
2.4
V
I
I
I
=–4mA except HSB
= 8mA except HSB
= 3mA
OH
OL
BL
OUT
OUT
OUT
0.4
0.4
70
0.4
0.4
V
V
0
–40/-55
85/125
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ).
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Note e: VCC reference levels throughout this datasheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground.
5.0V
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
480 Ohms
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
OUTPUT
30 pF
255 Ohms
CAPACITANCEf
(TA = 25°C, f = 1.0MHz)
INCLUDING
SCOPE AND
FIXTURE
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
ΔV = 0 to 3V
ΔV = 0 to 3V
C
Input Capacitance
Output Capacitance
8
7
pF
IN
C
pF
OUT
Figure 1. AC Output Loading
Note f: These parameters are guaranteed but not tested.
Rev 2.0
Document Control #ML0008
June, 2008
3
STK12C68, STK12C68-5 (SMD5962-94599)
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)e
STK12C68,
STK12C68,
STK12C68,
STK12C68,
SYMBOLS
#1, #2
STK12C68-5-25 STK12C68-5-35 STK12C68-5-45 STK12C68-5-55
NO.
PARAMETER
UNITS
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
35
45
55
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
g
t
, ELEH
25
35
45
55
AVAV
h
Address Access Time
25
10
35
15
45
20
55
35
AVQV
Output Enable to Data Valid
Output Hold after Address Change
GLQV
AXQX
ELQX
OE
OH
LZ
h
5
5
5
5
5
5
5
5
Address Change or Chip Enable to
Output Active
ns
ns
7
Address Change or
Chip Disable to Output Inactive
i
t
t
10
10
12
12
EHQZ
GLQX
HZ
8
9
t
t
t
t
t
t
t
t
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
0
0
0
0
0
0
0
ns
ns
ns
ns
OLZ
OHZ
PA
i
10
25
10
35
12
45
12
55
GHQZ
f
f
10
11
ELICCH
EHICCL
PS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
,
h
SRAM READ CYCLE #1: Address Controlledg
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E and G Controlledg
2
t
AVAV
ADDRESS
1
11
EHICCL
t
ELQV
t
6
E
t
ELQX
7
27
t
EHQZ
t
AVEL
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
Rev 2.0
Document Control #ML0008
June, 2008
4
STK12C68, STK12C68-5 (SMD5962-94599)
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)e
STK12C68,
STK12C68,
STK12C68,
STK12C68,
SYMBOLS
STK12C68-5-25 STK12C68-5-35 STK12C68-5-45 STK12C68-5-55
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
MIN
55
45
45
25
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
AW
t
t
t
20
0
25
0
30
0
45
0
AVWH
AVEH
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
0
WHAX
i, j
EHAX
WR
t
t
10
13
14
15
WLQZ
WZ
t
t
5
5
5
5
WHQX
OW
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
W
t
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledk, l
12
t
AVAV
ADDRESS
E
14
ELEH
18
AVEL
19
EHAX
t
t
t
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Rev 2.0
Document Control #ML0008
June, 2008
5
STK12C68, STK12C68-5 (SMD5962-94599)
HARDWARE MODE SELECTION
E
H
L
W
X
H
L
HSB
A
- A (hex)
0
MODE
Not Selected
I/O
POWER
Standby
Active
Active
l
NOTES
12
H
X
X
X
X
Output High Z
Output Data
Input Data
H
Read SRAM
o
L
H
Write SRAM
X
X
L
Nonvolatile STORE
Output High Z
m
CC
2
0000
1555
0AAA
1FFF
10F0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
L
L
H
H
H
H
Active
n, o
0F0F
Nonvolatile STORE
Output High Z
l
CC2
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output DataOutput
Data
Output Data
Output Data
Output Data
Output High Z
Active
n, o
Nonvolatile RECALL
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the
part will go into standby mode, inhibiting all operations until HSB rises.
Note n: The six consecutive addresses must be in the order listed. W must be high during all six consecutive E controlled cycles to enable a nonvolatile
cycle.
Note o: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE STORE CYCLE
(VCC = 5.0V ± 10%)e
STK12C68,
STK12C68-5
SYMBOLS
NO.
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
1
MAX
22
23
24
25
26
t
t
t
t
t
t
t
t
STORE Cycle Duration
10
ms
μs
ns
ns
ns
i, p
i, q
p, r
STORE
DELAY
RECOVER
HLHX
HLHZ
HLQZ
HHQX
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
700
300
15
Hardware STORE Low to Store Busy
HLBL
Note p: E and G low for output behavior.
Note q: E and G low and W high for output behavior.
Note r: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25
HLHX
t
HSB (IN)
24
RECOVER
t
22
STORE
t
26
HLBL
t
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
23
DELAY
t
DQ (DATA OUT)
DATA VALID
Rev 2.0
Document Control #ML0008
June, 2008
6
STK12C68, STK12C68-5 (SMD5962-94599)
AutoStore™/POWER-UP RECALL
(VCC = 5.0V ± 10%)e
STK12C68,
STK12C68-5
SYMBOLS
NO.
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
MAX
550
10
27
28
29
30
31
32
t
Power-up RECALL Duration
STORE Cycle Duration
μs
ms
ns
μs
V
s
RESTORE
t
t
t
t
t
p, q, t
STORE
VSBL
HLHZ
BLQZ
Low Voltage Trigger (V
) to HSB Low
300
l
SWITCH
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
1
p
DELAY
V
V
4.0
4.5
3.9
SWITCH
RESET
Low Voltage Reset Level
V
Note s: tRESTORE starts from the time VCC rises above VSWITCH
.
Note t: HSB is asserted low for 1μs when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
will be released and no STORE will take place.
AutoStore™/POWER-UP RECALL
V
CC
31
SWITCH
V
32
RESET
V
TM
AutoStore
POWER-UP RECALL
29
VSBL
28
STORE
27
RESTORE
t
t
t
HSB
30
DELAY
t
W
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
NO STORE
BROWN OUT
AutoStore
BROWN OUT
AutoStore
(NO SRAM WRITES)
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
Rev 2.0
Document Control #ML0008
June, 2008
7
STK12C68, STK12C68-5 (SMD5962-94599)
SOFTWARE-CONTROLLED STORE/RECALL CYCLEv
(VCC = 5.0V ± 10%)e
STK12C68,
STK12C68-5-25 STK12C68-5-35 STK12C68-5-45 STK12C68-5-55
UNITS NOTES
STK12C68,
STK12C68,
STK12C68,
SYMBOLS
NO.
PARAMETER
Standard Alternate
MIN
25
0
MAX
MIN
35
0
MAX
MIN
45
0
MAX
MIN
55
0
MAX
33
34
35
36
37
t
t
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
ns
ns
ns
ns
μs
p
u
u
u
AVAV
RC
AS
AVEL
20
20
25
20
30
20
30
20
ELEH
ELAX
RECALL
CW
Address Hold Time
RECALL Duration
20
20
20
20
Note u: The software sequence is clocked on the falling edge of E without involving G (double clocking will abort the sequence). See application note:
MA0002 http://www.simtek.com/attachments/AppNote02.pdf.
Note v: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0000, 1555, 0AAA, 1FFF,
10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledv
33
AVAV
33
t
AVAV
t
ADDRESS #1
ADDRESS #6
ADDRESS
34
AVEL
35
t
ELEH
t
E
36
ELAX
t
28
37
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA OUT)
Rev 2.0
Document Control #ML0008
June, 2008
8
STK12C68, STK12C68-5 (SMD5962-94599)
DEVICE OPERATION
The STK12C68, STK12C68-5 has two separate
POWER-UP RECALL
modes of operation: SRAM mode and nonvolatile
mode. In SRAM mode, the memory operates as a
standard fast static RAM. In nonvolatile mode, data
is transferred from SRAM to Nonvolatile Elements
(the STORE operation) or from Nonvolatile Elements
to SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
During power up, or after any low-power condition
(VCAP < VRESET), an internal RECALL request will be
latched. When VCAP once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK12C68, STK12C68-5 is in a WRITE state at
the end of power-up RECALL, the SRAM data will be
corrupted. To help avoid this situation, a 10K Ohm
resistor should be connected either between W and
system VCC or between E and system VCC.
NOISE CONSIDERATIONS
The STK12C68, STK12C68-5 is a high-speed mem-
ory and so must have a high-frequency bypass
capacitor of approximately 0.1μF connected
between VCAP and VSS, using leads and traces that
are as short as possible. As with all high-speed
CMOS ICs, normal careful routing of power, ground
and signals will help prevent noise problems.
SOFTWARE NONVOLATILE STORE
The STK12C68, STK12C68-5 software STORE cycle
is initiated by executing sequential E controlled
READ cycles from six specific address locations.
During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a pro-
gram of the nonvolatile elements. The program
operation copies the SRAM data into nonvolatile
memory. Once a STORE cycle is initiated, further
input and output are disabled until the cycle is com-
pleted.
SRAM READ
The STK12C68, STK12C68-5 performs a READ
cycle whenever E and G are low and W and HSB
are high. The address specified on pins A0-12 deter-
mines which of the 8,192 data bytes will be
accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of
tAVQV (READ cycle #1). If the READ is initiated by E or
G, the outputs will be valid at tELQV or at tGLQV, which-
ever is later (READ cycle #2). The data outputs will
repeatedly respond to address changes within the
tAVQV access time without the need for transitions on
any control input pins, and will remain valid until
another address change or until E or G is brought
high, or W or HSB is brought low.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important
that no other READ or WRITE accesses intervene in
the sequence, or the sequence will be aborted and
no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
Rev 2.0
Document Control #ML0008
June, 2008
9
STK12C68, STK12C68-5 (SMD5962-94599)
VCAP (Figure 3). This is the AutoStore Inhibit mode, in
SOFTWARE NONVOLATILE RECALL
which the AutoStore function is disabled. If the
STK12C68, STK12C68-5 is operated in this configu-
ration, references to VCC should be changed to VCAP
throughout this data sheet. In this mode, STORE
operations may be triggered through software con-
trol or the HSB pin. To enable or disable AutoStore
using an IO port pin, see “PREVENTING STORES”
on page 11.
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of E controlled READ opera-
tions must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
In order to prevent unneeded STORE operations,
automatic STOREs as well as those initiated by
externally driving HSB low will be ignored unless at
least one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software initi-
ated STORE cycles are performed regardless of
whether a WRITE operation has taken place. An
optional pull-up resistor is shown connected to HSB.
This can be used to signal the system that the
AutoStore cycle is in progress.
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. After
the tRECALL cycle time the SRAM will once again be
ready for READ and WRITE operations. The RECALL
operation in no way alters the data in the Nonvolatile
Elements. The nonvolatile data can be recalled an
unlimited number of times.
If the power supply drops faster than 20 μs/volt
before VCC reaches VSWITCH, then a 2.2 ohm resistor
should be inserted between VCC and the system sup-
ply to avoid momentary excess of current between
AutoStore MODE
The STK12C68, STK12C68-5 can be powered in
one of three modes.
Vcc and Vcap
.
During normal AutoStore operation, the STK12C68,
STK12C68-5 will draw current from VCC to charge a
capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single
STORE operation. After power up, when the voltage
on the VCAP pin drops below VSWITCH, the part will
automatically disconnect the VCAP pin from VCC and
initiate a STORE operation.
1
28
27
26
+
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68μF and
220μF (± 20%) rated at 6V should be provided.
14
15
Figure 2: AutoStore Mode
*If HSB is not used, it should be left unconnected.
In system power mode, both VCC and VCAP are con-
nected to the + 5V power supply without the 68μF
capacitor. In this mode the AutoStore function of the
STK12C68, STK12C68-5 will operate on the stored
system charge as power goes down. The user must,
however, guarantee that VCC does not drop below
3.6V during the 10ms STORE cycle.
1
28
27
26
AutoStore INHIBIT MODE
14
15
If an automatic STORE on power loss is not required,
then VCC can be tied to ground and + 5V applied to
Figure 3: AutoStore Inhibit Mode
Rev 2.0
Document Control #ML0008
June, 2008
10
STK12C68, STK12C68-5 (SMD5962-94599)
If HSB is not used, it should be left unconnected.
HSB OPERATION
The STK12C68, STK12C68-5 provides the HSB pin
for controlling and acknowledging the STORE opera-
tions. The HSB pin is used to request a hardware
STORE cycle. When the HSB pin is driven low, the
STK12C68, STK12C68-5 will conditionally initiate a
STORE operation after tDELAY; an actual STORE cycle
will only begin if a WRITE to the SRAM took place
since the last STORE or RECALL cycle. The HSB pin
has a very resistive pullup and is internally driven
low to indicate a busy condition while the STORE
(initiated by any means) is in progress.
PREVENTING STORES
The STORE function can be disabled on the fly by
holding HSB high with a driver capable of sourcing
30mA at a VOH of at least 2.2V, as it will have to
overpower the internal pull-down device that drives
HSB low for 20μs at the onset of a STORE. When
the STK12C68, STK12C68-5 is connected for
AutoStore operation (system VCC connected to VCC
and a 68μF capacitor on VCAP) and VCC crosses
VSWITCH on the way down, the STK12C68,
STK12C68-5 will attempt to pull HSB low; if HSB
doesn’t actually get below VIL, the part will stop try-
ing to pull HSB low and abort the STORE attempt.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK12C68,
STK12C68-5 will continue SRAM operations for tDE-
HARDWARE PROTECT
The STK12C68, STK12C68-5 offers hardware pro-
tection against inadvertent STORE operation and
SRAM WRITEs during low-voltage conditions. When
VCAP < VSWITCH, all externally initiated STORE opera-
tions and SRAM WRITEs are inhibited.
. During tDELAY, multiple SRAM READ operations
LAY
may take place. If a WRITE is in progress when HSB
is pulled low it will be allowed a time, tDELAY, to com-
plete. However, any SRAM WRITE cycles requested
after HSB goes low will be inhibited until HSB
returns high.
AutoStore can be completely disabled by tying VCC
to ground and applying + 5V to VCAP. This is the
AutoStore Inhibit mode; in this mode, STOREs are
only initiated by explicit request using either the soft-
ware sequence or the HSB pin.
The HSB pin can be used to synchronize multiple
STK12C68, STK12C68-5s while using a single
larger capacitor. To operate in this mode the HSB
pin should be connected together to the HSB pins
from the other STK12C68, STK12C68-5s. An exter-
nal pull-up resistor to + 5V is required since HSB
acts as an open drain pull down. The VCAP pins from
the other STK12C68, STK12C68-5 parts can be tied
together and share a single capacitor. The capacitor
size must be scaled by the number of devices con-
nected to it. When any one of the STK12C68,
STK12C68-5s detects a power loss and asserts
HSB, the common HSB pin will cause all parts to
request a STORE cycle (a STORE will take place in
those STK12C68, STK12C68-5s that have been
written since the last nonvolatile cycle).
LOW AVERAGE ACTIVE POWER
The STK12C68, STK12C68-5 draws significantly
less current when it is cycled at times longer than
50ns. Figure 4 shows the relationship between ICC
and READ cycle time. Worst-case current consump-
tion is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100%
duty cycle on chip enable). Figure 5 shows the
same relationship for WRITE cycles. If the chip
enable duty cycle is less than 100%, only standby
current is drawn when the chip is disabled. The
overall average current drawn by the STK12C68,
STK12C68-5 depends on the following items: 1)
CMOS vs. TTL input levels; 2) the duty cycle of chip
enable; 3) the overall cycle rate for accesses; 4) the
ratio of READs to WRITEs; 5) the operating tempera-
ture; 6) the Vcc level; and 7) I/O loading.
During any STORE operation, regardless of how it
was initiated, the STK12C68, STK12C68-5 will con-
tinue to drive the HSB pin low, releasing it only when
the STORE is complete. Upon completion of the
STORE operation the STK12C68, STK12C68-5 will
remain disabled until the HSB pin returns high.
Rev 2.0
Document Control #ML0008
June, 2008
11
STK12C68, STK12C68-5 (SMD5962-94599)
100
80
100
80
60
60
TTL
40
20
40
20
CMOS
TTL
CMOS
0
0
50
100
150
200
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 4: Icc (max) Reads
Figure 5: Icc (max) Writes
desired state as a safeguard against events that
might flip the bit inadvertently (program bugs,
incoming inspection routines, etc.).
BEST PRACTICES
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the
product’s main system values, experience gained
working with hundreds of applications has resulted
in the following suggestions as best practices:
• The Vcap value specified in this datasheet
includes a minimum and a maximum value size.
Best practice is to meet this requirement and not
exceed the max Vcap value because the higher
inrush currents may reduce the reliability of the
internal pass transistor. Customers that want to
use a larger Vcap value to make sure there is
extra store charge should discuss their Vcap size
selection with Simtek.
• The non-volatile cells in an nvSRAM are pro-
grammed on the test floor during final test and
quality assurance. Incoming inspection routines
at customer or contract manufacturer’s sites will
sometimes reprogram these values. Final NV
patterns are typically repeating patterns of AA,
55, 00, FF, A5, or 5A. End product’s firmware
should not assume an NV array is in a set pro-
grammed state. Routines that check memory
content values to determine first time system
configuration, cold or warm boot status, etc.
should always program a unique NV pattern
(e.g., complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final sys-
tem manufacturing test to ensure these system
routines work consistently.
• Power up boot firmware routines should rewrite
the nvSRAM into the desired state. While the
nvSRAM is shipped in a preset state, best prac-
tice is to again rewrite the nvSRAM into the
Rev 2.0
Document Control #ML0008
June, 2008
12
STK12C68, STK12C68-5 (SMD5962-94599)
COMMERCIAL AND INDUSTRIAL ORDERING INFORMATION
STK12C68 - S F 45 I TR
Packing Option
Blank = Tube
TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
S = Plastic 28-pin 330 mil SOIC
W = Plastic 28-pin 600 mil DIP
P = Plastic 28-pin 300 mil DIP
C = Ceramic 28-pin 300 mil DIP
L = Ceramic 28-pin LLC
Rev 2.0
Document Control #ML0008
June, 2008
13
STK12C68, STK12C68-5 (SMD5962-94599)
MILITARY ORDERING INFORMATION
STK12C68 - 5 C 35 M
Temperature Range
M = Military (–55 to 125°C)
Access Time
35 = 35ns
55 = 55ns
Package
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (solder dip finish)
L = Ceramic 28 pin LCC
Retention / Endurance
5 = Military (10 years or 105cycles)
5962 - 94599 01 MX X
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Case Outline
X = Ceramic 28 pin 300-mil DIP
Y = Ceramic 28 pin LCC
Device Class Indicator - Class M
Device Type
01 = 55ns
03 = 35ns
Rev 2.0
Document Control #ML0008
June, 2008
14
STK12C68, STK12C68-5 (SMD5962-94599)
ORDERING INFORMATION
Part Number
Description
Access Times
Temperature
Commercial
Commercial
Commercial
Commercial
Commercial
STK12C68-C35
STK12C68-C45
STK12C68-L35
STK12C68-L45
STK12C68-PF25
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM LCC28
5V 8Kx8 AutoStore nvSRAM LCC28
5V 8Kx8 AutoStore nvSRAM PDIP28-600
35 ns access time
45 ns access time
35 ns access time
45 ns access time
25 ns access time
STK12C68-PF45
5V 8Kx8 AutoStore nvSRAM PDIP28-600
45 ns access time
Commercial
STK12C68-SF25
5V 8Kx8 AutoStore nvSRAM SOP28-330
5V 8Kx8 AutoStore nvSRAM SOP28-330
5V 8Kx8 AutoStore nvSRAM SOP28-330
5V 8Kx8 AutoStore nvSRAM SOP28-330
5V 8Kx8 AutoStore nvSRAM PDIP28-600
5V 8Kx8 AutoStore nvSRAM PDIP28-600
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM LCC28
25 ns access time
25 ns access time
45 ns access time
45 ns access time
25 ns access time
45 ns access time
35 ns access time
45 ns access time
35 ns access time
45 ns access time
25 ns access time
45 ns access time
25 ns access time
25 ns access time
45 ns access time
45 ns access time
25 ns access time
45 ns access time
55 ns access time
55 ns access time
55 ns access time
55 ns access time
55 ns access time
35 ns access time
35 ns access time
35 ns access time
35 ns access time
35 ns access time
35 ns access time
35 ns access time
35 ns access time
35 ns access time
35 ns access time
35 ns access time
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Military
STK12C68-SF25TR
STK12C68-SF45
STK12C68-SF45TR
STK12C68-WF25
STK12C68-WF45
STK12C68-C35I
STK12C68-C45I
STK12C68-L35I
STK12C68-L45I
5V 8Kx8 AutoStore nvSRAM LCC28
STK12C68-PF25I
5V 8Kx8 AutoStore nvSRAM PDIP28-600
5V 8Kx8 AutoStore nvSRAM PDIP28-600
5V 8Kx8 AutoStore nvSRAM SOP28-330
5V 8Kx8 AutoStore nvSRAM SOP28-330
5V 8Kx8 AutoStore nvSRAM SOP28-330
5V 8Kx8 AutoStore nvSRAM SOP28-330
5V 8Kx8 AutoStore nvSRAM PDIP28-600
5V 8Kx8 AutoStore nvSRAM PDIP28-600
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM LCC28
STK12C68-PF45I
STK12C68-SF25I
STK12C68-SF25ITR
STK12C68-SF45I
STK12C68-SF45ITR
STK12C68-WF25I
STK12C68-WF45I
SMD5962-9459901MXA
SMD5962-9459901MXC
SMD5962-9459901MXX
SMD5962-9459901MYA
SMD5962-9459901MYX
SMD5962-9459903MXA
SMD5962-9459903MXC
SMD5962-9459903MXX
SMD5962-9459903MYA
SMD5962-9459903MYX
STK12C68-5C35M
STK12C68-5C55M
STK12C68-5K35M
STK12C68-5K55M
STK12C68-5L35M
STK12C68-5L55M
Military
Military
Military
5V 8Kx8 AutoStore nvSRAM LCC28
Military
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM LCC28
Military
Military
Military
Military
5V 8Kx8 AutoStore nvSRAM LCC28
Military
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM CDIP28-300
5V 8Kx8 AutoStore nvSRAM LCC28
Military
Military
Military
Military
Military
5V 8Kx8 AutoStore nvSRAM LCC28
Military
Rev 2.0
15
Document Control #ML0008
June, 2008
STK12C68, STK12C68-5 (SMD5962-94599)
Package Diagrams
28-Lead, 330 mil SOIC Gull Wing
0.713
0.733
18.11
18.62
(
)
0.112
0.004
(2.845)
(0.102)
0.020
0.014
0.508
0.356
0.050 (1.270)
(
)
0.103
0.093
2.616
2.362
(
)
0.336
0.326
8.534
8.280
0.477
12.116
11.506
(
)
(
)
0.453
Pin 1
10°
0°
0.014
0.008
0.356
0.203
(
)
0.044
1.117
(
)
0.028
0.711
MIN
MAX
DIM = INCHES
DIM = mm
16
MIN
( MAX )
Rev 2.0
Document Control #ML0008
June, 2008
STK12C68, STK12C68-5 (SMD5962-94599)
28-Lead 300 mil PDIP
.275 6.98
.295(7.49)
Pin 1
Index
.020
0.51
.030 (0.76)
1.345 34.16
1.385 (35.18 )
----
----
(4.57).180
.015
----
0.38
----
)
(
.125 (3.18)
MIN
.100
(2.54)
BSC
.030
0.76
.014
0.36
.045 1.14
.060 (1.52)
.045 (1.14)
.022 (0.56)
.300 7.62
.325 (8.26)
MIN
MAX
DIM = INCHES
MIN
MAX
DIM = mm
(
)
0o
.008 0.20
.015 (0.38)
15o
.300
(7.62)
BSC
----
.430
----
( )
10.92
Rev 2.0
Document Control #ML0008
June, 2008
17
STK12C68, STK12C68-5 (SMD5962-94599)
28-Lead, 600 mil PDIP
0.530 13.46
0.550 13.97
(
)
Pin 1
Index
0.040 1.02
0.050(1.27 )
1.440 36.58
1.460 (37.08)
---- ----
(4.57) .180
0.015 (0.38)
----
----
0.125 (3.18)
MIN
0.10
(2.54)
BSC
0.36
0.014
0.045 1.14
)
(
0.060 1.52
(
)
0.022 0.56
15.11
15.88
0.595
0.625
(
)
MIN
MAX
DIM = INCHES
MIN
MAX
)
DIM = mm
(
o
o
15
0.20
0.38
0.008
0.015
0
(
)
0.600
0.660
15.24
16.76
)
(
Rev 2.0
Document Control #ML0008
June, 2008
18
STK12C68, STK12C68-5 (SMD5962-94599)
28-Lead, 300 mil Side Braze DIL
1.386
35.20
1.414 (35.92)
7.36
(7.87)
.280
.310
PIN
14
---
---
.060 (1.52)
3.15 .124
4.14 .162
)
(
.040 1.02
.060 ( )
1.52
.125 (3.18)
MIN
.090 2.29
)
(
0.41
.110 2.79
.016
1.22
.048
.020 (0.51)
.052 (1.32)
.290 7.37
.310 (7.87 )
MIN
DIM = INCHES
MIN
MAX
(
DIM = mm
)
MAX
.009 0.23
.012 (0.30)
.300 7.62
.320 (8.13)
Rev 2.0
Document Control #ML0008
June, 2008
19
STK12C68, STK12C68-5 (SMD5962-94599)
28-Pad, 350 mil Ceramic LCC
0.542 13.77
(
)
0.558 14.17
ο
(1.02) 0.040 REF X 45
3 places
(
0.342 8.69
0.358 9.09
)
ο
(0.51) 0.020 REF X 45
0.075 1.91
0.095 (2.41 )
0.055 (1.40 )
(0.23) 0.009 REF
28 places
1.14
0.045
Pad 1
Index
0.006
0.022
0.022
0.028
0.56
0.15
0.56
(
)
)
(
0.71
0.015
---
0.045 1.14
0.381
)
(
( )
---
0.055 1.40
0.070 1.78
(
)
0.090
2.29
---
---
0.062 1.57
(
( )
)
0.558 14.17
0.078 1.98
MIN
MAX
DIM = INCHES
MIN
MAX
DIM = mm
(
)
Rev 2.0
Document Control #ML0008
June, 2008
20
STK12C68, STK12C68-5 (SMD5962-94599)
Document Revision History
Revision
0.0
Date
Summary
December 2002 Combined commercial, industrial and military data sheets. Removed 20 nsec device.
0.1
January 2003
July 2003
Added 35ns SMD to order information
0.2
Added “28 - SOIC” label to page 1 pinout drawing
0.3
September 2003 Added lead-free lead finish
0.4
October 2003
March 2006
Restored “W” 600 mil DIP package to ordering information
0.5
Removed Commercial 35 ns and leaded lead finish, Removed Military 45ns device
Reformat SMD Ordering Information to SDDC Part Number Format
0.6
August 2006
February 2007
0.7
Add Fast Power-Down Slew Rate Information
Restore Comm/Ind C & L Package Options
Add Tape Reel Ordering Options
Add Product Ordering Code Listing
Add Package Outline Drawings
Reformat Entire Document
0.8
2.0
July 2007
June 2008
extend definition of t (#7)
HZ
update fig. SRAM READ CYCLE #2, SRAM WRITE CYCLE #1,
update notes in tables HARDWARE STORE CYCLE, AutoStore / POWER_UP RECALL,
update Note s and Note u
split off SOFTWARE STORE / RECALL MODE SELEKTION table to clarify product usage
Added STK-12C68-5 part number to header.
Page 3: in the DC characteristics table, identified access times valid for commercial and industrial appli-
cations only; referred users to Website for package thermal characteristics.
Page 4: in SRAM Read Cycles #1 & #2 table, revised description for t
and t
, and changed
ELQX
ELQX
t
Symbol #2 to
for Read Cycle Time; updated SRAM Read Cycle #2 timing diagram and changed
ELEH
title to add G controlled.
Page 11: under HSB Operation, revised first paragraph to read “The HSB pin has a very resistive
pullup...”
Page 14: added access time column to table.
SIMTEK STK12C68, STK12C68-5 Datasheet, June 2008
Copyright 2008, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other
form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be
accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including
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Rev 2.0
Document Control #ML0008
June, 2008
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