STK11C68-5L25M [SIMTEK]
Non-Volatile SRAM, 8KX8, 25ns, CMOS, CQCC28, CERAMIC, LCC-28;
| 型号： | STK11C68-5L25M |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | Non-Volatile SRAM, 8KX8, 25ns, CMOS, CQCC28, CERAMIC, LCC-28 静态存储器 |
| 文件： | 总10页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK11C68
STK11C68-M SMD#5962-92324
8K x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
DESCRIPTION
• 25ns, 35ns, 45ns and 55ns Access Times
The Simtek STK11C68 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent non-
volatile data resides in the Nonvolatile Elements.
Data transfers from the SRAM to the Nonvolatile Ele-
ments (the STORE operation), or from Nonvolatile
Elements to SRAM (the RECALL operation), take
place using a software sequence. Transfers from the
Nonvolatile Elements to the SRAM (the RECALL
operation) also take place automatically on restora-
tion of power.
• STORE to Nonvolatile Elements Initiated by
Software
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments (Industrial/Commercial)
• 100-Year Data Retention (Industrial/Commer-
cial)
• Commercial, Industrial and Military Tempera-
tures
• 28-Pin DIP, SOIC and LCC Packages
The STK11C68 is pin-compatible with industry-
standard SRAMs. MIL-STD-883 device is also
available (STK11C68-M).
BLOCK DIAGRAM
PIN CONFIGURATIONS
NC
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
QUANTUM TRAP
128 x 512
2
3
4
5
6
7
8
9
NC
A8
A6
A5
A6
A5
A9
STORE
A4
A11
G
A10
E
STORE/
RECALL
A3
A7
A8
A9
A2
STATIC RAM
ARRAY
CONTROL
A1
RECALL
10
11
12
13
14
A0
DQ7
DQ6
DQ5
DQ4
DQ3
128 x 512
DQ0
DQ1
DQ2
VSS
A11
A12
SOFTWARE
DETECT
A
- A
12
0
28 - LCC
28 - DIP
28 - SOIC
DQ
DQ
DQ
0
1
2
COLUMN I/O
PIN NAMES
COLUMN DEC
DQ
A
- A
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
3
4
0
12
DQ
W
DQ
DQ
DQ
5
6
7
A
A A
A A
1 4
2 3
A
0
10
G
DQ - DQ
0
7
E
E
W
G
V
V
CC
SS
September 2003
1
Document Control # ML0007 rev 0.1
STK11C68
ABSOLUTE MAXIMUM RATINGSa
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS
(VCC = 5.0V ± 10%)
INDUSTRIAL/
MILITARY
COMMERCIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V Current
90
75
90
75
65
55
mA
mA
mA
mA
t
t
t
t
= 25ns
= 35ns
= 45ns
= 55ns
CC
CC
AVAV
AVAV
AVAV
AVAV
1
65
N/A
c
I
I
Average V Current during STORE
3
3
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
b
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
AVAV
CC
3
10
10
mA
5V, 25°C, Typical
All Others Cycling, CMOS Levels
d
I
Average V Current
27
23
28
24
21
20
mA
mA
mA
mA
t
t
t
t
= 25ns, E ≥ V
IH
SB
CC
AVAV
AVAV
AVAV
AVAV
1
(Standby, Cycling TTL Input Levels)
= 35ns, E ≥ V
= 45ns, E ≥ V
= 55ns, E ≥ V
IH
IH
IH
20
N/A
d
I
I
I
V
Standby Current
E ≥ (V
- 0.2V)
CC
SB
CC
2
750
±1
1500
±1
µA
µA
µA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V
V
= max
CC
IN
ILK
= V to V
CC
SS
Off-State Output Leakage Current
V
V
= max
CC
IN
OLK
±5
±5
= V to V , E or G ≥ V
SS
CC
IH
V
V
V
V
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
V + .5
CC
V
V
All Inputs
All Inputs
IH
CC
V
– .5
0.8
V – .5
SS
0.8
IL
SS
2.4
2.4
V
I
I
=–4mA
= 8mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
T
0
–40
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 is the average current required for the duration of the STORE cycle (tSTORE ).
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
5.0V
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
480 Ohms
OUTPUT
30 pF
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
CAPACITANCEe
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
Input capacitance
Output Capacitance
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
C
C
8
7
pF
IN
pF
OUT
Figure 1: AC Output Loading
Note e: These parameters are guaranteed but not tested.
September 2003
2
Document Control # ML0007 rev 0.1
STK11C68
SRAM READ CYCLES #1 & #2
(VCC = 5.0V + 10%)
SYMBOLS
STK11C68-25 STK11C68-35 STK11C68-45 STK11C68-55
PARAMETER
UNITS
NO.
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
25
35
45
55
AVAV
RC
AA
g
3
Address Access Time
25
10
35
15
45
20
55
25
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
g
5
5
5
5
5
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
13
13
35
15
15
45
25
25
55
EHQZ
HZ
8
0
0
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
EHICCL
d, e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledf
2
t
AVAV
ADDRESS
1
11
EHICCL
t
ELQV
t
6
E
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
September 2003
3
Document Control # ML0007 rev 0.1
STK11C68
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V + 10%)
SYMBOLS
STK11C68-25
STK11C68-35
STK11C68-45
STK11C68-55
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
MIN
55
45
45
30
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
AW
t
t
t
20
0
25
0
30
0
45
0
AVWH
AVEH
t
t
t
AVWL
AVEL
EHAX
AS
t
t
t
0
0
0
0
WHAX
WR
h, i
t
t
10
13
15
35
WLQZ
WZ
t
t
5
5
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12
t
AVAV
ADDRESS
19
14
t
WHAX
t
ELWH
E
17
t
AVWH
18
t
AVWL
13
W
t
WLWH
15
16
t
t
DVWH
WHDX
DATA IN
DATA VALID
20
t
WLQZ
21
t
WHQX
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledj
12
t
AVAV
ADDRESS
14
18
19
t
t
ELEH
t
AVEL
EHAX
E
17
t
AVEH
13
t
WLEH
W
15
16
t
DVEH
t
EHDX
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
September 2003
4
Document Control # ML0007 rev 0.1
STK11C68
STORE INHIBIT/POWER-UP RECALL
(VCC = 5.0V + 10%)
SYMBOLS
STK11C68
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
550
10
22
23
24
25
t
t
Power-up RECALL Duration
STORE Cycle Duration
µs
ms
V
k
RESTORE
STORE
V
V
Low Voltage Trigger Level
Low Voltage Reset Level
4.0
4.5
SWITCH
RESET
3.6
V
Note k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE INHIBIT/POWER-UP RECALL
VCC
5V
24
VSWITCH
25
VRESET
STORE INHIBIT
POWER-UP RECALL
22
t
RESTORE
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
BROWN OUT
STORE INHIBIT
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
September 2003
5
Document Control # ML0007 rev 0.1
STK11C68
SOFTWARE STORE/RECALL MODE SELECTION
E
W
A
- A (hex)
MODE
I/O
NOTES
12
0
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
L
H
l
Read SRAM
Read SRAM
Nonvolatile STORE
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
L
H
l
Read SRAM
Read SRAM
Nonvolatile RECALL
Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
SOFTWARE STORE/RECALL CYCLEm, n
(VCC = 5.0V ± 10%)
STK11C68-25
STK11C68-35
STK11C68-45
STK11C68-55
NO.
SYMBOLS
PARAMETER
UNITS
MIN
25
0
MAX
MIN
35
0
MAX
MIN
45
0
MAX
MIN
55
0
MAX
26
27
28
29
30
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
ns
ns
ns
ns
µs
AVAV
AVEL
m
m
20
20
25
20
30
20
35
20
ELEH
m
Address Hold Time
ELAX
m
RECALL Duration
20
20
20
20
RECALL
Note m: The software sequence is clocked with E controlled reads.
Note n: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0000, 1555, 0AAA, 1FFF,
10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledn
26
AVAV
26
AVAV
t
t
ADDRESS #1
ADDRESS #6
ADDRESS
27
AVEL
28
ELEH
t
t
E
29
ELAX
t
23
30
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA
September 2003
6
Document Control # ML0007 rev 0.1
STK11C68
DEVICE OPERATION
The STK11C68 is a versatile memory chip that pro-
SOFTWARE NONVOLATILE STORE
vides several modes of operation. The STK11C68
can operate as a standard 8K x 8 SRAM. It has an
8K x 8 Nonvolatile Elements shadow to which the
SRAM information can be copied or from which the
SRAM can be updated in nonvolatile mode.
The STK11C68 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
NOISE CONSIDERATIONS
Note that the STK11C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1µF connected between V
cc
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
and V , using leads and traces that are as short as
ss
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
To initiate the software STORE cycle, the following
READ sequence must be performed:
The STK11C68 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-12 determines which of the 8,192 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
September 2003
7
Document Control # ML0007 rev 0.1
STK11C68
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
HARDWARE PROTECT
The STK11C68 offers hardware protection against
inadvertent STORE operation during low-voltage
conditions. When VCC < VSWITCH, software STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK11C68 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK11C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
temperature; 6) the V level; and 7) I/O loading.
cc
100
80
100
80
60
60
TTL
CMOS
40
40
TTL
20
20
CMOS
0
0
50
100
150
200
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 2: I (max) Reads
Figure 3: I (max) Writes
CC
CC
September 2003
8
Document Control # ML0007 rev 0.1
STK11C68
ORDERING INFORMATION
STK11C68 - 5 P F 45 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
M = Military (–55 to 125°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
55 = 55ns (Military only)
Lead Finish (Plastic only)
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
P = Plastic 28-pin 300 mil DIP
S = Plastic 28-pin 350 mil SOIC
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (solder dip finish)
L = Ceramic 28 pin LCC
Retention / Endurance
6
Blank = Comm/Ind (100 years/10 cycles)
5
5 = Military (10 years/10 cycles)
5962-92324 04 MX X
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Access Time
04 = 55ns
05 = 45ns
06 = 35ns
September 2003
9
Document Control # ML0007 rev 0.1
STK11C68
Document Revision History
Revision
0.0
Date
December 2002
September 2003
Summary
Combined commercial, industrial and military data sheets. Removed 20 nsec device.
Added lead-free lead finish
0.1
September 2003
10
Document Control # ML0007 rev 0.1
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