STK14C88-3RF55I [SIMTEK]
Non-Volatile SRAM, 32KX8, 55ns, CMOS, PDSO48, 0.300 INCH, PLASTIC, SSOP-48;
| 型号： | STK14C88-3RF55I |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | Non-Volatile SRAM, 32KX8, 55ns, CMOS, PDSO48, 0.300 INCH, PLASTIC, SSOP-48 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK14C88-3
32K x 8 AutoStore™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
DESCRIPTION
The Simtek STK14C88-3 is a fast static RAM with a
• 35ns, 45ns and 55ns Access Times
• “Hands-off” Automatic STORE with External
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent, non-
volatile data resides in nonvolatile elements. Data
transfers from the SRAM to the nonvolatile elements
(the STORE operation) can take place automatically
on power down. A 68µF or larger capacitor tied from
VCAP to ground guarantees the STORE operation,
regardless of power-down slew rate or loss of power
from “hot swapping”. Transfers from the nonvolatile
elements to the SRAM (the RECALL operation) take
place automatically on restoration of power. Initia-
tion of STORE and RECALL cycles can also be soft-
ware controlled by entering specific read
sequences. A hardware STORE may be initiated with
the HSB pin.
68µF Capacitor on Power Down
• STORE to nonvolatile elements Initiated by
Hardware, Software or AutoStore™
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to nonvolatile ele-
ments (Commercial/Industrial)
• 100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
• Single 3.3V + 0.3V Operation
• Commercial and Industrial Temperatures
• 32-Pin SOIC and DIP Packages
PIN CONFIGURATIONS
BLOCK DIAGRAM
V
V
CAP
CCX
Quantum Trap
512 x 512
POWER
VCCX
HSB
W
A13
A8
A9
A11
G
NC
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VCAP
A14
A12
A7
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CONTROL
A5
A6
STORE
A7
STORE/
RECALL
A8
STATIC RAM
HSB
RECALL
A9
ARRAY
CONTROL
A11
A12
A13
A14
512 x 512
A6
A5
A4
SOFTWARE
DETECT
A
- A
13
0
DQ
0
A3
COLUMN I/O
DQ
1
NC
A2
9
COLUMN DEC
DQ
2
DQ
3
10
11
12
13
14
15
16
DQ
4
A1
DQ
5
A
A A A A A
1 2 3 4 10
0
DQ
G
6
DQ
A0
7
DQ0
DQ1
DQ2
VSS
E
W
32 - DIP
32 - SOIC
48 - SSOP
(not to scale)
PIN NAMES
A
- A
DQ -DQ
E
W
G
HSB
V
V
V
0
14
0
7
CCX
CAP
SS
Address
Inputs
Data In/Out
Chip
Enable
Write
Enable
Output
Enable
Hardware
Store
Busy (I/O)
Power
(+ 3.3V)
Capacitor
Ground
November 2003
1
Document Control # ML0015 rev 0.3
STK14C88-3
ABSOLUTE MAXIMUM RATINGSa
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.5V
Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (V + 0.5V)
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (V + 0.5V)
CC
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
CC
DC CHARACTERISTICS
(VCC = 3.0V-3.6V)e
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V Current
50
42
37
52
44
39
mA
mA
mA
t
t
t
= 35ns
= 45ns
= 55ns
CC
CC
AVAV
AVAV
AVAV
1
c
I
I
Average V Current during STORE
3
3
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
b
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
AVAV
CC
3
9
9
mA
5V, 25°C, Typical
All Others Cycling, CMOS Levels
c
I
I
Average V
Current during
CAP
All Inputs Don’t Care
CC
4
2
2
mA
AutoStore™ Cycle
d
Average V Current
(Standby, Cycling TTL Input Levels)
18
16
15
19
17
16
mA
mA
mA
t
t
t
= 35ns, E ≥ V
= 45ns, E ≥ V
= 55ns, E ≥ V
SB
CC
AVAV
AVAV
AVAV
IH
IH
IH
1
d
I
I
I
V
Standby Current
E ≥ (V – 0.2V)
CC
SB
CC
2
1
1
mA
µA
µA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V
V
= max
CC
ILK
±1
±1
±1
±1
= V to V
CC
IN
SS
Off-State Output Leakage Current
V
V
= max
CC
OLK
= V to V , E or G ≥ V
IH
IN
SS
CC
V
V
V
V
V
Input Logic “1” Voltage
2.2
V
+ .5
2.2
V + .5
CC
V
V
All Inputs
All Inputs
IH
CC
Input Logic “0” Voltage
V
– .5
0.8
V – .5
SS
0.8
IL
SS
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
2.4
2.4
V
I
I
I
=–4mA except HSB
= 8mA except HSB
= 3mA
OH
OL
BL
OUT
OUT
OUT
0.4
0.4
70
0.4
0.4
85
V
V
T
0
–40
°C
A
Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC3 are the average currents required for the duration of the respective STORE cycles (tSTORE ).
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Note e: VCC reference levels throughout this datasheet refer to VCCX
.
AC TEST CONDITIONS
3.3V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
317 Ohms
OUTPUT
CAPACITANCEf
(TA = 25°C, f = 1.0MHz)
351 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
C
C
Input Capacitance
Output Capacitance
5
7
pF
IN
pF
OUT
Note f: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
November 2003
2
Document Control # ML0015 rev 0.3
STK14C88-3
SRAM READ CYCLES #1 & #2
(VCC = 3.0V-3.6V)e
SYMBOLS
STK14C88-3-35 STK14C88-3-45 STK14C88-3-55
NO.
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
Read Cycle Time
35
45
55
AVAV
h
3
Address Access Time
35
15
45
20
55
25
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
h
5
5
5
5
5
5
5
AXQX
6
ELQX
i
7
13
13
35
15
15
45
20
20
55
EHQZ
HZ
8
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
i
9
GHQZ
f
f
10
11
ELICCH
EHICCL
PS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: I/O state asumes E and G < V and W > V ; device is continuously selected.
IL
IH
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledg
2
AVAV
t
ADDRESS
E
1
ELQV
11
EHICCL
t
t
6
ELQX
t
7
EHQZ
t
G
9
4
GLQV
t
GHQZ
t
8
GLQX
t
DATA VALID
DQ (DATA OUT)
10
ELICCH
t
ACTIVE
STANDBY
I
CC
November 2003
3
Document Control # ML0015 rev 0.3
STK14C88-3
SRAM WRITE CYCLES #1 & #2
(VCC = 3.0V-3.6V)e
SYMBOLS
STK14C88-3-35 STK14C88-3-45
STK14C88-3-55
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
MIN
55
40
40
25
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
AW
t
t
t
25
0
30
0
40
0
AVWH
AVEH
t
t
t
AVWL
WHAX
AVEL
EHAX
AS
t
t
t
0
0
0
WR
i, j
t
t
13
15
20
WLQZ
WZ
t
t
5
5
5
WHQX
OW
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
15
16
WHDX
t
t
DVWH
DATA VALID
DATA IN
DATA IN
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledk, l
12
AVAV
t
ADDRESS
18
AVEL
14
ELEH
19
t
t
t
EHAX
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
November 2003
4
Document Control # ML0015 rev 0.3
STK14C88-3
HARDWARE MODE SELECTION
E
H
L
W
X
H
L
HSB
A
- A (hex)
MODE
Not Selected
I/O
POWER
NOTES
13
0
H
X
X
X
X
Output High Z
Output Data
Input Data
Standby
Active
H
Read SRAM
t
L
H
Write SRAM
Active
X
X
L
Nonvolatile STORE
Output High Z
l
m
CC
2
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,
the part will go into standby mode, inhibiting all operations until HSB rises.
HARDWARE STORE CYCLE
(VCC = 3.0V-3.6V)e
SYMBOLS
STK14C88-3
NO.
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
MAX
22
23
24
25
26
t
t
t
t
t
t
t
t
STORE Cycle Duration
10
ms
µs
ns
ns
ns
i, n
i, n
STORE
DELAY
RECOVER
HLHX
HLHZ
HLQZ
HHQX
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
1
700
300
n, o
15
Hardware STORE Low to STORE Busy
HLBL
Note n: E and G low and W high for output behavior.
Note o: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25
HLHX
t
HSB (IN)
24
RECOVER
t
22
STORE
t
26
HLBL
t
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
23
DELAY
t
DQ (DATA OUT)
DATA VALID
November 2003
5
Document Control # ML0015 rev 0.3
STK14C88-3
AutoStore™/POWER-UP RECALL
(VCC = 3.0V-3.6V)e
SYMBOLS
STK14C88-3
NO.
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
MAX
550
10
27
28
29
30
31
32
t
t
t
t
Power-up RECALL Duration
STORE Cycle Duration
µs
ms
ns
µs
V
p
n, q
l
RESTORE
STORE
VSBL
t
t
HLHZ
BLQZ
Low Voltage Trigger (V
) to HSB Low
300
SWITCH
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
1
n
DELAY
V
V
2.7
2.95
2.4
SWITCH
RESET
Low Voltage Reset Level
V
Note p: tRESTORE starts from the time VCC rises above VSWITCH
.
Note q: HSB is asserted low for 1µs when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB
will be released and no STORE will take place.
AutoStore™/POWER-UP RECALL
V
CC
31
SWITCH
V
32
RESET
V
AutoStore™
POWER-UP RECALL
29
VSBL
28
STORE
27
RESTORE
t
t
t
HSB
30
DELAY
t
W
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
NO STORE
(NO SRAM WRITES)
BROWN OUT
AutoStore™
BROWN OUT
AutoStore™
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
November 2003
6
Document Control # ML0015 rev 0.3
STK14C88-3
SOFTWARE STORE/RECALL MODE SELECTION
E
W
A
- A (hex)
MODE
I/O
POWER
NOTES
13
0
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
Active
L
H
r, s, t
Read SRAM
Read SRAM
Nonvolatile STORE
l
CC
2
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
r, s, t
L
H
Active
Read SRAM
Read SRAM
Nonvolatile RECALL
SOFTWARE-CONTROLLED STORE/RECALL CYCLEv
(VCC = 3.0V-3.6V)e
SYMBOLS
STK14C88-3-25 STK14C88-3-35 STK14C88-3-45
NO.
PARAMETER
UNITS NOTES
Standard Alternate
MIN
35
0
MAX
MIN
45
0
MAX
MIN
MAX
33
34
35
36
37
t
t
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
55
0
ns
ns
ns
ns
µs
n
u
u
u
AVAV
RC
AS
AVEL
25
20
30
20
45
20
ELEH
ELAX
RECALL
CW
Address Hold Time
RECALL Duration
20
20
20
Note r: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note s: While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes.
Note t: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
Note u: The software sequence is clocked with E controlled READs.
Note v: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for
a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDv
33
AVAV
33
AVAV
t
t
ADDRESS #1
ADDRESS #6
ADDRESS
34
AVEL
35
ELEH
t
t
E
36
ELAX
t
28
37
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA
November 2003
7
Document Control # ML0015 rev 0.3
STK14C88-3
DEVICE OPERATION
The STK14C88-3 has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static RAM. In nonvolatile mode, data is transferred
from SRAM to nonvolatile elements (the STORE
operation) or from nonvolatile elements to SRAM
(the RECALL operation). In this mode SRAM func-
tions are disabled.
POWER-UP RECALL
During power up, or after any low-power condition
(VCAP < VRESET), an internal RECALL request will be
latched. When VCAP once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK14C88-3 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
NOISE CONSIDERATIONS
The STK14C88-3 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCAP and
VSS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
VCC or between E and system VCC.
SOFTWARE NONVOLATILE STORE
The STK14C88-3 software STORE cycle is initiated
by executing sequential E controlled READ cycles
from six specific address locations. During the
STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the
nonvolatile elements. The program operation copies
the SRAM data into nonvolatile memory. Once a
STORE cycle is initiated, further input and output are
disabled until the cycle is completed.
SRAM READ
The STK14C88-3 performs a READ cycle whenever
E and G are low and W and HSB are high. The
address specified on pins A0-14 determines which of
the 32,768 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of tAVQV (READ cycle
#1). If the READ is initiated by E or G, the outputs will
be valid at tELQV or at tGLQV, whichever is later (READ
cycle #2). The data outputs will repeatedly respond
to address changes within the tAVQV access time with-
out the need for transitions on any control input pins,
and will remain valid until another address change or
until E or G is brought high, or W or HSB is brought
low.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
SRAM WRITE
Valid READ
Valid READ
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
November 2003
8
Document Control # ML0015 rev 0.3
STK14C88-3
SOFTWARE NONVOLATILE RECALL
10kΩ∗
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of E controlled READ opera-
tions must be performed:
1
32
31
30
+
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
16
17
Internally, RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. After
the tRECALL cycle time the SRAM will once again be
ready for READ and WRITE operations. The RECALL
operation in no way alters the data in the nonvolatile
elements. The nonvolatile data can be recalled an
unlimited number of times.
Figure 2: AutoStore™ Mode
*If HSB is not used, it should be left unconnected.
If the power supply drops faster than 20 µs/volt
before VCCX reaches VSWITCH, then a 1 ohm resistor
should be inserted between VCCX and the system
supply to avoid a momentary excess of current
between Vccx and Vcap.
AutoStore™ OPERATION
During normal AutoStore™ operation, the
STK14C88-3 will draw current from VCCX to charge a
capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single
STORE operation. After power up, when the voltage
on the VCAP pin drops below VSWITCH, the part will
automatically disconnect the VCAP pin from VCCX and
initiate a STORE operation.
HSB OPERATION
The STK14C88-3 provides the HSB pin for control-
ling and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK14C88-3 will conditionally initiate a STORE oper-
ation after tDELAY; an actual STORE cycle will only
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin also acts
as an open drain driver that is internally driven low
to indicate a busy condition while the STORE (initi-
ated by any means) is in progress.
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68µF and
220µF (± 20%) rated at 4.7V should be provided.
In order to prevent unneeded STORE operations,
automatic STOREs as well as those initiated by
externally driving HSB low, will be ignored unless at
least one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software-
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. An
optional pull-up resistor is shown connected to HSB.
This can be used to signal the system that the
AutoStore™ cycle is in progress.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14C88-3
will continue SRAM operations for tDELAY. During tDELAY
,
multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
The HSB pin can be used to synchronize multiple
STK14C88-3s while using a single larger capacitor.
November 2003
9
Document Control # ML0015 rev 0.3
STK14C88-3
To operate in this mode the HSB pin should be con-
nected together to the HSB pins from the other
STK14C88-3s. An external pull-up resistor to + 3.3V
is required since HSB acts as an open drain pull
down. The VCAP pins from the other STK14C88-3
parts can be tied together and share a single capac-
itor. The capacitor size must be scaled by the num-
ber of devices connected to it. When any one of the
STK14C88-3s detects a power loss and asserts
HSB, the common HSB pin will cause all parts to
request a STORE cycle (a STORE will take place in
those STK14C88-3s that have been written since
the last nonvolatile cycle).
50
40
30
20
10
TTL
CMOS
During any STORE operation, regardless of how it
was initiated, the STK14C88-3 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK14C88-3 will remain disabled until the HSB
pin returns high.
0
50
100
150
200
Cycle Time (ns)
Figure 3: Icc (max) Reads
50
If HSB is not used, it should be left unconnected.
HARDWARE PROTECT
40
30
20
10
0
The STK14C88-3 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs dur-
ing low-voltage conditions. When VCAP < VSWITCH, all
externally initiated STORE operations and SRAM
WRITEs will be inhibited.
TTL
CMOS
LOW AVERAGE ACTIVE POWER
The STK14C88-3 draws significantly less current
when it is cycled at times longer than 55ns. Figure 3
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 3.6V, 100% duty cycle on chip
enable). Figure 4 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK14C88-3 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the Vcc level; and 7) I/O loading.
50
100
150
200
Cycle Time (ns)
Figure 4: Icc (max) Writes
November 2003
10
Document Control # ML0015 rev 0.3
STK14C88-3
ORDERING INFORMATION
STK14C88-3 N F 45 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
35 = 35ns
45 = 45ns
55 = 55ns
Lead Finish
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
N = Plastic 32-pin 300 mil SOIC
W = Plastic 32-pin 600 mil DIP
R = Plastic 48-pin 300 mil SSOP
November 2003
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Document Control # ML0015 rev 0.3
STK14C88-3
Document Revision History
Revision
Date
Summary
Added 35 nsec device; added HSB operation; current limiting resistor added to Vccx for
extreme power-off slew rate
0.0
January 2003
0.1
0.2
0.3
February 2003
September 2003
November 2003
Added 48 SSOP package
Added lead-free lead finish
Modified pin assignments on 48 SSOP package
November 2003
12
Document Control # ML0015 rev 0.3
STK14C88-3
November 2003
13
Document Control # ML0015 rev 0.3
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