STK14CA8-NF25 [SIMTEK]
128Kx8 Autostore nvSRAM; 128Kx8自动存储的nvSRAM
| 型号： | STK14CA8-NF25 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | 128Kx8 Autostore nvSRAM |
| 文件： | 总19页 (文件大小：595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK14CA8
128Kx8 Autostore nvSRAM
DESCRIPTION
FEATURES
• 25, 35, 45 ns Read Access & R/W Cycle Time
The Simtek STK14CA8 is a 1Mb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
• Unlimited Read/Write Endurance
• Automatic Non-volatile STORE on Power Loss
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
• Non-Volatile STORE Under Hardware or Software
Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the STORE
operation). On power up, data is automatically
restored to the SRAM (the RECALL operation). Both
STORE and RECALL operations are also available
under software control.
• 200K STORE Cycles
• 20-Year Non-volatile Data Retention
• Single 3 V + 20%, -10% Power Supply
• Commercial and Industrial Temperatures
The Simtek nvSRAM is the first monolithic non-vola-
tile memory to offer unlimited writes and reads. It is
the highest performance, most reliable non-volatile
memory available.
• Small Footprint SOIC & SSOP Packages (RoHS-
Compliant)
BLOCK DIAGRAM
VCAP
VCC
Quantum Trap
1024 X 1024
A5
POWER
A6
A7
A8
A9
A12
A13
A14
A15
A16
CONTROL
STORE
RECALL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
1024 X 1024
HSB
SOFTWARE
DETECT
A15 – A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10 A11
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
Rev 1.5
1
Document Control #ML0022
February 2007
STK14CA8
PACKAGES
VCAP
A16
A14
1
2
VCC
A15
HSB
48
47
VCAP
A16
A14
1
2
3
4
5
6
VCC
A15
32
31
3
4
5
6
HSB
W
A13
A8
30
29
28
27
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A12
A7
A6
A12
A7
A6
A5
W
A13
A8
A5
A4
A3
A2
A1
A9
7
8
9
10
11
12
13
14
15
16
26
25
24
23
22
21
20
19
18
17
7
8
9
10
11
12
13
14
15
16
A9
A11
G
A10
E
DQ7
A4
A11
A0
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
DQ4
DQ3
VSS
VSS
DQ0
A3
A2
A1
A0
DQ6
G
A10
E
DQ7
DQ5
DQ4
DQ3
VCC
32 Pin SOIC
17
18
32
31
30
29
28
27
26
25
19
20
21
22
23
24
DQ1
DQ2
Relative PCB area usage.
48 Pin SSOP
See website for detailed package
size specifications.
PIN DESCRIPTIONS
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
16
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
Power Supply
I/O
Power: 3.0V, +20%, -10%
CC
HSB
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
V
V
Power Supply
Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
CAP
Power Supply
No Connect
Ground
SS
(Blank)
Unlabeled pins have no internal connections.
Rev 1.5
Document Control #ML0022
February 2007
2
STK14CA8
ABSOLUTE MAXIMUM RATINGS
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 4.1V
Voltage on Input Relative to VSS . . . . . . . . . .–0.5V to (V + 0.5V)
CC
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (V + 0.5V)
CC
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .–55°C to 140°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
DC CHARACTERISTICS(V = 2.7V-
CC
Package Thermal Characteristics - See Website at http://www.simtek.com
3.6V)
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
Average V Current
UNITS
NOTES
MIN
MAX
MIN
MAX
I
CC
1
CC
65
55
50
70
60
55
mA
mA
mA
t
t
t
= 25ns
= 35ns
= 45ns
AVAV
AVAV
AVAV
Dependent on output loading and cycle
rate. Values obtained without output
loads.
I
I
Average V Current during STORE
All Inputs Don’t Care, V = max
CC
Average current for duration of STORE
CC
CC
CC
2
3
3
mA
mA
cycle (t
)
STORE
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
AVAV
CC
3
3V, 25°C, Typical
All Other Inputs Cycling at CMOS Levels
Dependent on output loading and cycle
rate. Values obtained without output
loads.
10
10
I
I
Average V
Cycle
Current during AutoStore
CAP
All Inputs Don’t Care
Average current for duration of STORE
CC
SB
4
3
3
3
3
mA
mA
cycle (t
)
STORE
V
Standby Current
E ≥ (V -0.2V)
CC
CC
(Standby, Stable CMOS Levels)
All Others V ≤ 0.2V or ≥ (V -0.2V)
IN
CC
Standby current level after nonvolatile
cycle complete
I
I
Input Leakage Current
V
= max
CC
ILK
1
1
1
1
μA
μA
V
= V to V
CC
IN
SS
Off-State Output Leakage Current
V = max
CC
OLK
V
= V to V , E or G ≥ V
IH
IN
SS
CC
V
V
V
V
T
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
2.0
V
+ 0.3
2.0
V + 0.3
CC
V
V
All Inputs
All Inputs
IH
CC
V
–0.5
0.8
V –0.5
SS
0.8
IL
SS
2.4
2.4
V
I
=–2mA
= 4mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
I
0
–40
2.7
17
°C
V
A
V
2.7
17
3.6
120
3.6
120
3.3V + 0.3V
Between V
CC
V
Storage Capacitance
Nonvolatile STORE operations
Data Retention
μF
K
pin and V , 5V rated.
CAP SS
CAP
NV
200
20
200
20
C
DATA
Years
@ 55 deg C
R
Note: The HSB pin has I
=-10 uA for V of 2.4 V, this parameter is characterized but not tested.
OH
OUT
Rev 1.5
Document Control #ML0022
February 2007
3
STK14CA8
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1 and 2
b
CAPACITANCE
(T = 25°C, f = 1.0MHz)
A
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
ΔV = 0 to 3V
ΔV = 0 to 3V
C
Input Capacitance
Output Capacitance
7
7
pF
IN
C
pF
OUT
Note b: These parameters are guaranteed but not tested.
3.0V
577 Ohms
OUTPUT
30 pF
789 Ohms
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
3.0V
577 Ohms
OUTPUT
5 pF
789 Ohms
INCLUDING
SCOPE AND
FIXTURE
Figure 2: AC Output Loading for Tristate Specs (tHZ, tLZ, tWLQZ, tWHQZ, tGLQX, tGHQZ
)
Rev 1.5
Document Control #ML0022
February 2007
4
STK14CA8
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
STK14CA8-25
STK14CA8-35
STK14CA8-45
UNITS
PARAMETER
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
c
c
t
t
25
35
45
AVAV
AVAV
d
d
3
Address Access Time
25
12
35
15
45
20
AVQV
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
AXQX
ELQX
EHQZ
GLQX
OE
OH
LZ
d
d
e
e
5
t
3
3
3
3
3
3
AXQX
6
7
10
10
25
13
13
35
15
15
45
HZ
8
0
0
0
0
0
0
OLZ
OHZ
PA
9
GHQZ
b
b
10
11
ELICCH
EHICCL
PS
Note c: W must be high during SRAM READ cycles.
Note d: Device is continuously selected with E and G both low
Note e: Measured 200mV from steady state output voltage.
Note f: HSB must remain high during READ and WRITE cycles.
c,d,f
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
c,f
SRAM READ CYCLE #2: E Controlled
2
AVAV
t
ADDRESS
1
ELQV
11
EHICCL
t
t
6
ELQX
E
t
7
EHQZ
t
G
9
4
GLQV
t
GHQZ
t
8
GLQX
t
DATA VALID
DQ (DATA OUT)
10
ELICCH
t
ACTIVE
STANDBY
I
CC
Rev 1.5
Document Control #ML0022
February 2007
5
DATA VALID
STK14CA8
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
STK14CA8-25
STK14CA8-35
STK14CA8-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
t
t
t
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
WC
WP
CW
DW
t
t
Write Pulse Width
WLWH
WLEH
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
20
0
25
0
30
0
AVWH
AVEH
AW
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
0
WHAX
e, g
EHAX
WR
t
t
10
13
15
WLQZ
WZ
t
t
3
3
3
WHQX
OW
Note g: If W is low when E goes low, the outputs remain in the high-impedance state.
Note h: E or W must be ≥ VIH during address transitions.
g,h
SRAM WRITE CYCLE #1: W Controlled
12
t
AVAV
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
DATA IN
15
DVWH
16
WHDX
t
t
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
g,h
SRAM WRITE CYCLE #2: E Controlled
12
AVAV
t
ADDRESS
18
AVEL
14
ELEH
19
t
t
t
EHAX
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Rev 1.5
Document Control #ML0022
February 2007
6
STK14CA8
AutoStore/POWER-UP RECALL
SYMBOLS
NO.
STK14CA8
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
MAX
20
22
23
24
25
t
t
Power-up RECALL Duration
STORE Cycle Duration
ms
ms
V
i
HRECALL
STORE
t
12.5
2.65
j,k
HLHZ
V
V
Low Voltage Trigger Level
SWITCH
CCRISE
V
Rise Time
150
μs
CC
Note i: tHRECALL starts from the time VCC rises above VSWITCH
Note j: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
Note k: Industrial Grade Devices require 15 ms MAX.
AutoStore/POWER-UP RECALL
STORE occurs only if a
SRAM write has
happened.
No STORE occurs
without at least one
SRAM write.
VCC
24
VSWITCH
25
tVCCRISE
AutoStore
23
tSTORE
23
tSTORE
POWER-UP RECALL
22
tHRECALL
22
tHRECALL
Read & Write Inhibited
POWER DOWN
BROWN OUT
POWER-UP
RECALL
POWER-UP
RECALL
AutoStore
AutoStoreTM
Note: Read and Write cycles will be ignored during STORE, RECALL and while V is below V
CC
SWITCH
Rev 1.5
Document Control #ML0022
February 2007
7
STK14CA8
l,m
SOFTWARE-CONTROLLED STORE/RECALL CYCLE
Symbols
STK14CA8-35 STK14CA8-35 STK14CA8-45
NO.
PARAMETER
UNITS NOTES
E Cont
G Cont
Alternate
MIN
25
0
MAX
MIN
35
0
MAX
MIN
45
0
MAX
26
27
28
29
30
t
t
t
t
t
t
t
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
ns
ns
ns
ns
μs
m
AVAV
AVAV
RC
AS
AVEL
AVGL
20
1
25
1
30
1
ELEH
EHAX
RECALL
GLGH
GHAX
RECALL
CW
Address Hold Time
RECALL Duration
50
50
50
Note l: The software sequence is clocked with E controlled READs or G controlled READs
Note m: The six consecutive addresses must be read in the order listed in the Mode Selection Table. W must be high during all six consecutive cycles.
m
SOFTWARE STORE/RECALL CYCLE: E CONTROLLED
26
26
tAVAV
tAVAV
ADDRESS #1
ADDRESS #6
ADDRESS
E
27
tAVEL
28
tELEH
29
tEHAX
G
23
30
/
tSTORE tRECALL
HIGH IMPEDENCE
DATA VALID
DATA VALID
DQ (DATA)
m
SOFTWARE STORE/RECALL CYCLE: G CONTROLLED
26
26
tAVAV
tAVAV
ADDRESS #1
ADDRESS #6
ADDRESS
E
28
tGLGH
27
tAVGL
G
30
tRECALL
23
tSTORE
/
29
tGHAX
HIGH IMPEDENCE
DATA VALID
DATA VALID
DQ (DATA)
Rev 1.5
Document Control #ML0022
February 2007
8
STK14CA8
HARDWARE STORE CYCLE
SYMBOLS
STK14CA8
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
1
MAX
31
32
t
t
Hardware STORE to SRAM Disabled
Hardware STORE Pulse Width
70
μs
n
DELAY
HLQZ
t
15
ns
HLHX
Note n: On a hardware STORE initiation, SRAM operation continues to be enabled for time t
to allow read/write cycles to complete
DELAY
HARDWARE STORE CYCLE
32
tHLHX
HSB (IN)
23
tSTORE
HSB (OUT)
31
tDELAY
DQ (DATA OUT)
SRAM Enabled
SRAM Enabled
Soft Sequence Commands
STK14
NO.
SYMBOLS
Standard
PARAMETER
UNITS NOTES
CA8
MIN
MAX
34
t
Soft Sequence Processing Time
70
μs
o,p
SS
Notes:
o: This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register com-
mand.
p: Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
34
tSS
34
tSS
Soft Sequence Command
Soft Sequence Command
ADDRESS #1
ADDRESS #1
ADDRESS #6
ADDRESS #6
ADDRESS
Vcc
Rev 1.5
Document Control #ML0022
February 2007
9
STK14CA8
MODE SELECTION
E
W
G
A -A
Mode
I/O
Power
Notes
15
0
H
L
L
X
H
L
X
L
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
X
Active
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
q,r,s
q,r,s
q,r,s
q,r,s
L
L
L
H
H
H
H
L
L
L
L
Active
AutoStore Disable
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
Active
AutoStore Enable
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
I
CC2
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
Active
Nonvolatile Recall
Notes
q: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
r: While there are 17 addresses on the STK14CA8, only the lower 16 are used to control software modes
s: I/O state depends on the state of G. The I/O table shown assumes G low
Rev 1.5
Document Control #ML0022
February 2007
10
STK14CA8
nvSRAM OPERATION
nvSRAM
AutoStore OPERATION
The STK14CA8 nvSRAM is made up of two func-
tional components paired in the same physical cell.
These are the SRAM memory cell and a nonvolatile
QuantumTrap cell. The SRAM memory cell operates
like a standard fast static RAM. Data in the SRAM
can be transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to
SRAM (the RECALL operation). This unique archi-
tecture allows all cells to be stored and recalled in
parallel. During the STORE and RECALL operations
SRAM READ and WRITE operations are inhibited.
The STK14CA8 supports unlimited read and writes
like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and
up to 200K STORE operations.
The STK14CA8 stores data to nvSRAM using one
of three storage operations. These three operations
are Hardware Store (activated by HSB), Software
Store (activated by an address sequence), and
AutoStore (on power down).
AutoStore operation is a unique feature of Simtek
QuanumTrap technology is enabled by default on
the STK14CA8.
During normal operation, the device will draw cur-
rent from V
to charge a capacitor connected to
CC
the V
pin. This stored charge will be used by the
CAP
chip to perform a single STORE operation. If the
voltage on the V pin drops below V , the
CC
SWITCH
part will automatically disconnect the V
pin from
CAP
V
. A STORE operation will be initiated with power
CC
SRAM READ
provided by the V
capacitor.
CAP
The STK14CA8 performs a READ cycle whenever
E and G are low while W and HSB are high. The
Figure 3 shows the proper connection of the storage
capacitor (V ) for automatic store operation.
CAP
address specified on pins A
determine which of
Refer to the DC CHARACTERISTICS table for the
size of V . The voltage on the V pin is driven
0-16
the 131,072 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
CAP
CAP
to 5V by a charge pump internal to the chip. A pull
up should be placed on W to hold it inactive during
power up.
puts will be valid after a delay of t
(READ cycle
AVQV
#1). If the READ is initiated by E and G, the outputs
will be valid at t or at t , whichever is later
ELQV
GLQV
To reduce unneeded nonvolatile stores, AutoStore
and Hardware Store operations will be ignored
unless at least one WRITE operation has taken
place since the most recent STORE or RECALL
cycle. Software initiated STORE cycles are per-
formed regardless of whether a WRITE operation
(READ cycle #2). The data outputs will repeatedly
respond to address changes within the t
AVQV
access time without the need for transitions on any
control input pins, and will remain valid until another
address change or until E or G is brought high, or W
and HSB is brought low.
SRAM WRITE
VCC
VCAP
VCC
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
W
DQ0-7 will be written into memory if it is valid t
DVWH
before the end of a W controlled WRITE or t
before the end of an E controlled WRITE.
DVEH
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
low.
after W goes
WLQZ
Figure 3. AutoStore Mode
Rev 1.5
Document Control #ML0022
February 2007
11
STK14CA8
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1 Read Address 0x4E38 Valid READ
2 Read Address 0xB1C7 Valid READ
3 Read Address 0x83E0 Valid READ
4 Read Address 0x7C1F Valid READ
5 Read Address 0x703F Valid READ
6 Read Address 0x8FC0 Initiate STORE Cycle
HARDWARE STORE (HSB) OPERATION
The STK14CA8 provides the HSB pin for controlling
and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK14CA8 will conditionally initiate a STORE oper-
ation after t
. An actual STORE cycle will only
DELAY
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin also
acts as an open drain driver that is internally driven
low to indicate a busy condition while the STORE
(initiated by any means) is in progress. This pin
should be externally pulled up if it is used to drive
other inputs.
sequence and that G is active. After the t
STORE
cycle time has been fulfilled, the SRAM will again be
activated for READ and WRITE operation.
SOFTWARE RECALL
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14CA8 will
Data can be transferred from the nonvolatile mem-
ory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL
cycle, the following sequence of E controlled or G
controlled READ operations must be performed:
continue to allow SRAM operations for t
. Dur-
DELAY
ing t
, multiple SRAM READ operations may
DELAY
take place. If a WRITE is in progress when HSB is
pulled low, it will be allowed a time, t , to com-
DELAY
plete. However, any SRAM WRITE cycles
requested after HSB goes low will be inhibited until
HSB returns high.
1 Read Address 0x4E38 Valid READ
2 Read Address 0xB1C7 Valid READ
3 Read Address 0x83E0 Valid READ
4 Read Address 0x7C1F Valid READ
5 Read Address 0x703F Valid READ
6 Read Address 0x4C63 Initiate RECALL Cycle
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(V <V
latched. When V
voltage of V
cally be initiated and will take t
), an internal RECALL request will be
CC
SWITCH
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
once again exceeds the sense
CC
, a RECALL cycle will automati-
SWITCH
to complete.
HRECALL
After the t
cycle time, the SRAM will once
RECALL
SOFTWARE STORE
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements.
Data can be transferred from the SRAM to the non-
volatile memory by a software address sequence.
The STK14CA8 software STORE cycle is initiated
by executing sequential E controlled or G controlled
READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data
is erased and then the new data is programmed into
the nonvolatile elements. Once a STORE cycle is
initiated, further memory inputs and outputs are dis-
abled until the cycle is completed.
Rev 1.5
Document Control #ML0022
February 2007
12
STK14CA8
LOW AVERAGE ACTIVE POWER
DATA PROTECTION
The STK14CA8 protects data from corruption during
low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The low-
CMOS technology provides the STK14CA8 with the
benefit of power supply current that scales with
cycle time. Less current will be drawn as the mem-
ory cycle time becomes longer than 50 ns. Figure 4
voltage condition is detected when V <V
.
CC
SWITCH
shows the relationship between I
WRITE cycle time. Worst-case current consumption
is shown for commercial temperature range,
and READ/
CC
If the STK14CA8 is in a WRITE mode (both E and
W low) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
V
=3.6V, and chip enable at maximum frequency.
CC
Only standby current is drawn when the chip is dis-
abled. The overall average current drawn by the
STK14CA8 depends on the following items:
NOISE CONSIDERATIONS
1
2
3
4
5
6
The duty cycle of chip enable
The overall cycle rate for operations
The ratio of READs to WRITEs
The operating temperature
The VCC Level
The STK14CA8 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1 μF connected between V
and
CC
V
, using leads and traces that are a short as pos-
SS
sible. As with all high-speed CMOS ICs, careful
routing of power, ground, and signals will reduce cir-
cuit noise.
I/O Loading
Figure 4 - Current vs Cycle Time
Rev 1.5
Document Control #ML0022
February 2007
13
STK14CA8
operations is performed in a manner similar to the
software RECALL initiation. To initiate the AutoStore
Enable sequence, the following sequence of E con-
trolled or G controlled READ operations must be per-
formed:
PREVENTING AUTOSTORE
The AutoStore function can be disabled by initiating
an AutoStore Disable sequence. A sequence of
READ operations is performed in a manner similar to
the software STORE initiation. To initiate the
AutoStore Disable sequence, the following sequence
of E controlled or G controlled READ operations
must be performed:
1 Read Address 0x4E38 Valid READ
2 Read Address 0xB1C7 Valid READ
3 Read Address 0x83E0 Valid READ
4 Read Address 0x7C1F Valid READ
5 Read Address 0x703F Valid READ
6 Read Address 0x4B46 AutoStore Enable
1 Read Address 0x4E38 Valid READ
2 Read Address 0xB1C7 Valid READ
3 Read Address 0x83E0 Valid READ
4 Read Address 0x7C1F Valid READ
5 Read Address 0x703F Valid READ
6 Read Address 0x8B45 AutoStore Disable
If the AutoStore function is disabled or re-enabled, a
manual STORE operation (Hardware or Software)
needs to be issued to save the AutoStore state
through subsequent power down cycles. The part
comes from the factory with AutoStore enabled.
The AutoStore can be re-enabled by initiating an
AutoStore Enable sequence. A sequence of READ
ORDERING INFORMATION
STK14CA8-R F 45 I TR
Packing Option
Blank=Tube
TR=Tape and Reel
Temperature Range
Blank=Commercial (0 to +70 C)
I= Industrial (-45 to +85 C)
Access Time
25=25 ns
35=35 ns
45=45 ns
Lead Finish
F=100% Sn (Matte Tin) RoHS Compliant
Package
N=Plastic 32-pin 300 mil SOIC (50 mil pitch)
R=Plastic 48-pin 300 mil SSOP (25 mil pitch)
Rev 1.5
Document Control #ML0022
February 2007
14
STK14CA8
ORDERING CODES
STK14CA8-NF25
STK14CA8-NF35
STK14CA8-NF45
STK14CA8-NF25TR
STK14CA8-NF35TR
STK14CA8-NF45TR
STK14CA8-RF25
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
STK14CA8-RF35
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SOP32-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
3V 128Kx8 AutoStore nvSRAM SSOP48-300
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
STK14CA8-RF45
STK14CA8-RF25TR
STK14CA8-RF35TR
STK14CA8-RF45TR
STK14CA8-NF25I
STK14CA8-NF35I
STK14CA8-NF45I
STK14CA8-NF25ITR
STK14CA8-NF35ITR
STK14CA8-NF45ITR
STK14CA8-RF25I
STK14CA8-RF35I
STK14CA8-RF45I
STK14CA8-RF25ITR
STK14CA8-RF35ITR
STK14CA8-RF45ITR
Rev 1.5
Document Control #ML0022
February 2007
15
STK14CA8
PACKAGE DRAWINGS
32 Pin 300 mil SOIC
0.292 7.42
(
)
0.300 7.60
0.405 10.29
(
)
0.419 10.64
Pin 1
Index
.050 (1.27)
BSC
0.810 20.57
0.822 20.88
)
(
0.026 0.66
0.032 0.81
(
)
0.090 2.29
0.100(2.54)
2.18
0.086
0.12
0.22
0.090 (2.29)
0.004 0.10
0.010(0.25 )
0.014 0.36
0.020 0.51
)
(
MIN
MAX
DIM = INCHES
MIN
DIM = mm
(MAX)
0o
8o
0.006 0.15
( )
0.013 0.32
0.021 0.53
0.041(1.04 )
Rev 1.5
Document Control #ML0022
February 2007
16
STK14CA8
48 Pin 300 mil SSOP
TOP VIEW
0.620 15.75
BOTTOM VIEW
(
)
N
16.00
0.630
0.400
0.410
10.16
10.41
)
(
7.42
7.59
7.42
7.59
0.292
0.299
0.292
0.299
)
(
)
(
.045 11.43
.055 (13.97)
1
2
3
Pin 1 indicator
.045 DIA.
(11.43)
.035
8.89
.045 (11.43)
.020
(5.1)
SIDE VIEW
0.25
0.41
0.010
0.016
(
)
0.008
0.0135
0.203
0.343
0.025
(0.635)
END VIEW
(
)
45°
2.41
2.79
0.095
0.110
0.088
0.092
2.24
2.34
)
(
(
)
0.620 15.75
( )
SEATING
PLANE
16.00
0.630
SEE DETAIL
A
0.20
0.41
0.008
0.016
)
(
MIN
END VIEW
PARTING
LINE
DIM = INCHES
MAX
GAUGE PLANE
0.010
(0.25)
MIN
SEATING PLANE
DIM = mm
(
)
MAX
DETAIL A
0.61
1.02
0.024
0.040
(
)
Rev 1.5
Document Control #ML0022
February 2007
17
STK14CA8
Document Revision History
Rev
0.0
0.1
Date
Change
January 2003
May 2003
Publish New Datasheet
Add 48-pin SSOP, Modify AutoStore Diagram, Update Mode Selection
Table and Absolute Maximum Ratings, Added G controlled software
store.
0.2
1.0
September 2003
December 2004
Added lead-free finish
Parameter
VCAP Min
tVCCRISE
Old Value New Value Notes
10uF
17uF
NA
150 us
50 mA
55 mA
65 mA
55 mA
60 mA
70 mA
3.0 mA
3.0 mA
20 ms
12.5 ms
40 us
New Spec
I
CC1 Max Com.
35 mA
40 mA
50 mA
35 mA
45 mA
55 mA
1.5 mA
0.5 mA
5 ms
@45 ns access
@35 ns access
@25 ns access
@45 ns access
@35 ns access
@25 ns access
Com. & Ind.
ICC1 Max Com.
ICC1 Max Com.
ICC1 Max Ind.
ICC1 Max Ind.
ICC1 Max Ind.
I
CC2 Max
ICC4 Max
tHRECALL
tSTORE
Com. & Ind.
10 ms
20 us
10 ns
tRECALL
tGLQV
12 ns
25 ns device
1.1
August 2005
Parameter
Old Value New Value
Notes
I
CC3 Max Com.
5 mA
5 mA
2 mA
2 mA
40 us
10 mA
10 mA
3 mA
ICC3 Max Ind.
ISB Max Com.
ISB Max Ind.
tRECALL
3 mA
Soft Recall
Industrial Grade
Only
50 us
tSTORE
NVc
12.5 ms
1x106
15 ms
5x105
Contact Simtek For
Details
Rev 1.5
Document Control #ML0022
February 2007
18
STK14CA8
Rev
1.2
Date
Change
September 2005
Added an Extended Temperature Range device tested from -55 degree
C to +85 degree C
1.3
December 2005
Parameter
Old Value
60 us
New Value
Notes
Typographical Error
In Datasheet
50 us
70 us
tRECALL
tSS
Undefined
100 Years at 20 Years @
Unspecified Max
New Data Retention
Temperature Temperature Specification
DATAR
1.4
1.5
March 2006
Removed Lead Plated Lead Finish
February 2007
Parameter
NVC
Old Value
New Value
Notes
New Nonvolatile
Store Cycle Spec
500K
200K
20 Years @ 20 Years @ New Data Retention
85 C
55 C
Spec
DATAR
2.55 V
No Min. Spec
VSWITCH Min.
-10 uA
Not Specified Before
Removed
IOUT (HSB)
tELAX, tGLAX
tEHAX, tGHAX
tDELAY Max.
tHLBL
20 ns
1 ns
New Spec
70 us
New Spec
300ns
Spec Not Required
70 uS Min.
70 uS Max. Typo
Supports Upgrades
From 14C88-3
tSS
57 uF
120 uF
V
CAP Max
Deleted -G Extended Temperature Option
Added tape and reel ordering option
Added product order code listing
Added package drawings
Reformated Entire Document
SIMTEK STK14CA8 Datasheet, February 2007
Copyright 2007, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other
form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be
accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein consti-
tutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
Rev 1.5
Document Control #ML0022
February 2007
19
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