STK14D88-3N25 [SIMTEK]
Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO32, 0.300 INCH, 0.50 MM PITCH, PLASTIC, SOIC-32;
| 型号： | STK14D88-3N25 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO32, 0.300 INCH, 0.50 MM PITCH, PLASTIC, SOIC-32 静态存储器 光电二极管 |
| 文件： | 总15页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK14D88-3
32K x 8 AutoStoreTM nvSRAM
QuantumTrapTM CMOS
Nonvolatile Static RAM
FEATURES
DESCRIPTION
• 25ns, 35ns and 45ns Access Times
• “Hands-off” Automatic STORE on Power Down
with only a small capacitor
• STORE to QuantumTrap™ Nonvolatile
Elements is Initiated by Software , device pin
or AutoStore™ on Power Down
The Simtek STK14D88-3 is a fast static RAM with a
nonvolatile element in each memory cell. The
embedded
nonvolatile
elements
incorporate
Simtek’s QuantumTrap™ technology producing the
world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles,
while independent, nonvolatile data resides in the
highly reliable QuantumTrapTM cell. Data transfers
from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at
power down. On power up, data is restored to the
SRAM (the RECALL operation) from the nonvolatile
memory. Both the STORE and RECALL operations
are also available under software control.
• RECALL to SRAM Initiated by Software or
Power Restore
• Unlimited READ, WRITE and RECALL Cycles
• 5mA Typical ICC at 200ns Cycle Time
• 1,000,000 STORE Cycles to QuantumTrap™
• 100-Year Data Retention to QuantumTrap™
• Single 3V +20%, -10% Operation
• Commercial and Industrial Temperatures
• SSOP and SOIC Packages
• RoHS Compliance
BLOCK DIAGRAM
VCC
VCAP
Quatum Trap
512 X 512
A5
A6
A7
A8
POWER
CONTROL
STORE
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
A9
RECALL
A11
A12
A13
A14
HSB
512 X 512
SOFTWARE
DETECT
A13 – A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
Figure 1. Block Diagram
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
PACKAGES
VCAP
A14
1
2
VCC
48
47
VCAP
A14
1
2
3
4
5
6
VCC
HSB
W
A13
A8
32
31
HSB
3
4
5
6
46
45
44
43
A12
A7
A6
30
29
28
27
A12
A7
A6
W
A13
A8
A9
A11
G
A5
A4
A3
A5
7
8
9
10
11
12
13
14
15
16
A9
42
41
40
39
38
37
36
35
34
33
7
8
9
10
11
12
13
14
15
16
26
25
24
23
22
21
20
19
18
17
A4
A11
A10
E
DQ7
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VSS
VSS
DQ6
DQ5
DQ4
DQ3
DQ0
A3
A2
A1
A0
DQ6
G
A10
E
DQ7
17
18
32
31
30
29
28
27
26
25
32 Pin SOIC
19
20
21
22
23
24
DQ1
DQ2
DQ5
DQ4
DQ3
VCC
48 Pin SSOP
Relative PCB area usage.
See website for detailed
package size specifications.
PIN DESCRIPTIONS
Pin Name
I/O
Description
A14 – A0
Input
I/O
Address: The 15 address inputs select one of 32,752 bytes in the nvSRAM array.
Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
DQ7 –DQ0
E
Chip Enable: The active low
E
input selects the device.
Input
Write Enable: The active low
W
enables data on the DQ pins to be written to the address location latched by
W
G
Input
the falling edge of E
.
Output Enable: The active low
G
input enables the data output buffers during read cycles. De-asserting G
Input
high causes the DQ pins to tri-state.
Power 3.0V +20%, -10%
Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external
VCC
Power Supply
I/O
HSB
to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not
connected. (Connection Optional)
Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile
elements.
VCAP
Power Supply
VSS
(Blank)
Power Supply
No Connect
Ground
Unlabeled pins have no internal connection.
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
ABSOLUTE MAXIMUM RATINGSa
Notes
-0.5V to +4.1V
Power Supply Voltage
Voltage on Input Relative to VSS
Voltage on Outputs
a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
-0.5V to (VCC + 0.5V)
-0.5V to (VCC + 0.5V)
–55°C to 125°C
–55°C to 140°C
–65°C to 150°C
1W
Temperature under Bias
Junction Temperature
Storage Temperature
Power Dissipation
DC Output Current (1 output at a time, 1s duration)
15mA
Package Thermal Characteristics see website: http://www.simtek.com/
DC CHARACTERISTICS
Commercial
Industrial
Symbol
Parameter
Units
mA
mA
mA
Notes
MIN
MAX
65
55
50
MIN
MAX
70
60
55
tAVAV = 25ns
tAVAV = 35ns
tAVAV = 45ns
Average VCC Current
ICC1
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (tSTORE).
Average VCC Current during STORE
Average VCC Current at tAVAV = 200ns
3V, 25°C, Typical
ICC2
ICC3
ICC4
ISB
3
3
mA
W
≥ (VCC – 0.2V)
All Others Inputs Cycling, at CMOS Levels.
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE).
5
3
5
3
mA
mA
Average VCAP Current during
AutoStore™ Cycle
VCC Standby Current
E
≥ (VCC – 0.2V)
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Standby current level after nonvolatile
cycle is complete.
(Standby, Stable CMOS Input Levels)
2
2
mA
µA
VCC = max
Input Leakage Current
IILK
±1
±1
±1
VIN = VSS to VCC
VCC = max
Off-State Output Leakage Current
IOLK
VIN = VSS to VCC, E or G ≥ VIH
±1
VCC + 0.3
0.8
µA
V
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
VIH
VIL
2.0
V
CC + 0.3
0.8
2.0
VSS – 0.5
2.4
All Inputs
All Inputs
V
SS – 0.5
2.4
V
VOH
VOL
TA
V
IOUT = –2mA
0.4
70
0.4
85
V
IOUT = 4mA
0
–40
2.7
17
oC
VCC
VCAP
2.7
17
3.6
57
3.6
57
V
3.0V +20%, -10%
Between Vcap pin and Vss, 5V rated.
Storage Capacitor
µF
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
AC TEST CONDITIONS
0V to 3V
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
≤ 5ns
1.5V
Output Load
See Figure 2 and Figure 3
CAPACITANCEb
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
pF
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
CIN
Input Capacitance
Output Capacitance
7
7
COUT
pF
Notes
b: These parameters are guaranteed but not tested
3.0V
3.0V
577 Ohms
577 Ohms
OUTPUT
OUTPUT
5 pF
30 pF
INCLUDING
SCOPE AND
FIXTURE
789 Ohms
789 Ohms
INCLUDING
SCOPE AND
FIXTURE
Figure 2. AC Output Loading
Figure 3. AC Output Loading,
for tristate specs (
tHZ, tLZ, tWLQZ, tWHQZ
tGLQX, tGHQZ
,
)
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
SRAM READ CYCLES #1 & #2
SYMBOLS
STK14D88-3-25
STK14D88-3-35
STK14D88-3-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
tACS
MIN
MAX
MIN
MAX
MIN
MAX
tELQV
1
2
Chip Enable Access Time
Read Cycle Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c
c
tAVAV
tAVAV
tRC
tAA
tOE
tOH
tLZ
25
35
45
d
tAVQV
3
Address Access Time
25
12
35
15
45
20
tGLQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
d
tAXQX
5
3
3
3
3
3
3
tELQX
tEHQZ
tGLQX
6
e
tHZ
tOLZ
tOHZ
tPA
tPS
7
10
10
25
13
13
35
15
15
45
8
0
0
0
0
0
0
e
tGHQZ
9
b
tELICC
10
b
tEHICC
11
Notes
c:
W
must be high during SRAM READ cycles
and
d: Device is continuously selected with
E
G
both low
e: Measured ± 200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlledc,d,f
2
tAVAV
ADDRESS
3
tAVQV
5
tAXQX
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2: E Controlledc,f
2
tAVAV
ADDRESS
1
tELQV
11
tEHICCL
6
tELQX
E
7
tEHQZ
G
9
tGHQZ
4
tGLQV
8
tGLQX
DQ (DATA OUT)
DATA VALID
10
tELICCH
ACTIVE
STANDBY
ICC
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
STK14D88-3-25 STK14D88-3-35 STK14D88-3-45 UNITS
PARAMETER
#1
#2
Alt.
tWC
tWP
tCW
tDW
tDH
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
Write Cycle Time
12
13
14
15
16
17
18
19
20
21
tAVAV
tWLWH
tELWH
tDVWH
tWHDX
tAVWH
tAVWL
tWHAX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
tAW
tAS
20
0
25
0
30
0
tWR
tWZ
tOW
0
0
0
e,g
tWLQZ
10
13
15
tWHQX
3
3
3
Notes
g: If
h:
W
is low when E goes low, the outputs remain in the high-impedance state.
E
or
W
must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledh,f
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
13
tWLWH
tAVWL
W
15
16
tDVWH
tWHDX
DATA VALID
DATA IN
20
tWLQZ
21
tWHQX
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
SRAM WRITE CYCLE #2: E Controlledh,f
12
tAVAV
ADDRESS
14
tELEH
18
tAVEL
19
tEHAX
E
17
tAVEH
13
tWLEH
W
16
tEHDX
15
tDVEH
DATA VALID
DATA IN
HIGH IMPEDANCE
DATA OUT
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
MODE SELECTION
E
W
G
A13 - A0
MODE
I/O
POWER
NOTES
H
L
L
X
H
L
X
L
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
Standby
Active
X
Active
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
L
L
H
H
L
L
Active
Active
i, j, k
Autostore Disable
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
i, j, k
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
ICC2
L
L
H
H
L
L
i, j, k
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
i, j, k
Nonvolatile Recall
Notes
i: The six consecutive addresses must be in the order listed.
j: While there are 15 addresses on the STK14D88-3, only the lower 14 are used to control software modes
W
must be high during all six consecutive cycles to enable a nonvolatile cycle.
k: I/O state depends on the state of
G
. The I/O table shown assumes
G
low.
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
AutoStore™ /POWER-UP RECALL
SYMBOLS
NO.
PARAMETER
STK14D88-3
UNITS
NOTES
Standard
Alternate
MIN
MAX
22
23
24
25
tHRECALL
20
ms
ms
V
l
Power-up RECALL Duration
tSTORE
tHLHZ
12.5
2.65
m
STORE Cycle Duration
VSWITCH
tVCCRISE
2.55
150
Low Voltage Trigger Level
µs
V
CC Rise Time
Notes
l: tHRECALL starts from the time VCC rises above VSWITCH
m: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
STORE occurs only if a
SRAM write has
happened.
No STORE occurs
without at least one
SRAM write.
AutoStore™/POWER-UP RECALL
VCC
24
VSWITCH
25
tVCCRISE
AutoStoreTM
23
tSTORE
23
tSTORE
POWER-UP RECALL
22
tHRECALL
22
tHRECALL
Read & Write Inhibited
POWER DOWN
BROWN OUT
POWER-UP
RECALL
POWER-UP
RECALL
AutoStoreTM
AutoStoreTM
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH.
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
SOFTWARE-CONTROLLED STORE/RECALL CYCLEn,o
SYMBOLS
STK14D88-3-25
STK14D88-3-35
STK14D88-3-45
NO.
PARAMETER
UNITS
NOTES
o
E
G
cont
tAVAV
Alt.
tRC
MIN
MAX
MIN
MAX
MIN
MAX
cont
tAVAV
26
27
25
0
35
0
45
0
ns
ns
ns
ns
µs
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
tAVEL
tAVGL
tAS
28
tELEH
tELAX
tGLGH
tGLAX
tCW
20
20
25
20
30
20
29
Address Hold Time
30
tRECALL
tRECALL
40
40
40
RECALL Duration
Notes
n: The software sequence is clocked with
E
controlled READs or G controlled READs.
o: The six consecutive addresses must be read in the order listed in the Mode Selection Table.
W
must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
26
tAVAV
26
tAVAV
ADDRESS #1
ADDRESS #6
ADDRESS
E
27
tAVEL
28
tELEH
29
tELAX
G
23
30
/
tSTORE tRECALL
HIGH IMPEDENCE
DATA VALID
DQ (DATA)
DATA VALID
SOFTWARE STORE/RECALL CYCLE: G Controlledo
26
26
tAVAV
tAVAV
ADDRESS #1
ADDRESS #6
ADDRESS
E
28
tGLGH
27
tAVGL
G
30
tRECALL
23
tSTORE
/
29
tGLAX
HIGH IMPEDENCE
DATA VALID
DATA VALID
DQ (DATA)
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
HARDWARE STORE CYCLE
SYMBOLS
NO.
STK14D88-3
PARAMETER
UNITS
NOTES
Standard
tDELAY
tHLHX
tHLBL
Alternate
MIN
MAX
tHLQZ
31
32
33
Time Allowed to Complete SRAM Cycle
Hardware STORE Pulse Width
1
µs
ns
ns
p
15
Hardware STORE Low to STORE Busy
300
Notes
p: Read and Write cycles in progress before HSB is asserted are given this amount of time to complete.
HARDWARE STORE CYCLE
32
tHLHX
HSB (IN)
23
tSTORE
33
tHLBL
HSB (OUT)
HIGH IMPEDENCE
DATA VALID
HIGH IMPEDENCE
31
tDELAY
DQ (DATA OUT)
DATA VALID
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
DEVICE OPERATION
nvSRAM
SRAM WRITE
The STK14D88-3 nvSRAM is made up of two
functional components paired in the same physical
cell. These are a SRAM memory cell and a
nonvolatile QuantumTrap™ cell. The SRAM memory
cell operates as a standard fast static RAM. Data in
the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell
to SRAM (the RECALL operation). This unique
architecture allows all cells to be stored and recalled
in parallel. During the STORE and RECALL
operations SRAM READ and WRITE operations are
inhibited. The STK14D88-3 supports unlimited reads
and writes just like a typical SRAM. In addition, it
provides unlimited RECALL operations from the
nonvolatile cells and up to 1 million STORE
operations.
A WRITE cycle is performed whenever E and
W
are low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry will
turn off the output buffers tWLQZ after W goes low.
AutoStore™ OPERATION
The STK14D88-3 stores data to nvSRAM using one of
three storage operations. These three operations are
Hardware Store, activated by HSB , Software Store,
actived by an address sequence, and AutoStore™, on
device power down.
SRAM READ
The STK14D88-3 performs a READ cycle whenever
E
and
G
are low while
W
and HSB are high.
The address specified on pins A14-0 determines which
of the 32,752 data bytes will be accessed. When the
READ is initiated by an address transition, the
outputs will be valid after a delay of tAVQV (READ
cycle #1). If the READ is initiated by E or G , the
outputs will be valid at tELQV or at tGLQV, whichever is
later (READ cycle #2). The data outputs will
repeatedly respond to address changes within the
tAVQV access time without the need for transitions on
any control input pins, and will remain valid until
another address change or until E or G is brought
high, or W or HSB is brought low.
AutoStore™ operation is a unique feature of Simtek
QuantumTrap™ technology and is enabled by default
on the STK14D88-3.
During normal operation, the device will draw current
from Vcc to charge a capacitor connected to the Vcap
pin. This stored charge will be used by the chip to
perform a single STORE operation. If the voltage on
the Vcc pin drops below Vswitch, the part will
automatically disconnect the Vcap pin from Vcc. A
STORE operation will be initiated with power provided
by the Vcap capacitor.
VCC
Figure 4 shows the proper connection of the storage
capacitor (Vcap) for automatic store operation. Refer
to the DC CHARACTERISTICS table for the size of
Vcap. The voltage on the Vcap pin is driven to 5V by a
charge pump internal to the chip. A pull up should be
placed on W to hold it inactive during power up.
VCAP
VCC
W
To reduce unneeded nonvolatile stores, AutoStore™
and Hardware Store operations will be ignored unless
at least one WRITE operation has taken place since
the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The
HSB signal can be monitored by the system to detect
an AutoStore™ cycle is in progress.
Figure 4: AutoStoreTM Mode
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
SOFTWARE STORE
HARDWARE STORE ( HSB ) OPERATION
Data can be transferred from the SRAM to the
nonvolatile memory by a software address sequence.
The STK14D88-3 software STORE cycle is initiated
The STK14D88-3 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK14D88-3 will
by executing sequential
E
controlled READ cycles
from six specific address locations in exact order.
During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE
cycle is initiated, further input and output are disabled
until the cycle is completed.
conditionally initiate a STORE operation after tDELAY
.
An actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a
busy condition while the STORE (initiated by any
means) is in progress.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important
that no other READ or WRITE accesses intervene in
the sequence, or the sequence will be aborted and no
STORE or RECALL will take place.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK14D88-3
will continue SRAM operations for tDELAY. During
tDELAY, multiple SRAM READ operations may take
place. If a WRITE is in progress when HSB is pulled
low it will be allowed a time, tDELAY, to complete.
However, any SRAM WRITE cycles requested after
HSB goes low will be inhibited until HSB returns
high.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
During any STORE operation, regardless of how it
was initiated, the STK14D88-3 will continue to drive
the HSB pin low, releasing it only when the STORE
is complete. Upon completion of the STORE
operation the STK14D88-3 will remain disabled until
the HSB pin returns high.
The software sequence may be clocked with
controlled READs or G controlled READs.
E
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up, or after any low-power condition
(VCC < VSWITCH), an internal RECALL request will be
latched. When VCC once again exceeds the sense
SOFTWARE RECALL
voltage of VSWITCH
automatically be initiated and will take tHRECALL to
complete.
,
a
RECALL cycle will
Data can be transferred from the nonvolatile memory
to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence of
READ operations in a manner similar to the software
STORE initiation. To initiate the RECALL cycle, the
following sequence of E controlled READ operations
must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
January 2005
12
Document Control #ML0033 rev 1.1
STK14D88-3
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the
nonvolatile information is transferred into the SRAM
cells. After the tRECALL cycle time the SRAM will once
again be ready for READ and WRITE operations.
The RECALL operation in no way alters the data in
the nonvolatile elements.
NOISE CONSIDERATIONS
The STK14D88-3 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCC and VSS,
using leads and traces that are as short as possible.
As with all high-speed CMOS ICs, careful routing of
power, ground and signals will reduce circuit noise.
PREVENTING AUTOSTORETM
LOW AVERAGE ACTIVE POWER
The AutoStore™ function can be disabled by initiat-
ing an AutoStore Disable sequence. A sequence of
read operations is performed in a manner similar to
the software STORE initiation. To initiate the
AutoStore Disable sequence, the following sequence
of E controlled read operations must be performed:
CMOS technology provides the STK14D88-3 this the
benefit of drawing significantly less current when it is
cycled at times longer than 50ns. Figure 5 shows the
relationship between ICC and READ/WRITE cycle
time. Worst-case current consumption is shown for
commercial temperature range, VCC = 3.6V, and chip
enable at maximum frequency. Only standby current
is drawn when the chip is disabled. The overall
average current drawn by the STK14D88-3 depends
on the following items:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
AutoStore Disable
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. The operating temperature.
5. The VCC level.
The AutoStore™ can be re-enabled by initiating an
AutoStore Enable sequence. A sequence of read
operations is performed in a manner similar to the
software RECALL initiation. To initiate the AutoStore
Enable sequence, the following sequence of
E
6. I/O loading.
controlled read operations must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
AutoStore Enable
50
40
30
If the AutoStore™ function is disabled or re-enabled
a manual STORE operation (Hardware or Software)
needs to be issued to save the AutoStore state
through subsequent power down cycles. The part
comes from the factory with AutoStore™ enabled.
Writes
20
DATA PROTECTION
10
Reads
The STK14D88-3 protects data from corruption
during low-voltage conditions by inhibiting all
externally initiated STORE and WRITE operations.
0
The low-voltage condition is detected when VCC
VSWITCH .
<
50 100 150 200 300
Cycle Time (ns)
If the STK14D88-3 is in a WRITE mode (both
E
and W low ) at power-up, after a RECALL, or after
a STORE, the WRITE will be inhibited until a
negative transition on E or
protects against inadvertent writes during power up
or brown out conditions.
W
is detected. This
Figure 5 Current vs. Cycle time
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
ORDERING INFORMATION
STK14D88-3 R F 45 I
Temperature Range
Blank = Commercial (0 to 70ºC)
I = Industrial (-40 to 85ºC)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
Blank = 85% Sn / 15% Pb
F = 100% Sn (Matte Tin) RoHS Compliant
Package
N = Plastic 32-pin 300 mil SOIC (50 mil pitch)
R = Plastic 40-pin 300 mil SSOP (25 mil pitch)
January 2005
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Document Control #ML0033 rev 1.1
STK14D88-3
Document Revision History
Revision
1.0
Date
Summary
December 2004
January 2005
Initial Revision
Changed Vcap MAX from 120 µF down to 57 µF.
1.1
SIMTEK STK14D88-3 Data Sheet, January 2005
Copyright 2005, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the express use of Simtek Customers. No part of this datasheet may be reproduced in any
other form or means without express written permission from Simtek Corporation. The information contained in this publication is
believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any
warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its
use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark or other
proprietary right.
January 2005
15
Document Control #ML0033 rev 1.1
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