STK17C88-R25 [SIMTEK]
Real Time Clock, CMOS, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | STK17C88-R25 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | Real Time Clock, CMOS, PDSO48, 0.300 INCH, SSOP-48 时钟 双倍数据速率 光电二极管 外围集成电路 |
| 文件： | 总22页 (文件大小：572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK17C88
nvTime™Event Data Recorder
32K x 8 AutoStore™ nvSRAM
with Real-Time Clock
Product Preview
FEATURES
DESCRIPTION
• Data Integrity of Simtek nvSRAM Combined
The Simtek STK17C88 combines a 256 Kbit nonvol-
atile static RAM with a full-featured real-time clock in
a reliable, monolithic integrated circuit. The embed-
ded nonvolatile elements incorporate Simtek’s
QuantumTrap™ technology producing the world’s
most reliable nonvolatile memory. The SRAM can be
read and written an unlimited number of times, while
independent, nonvolatile data resides in the nonvol-
atile elements.
with Full-Featured Real-Time Clock
• 25ns, 35ns and 45ns Access Times
• Software or AutoStore™STORE to Quan-
tumTrap™ Nonvolatile Elements
• RECALL to SRAM Initiated by Software or
Power Restore
• Unlimited READ, WRITE and RECALL Cycles
• 100-Year Data Retention
• Watchdog Timer
The Real-Time Clock function provides an accurate
clock with leap year tracking and a programmable,
high accuracy oscillator. The Alarm function is pro-
grammable for one-time alarms or periodic seconds,
minutes, hours, or days. There is also a programma-
ble Watchdog Timer for process control.
• Clock Alarm with programmable Interrupts
• Capacitor or battery backup for RTC
• Single 3V +20%, -10% Operation
• Commercial and Industrial Temperatures
• Packages: 48 pin SSOP, 40 pin DIP
BLOCK DIAGRAM
HSB
V
V
CAP
CCX
Quantum Trap
512 x 512
A5
V
STORE/
RECALL
rtcbat
A6
POWER
STORE
A7
Vrtccap
CONTROL
CONTROL
A8
STATIC RAM
ARRAY
A9
RECALL
A11
A12
A13
A14
SOFTWARE
DETECT
512 x 512
A - A
0 14
X
1
2
X
RTC
MUX
DQ
DQ
DQ
0
1
2
COLUMN I/O
INT
COLUMN DEC
DQ
3
4
DQ
A
A
-
0
DQ
DQ
DQ
5
6
7
14
A
A A A A A
1 2 3 4 10
0
G
E
W
June 2003
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Document Control # ML0024 rev 0.0
STK17C88
PACKAGES
48 Pin 300 mil SSOP
40 Pin 600 mil DIP
(not to scale)
PIN DESCRIPTIONS
Pin Name
I/O
Description
A - A
Input
I/O
Address: The 15 address inputs select one of 32,752 bytes in the
0
14
nvSRAM array or one of 16 bytes in the clock register map.
Data: Bi-directional 8-bit data bus for accessing the nvSRAM array and
clock.
DQ -DQ
0
7
Input
Input
E
W
Chip Enable: The active low E input selects the device.
Write Enable: The active low W enables data on the DQ pins to be
written to the adddress location latched by the falling edge of E.
Input
Input
Power Supply
Power Supply
Power Supply
I/O
G
Output Enable: The active low G input enables the data output buffers
during read cycles. Deasserting G high causes the DQ pins to tri-state.
X , X
Crystal: Connections for 32.768 kHz crystal.
Capacitor RTC supply voltage.
Battery RTC supply voltage.
Power (+ 3V)
1
2
V
rtccap
V
rtcbat
V
CCX
HSB
INT
Hardware Store Busy (I/O)
Output
Interrupt Output: Can be programmed to respond to the clock alarm,
the watchdog timer and the power monitor. Programmable to either
active high (push/pull) or active low (open-drain).
V
V
Power Supply
Power Supply
Autostore Capacitor: Supplies power to nvSRAM during power loss to
CAP
store data from SRAM to nonvolatile elements.
Ground
SS
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Document Control # ML0024 rev 0.0
STK17C88
ABSOLUTE MAXIMUM RATINGSa
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Power Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . .–0.5V to +3.9V
Voltage on Input Relative to VSS . . . . . . . . . . –0.5V to (V + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (V + 0.5V)
CC
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . .15mA
CC
DC CHARACTERISTICS(VCC = 3.0V +20%, -10%)e
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V Current
70
60
55
75
65
60
mA
mA
mA
t
t
t
= 25ns
= 35ns
= 45ns
CC
CC
AVAV
AVAV
AVAV
1
c
I
I
Average V Current during STORE
1
1
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
b
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
AVAV
CC
3
5
5
mA
3V, 25°C, Typical
All Others Cycling, CMOS Levels
c
I
I
I
I
I
Average V
Current during
CAP
All Inputs Don’t Care
CC
4
0.5
0.3
±1
0.5
0.3
±1
mA
mA
µA
AutoStore™ Cycle
d
V
Standby Current
E ≥ (V – 0.2V)
CC
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
SB
CC
(Standby, Stable CMOS Input Levels)
Input Leakage Current
V
V
= max
CC
ILK
= V to V
CC
IN
SS
Off-State Output Leakage Current
V
V
= max
CC
OLK
BAK
±1
±1
µA
= V to V , E or G ≥ V
IH
IN
SS
CC
RTC Backup Current
RTC Backup Voltage
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
200
300
nA
V
V
V
V
V
V
1.6
2.0
1.6
2.0
BAK
IH
V
+ .3
V
+ .3
CC
V
All Inputs
All Inputs
CC
V
– .5
0.8
V – .5
SS
0.8
V
IL
SS
2.4
2.4
V
I
I
=–2mA
= 4mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
T
0
–40
°C
A
Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC3 are the average currents required for the duration of the respective STORE cycles (tSTORE ).
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Note e: VCC reference levels throughout this datasheet refer to VCCX
.
3.0V
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
577 Ohms
OUTPUT
30 pF
789 Ohms
INCLUDING
SCOPE AND
FIXTURE
CAPACITANCEf
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
C
C
Input Capacitance
Output Capacitance
5
7
pF
IN
pF
OUT
Figure 1: AC Output Loading
Note f: These parameters are guaranteed but not tested.
June 2003
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Document Control # ML0024 rev 0.0
STK17C88
SRAM READ CYCLES #1 & #2
(VCC = 3.0V +20%, -10%)e
SYMBOLS
STK17C88-25
STK17C88-35
STK17C88-45
NO.
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
Read Cycle Time
25
35
45
AVAV
h
3
Address Access Time
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
h
5
3
3
3
3
3
3
AXQX
6
ELQX
i
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
i
9
GHQZ
f
f
10
11
ELICCH
EHICCL
PS
Note g: W must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledg
2
t
AVAV
ADDRESS
E
1
11
t
ELQV
t
EHICCL
6
t
ELQX
7
t
EHQZ
G
9
4
t
GHQZ
t
GLQV
8
t
GLQX
DATA VALID
DQ (DATA OUT)
10
t
ELICCH
ACTIVE
STANDBY
I
CC
June 2003
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Document Control # ML0024 rev 0.0
DATA VALID
STK17C88
SRAM WRITE CYCLES #1 & #2
(VCC = 3.0V +20%, -10%)e
SYMBOLS
STK17C88-25 STK17C88-35 STK17C88-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
20
0
25
0
30
0
AVWH
AVEH
AW
t
t
t
AVWL
WHAX
AVEL
EHAX
AS
t
t
t
0
0
0
WR
i, j
t
t
10
13
15
WLQZ
WZ
t
t
3
3
3
WHQX
OW
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM write cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12
t
AVAV
ADDRESS
19
14
t
WHAX
t
ELWH
E
17
t
AVWH
18
t
AVWL
13
t
W
DATA IN
WLWH
15
16
t
t
DVWH
WHDX
20
t
WLQZ
21
t
WHQX
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledk, l
12
t
AVAV
ADDRESS
18
14
19
t
t
t
AVEL
ELEH
EHAX
E
17
t
AVEH
13
t
WLEH
W
15
16
t
t
DVEH
EHDX
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
June 2003
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Document Control # ML0024 rev 0.0
STK17C88
MODE SELECTION
E
H
L
W
X
H
L
G
X
L
A
- A (hex)
0
MODE
I/O
POWER
Standby
Active
NOTES
15
X
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
L
X
Active
0E38
31C7
03E0
3C1F
303F
0B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Autostore Inhibit
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
L
L
L
L
H
H
H
H
L
L
L
L
m, n, o
m, n, o
0E38
31C7
03E0
3C1F
303F
3B46
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Read SRAM
Active
Active
Read SRAM
Read SRAM
Autostore inhibit off
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
m, n, o
m, n, o
l
CC
2
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
Active
Read SRAM
Read SRAM
Nonvolatile Recall
Note m: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note n: While there are 15 addresses on the STK17C88, only the lower 14 are used to control software modes.
Note o: I/O state depends on the state of G. The I/O table shown assumes G low.
June 2003
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Document Control # ML0024 rev 0.0
STK17C88
AutoStore™/POWER-UP RECALL
(VCC = 3.0V +20%, -10%)e
SYMBOLS
STK17C88
NO.
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
MAX
5
22
23
24
t
t
Power-up RECALL Duration
STORE Cycle Duration
ms
ms
V
p
RESTORE
STORE
t
10
q
HLHZ
V
Low Voltage Trigger Level
2.55
2.65
SWITCH
Note p: tRESTORE starts from the time VCC rises above VSWITCH
.
Note q: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
AutoStore™/POWER-UP RECALL
V
CC
24
V
SWITCH
AutoStore™
23
t
STORE
POWER-UP RECALL
22
t
RESTORE
W
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
NO STORE if
NO SRAM WRITES
BROWN OUT
AutoStore™ Recall
when Vcc returns
above Vswitch
POWER DOWN
AutoStore™
June 2003
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Document Control # ML0024 rev 0.0
STK17C88
SOFTWARE-CONTROLLED STORE/RECALL CYCLEs
(VCC = 3.0V +20%, -10%)e
SYMBOLS
STK17C88-25 STK17C88-35 STK17C88-45
NO.
PARAMETER
UNITS NOTES
E cont
G cont
Alternate
MIN
25
0
MAX
MIN
35
0
MAX
MIN
45
0
MAX
25
26
27
28
29
t
t
t
t
t
t
t
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
Clock Pulse Width
ns
ns
ns
ns
µs
s
AVAV
AVAV
RC
AS
AVEL
AVGL
20
20
25
20
30
20
ELEH
ELAX
RECALL
GLGH
GLAX
RECALL
CW
Address Hold Time
RECALL Duration
20
20
20
Note r: The software sequence is clocked with E controlled READs or G controlled READs.
Note s: The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (4E38, B1C7, 83E0, 7C1F, 703F, 8FC0) for a
STORE cycle or (4E38, B1C7, 83E0, 7C1F, 703F, 4C63) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDs
25
AVAV
25
AVAV
t
t
ADDRESS #1
ADDRESS #6
ADDRESS
26
AVEL
27
ELEH
t
t
E
28
ELAX
t
G
23
29
t
STORE / t
RECALL
HIGH IMPEDANCE
DQ (DATA)
DATA VALID
DATA VALID
SOFTWARE STORE/RECALL CYCLE: G CONTROLLEDs
25
AVAV
25
AVAV
t
t
ADDRESS #1
ADDRESS #6
ADDRESS
E
26
AVGL
27
GLGH
t
t
G
23
29
t
STORE / t
RECALL
28
t
GLAX
HIGH IMPEDANCE
DQ (DATA)
DATA VALID
DATA VALID
June 2003
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Document Control # ML0024 rev 0.0
STK17C88
HARDWARE STORE CYCLEt (V = 3.0V +20%, -10%)
e
CC
SYMBOLS
STK17C88
MIN MAX
NO.
PARAMETER
UNITS NOTES
Standard
Alternate
30
31
32
33
34
t
t
t
t
t
t
t
t
STORE Cycle Duration
10
ms
µs
ns
ns
ns
i
i
STORE
DELAY
RECOVER
HLHX
HLHZ
HLQZ
HHQX
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
1
100
300
t
15
Hardware STORE Low to STORE Busy
HLBL
Note t: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
33
t
HLHX
HSB (IN)
32
t
RECOVER
30
t
STORE
34
t
HLBL
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
31
t
DELAY
DATA VALID
DQ (DATA OUT)
DATA VALID
June 2003
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Document Control # ML0024 rev 0.0
STK17C88
nvSRAM
The STK17C88 has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast
static RAM. In nonvolatile mode, data is transferred
from SRAM to the nonvolatile elements (the STORE
operation) or from the nonvolatile elements to SRAM
(the RECALL operation). In this mode SRAM func-
tions are disabled. The STK17C88 supports unlim-
ited reads and writes to the SRAM, unlimited recalls
from the nonvolatile elements and up to 1 million
stores to the nonvolatile elements
DEVICE OPERATION
current from VCCX to charge a capacitor connected to
the VCAP pin. This stored charge will be used by the
chip to perform a single STORE operation. After
power up, when the voltage on the VCCX pin drops
below VSWITCH, the part will automatically disconnect
the VCAP pin from VCCX and initiate a STORE opera-
tion.
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 10µF and
100µF (± 20%) rated at minimum of 5V should be
provided.
In order to prevent unneeded STORE operations,
automatic STOREs as well as those initiated by
externally driving HSB low, will be ignored unless at
least one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software initi-
ated STORE cycles are performed regardless of
whether a WRITE operation has taken place. HSB
can be used to signal the system that the
AutoStore™ cycle is in progress.
SRAM READ
The STK17C88 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-16 determines which of the 131,072 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high, or W is brought low.
10k
Ω
Vccx
W
Vcap
+
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
Vss
Figure 2: AutoStore™ Mode
If HSB is not used it should be left unconnected
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
HSB OPERATION
The STK17C88 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK17C88 will
AutoStore™ OPERATION
The STK17C88 can be powered in one of three
conditionally initiate a STORE operation after tDELAY
;
modes.
an actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
During normal operation, the STK17C88 will draw
June 2003
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STK17C88
RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a
busy condition while the STORE (initiated by any
means) is in progress.
SOFTWARE NONVOLATILE STORE
The STK17C88 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations. During the STORE
cycle an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvol-
atile elements. The program operation copies the
SRAM data into nonvolatile memory. Once a STORE
cycle is initiated, further input and output are dis-
abled until the cycle is completed.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK17C88 will
continue SRAM operations for tDELAY. During tDELAY
,
multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence, or the sequence will be
aborted and no STORE or RECALL will take place.
The HSB pin can be used to synchronize one
STK17C88 with one or more STK14CA8 nvSRAMs
to expand the memory space. To operate in this
mode the HSB pins from each device should be
connected together. An external pull-up resistor to +
3.0V is required since HSB acts as an open drain
pull down. The VCAP pins from the other parts can be
tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
devices detects a power loss and asserts HSB, the
common HSB pin will cause all parts to request a
STORE cycle (a STORE will take place in those
devices that have been written since the last nonvol-
atile cycle).
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence may be clocked with E con-
trolled READs or G controlled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
During any STORE operation, regardless of how it
was initiated, the STK17C88 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK17C88 will remain disabled until the HSB
pin returns high.
SOFTWARE NONVOLATILE RECALL
If HSB is not used, it should be left unconnected.
A software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of E controlled READ opera-
tions must be performed:
POWER-UP RECALL
During power up, or after any low-power condition
(VCCX < VSWITCH), an internal RECALL request will be
latched. When VCAP once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
Valid READ
Valid READ
Valid READ
Valid READ
If the STK17C88 is in a WRITE state at the end of
power-up RECALL, the WRITE will be inhibited and E
or W must be brought high and then low for a write
to initiate.
Valid READ
Initiate RECALL cycle
Int6e.rnRaellayd, aRdEdCreAssLL is0aC6tw3 o(h-esxt)ep procedure. First, the
SRAM data is cleared, and second, the nonvolatile
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WRITEs will be inhibited.
information is transferred into the SRAM cells. After
the tRECALL cycle time the SRAM will once again be
ready for READ and WRITE operations. The RECALL
operation in no way alters the data in the nonvolatile
elements.
LOW AVERAGE ACTIVE POWER
The STK17C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 3
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
commercial temperature range, VCC = 3.6V, and
100% duty cycle on chip enable. Figure 4 shows the
same relationship for WRITE cycles. If the chip
enable duty cycle is less than 100%, only standby
current is drawn when the chip is disabled. The
overall average current drawn by the STK17C88
depends on the following items: 1) the duty cycle of
chip enable; 2) the overall cycle rate for accesses;
3) the ratio of READs to WRITEs; 4) the operating
PREVENTING STORES
The AutoStore™ function can be disabled by initiat-
ing an AutoStore Inhibit sequence. A sequence of
read operations is performed in a manner similar to
the software STORE initiation. To initiate the
AutoStore Inihibit sequence, the following sequence
of E controlled read operations must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0B45 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
AutoStore Inhibit
temperature; 5) the V level; and 6) I/O loading.
cc
50
40
30
The AutoStore Inhibit can be disabled by initiating
an AutoStore Inhibit Off sequence. A sequence of
read operations is performed in a manner similar to
the software RECALL initiation. To initiate the
AutoStore Inhibit Off sequence, the following
sequence of E controlled read operations must be
performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
20
10
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
3B46 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
0
Valid READ
AutoStore Inhibit Off
50
100
150
200
Cycle Time (ns)
The last AutoStore Inhibit state is stored in nonvola-
tile memory and is retained through power cycling.
Figure 3: Icc (max) Reads
50
40
30
NOISE CONSIDERATIONS
The STK17C88 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCAP and
VSS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
20
10
HARDWARE WRITE PROTECT
The STK17C88 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs dur-
ing low-voltage conditions. When VCCX < VSWITCH, all
externally initiated STORE operations and SRAM
0
50
100
150
200
Cycle Time (ns)
Figure 4: Icc (max) Writes
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actual clock counters, after which the clock resumes
normal operation.
nvTIME OPERATION
The STK17C88 offers internal registers that contain
Clock, Alarm, Watchdog, Interrupt, and Control func-
tions. Internal double buffering of the clock and the
clock/timer information registers prevents accessing
transitional internal clock data during a read or write
operation. Double buffering also circumvents dis-
rupting normal timing counts or clock accuracy of
the internal clock while accessing clock data. Clock
and Alarm Registers store data in BCD format.
Refer to the Register Map Detail on page 17.
BACKUP POWER
The STK17C88 is intended for permanently pow-
ered operation, but when primary power, Vcc, fails
and drops below Vswitch the device will switch to
backup power from either Vbakcap or Vbakbat,
depending on whether a capacitor or battery is cho-
sen for the application.
CLOCK OPERATIONS
The clock oscillator uses very little current, which
maximizes the backup time available from the
backup source. Regardless of clock operation with
the primary source removed, the data stored in
vSRAM is secure, having been stored in the nonvol-
atile elements as power was lost. Factors to be con-
sidered when choosing a backup power source
include: the expected duration of power outages and
the cost tradeoff of using a battery versus a capaci-
tor.
The clock registers maintain time up to 9,999 years
in one second increments. The user can set the time
to any calendar time and the clock automatically
keeps track of days of the week and month, leap
years and century transitions. There are eight regis-
ters dedicated to the clock functions which are used
to set time with a write cycle and to read time during
a read cycle. These registers contain the Time of
Day in BCD format. Bits defined as “X” are currently
not used and are reserved for future use by Simtek.
During backup operation the STK17C88 consumes
a maximum of 300 nanoamps at 2 volts. Capacitor
or battery values should be chosen according to the
application. Backup time values based on maximum
current specs are shown below. Nominal times are
approximately 3 times longer.
READING THE CLOCK
While the double-buffered RTC register structure
reduces the chance of reading incorrect data from the
clock, the user should halt internal updates to the
STK17C88 clock registers before reading clock data
to prevent the reading of data in transition. Stopping
the internal register updates does not affect clock
accuracy.
Capacitor Value
0.1 F
Backup Time
72 hours
14 days
30 days
0.47 F
1.0 F
The updating process is stopped by writing a “1” to
the read bit (in the control register 1FFF0h), and will
not restart until a “0” is written to the read bit. The
RTC registers can then be read while the internal
clock continues to run.
Using a capacitor has the obvious advantage of
recharging the backup source each time the system
is powered up.
If a battery is used a 3V lithium is recommended and
the STK17C88 will only source current from the bat-
tery when the primary power is removed. The bat-
tery will not, however, be recharged at any time by
the STK17C88. The battery capacity should be cho-
sen for total anticipated cumulative down-time
required over the life of the system.
Within 10 msec after a “0” is written to the read bit,
all STK17C88 registers are simultaneously updated.
Refer to the Register Map Detail on page 17.
SETTING THE CLOCK
Setting the write bit (in the control register 1FFF0h)
to a “1” halts updates to the STK17C88 registers.
The correct day, date and time can then be written
into the registers in 24-hour BCD format. Resetting
the write bit to “0” transfers those values to the
STOPPING AND STARTING THE OSCIL-
LATOR
The oscillator may be stopped at any time. This fea-
ture may be used to save battery or capacitor
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energy during long-term storage to increase shelf
life. Setting the OSCEN bit in register 1FFF8h to 1
halts the oscillator. Setting the bit to 0 enables the
oscillator. The RTC does not run until the oscillator
is enabled.
ALARM
The alarm function compares user-programmed val-
ues to the corresponding time-of-day values. When
a match occurs, the alarm event occurs. The alarm
drives an internal flag, AF, and may drive the INT pin
if desired.
CALIBRATING THE CLOCK
The RTC is driven by a quartz controlled oscillator
with a nominal frequency of 32.768 KHz. Clock
accuracy will depend on the quality of the crystal,
usually specified to 35 ppm limits at 25°C. This error
could equate to + 1.53 minutes per month. The
STK17C88 employs a calibration circuit that can
improve the accuracy to + 1/-2 ppm at 25°C. The
calibration circuit adds or subtracts counts from the
oscillator divider circuit.
There are four alarm match fields. They are date,
hours, minutes and seconds. Each of these fields
also has a Match bit that is used to determine if the
field is used in the alarm match logic. Setting the
Match bit to “0” indicates that the corresponding field
will be used in the match process.
Depending on the Match bits, the alarm can occur
as specifically as one particular second on one day
of the month, or as frequently as once per second
continuously. The MSB of each alarm register is a
Match bit. Selecting none of the Match bits (all 1’s)
indicates that no match is required. The alarm
occurs every second. Setting the match select bit for
seconds to “0” causes the logic to match the sec-
onds alarm value to the current time of day. Since a
match will occur for only one value per minute, the
alarm occurs once per minute. Likewise, setting the
seconds and minutes Match bits causes an exact
match of these values. Thus, an alarm will occur
once per hour. Setting seconds, minutes and hours
causes a match once per day. Lastly, selecting all
match values causes an exact time and date match.
Selecting other bit combinations will not produce
meaningful results, however the alarm circuit should
follow the functions described.
The number of times pulses are suppressed (sub-
tracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into the
five calibration bits found in control register 1FFF8h.
Adding counts speeds the clock up; subtracting
counts slows the clock down. The Calibration bits
occupy the five lower order bits in the control regis-
ter 8. These bits can be set to represent any value
between 0 and 31 in binary form. Bit D5 is a Sign bit,
where a “1” indicates positive calibration and a “0”
indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the
cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles.
If a binary “1” is loaded into the register, only the first
2 minutes of the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected, and
so on. Therefore each calibration step has the effect
of adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is
+4.068 or -2.034 ppm of adjustment per calibration
step in the calibration register.
There are two ways a user can detect an alarm
event, by reading the AF flag or monitoring the INT
pin. The AF flag in the register 1FFF0h will indicate
that a date/time match has occurred. The AF bit will
be set to 1 when a match occurs. Reading the
Flags/Control register clears the alarm flag bit (and
all others). A hardware interrupt pin may also be
used to detect an alarm event.
In order to determine how to set the calibration one
may set the CAL bit in register 1FFF0h to 1, which
causes the INT pin to toggle at a nominal 512 Hz.
Any deviation measured from the 512 Hz will indi-
cate the degree and direction of the required correc-
tion. For example, a reading of 512.010124 Hz
would indicate a +20 ppm error, requiring a -10
(001010) to be loaded into the Calibration register.
Note that setting or changing the calibration register
does not affect the frequency test output frequency.
WATCHDOG TIMER
The watchdog timer is a free running down counter
that uses the 32 Hz clock (31.25 ms) derived from
the crystal oscillator. The oscillator must be running
for the watchdog to function. It begins counting
down from the value loaded in the Watchdog Timer
register.
The counter consists of a loadable register and a
free running counter. On power up, the watchdog
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timeout value in register 1FFF7h is loaded into the
counter load register. Counting begins on power up
and restarts from the loadable value any time the
Watchdog Strobe (WDS) bit is set to 1. The counter
is compared to the terminal value of 0. If the counter
reaches this value, it causes an internal flag and an
optional interrupt output. The user can prevent the
timeout interrupt by setting WDS bit to 1 prior to the
counter reaching 0. This causes the counter to be
reloaded with the watchdog timeout value and to be
restarted. As long as the user sets the WDS bit prior
to the counter reaching the terminal value, the inter-
rupt and flag never occurs.
controls the internal switch to backup power for the
clock and protects the memory from low-Vcc
access. The power monitor is based on an internal
band-gap reference circuit that compares the Vcc
voltage to various thresholds.
As descibed in the AutoStore™ section previously,
when Vswitch is reached as Vcc decays from power
loss, a data store operation is initiated from SRAM
to the nonvolatile elements, securing the last SRAM
data state. Power is also switched from Vccx to the
backup supply (battery or capacitor) to operate the
RTC oscillator.
When operating from the backup source no data
may be read or written and the clock functions are
not available to the user. The clock continues to
operate in the background. Updated clock data is
available to the user 10 msec after Vcc has been
restored to the device.
New timeout values can be written by setting the
watchdog write bit to 0. When the WDW is 0 (from
the previous operation), new writes to the watchdog
timeout value bits D5-D0 allow the timeout value to
be modified. When WDW is a 1, then writes to bits
D5-D0 will be ignored. The WDW function allows a
user to set the WDS bit without concern that the
watchdog timer value will be modified. A logical dia-
gram of the watchdog timer is shown below. Note
that setting the watchdog timeout value to 0 would
be otherwise meaningless and therefore disables
the watchdog function.
INTERRUPTS
The STK17C88 provides three potential interrupt
sources. They include the watchdog timer, the
power monitor, and the clock/calendar alarm. Each
can be individually enabled and assigned to drive
the INT pin. In addition, each has an associated flag
bit that the host processor can use to determine the
cause of the interrupt.
The output of the watchdog timer is a flag bit WDF
that is set if the watchdog is allowed to timeout. The
flag is set upon a watchdog timeout and cleared
when the Flags/Control register is read by the user.
The user can also enable an optional interrupt
source to drive the INT pin if the watchdog timeout
occurs.
Some of the sources have additional control bits that
determine functional behavior. In addition, the pin
driver has three bits that specify its behavior when
an interrupt occurs. A functional diagram of the
interrupt logic is shown below.
POWER MONITOR
The STK17C88 provides a power management
scheme with power-fail interrupt capability. It also
Figure 6. Interrupt Block Diagram
The three interrupts each have a source and an
enable. Both the source and the enable must be
active (true high) in order to generate an interrupt
output. Only one source is necessary to drive the
Figure 5. Watchdog Timer Block Diagram
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STK17C88
pin. The user can identify the source by reading the
Flags/Control register, which contains the flags
associated with each source. All flags are cleared to
0 when the register is read. The cycle must be a
complete read cycle (WE high); otherwise the flags
will not be cleared. The power monitor has two pro-
grammable settings that are explained in the power
monitor section.
the power monitor will drive the interrupt during all
normal Vcc conditions regardless of the ABE bit.
The application for ABE is intended for power con-
trol, where the system powers up at a predeter-
mined time. Depending on the application, it may
require dedicating the INT pin to this function.
High/Low - H/L. When set to a 1, the INT pin is
active high and the driver mode is push-pull. The
INT pin can drive high only when Vcc>Vswitch.
When set to a 0, the INT pin is active low and the
drive mode is open-drain. Active low (open drain) is
operational even in battery backup mode.
Once an interrupt source is active, the pin driver
determines the behavior of the output. It has two
programmable settings as shown below. Pin driver
control bits are located in the Interrupts register.
According to the programming selections, the pin
can be driven in the backup mode for an alarm inter-
rupt. In addition, the pin can be an active low (open-
drain) or an active high (push-pull) driver. If pro-
grammed for operation during backup mode, it can
only be active low. Lastly, the pin can provide a one-
shot function so that the active condition is a pulse
or a level condition. In one-shot mode, the pulse
width is internally fixed at approximately 200 ms.
This mode is intended to reset a host microcontrol-
ler. In level mode, the pin goes to its active polarity
until the Flags/Control register is read by the user.
This mode is intended to be used as an interrupt to
a host microcontroller. The control bits are summa-
rized as follows:
Pulse/Level - P/L. When set to a 1 and an interrupt
occurs, the INT pin is driven for approximately 200
ms. When P/L is set to a 0, the INT pin is driven high
or low (determined by H/L) until the Flags/Control
register is read.
When an enabled interrupt source activates the INT
pin, an external host can read the Flags/Control reg-
ister to determine the cause. Remember that all
flags will be cleared when the register is read. If the
INT pin is programmed for Level mode, then the
condition will clear and the INT pin will return to its
inactive state. If the pin is programmed for Pulse
mode, then reading the flag also will clear the flag
and the pin. The pulse will not complete its specified
duration if the Flags/Control register is read. If the
INT pin is used as a host reset, then the Flags/Con-
trol register cannot be read during a reset.
Watchdog Interrupt Enable - WIE. When set to 1,
the watchdog timer drives the INT pin as well as an
internal flag when a watchdog timeout occurs.
WhenWIE is set to 0, the watchdog timer affects
only the internal flag.
During a power-on reset with no battery, the inter-
rupt register is automatically loaded with the value
24h. This causes power-fail interrupt to be enabled
with an active-low pulse.
Alarm Interrupt Enable - AIE. When set to 1, the
alarm match drives the INT pin as well as an internal
fla. When set to 0, the alarm match only affects the
internal flag.
Power Fail Interrupt Enable - PFE. When set to 1,
the power fail monitor drives the pin as well as an
internal flag. When set to 0, the power fail monitor
affects only the internal flag.
Alarm Battery-backup Enable - ABE. When set to 1,
the clock alarm interrupt (as controlled by AIE) will
function even in battery backup mode. When set to
0, the alarm will occur only when Vcc>Vswitch. AIE
should only be set when the INT pin is programmed
for active low operation. In addition, it only functions
with the clock alarm, not the watchdog. If enabled,
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RTC Register Map
BCD DATA
Register
FUNCTION/RANGE
D7
D6
D5
D4
D3
D2
D1
D0
7FFFh
7FFEh
10 Years
Years
Years:
00 - 99
01 - 12
10s
Months
X
X
X
Months
Months:
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
X
X
X
X
X
X
X
X
10s Day of month
Day of Month
Day of Week
Hours
Day of Month:01 - 31
Day of Week:01 - 07
X
X
X
10s Hours
Hours:
00 - 23
10s Minutes
10s Seconds
Cal Sign
Minutes
Minutes: 00 - 59
Seconds: 00 - 59
Calibration values*
Watchdog*
Seconds
7FF8h
7FF7h
7FF6h
7FF5h
7FF4h
7FF3h
7FF2h
7FF1h
7FF0h
OSCEN
WDS
WIE
M
X
Calibration
WDT
WDW
AIE
X
PFE
ABE
H/L
P/L
alarm date
alarm hours
X
X
Interrupts*
10s alarm date
10s alarm hours
10 alarm minutes
10 alarm seconds
10s Centuries
AF PF
Alarm, Day of the Month: 01-31
Alarm, Hours: 00-23
Alarm, minutes: 00-59
Alarm, seconds: 00-59
Centuries: 00 - 99
Flags*
M
X
M
alarm minutes
alarm seconds
Centuries
M
WDF
X
X
CAL
W
R
X - resevered for future use
* - not BCD values
Register Map Detail
Timekeeping - Years
D4 D3
7FFFh
D7
D6
D5
D2
D1
D0
10 Years
Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years.
Each nibble operates from 0 to 9. The range for the register is 0-99.
Timekeeping - Months
7FFEh
7FFDh
7FFCh
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
10s Months
Months
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble ( one bit) contains the
upper digit and operates from 0 to 1. The range for the register is 1-12.
Timekeeping - Date
D7
D6
D5
D4
D3
D2
D1
D0
X
X
10s Day of month
Day of Month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the
upper digit and operates from 0 to 3. The range for the register is 1-31.
Timekeeping - Day
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
Day of Week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1.
The user must assign meaning to the day value, as the day is not integrated with the date.
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Timekeeping - Hours
D4 D3
7FFBh
D7
D6
D5
D2
D1
D0
12/24
X
10s Hours
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits)
contains the upper digit and operates from 0 to 2. The range for the register is 0-23.
Timekeeping - Minutes
7FFAh
7FF9h
D7
X
D6
D5
D4
D3
D2
D1
D0
10s Minutes
Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper min-
utes digit and operates from 0 to 5. The range for the register is 0-59.
Timekeeping - Seconds
D7
D6
D5
D4
D3
D2
D1
D0
X
10s Seconds
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit
and operates from 0 to 5. The range for the register is 0-59.
Contol/Calibration
7FF8h
D7
D6
D5
D4
D3
D2
D1
D0
Calibration
Sign
OSCEN
X
Calibration
Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the oscillator saves battery/capacitor
power during storage. On a no-battery power-up, this bit is set to 1. The RTC will not run until the oscillator is enabled. Set this bit to 0 to
activate the RTC.
OSCEN
Calibration Sign Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base.
Calibration
These five bits control the calibration of the clock.
Watchdog Timer
D4 D3
7FF7h
D7
D6
D5
D2
D1
D0
WDS
WDW
WDT
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no affect. The bit is cleared automat-
ically once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0.
WDS
Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT5-WDT0) so it cannot be written. This allows the user
to strobe the watchdog without disturbing the timeout value. Setting this bit to 0 allows bits 5-0 to be witten on the next write to the Watch-
dog register. The new value will be loaded on the next internal watchdog clock after the write cycle is complete. This function is explained
in more detail in the watchdog timer section.
WDW
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz
count (31.25 ms). The minimum range or timeout value is 31.25 ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3Fh).
Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was cleared to 0 on a previous
cycle.
WDT
Interrupt Status/Control
7FF6h
D7
D6
AIE
D5
PFE
D4
D3
D2
P/L
D1
D0
WIE
ABE
H/L
X
X
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin as well as the WDF flag.
When set to 0, the watchdog timeout affects only the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When set to 0, the alarm match only
affects the AF flag.
WIE
AIE
Power-Fail Enable. When set to 1, the alarm match drives the INT pin as well as the PF flag. When set to 0, the power-fail monitor affects
only the PF flag.
PFE
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function even in battery backup mode. When
set to 0, the alarm will occur only when Vcc>Vswitch.
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set
to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags/Control register is read.
ABE
H/L
P/L
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Document Control # ML0024 rev 0.0
STK17C88
Alarm - Day
7FF5h
D7
D6
D5
D4
10s alarm date
D3
D2
D1
D0
M
0
alarm date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the
date value.
M
Alarm - Hours
7FF4h
D7
D6
D5
D4
D3
D2
D1
alarm hours
D0
M
0
10s alarm hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the
hours value.
M
Alarm - Minutes
7FF3h
D7
D6
D5
D4
D3
D2
D1
alarm minutes
D0
M
10s alarm minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value
Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore
the minutes value.
M
Alarm - Seconds
7FF2h
D7
D6
D5
D4
D3
D2
D1
alarm seconds
D0
M
10s alarm seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds value
Match. Setting this bit to 0 causes the seconds value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore
the seconds value.
M
Timekeeping - Centuries
7FF1h
D7
D6
D5
D4
D3
D2
D1
D0
X
X
10s Centuries
Centuries
Flags
7FF0h
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
X
X
CAL
W
R
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. It is
cleared to 0 when the Flags/Control register is read.
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is
cleared when the Flags/Control register is read.
WDF
AF
Power-Fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold Vswitch. It is cleared to 0 when the Flags/
Control register is read.
Calibration Mode. When set to 1, the clock enters calibration mode. When set to 0, the clock operates normally.
Write Time. Setting the W bit to 1 freezes updates of the timekeeping registers. The user can then write them with updated values. Setting
the W bit to 0 causes the contents of the time registers to be transferred to the timekeeping counters.
PF
CAL
W
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a holding register. The user can
then read them without concerns over changing values causing system errors. The R bit going from 0 to 1 causes the timekeeping capture,
so the bit must be returned to 0 prior to reading again.
R
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Document Control # ML0024 rev 0.0
STK17C88
ORDERING INFORMATION
STK17C88 - R 45 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Package
R = Plastic 48-pin 300 mil SSOP
W = Plastic 40-pin 600 mil DIP
June 2003
20
Document Control # ML0024 rev 0.0
STK17C88
Document Revision History
Revision
0.0
Date
June 2003
Summary
Publish new datasheet
June 2003
21
Document Control # ML0024 rev 0.0
STK17C88
June 2003
22
Document Control # ML0024 rev 0.0
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