STK18TA8-R40 [SIMTEK]
Non-Volatile SRAM, 128KX8, CMOS, PDSO48, 0.300 INCH, 0.025 INCH PITCH, PLASTIC, SSOP-48;
| 型号： | STK18TA8-R40 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | Non-Volatile SRAM, 128KX8, CMOS, PDSO48, 0.300 INCH, 0.025 INCH PITCH, PLASTIC, SSOP-48 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总28页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK18TA8
nvTimeTM Event Data Recorder
Serial Peripheral Interface nvSRAM
QuantumTrapTM CMOS
Nonvolatile Static RAM
Preliminary
DESCRIPTION
FEATURES
• Data integrity of Simtek nvSRAM Combined
with Full-Featured Real-Time Clock
• 40 MHZ SPI interface with compatible
commands to industry standards 1 Mbit SPI
EEPROMs
• STORE to QuantumTrap™ Nonvolatile
Elements is Initiated by Software , device pin
or AutoStore™ on Power Down
• RECALL to SRAM Initiated by Software or
Power Restore
• Unlimited READ and WRITE and RECALL
Cycles
• Watchdog Timer
• Clock Alarm with programmable Interrupts
• Capacitor or battery backup for RTC
• Single 3V +20%, -10% Operation
• Commercial and Industrial Temperatures
• High-reliability
The Simtek STK18TA8 combines a 1 Mbit nonvolatile
static RAM and a full-featured real-time clock, in a
reliable, monolithic integrated circuit.
A
Serial
Peripheral Interface (SPI) makes system integration
simple. The embedded nonvolatile elements
incorporate Simtek’s QuantumTrapTM technology
producing the world’s most reliable nonvolatile
memory. The SRAM provides unlimited read and write
cycles, while independent, nonvolatile data resides in
the highly reliable QuantumTrapTM cell. Data transfers
from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power
down. On power up, data is restored to the SRAM (the
RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also
available under software control.
The Real-Time Clock function provides an accurate
clock with leap year tracking and a programmable,
high accuracy oscillator. The Alarm function is
programmable for one-time alarms or periodic
seconds, minutes, hours, or days. There is also a
programmable Watchdog Timer for process control.
o
o
Endurance to 1 Million Cycles
Retention to 100 years at 85 ºC
• Package: 48-Pin SSOP
BLOCK DIAGRAM
VCC
VCAP
Quantum Trap
1024 X 1024
VRTCbat
VRTCcap
POWER
CONTROL
STORE
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
1024 X 1024
RECALL
HSB
SCK
SI
SO
SPI
CONTROLLER
HOLD
Data
COLUMN I/O
CS
COLUMN DEC
X1
RTC
X2
Address
INT
Figure 1. Block Diagram
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Document Control #ML0028 rev 0.8
STK18TA8
PACKAGES
VCAP
1
2
3
4
5
6
VCC
48
47
46
45
44
43
HSB
7
8
9
10
11
12
13
14
15
16
42
41
40
39
38
37
36
35
34
33
INT
VSS
VSS
VSS
VSS
VRTCcap
VRTCbat
SCK
CS
17
18
32
31
30
29
28
27
26
25
19
20
21
22
23
24
HOLD
SI
PCB area usage.
See website for detailed
package size specifications.
X1
X2
SO
VCC
48 Pin SSOP
PIN DESCRIPTIONS
Pin Name
I/O
Description
The SI pin is used to transfer data into the device. Data is latched from this pin on the rising
edge of the SCK clock pin. Instructions, addresses and data are all transmitted over this pin.
The SO pin is used to transfer data out of the STK18TA8. During a read cycle, data is shifted out
on this pin after the falling edge of the serial clock.
SI - Serial Input
Input
SO - Serial Output
3-state Output
A low level on this pin selects the device. A falling edge is required on CS before each
command code. Nonvolatile operations which are already in progress will be completed
regardless of the CS input signal. When the device is deselected, SO goes to the high
impedance state allowing other devices to share the SPI bus. When CS is held high and all
internal commands have completed the device enters the standby mode (low-power).
The SCK is used to synchronize the communication between a master and the STK18TA8.
Instructions, addresses, or data present on the SI pin are latched on the rising edge of the clock
input, while data placed on the SO pin changes on the falling edge of the clock input.
CS - Chip Select
Input
SCK - Serial Clock
HOLD
Input
Input
The HOLD pin is used to pause the serial interface. If HOLD is driven low, the chip ignores
all serial input as long as CS is held low. When HOLD is again driven high, normal
operation resumes on the next clock edge. If CS is driven high at any time, the hold
operation is aborted. This pin has an internal pullup.
VCC - Chip Power
VSS - Chip Ground
Power
Power
The VCC pin supplies the power for the chip during normal operation.
Ground.
A capacitor should be connected with a minimum of 17uF, 5V minimum. Upon power down, VCAP
supplies the power for the AutoStoreTM operation whereby SRAM data elements are transferred
in parallel to the nonvolatile QuantumTrapTM elements.
VCAP - Power for Non-
Power
volatile AutoStoreTM
VRTCcap
VRTCbat
X1 - Crystal Out
X2 - Crystal in
Power
Power
Output
Input
Capacitor supplied backup RTC supply voltage. (Left unconnected if VRTCbat is used.)
Battery supplied backup RTC supply voltage. (Left unconnected if VRTCcap is used. )
Crystal Connection, drives crystal on startup.
Crystal Connection, 32.768Khz crystal.
When low this output indicates a Hardware Store is in progress. When pulled low externally to
the chip it will initiate a nonvolatile STORE operation. Left undriven the pin is weakly pulled up
HSB - STORE
In/Output
request and status
internal to the chip. STORE operation will not be started when VCC is below Vswitch
.
Pin which can be programmed to respond to the clock alarm, the watchdog timer, or the power
monitor. Programmable to either active high (push/pull) or active low (open-drain).
Unlabeled pins should be left with no connections on the printed circuit board.
INT - interrupt out
(Blank)
Output
No Connect
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ABSOLUTE MAXIMUM RATINGSa
Notes
-0.5V to +4.1V
Power Supply Voltage
Voltage on Input Relative to VSS
Voltage on Outputs
a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
-0.5V to (VCC + 0.5V)
-0.5V to (VCC + 0.5V)
–55°C to 125°C
–55°C to 140°C
–65°C to 150°C
1W
Temperature under Bias
Junction Temperature
Storage Temperature
Power Dissipation
DC Output Current (1 output at a time, 1s duration)
15mA
Package Thermal Characteristics see website: http://www.simtek.com/
DC CHARACTERISTICS
Commercial
Industrial
MIN MAX
Symbol
Parameter
Units
Notes
MIN
MAX
Based on 40MHz cycle rate. Values
obtained without output loads.
All Inputs Don’t Care, VCC = max
Average current for duration of STORE
cycle (tSTORE).
All Inputs Don’t Care
Average current for duration of STORE
cycle (tSTORE).
Average VCC Current
ICC1
10
10
3
mA
Average VCC Current during STORE
ICC2
3
3
mA
mA
Average VCAP Current during
AutoStore™ Cycle
ICC4
3
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
Standby current level after nonvolatile
cycle is complete.
VCC Standby Current
(Standby, Stable CMOS Input Levels)
ISB
2
2
mA
µA
VCC = max
Input Leakage Current
IILK
±1
±1
±1
VIN = VSS to VCC
VCC = max
VIN = VSS to VCC
Off-State Output Leakage Current
IOLK
±1
VCC + 0.3
0.8
µA
V
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
VIH
VIL
2.0
V
CC + 0.3
0.8
2.0
VSS – 0.5
2.4
All Inputs
All Inputs
V
SS – 0.5
2.4
V
VOH
VOL
TA
V
IOUT = –2mA
0.4
70
0.4
85
V
IOUT = 4mA
0
–40
oC
Nominal 3.0V +20%, -10% used for tested
specifications.
Operating Voltage
Storage Capacitor
VCC
2.7
17
3.6
57
2.7
17
3.6
57
V
VCAP
µf
Between Vcap pin and Vss, 5V rated.
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AC TEST CONDITIONS
0V to 3V
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
≤ 5ns
1.5V
Output Load
See Figure 2 and Figure 3
CAPACITANCEb
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
pF
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
CIN
Input Capacitance
Output Capacitance
7
7
COUT
pF
Notes
b: These parameters are guaranteed but not tested
3.0V
3.0V
577 Ohms
577 Ohms
OUTPUT
OUTPUT
30 pF
5 pF
789 Ohms
789 Ohms
INCLUDING
SCOPE AND
FIXTURE
INCLUDING
SCOPE AND
FIXTURE
Figure 2. AC Output Loading
Figure 3. AC Output Loading, for tri-
state specs ( tDIS
)
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STK18TA8
RTC DC CHARACTERISTICS
Commercial
Industrial
Symbol
Parameter
Units
Notes
MIN
MAX
MIN
MAX
RTC Backup Current
-
-
IBAK
300
350
nA
V
From either VRTCcap or VRTCbat
Typical = 3.0 Volts during normal
operation
Typical = 2.4 Volts during normal
operation
RTC Battery Pin Voltage
VRTCbat
VRTCcap
1.8
1.2
3.3
2.7
1.8
1.2
3.3
2.7
RTC Capacitor Pin Voltage
V
@ MIN Temperature from Power up
or Enable
-
-
-
-
1
1
min
sec
tOSCS
RTC Oscillator time to start
10
10
@25ºC from Power up or Enable
RTC RECOMMENDED COMPONENT CONFIGURATION
X1
X2
Recommended Values
Y1 = 32.768 KHz
RF = 10M Ohm
C1 = 2.2 pF
C2 = 47 pF
Figure 4. RTC COMPONENT CONFIGURATION
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STK18TA8
AC PARAMETERS
STK18TA8
NO.
SYMBOLS
PARAMETER
UNITS
MIN
MAX
1
2
FCLK
tCSS
Clock Frequency
CS setup time
40
MHZ
ns
5
CS hold time
3
tCSH
25
ns
4
5
tWH
tWL
tSU
tH
SCK high time
SCK low time
SI, Setup time
SI, hold time
10
10
3
ns
ns
ns
ns
ns
ns
ns
ns
6
7
5
8
5
tCS
tV
CS high time
Falling SCK to Output valid
Output hold time
9
7
3
10
11
tHO
tDIS
10
Output Disable time
SPITM Input Timing
1
8
1/FCLK
tCS
CS
SCK
SI
2
tCSS
4
tWH
5
tWL
3
tCSH
6
tSU
7
tH
SPITM Output Timing
CS
SCK
9
11
tDIS
tV
Delay Byte
HI-Z
7
6
5
SO
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STK18TA8
AutoStore™ /POWER-UP RECALL
STK18TA8
Notes
NO.
SYMBOLS
PARAMETER
UNITS
MIN
MAX
12
13
14
15
tHRECALL
tSTORE
VSWITCH
tVCCRISE
20
ms
ms
V
c
Power-up RECALL Duration
STORE Cycle Duration
Low Voltage Trigger Level
VCC Rise Time
12.5
2.65
d
2.55
150
µs
Notes
c: tHRECALL starts from the time VCC rises above VSWITCH
d: If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place
STORE occurs only if a
No STORE occurs
without at least one
SRAM write.
SRAM write has
happened.
VCC
14
VSWITCH
15
tVCCRISE
AutoStoreTM
13
tSTORE
13
tSTORE
POWER-UP RECALL
12
tHRECALL
12
tHRECALL
Read & Write Inhibited
POWER DOWN
BROWN-OUT
POWER-UP
RECALL
POWER-UP
RECALL
AutoStoreTM
AutoStoreTM
Note: Read and Write cycles will be ignored during STORE, RECALL and while VCC is below VSWITCH.
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STK18TA8
HARDWARE STORE CYCLE
SYMBOLS
STK18TA8
NO.
PARAMETER
UNITS
NOTES
Standard
tHLHX
Alternate
MIN
MAX
16
17
Hardware STORE Pulse Width
15
ns
ns
tHLBL
Hardware STORE Low to STORE Busy
300
16
tHLHX
HSB (In)
HSB (Out)
13
tSTORE
17
tHLBL
Hi-Z
SOFTWARE STORE CYCLE (CTLSEQ COMMAND)
SYMBOLS
STK18TA8
NO.
PARAMETER
UNITS
NOTES
Standard
Alternate
MIN
MAX
tRECALL
40
µs
18
RECALL Duration
Note: The parameter tSTORE or tRECALL are substituted for STORE or RECALL command respectively.
Endurance Parameters
SYMBOLS
STK18TA8
MIN MAX
NO.
PARAMETER
UNITS
NOTES
Standard Alternate
SRAM write cycles
Number of STORE cycles
Infinite
1 x 106
cycles
cycles
19
20
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STK18TA8
HOLD Signal Timing
SYMBOLS
STK18TA8
NO.
PARAMETER
SCK to HOLD Change
UNITS
NOTES
e
Standard
Alternate
MIN
MAX
tCH
tHQZ
tHQX
ns
ns
ns
21
22
23
5
HOLD active to Output Inactive
HOLD Inactive to Output Active
10
0
Notes
e: It is recommended that HOLD change on negative transitions of the SCK or while SCK is low.
CS
SCK
21
tCH
21
tCH
HOLD
SO
22
tHQZ
23
tHQX
22
tHQZ
23
tHQX
Hold
Hold
Normal Operation
Normal Operation
Normal Operation
Changes while SCK Low
(Recommended)
Delayed to falling
Edge of SCK
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STK18TA8
SERIAL PERIPHERAL INTERFACE
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last. Data is sampled on the first rising edge of SCK
after CS goes low. Refer to Figure 5 which shows
the connection of multiple SPI devices. The SO
output is shared since only the slave selected by
CS and a valid opcode is returns data to the master.
If no slave is selected the SO pin is tri-stated. If the
master device has a bi-directional pin capability, the
SO and SI pins may be shared by having the master
switch the pin to input when data is expected from
one of the slave SPI devices.
Serial Interface Description
The STK18TA8 is a 1 Mbit Serial nvSRAM (SRAM +
nonvolatile element in a combined cell) with 128K x 8
organization designed to interface directly with the
Serial Peripheral Interface (SPI) port of many popular
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port
by using discrete I/O lines programmed properly with
the software. The STK18TA8 SPI interface contains
an 8-bit instruction register. Data is clocked into the
device through the SI pin on the rising edge of SCK.
The CS pin must be low for the entire data transfer.
Table 1 contains a list of the possible instruction
SLAVE: DEVICES
MASTER: MPU
SI
DATA OUT (MOSI)
SO
DATA IN (MISO)
SCK
CS#
CLOCK (SPICK)
SS0
SS1
SS2
SS3
SI
SO
SCK
CS#
SI
SO
SCK
CS#
SI
SO
SCK
CS#
Figure 5. Multiple Device System
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STK18TA8
Table 1. SPITM INSTRUCTION SET
Instruction
Name
Code Description
READ
0x03
0x02
0x0B
0x0F
Read SRAM data from selected address.
WRITE
FREAD
CTLSEQ
Write SRAM data from selected address.
Fast read of SRAM data from selected address. (First byte is the delay byte).
Device control command sequence.
Table 2. CONTROL COMMAND SEQUENCES
Command
Name
CMD Bytes Description
0x4E38
0xB1C7
0x83E0
STORE
Commands Device to transfer the SRAM data to the nonvolatile memory elements.
0x7C1F
0x703F
0x8FC0
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
RECALL
AUTOENA
AUTODIS
Commands Device to transfer the nonvolatile memory contents to the SRAM memory.
Turns on the AUTOSTORETM feature of the device, enabling automatic stores to nonvolatile memory
when VCC drops below VSWITCH
.
Turns off the AUTOSTORETM feature of the device, disabling the automatic stores to nonvolatile
memory. STORES invoked by the control command STORE sequence and stores invoked by driving
the HSB pin remain enabled.
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STK18TA8
the SCK signal when CS falls or rises. Mode 0
has SCK=0 during SCK falls or rises. Mode 3 has
SCK high when CS falls or rises. The mode is
important for hardware SPI controllers and less so
for firmware based control. Refer to Figure 6 for a
diagram of signal waveforms.
SPI modes explained
SPI mode 0 and 3 are supported for the STK18TA8
device. In both modes, data is received from the SPI
master by presenting data tSU ns before the rising edge of
the clock. Data is driven out the SO pin on the falling
edge of SCK and received by the SPI master on the
rising edge. Mode 0 and mode 3 differ in the state of
CS
Mode 3
Mode 0
Mode 3
Mode 0
0
1
6
7
8
9
10
29
30
31
32
33
38
39
40
41
46
47
SCK
SI
7
6
1
0
23 22 21
2
1
0
7
6
1
0
7
6
1
0
SO
Figure 6. SPI Mode Waveforms
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STK18TA8
DEVICE OPERATION
On the falling edge of the 32th clock cycle (after the
command, and 3 address bytes) the data at the
specified address is shifted out on the SO output.
Every falling edge of SCK will generate another data
bit to be sampled by the master device on the next
rising edge of SCK. The READ command can be
continued by continuously holding the CS line low
and supplying additional SCK pulses. Internally the
byte address is automatically incremented and data
will continue to be shifted out. The delay byte is only
required on first memory access after the READ
command. All subsequent READs are pipelined and
are output on consecutive SCK falling edges. When
the highest SRAM address is reached, the address
counter will roll over to the lowest address allowing the
entire memory to be read in one continuous READ
cycle. When the CS line goes inactive the READ
command is terminated.
nvSRAM
The STK18TA8 nvSRAM is made up of two
functional components paired in the same physical
cell. These are a SRAM memory cell and a
nonvolatile QuantumTrap™ cell. The SRAM memory
cell operates as a standard fast static RAM. Data in
the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell
to SRAM (the RECALL operation). This unique
architecture allows all cells to be stored and recalled
in parallel. During the STORE and RECALL
operations SRAM READ and WRITE operations are
inhibited. The STK18TA8 supports unlimited reads
and writes just like a typical SRAM. In addition, it
provides unlimited RECALL operations from the
nonvolatile cells and up to 1 million STORE
operations.
SRAM READ
Please note that the top 16 bytes of the memory space
represent the RTC functions. The proper method for
reading these registers accurately is described in the
“Real Time Clock Operation” section of this document.
To logically separate the RTC registers from the SRAM
accesses, READ commands wrap back to 0x0000
after accessing 0x1FFEF. READs from addresses
above 0x1FFEF, which represents the RTC address
space, do not advance the address counter. Only 1
byte is read. As long as CS is held low the same
byte will continue be read.
Reading the STK18TA8 via the SO (Serial Output) pin
requires the following sequence. After the CS line is
pulled low to select a device, the READ op-code is
transmitted via the SI line clocked in on each rising
edge of SCK followed by a 3 byte address to be read
(Refer to Table 6). All data is sent with the most
significant bit first. After the address bytes SCK must
complete eight cycles. This allows time for the
memory to be access and the data to be loaded into
the output shift register.
Figure 7. Read Command Multi-byte Example
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SRAM FREAD
the 9th cycle the most significant bit of the memory byte
is ready to on the SO output. This command is
provided for systems that require the maximum clock
frequency but are unable to provide the delay required
for the SRAM access prior to valid data on SO. SO is
not driven during the delay byte and data during this
time period is considered invalid.
A fast READ command is also provided on the
STK18TA8 SPI interface. This command operates like
the standard READ command except that a delay byte
is inserted between the last address bit and the first
valid data bit. The master SPI controller is required to
supply 8 delay byte clock cycles. On the rising edge of
Figure 8. Fast Read Command Multi-byte Example
SRAM WRITE
To logically separate the RTC registers from the
SRAM access WRITE commands will wrap back to
0x0000 after writing 0x1FFEF. WRITEs targeted for
addresses above 0x1FFEF which represent the RTC
address space, do not advance the address counter.
Only one data byte is expected in write commands
targeted for the RTC. If multiple bytes are sent, later
bytes will overwrite bytes sent earlier.
Writing to the STK18TA8 requires the following
sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI
line (MSB first) followed by a three-byte address and
the data (D7 - D0) to be programmed (Refer to Table
6). A single or unlimited number of data bytes may be
sent after the first byte and the address will increment
after each byte is received. The WRITE command is
terminated when CS pin goes inactive.
Please note that the top 16 bytes of the memory
space represent the RTC registers on the chip. The
proper method for writing these registers accurately is
described in the “Real Time Clock Operation” section
of this document.
Figure 9. Write Command Multi-byte Example
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Figure 10 shows the proper connection of the storage
capacitor (Vcap) for automatic store operation. Refer to
the DC CHARACTERISTICS table for the size of Vcap.
The voltage on the Vcap pin is driven to 5V by a
charge pump internal to the chip.
AutoStore™ OPERATION
The STK18TA8 stores data to nvSRAM using one of
three storage operations. These three operations are
Hardware Store, activated by HSB , Software Store,
activated by a SPI command, and AutoStore™,
activated on device power down.
To reduce unneeded nonvolatile stores, AutoStore™
and Hardware Store operations will be ignored unless
at least one WRITE operation has taken place since
the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The
HSB signal can be monitored by the system to detect a
STORE cycle is in progress.
AutoStore™ operation is a unique feature of Simtek
QuantumTrap™ technology and is enabled by default
on the STK18TA8.
During normal operation, the device will draw current
from Vcc to charge a capacitor connected to the Vcap
pin. This stored charge will be used by the chip to
perform a single STORE operation. If the voltage on
the Vcc pin drops below Vswitch, the part will
automatically disconnect the Vcap pin from Vcc.
A
STORE operation will be initiated with power provided
by the Vcap capacitor.
VCC
VCAP
VCC
Figure 10. AutoStoreTM Mode
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STK18TA8
SOFTWARE STORE
HARDWARE STORE ( HSB ) OPERATION
Data can be transferred from the SRAM to the
nonvolatile memory by using a SPI command. The
STK18TA8 software STORE cycle is initiated by
issuing a CTLSEQ command through the SPI
interface. During the STORE cycle an erase of the
previous nonvolatile data is first performed, followed
by a program of the nonvolatile elements. Once a
STORE cycle is initiated, further READ and WRITE
commands are ignored until the cycle is completed.
After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation. Please see Table 2 and Figure 11 for
details on how to issue the appropriate CTLSEQ.
The STK18TA8 provides the HSB pin for controlling and
monitoring the STORE operations. The HSB pin can be
used to request a hardware STORE cycle. When
the HSB pin is driven low, the STK18TA8 will
conditionally initiate a STORE operation. An actual
STORE cycle will only begin if a WRITE to the SRAM
took place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is
internally driven low to indicate a busy condition while
the STORE (initiated by any means) is in progress.
The SPI controller checks the state of the HSB pin just
after the final bit of each byte being written. If HSB is
active the WRITE operation is cancelled. However, if
HSB goes low after the WRITE operation has been
initiated the WRITE will complete before the STORE
operation is started. Memory READ and incomplete
SPI commands will be cancelled and/or ignored when
SOFTWARE RECALL
Data can be transferred from the nonvolatile
memory to the SRAM by using a SPI command. A
software RECALL cycle is initiated by issuing a
CTLSEQ command through the SPI interface.
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the
nonvolatile information is transferred into the SRAM
cells. Once a RECALL cycle is initiated, further
READ and WRITE commands are ignored until the
cycle is completed. After the tRECALL cycle time the
SRAM will once again be ready for READ and
WRITE operations. The RECALL operation in no
way alters the data in the nonvolatile elements.
Please see Table 2 and Figure 11 for details on how
to issue the appropriate CTLSEQ.
HSB
is active. During any STORE operation,
regardless of how it was initiated, the STK18TA8 will
continue to drive the HSB pin low, releasing it only
when the STORE is complete. Upon completion of the
STORE operation the STK18TA8 will remain disabled
until the HSB pin returns high.
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up, or after any low-power condition (VCC
< VSWITCH), an internal RECALL request will be latched.
When VCC once again exceeds the sense voltage of
VSWITCH, a RECALL cycle will automatically be initiated
and will take tHRECALL to complete.
Figure 11. Control Sequence Command Example
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PREVENTING AUTOSTORETM
changes state while SCK is high the hold state will
not be recognized until the next falling edge of SCK.
During the hold state SCK can toggle and devices
sharing SO and SI can use these signal lines to
communicate without disturbing the command in
progress on this device. The STK18TA8 releases
the SO pin during the duration of the hold
operation so that other devices may communicate
with the SPI master. CS must be held low
selecting the device during the hold operation. If the
CS goes high while a hold is in progress the
command will be terminated.
The AutoStore™ function can be disabled by initiat-
ing an AutoStore Disable CTLSEQ command.
The AutoStore™ can be re-enabled by initiating an
AutoStore Enable CTLSEQ command. If the
AutoStore™ function is disabled or re-enabled a
manual STORE operation (Hardware or Software)
needs to be issued to save the AutoStore state
through subsequent power down cycles. The part
comes from the factory with AutoStore™ enabled.
Please see Table 2 and Figure 11 for details on
how to issue the appropriate CTLSEQ.
DATA PROTECTION
When AutoStore™ is disabled as described above
the RTC registers are not saved on power down.
If the RTC registers are changed during system
operation a CTLSEQ STORE needs to be issued
to update the non-volatile memory.
The STK18TA8 protects data from corruption during
low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The low-
voltage condition is detected when VCC < VSWITCH .
NOISE CONSIDERATIONS
HOLD OPERATION
The STK18TA8 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCC and
VSS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, careful
routing of power, ground and signals will reduce
circuit noise.
The
HOLD
pin is used to pause serial
communications without aborting the command in
progress. This can be useful if the SPI master is
interrupted during a burst read or write to service
another device. The HOLD signal is intended to be
asserted while SCK is low and to be de-asserted
again while SCK is low. HOLD is recognized by the
STK18TA8 only when SCK is low. If HOLD
Figure 12. HOLD Operation Example
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REAL TIME CLOCK OPERATION
nvTIME OPERATION
SETTING THE CLOCK
The STK18TA8 offers internal registers that contain Setting the write bit “W” (in the flags register at
Clock, Alarm, Watchdog, Interrupt, and Control 0x1FFF0) to a “1” halts updates to the STK18TA8
functions. Internal double buffering of the clock and registers. The correct day, date and time can then be
the clock/timer information registers prevents written into the registers in 24-hour BCD format. The
accessing transitional internal clock data during a time written is referred to as the “Base Time.” This
read or write operation. Double buffering also cir- value is stored in nonvolatile registers and used in
cumvents disrupting normal timing counts or clock calculation of the current time. Resetting the write bit
accuracy of the internal clock while accessing clock to “0” transfers those values to the actual clock
data. Clock and Alarm Registers store data in BCD counters, after which the clock resumes normal
format.
operation.
BACKUP POWER
CLOCK OPERATIONS
The RTC in the STK18TA8 is intended for
permanently powered operation. Either the VRTCcap or
VRTCbat pin is connected depending on whether a
capacitor or battery is chosen for the application.
When primary power, Vcc, fails and drops below Vswitch
the device will switch to the backup power supply.
The clock registers maintain time up to 9,999 years in
one second increments. The user can set the time to
any calendar time and the clock automatically keeps
track of days of the week and month, leap years and
century transitions. There are eight registers
dedicated to the clock functions which are used to set
time with a write cycle and to read time during a read
cycle. These registers contain the Time of Day in
BCD format. Bits defined as “X” are currently not used
and are reserved for future use by Simtek.
The clock oscillator uses very little current, which
maximizes the backup time available from the backup
source. Regardless of clock operation with the
primary source removed, the data stored in nvSRAM
is secure, having been stored in the nonvolatile
elements as power was lost. Factors to be considered
when choosing a backup power source include: the
expected duration of power outages and the cost
trade-off of using a battery versus a capacitor.
READING THE CLOCK
While the double-buffered RTC register structure
reduces the chance of reading incorrect data from the
clock, the user should halt internal updates to the
STK18TA8 clock registers before reading clock data
to prevent the reading of data in transition. Stopping
the internal register updates does not affect clock
accuracy.
During backup operation the STK18TA8 consumes a
maximum of 300 nanoamps at 2 volts. Capacitor or
battery values should be chosen according to the
application. Backup time values based on maximum
current specs are shown below. Nominal times are
approximately 3 times longer.
The updating process is stopped by writing a “1” to
the read bit “R” (in the flags register at 0x1FFF0), and
will not restart until a “0” is written to the read bit. The
RTC registers can then be read while the internal
clock continues to run.
Capacitor Value
0.1 F
Backup Time
72 hours
14 days
30 days
0.47 F
1.0 F
Within 20ms after a “0” is written to the read bit, all
STK18TA8 registers are simultaneously updated.
Using a capacitor has the obvious advantage of
recharging the backup source each time the system is
powered up.
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If a battery is used, a 3V lithium is recommended and calibration circuit adds or subtracts counts from the
the STK18TA8 will only source current from the bat- oscillator divider circuit.
tery when the primary power is removed. The battery
The number of times pulses are suppressed (sub-
will not, however, be recharged at any time by the
tracted, negative calibration) or split (added, positive
STK18TA8. The battery capacity should be chosen
calibration) depends upon the value loaded into the
for total anticipated cumulative down-time required
five calibration bits found in calibration register at
over the life of the system.
0x1FFF8. Adding counts speeds the clock up;
subtracting counts slows the clock down. The
Calibration bits occupy the five lower order bits in the
control register 8. These bits can be set to represent
STOPPING AND STARTING THE OSCIL-
LATOR
The OSCEN bit in calibration register at 0x1FFF8
controls the starting and stopping of the oscillator.
This bit is nonvolatile and shipped to customers in the
"enabled" (set to 0) state. To preserve battery life
while system is in storage OSCEN should be set to a
1. This will turn off the oscillator circuit extending the
battery life. If the OSCEN bit goes from disabled to
enabled, it will take approximately 5 seconds (10
seconds max) for the oscillator to start.
any value between 0 and 31 in binary form. Bit D5 is a
Sign bit, where a “1” indicates positive calibration and
a “0” indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the
cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles.
If a binary “1” is loaded into the register, only the first
2 minutes of the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so
on. Therefore each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is
+4.068 or -2.034 ppm of adjustment per calibration
step in the calibration register.
The STK18TA8 has the ability to detect oscillator
failure. This is recorded in the OSCF (Oscillator
Failed bit) of the flags register at address 0x1FFF0.
When the device is powered on (VCC goes above
Vswitch) the OSCEN bit is checked for "enabled" status.
If the OSCEN bit is enabled and the oscillator is not
active, the OSCF bit is set. The user should check for
this condition and then write a 0 to clear the flag. It
should be noted that in addition to setting the OSCF
flag bit, the time registers are reset to the “Base Time”
(see the section “Setting the Clock”), which is the
value last written to the timekeeping registers. The
Control/Calibration register and the OSCEN bit are not
affected by the oscillator failed condition.
In order to determine how to set the calibration one
may set the CAL bit in the flags register at 0x1FFF0 to
1, which causes the INT pin to toggle at a nominal
512 Hz. Any deviation measured from the 512 Hz will
indicate the degree and direction of the required
correction. For example, a reading of 512.010124 Hz
would indicate a +20 ppm error, requiring a -10
(001010) to be loaded into the Calibration register.
Note that setting or changing the calibration register
does not affect the frequency test output frequency.
If the voltage on the backup supply (either VRTCcap or
VRTCbat) falls below their respective minimum level the
oscillator may fail, leading to the oscillator failed
condition which can be detected when system power
is restored.
ALARM
The alarm function compares user-programmed val-
ues to the corresponding time-of-day values. When a
match occurs, the alarm event occurs. The alarm
drives an internal flag, AF, and may drive the INT pin
if desired.
The value of OSCF should be reset to 0 when the
time registers are written for the first time. This will
initialize the state of this bit which may have become
set when the system was first powered on.
There are four alarm match fields. They are date,
hours, minutes and seconds. Each of these fields also
has a Match bit that is used to determine if the field is
used in the alarm match logic. Setting the Match bit to
“0” indicates that the corresponding field will be used
in the match process.
CALIBRATING THE CLOCK
The RTC is driven by a quartz controlled oscillator
with a nominal frequency of 32.768 KHz. Clock
accuracy will depend on the quality of the crystal,
usually specified to 35 ppm limits at 25°C. This error
could equate to + 1.53 minutes per month. The
STK18TA8 employs a calibration circuit that can
improve the accuracy to +1/-2 ppm at 25°C. The
Depending on the Match bits, the alarm can occur as
specifically as one particular second on one day of
the month, or as frequently as once per second
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continuously. The MSB of each alarm register is a set the WDS bit without concern that the watchdog
Match bit. Selecting none of the Match bits (all 1’s) timer value will be modified. A logical diagram of the
indicates that no match is required. The alarm occurs watchdog timer is shown below. Note that setting the
every second. Setting the match select bit for seconds watchdog time-out value to 0 would be otherwise
to “0” causes the logic to match the seconds alarm meaningless and therefore disables the watchdog
value to the current time of day. Since a match will function.
occur for only one value per minute, the alarm occurs
once per minute. Likewise, setting the seconds and
Clock
Divider
Oscillator
1 Hz
minutes Match bits causes an exact match of these
values. Thus, an alarm will occur once per hour.
Setting seconds, minutes and hours causes a match
once per day. Lastly, selecting all match values
causes an exact time and date match. Selecting other
bit combinations will not produce meaningful results;
however the alarm circuit should follow the functions
described.
32.768KH2
32 Hz
Zero
Compare
WDF
Counter
Load
Register
WDS
WDW
There are two ways a user can detect an alarm event,
by reading the AF flag or monitoring the INT pin. The
AF flag in the flags register at 0x1FFF0 will indicate
that a date/time match has occurred. The AF bit will
be set to 1 when a match occurs. Reading the
Flags/Control register clears the alarm flag bit (and all
others). A hardware interrupt pin may also be used to
detect an alarm event.
D
Q
Q
Watchdog
Register
write to
Watchdog
Register
Figure 13. Watchdog Timer Block Diagram
The output of the watchdog timer is a flag bit WDF
that is set if the watchdog is allowed to time-out. The
flag is set upon a watchdog time-out and cleared
when the Flags/Control register is read by the user.
The user can also enable an optional interrupt source
to drive the INT pin if the watchdog time-out occurs.
WATCHDOG TIMER
The watchdog timer is a free running down counter
that uses the 32 Hz clock (31.25 ms) derived from the
crystal oscillator. The oscillator must be running for
the watchdog to function. It begins counting down
from the value loaded in the Watchdog Timer register.
The counter consists of a loadable register and a free
running counter. On power up, the watchdog time-out
value in register 0x1FFF7 is loaded into the counter
load register. Counting begins on power up and
restarts from the loadable value any time the
Watchdog Strobe (WDS) bit is set to 1. The counter is
compared to the terminal value of 0. If the counter
reaches this value, it causes an internal flag and an
optional interrupt output. The user can prevent the
time-out interrupt by setting WDS bit to 1 prior to the
counter reaching 0. This causes the counter to be
reloaded with the watchdog time-out value and to be
restarted. As long as the user sets the WDS bit prior
to the counter reaching the terminal value, the inter-
rupt and flag never occurs.
POWER MONITOR
The STK18TA8 provides a power management
scheme with power-fail interrupt capability. It also
controls the internal switch to backup power for the
clock and protects the memory from low-VCC access.
The power monitor is based on an internal band-gap
reference circuit that compares the VCC voltage to
various thresholds.
As described in the AutoStore™ section previously,
when Vswitch is reached as VCC decays from power
loss, a data store operation is initiated from SRAM to
the nonvolatile elements, securing the last SRAM
data state. Power is also switched from VCC to the
backup supply (battery or capacitor) to operate the
RTC oscillator.
New time-out values can be written by setting the
watchdog write bit to 0. When the WDW is 0 (from the
previous operation), new writes to the watchdog time-
out value bits D5-D0 allow the time-out value to be
modified. When WDW is a 1, then writes to bits D5-D0
will be ignored. The WDW function allows a user to
When operating from the backup source no data may
be read or written and the clock functions are not
available to the user. The clock continues to operate
in the background. Updated clock data is available to
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the user after tHRECALL delay (See AutoStore™ According to the programming selections, the pin can
/POWER-UP RECALL) after VCC has been restored be driven in the backup mode for an alarm interrupt.
to the device.
In addition, the pin can be an active low (open-drain)
or an active high (push-pull) driver. If programmed for
operation during backup mode, it can only be active
low. Lastly, the pin can provide a one-shot function so
that the active condition is a pulse or a level condition.
In one-shot mode, the pulse width is internally fixed at
approximately 200 ms. This mode is intended to reset
a host microcontroller. In level mode, the pin goes to
its active polarity until the Flags/Control register is
read by the user. This mode is intended to be used as
an interrupt to a host microcontroller. The control bits
are summarized as follows:
INTERRUPTS
The STK18TA8 provides three potential interrupt
sources. They include the watchdog timer, the power
monitor, and the clock/calendar alarm. Each can be
individually enabled and assigned to drive the INT pin.
In addition, each has an associated flag bit that the
host processor can use to determine the cause of the
interrupt.
Some of the sources have additional control bits that
determine functional behavior. In addition, the pin
driver has three bits that specify its behavior when an
interrupt occurs. A functional diagram of the interrupt
logic is shown below.
Watchdog Interrupt Enable - WIE. When set to 1, the
watchdog timer drives the INT pin as well as an
internal flag when a watchdog time-out occurs. When
WIE is set to 0, the watchdog timer affects only the
internal flag.
Alarm Interrupt Enable - AIE. When set to 1, the alarm
match drives the INT pin as well as an internal flag.
When set to 0, the alarm match only affects to internal
flag.
WDF
Watchdog
Timer
WIE
VCC
PF
PFE
AF
P/L
Power Fail Interrupt Enable - PFE. When set to 1, the
power fail monitor drives the pin as well as an internal
flag. When set to 0, the power fail monitor affects only
the internal flag.
Power
Monitor
Pin
Driver
INT
H/L
VINT
VSS
Clock
Alarm
High/Low - H/L. When set to a 1, the INT pin is active
high and the driver mode is push-pull. The INT pin
can drive high only when VCC>Vswitch. When set to a 0,
the INT pin is active low and the drive mode is open-
drain. Active low (open drain) is operational even in
battery backup mode.
AIE
Figure 14. Interrupt Block Diagram
Pulse/Level - P/L. When set to a 1 and an interrupt
occurs, the INT pin is driven for approximately 200
ms. When P/L is set to a 0, the INT pin is driven high
or low (determined by H/L) until the Flags/Control
register is read.
The three interrupts each have a source and an
enable. Both the source and the enable must be
active (true high) in order to generate an interrupt
output. Only one source is necessary to drive the pin.
The user can identify the source by reading the
Flags/Control register, which contains the flags
associated with each source. All flags are cleared to 0
when the register is read. The cycle must be a
complete read cycle ( WE high); otherwise the flags
will not be cleared. The power monitor has two pro-
grammable settings that are explained in the power
monitor section.
When an enabled interrupt source activates the INT
pin, an external host can read the Flags/Control reg-
ister to determine the cause. Remember that all flags
will be cleared when the register is read. If the INT pin
is programmed for Level mode, then the condition will
clear and the INT pin will return to its inactive state. If
the pin is programmed for Pulse mode, then reading
the flag also will clear the flag and the pin. The pulse
will not complete its specified duration if the
Flags/Control register is read. If the INT pin is used as
a host reset, then the Flags/Control register should
not be read during a reset.
Once an interrupt source is active, the pin driver
determines the behavior of the output. It has two
programmable settings as shown below. Pin driver
control bits are located in the Interrupts register.
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During a power-on reset with no battery, the interrupt
register is automatically loaded with the value 24h.
This causes power-fail interrupt to be enabled with an
active-low pulse.
RTC Register Map
BCD Format Data
Register
Function / Range
Years: 00-99
D7
D6
D5
D4
D3
D2
D1
D0
0x1FFFF
0x1FFFE
10s Years
Years
10s
Months
0
0
0
0
Months
Months: 01-12
10s Day of
Month
0x1FFFD
0
Day of Month
Day of Month: 01-31
0x1FFFC
0x1FFFB
0x1FFFA
0x1FFF9
0
0
0
0
0
0
0
0
Day of Week
Day of week: 01-07
Hours: 00-23
Minutes: 00-59
Seconds: 00-59
10s Hours
10s Minutes
10s Seconds
Cal
Hours
Minutes
Seconds
0x1FFF8
0x1FFF7
0x1FFF6
0x1FFF5
OSCEN
WDS
WIE
0
Calibration
WDT
H/L
Calibration values*
Watchdog*
Sign
WDW
AIE
0
PFE
ABE
P/L
0
0
Interrupts*
10s Alarm
Date
Alarm, Day of Month:
01-31
M
Alarm Day
10s Alarm
Hours
0x1FFF4
0x1FFF3
0x1FFF2
M
M
M
0
Alarm Hours
Alarm, hours: 00-23
Alarm, minutes: 00-59
Alarm, seconds: 00-59
10 Alarm Minutes
Alarm Minutes
10 Alarm Seconds
10s Centuries
Alarm Seconds
Centuries
0x1FFF1
0x1FFF0
Centuries: 00-99
Flags*
WDF
AF
PF
OSCF
0
CAL
W
R
* - Is a binary value, not a BCD value.
0 - Not implemented, reserved for future use.
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Register Map Detail
Timekeeping – Years
D4 D3
0x1FFFF
D7
D6
D5
D2
D1
Years
D0
10s Years
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper
nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the
register is 0-99.
Timekeeping – Months
0x1FFFE
0x1FFFD
0x1FFFC
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
10s Month
Months
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to
9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the
register is 1-12.
Timekeeping – Date
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Day of month
Day of month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and
operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for
the register is 1-31. Leap years are automatically adjusted for.
Timekeeping – Day
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
Day of week
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter
that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the
day is not integrated with the date.
Timekeeping – Hours
0x1FFFB
0x1FFFA
D7
D6
D5
D4
D3
D2
D1
D0
12/24
0
10s Hours
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and
operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The
range for the register is 0-23.
Timekeeping – Minutes
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Minutes
Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register
is 0-59.
Timekeeping – Seconds
0x1FFF9
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Seconds
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to
9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-
59.
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Calibration / Control
D4 D3
0x1FFF8
D7
D6
D5
D2
D1
D0
Calibration
Sign
OSCEN
0
Calibration
Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs.
Disabling the oscillator saves battery/capacitor power during storage. On a no-battery power-up,
this bit is set to 0.
OSCEN
Calibration
Sign
Determines if the calibration adjustment is applied as an addition to or as a subtraction from the
time-base.
These five bits control the calibration of the clock.
Calibration
Watchdog Timer
0x1FFF7
D7
D6
D5
D4
D3
D2
WDT
D1
D0
WDS
WDW
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0
has no affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is
write only. Reading it always will return a 0.
WDS
Watchdog Write Enable. Setting this bit to 1 masks the watchdog time-out value (WDT5-WDT0) so
it cannot be written. This allows the user to strobe the watchdog without disturbing the time-out
value. Setting this bit to 0 allows bits 5-0 to be written on the next write to the Watchdog register.
The new value will be loaded on the next internal watchdog clock after the write cycle is complete.
This function is explained in more detail in the watchdog timer section.
WDW
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this
register. It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or time-out
value is 31.25 ms (a setting of 1) and the maximum time-out is 2 seconds (setting of 3Fh). Setting
the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit
was cleared to 0 on a previous cycle.
WDT
Interrupt Status / Control
0x1FFF6
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFIE
ABE
H/L
P/L
0
0
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer
drives the INT pin as well as the WDF flag. When set to 0, the watchdog time-out affects only the
WDF flag.
WIE
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag.
When set to 0, the alarm match only affects the AF flag.
Power-Fail Enable. When set to 1, the alarm match drives the INT pin as well as the AF flag. When
set to 0, the power-fail monitor affects only the PF flag.
AIE
PFIE
ABE
H/L
Alarm Battery-backup Enable. When set to 1, the alarm interrupt (as controlled by AIE) will function
even in battery backup mode. When set to 0, the alarm will occur only when Vcc>Vswitch
.
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open
drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L ) by an interrupt
source for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set
by H/L ) until the Flags/Control register is read.
P/L
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Alarm – Day
D3
0x1FFF5
D7
D6
D5
D4
D2
D1
D0
M
0
10s Alarm Date
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date
value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the date value.
M
Alarm – Hours
0x1FFF4
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Hours
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to
1 causes the match circuit to ignore the hours value.
M
Alarm – Minutes
0x1FFF3
D7
D6
D5
D4
D3
D2
D1
D0
M
10s Alarm Minutes
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
Match. Setting this bit to 0 causes the minutes value to be used in the alarm match. Setting this bit
to 1 causes the match circuit to ignore the minutes value.
M
Alarm – Seconds
0x1FFF2
D7
D6
D5
D4
D3
D2
D1
D0
M
10s Alarm Seconds
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’
value.
Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this
bit to 1 causes the match circuit to ignore the seconds value.
M
Timekeeping – Centuries
0x1FFF1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Centuries
Centuries
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Flags
D3
0x1FFF0
D7
D6
D5
D4
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0
without being reset by the user. It is cleared to 0 when the Flags/Control register is read.
Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the
alarm registers with the match bits = 0. It is cleared when the Flags/Control register is read.
Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail threshold
Vswitch. It is cleared to 0 when the Flags/Control register is read.
WDF
AF
PF
Oscillator Fail Flag. Set to 1 on power-up only if the oscillator is not running in the first 5ms of
power-on operation. This indicates that time counts are no longer valid. The user must reset this
bit to 0 to clear this condition. The chip will not clear this flag. This bit survives power cycles.
Calibration Mode. When set to 1, a 512Hz square wave is output on the INT pin. When set to 0,
the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up.
Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then
write them with updated values. Setting the W bit to 0 causes the contents of the time registers to
be transferred to the timekeeping counters.
OSCF
CAL
W
Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places
them in a holding register. The user can then read them without concerns over changing values
causing system errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must
be returned to 0 prior to reading again.
R
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ORDERING INFORMATION
STK18TA8 – R F 40 I
Temperature Range
Blank = Commercial (0 to 70º C)
I = Industrial (-40 to 85ºC)
Maximum Clock Frequency
40 = 40 MHz
Lead Finish
Blank = 85% Sn / 15% Pb
F = 100% Sn (Matte Tin) ROHS Compliant
Package
R = Plastic 48-pin 300 mil SSOP (25 mil pitch)
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Document Revision History
Revision
Date
Summary
Publish new datasheet
0.0
June 2003
Revised Feature Set
0.4
November 2004
Changed SI hold time tH from 0 to 5 ns.
0.5
January 2005
Changed tV, SCK to Data Valid from 5ns to 7ns.
Changed tSU, SI hold time from 5ns to 3ns.
0.6
January 2005
Added HOLD signal to SPI interface.
Removed RDSR Command.
0.7
0.8
January 2005
April 2005
Changed RTC register unused bits “X” to require zero “0” value when writing values.
SIMTEK STK18TA8 Data Sheet, April 2005
Copyright 2005, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the express use of Simtek Customers. No part of this datasheet may be reproduced in any other form or
means without express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but
changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or
transfer of any rights to any Simtek patent, copyright, trademark or other proprietary right.
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